Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1925

1

T4

6

T8

1

T11

7

auto[1]

1869

1

T4

4

T8

2

T11

15

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2029

1

T4

10

T8

3

T11

19

auto[1]

1765

1

T11

3

T14

7

T27

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3019

1

T4

7

T8

2

T11

8

auto[1]

775

1

T4

3

T8

1

T11

14

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	739	1			T4	2		T11	7		T14	3
valid[1]	760	1			T4	2		T11	7		T14	5
valid[2]	783	1			T4	2		T8	2		T11	3
valid[3]	774	1			T4	4		T11	3		T14	8
valid[4]	738	1			T8	1		T11	2		T14	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	114	1			T4	1		T11	1		T14	1
auto[0]	auto[0]	valid[0]	auto[1]	166	1			T14	1		T30	2		T33	1
auto[0]	auto[0]	valid[1]	auto[0]	126	1			T4	1		T50	1		T52	3
auto[0]	auto[0]	valid[1]	auto[1]	186	1			T11	2		T30	1		T33	2
auto[0]	auto[0]	valid[2]	auto[0]	136	1			T4	1		T12	1		T52	2
auto[0]	auto[0]	valid[2]	auto[1]	172	1			T27	1		T33	1		T50	1
auto[0]	auto[0]	valid[3]	auto[0]	130	1			T4	2		T14	2		T52	4
auto[0]	auto[0]	valid[3]	auto[1]	197	1			T33	2		T89	1		T90	6
auto[0]	auto[0]	valid[4]	auto[0]	132	1			T11	1		T14	1		T52	1
auto[0]	auto[0]	valid[4]	auto[1]	162	1			T14	1		T33	3		T90	4
auto[0]	auto[1]	valid[0]	auto[0]	124	1			T4	1		T11	1		T14	1
auto[0]	auto[1]	valid[0]	auto[1]	183	1			T30	2		T90	1		T91	3
auto[0]	auto[1]	valid[1]	auto[0]	124	1			T11	1		T14	1		T52	2
auto[0]	auto[1]	valid[1]	auto[1]	181	1			T14	3		T89	1		T90	5
auto[0]	auto[1]	valid[2]	auto[0]	124	1			T8	1		T14	1		T52	5
auto[0]	auto[1]	valid[2]	auto[1]	177	1			T11	1		T27	1		T33	3
auto[0]	auto[1]	valid[3]	auto[0]	121	1			T4	1		T14	1		T52	1
auto[0]	auto[1]	valid[3]	auto[1]	162	1			T14	1		T30	1		T33	1
auto[0]	auto[1]	valid[4]	auto[0]	123	1			T8	1		T11	1		T49	1
auto[0]	auto[1]	valid[4]	auto[1]	179	1			T14	1		T27	1		T30	1
auto[1]	auto[0]	valid[0]	auto[0]	87	1			T11	2		T327	1		T328	4
auto[1]	auto[0]	valid[1]	auto[0]	72	1			T11	1		T14	1		T327	1
auto[1]	auto[0]	valid[2]	auto[0]	88	1			T4	1		T8	1		T52	1
auto[1]	auto[0]	valid[3]	auto[0]	82	1			T14	2		T50	1		T52	2
auto[1]	auto[0]	valid[4]	auto[0]	75	1			T14	2		T52	1		T188	1
auto[1]	auto[1]	valid[0]	auto[0]	65	1			T11	3		T328	1		T63	1
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T4	1		T11	3		T320	1
auto[1]	auto[1]	valid[2]	auto[0]	86	1			T11	2		T320	1		T317	1
auto[1]	auto[1]	valid[3]	auto[0]	82	1			T4	1		T11	3		T14	2
auto[1]	auto[1]	valid[4]	auto[0]	67	1			T50	1		T52	1		T325	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal