Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51741

1

T4

312

T8

196

T11

339

auto[1]

19888

1

T11

90

T14

102

T27

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52683

1

T4

216

T8

116

T11

282

auto[1]

18946

1

T4

96

T8

80

T11

147

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36822	1			T4	168		T8	97		T11	221
others[1]	6044	1			T4	24		T8	20		T11	42
others[2]	5988	1			T4	22		T8	19		T11	35
others[3]	6825	1			T4	21		T8	21		T11	31
interest[1]	3991	1			T4	15		T8	10		T11	27
interest[4]	23998	1			T4	94		T8	61		T11	139
interest[64]	11959	1			T4	62		T8	29		T11	73

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16738	1			T4	114		T8	59		T11	103
auto[0]	auto[0]	others[1]	2799	1			T4	15		T8	9		T11	17
auto[0]	auto[0]	others[2]	2724	1			T4	16		T8	11		T11	14
auto[0]	auto[0]	others[3]	3168	1			T4	14		T8	11		T11	10
auto[0]	auto[0]	interest[1]	1785	1			T4	12		T8	6		T11	13
auto[0]	auto[0]	interest[4]	10878	1			T4	64		T8	36		T11	66
auto[0]	auto[0]	interest[64]	5581	1			T4	45		T8	20		T11	35
auto[0]	auto[1]	others[0]	10337	1			T11	50		T14	53		T27	3
auto[0]	auto[1]	others[1]	1692	1			T11	8		T14	9		T33	12
auto[0]	auto[1]	others[2]	1650	1			T11	9		T14	7		T33	10
auto[0]	auto[1]	others[3]	1895	1			T11	9		T14	9		T33	6
auto[0]	auto[1]	interest[1]	1118	1			T11	5		T14	5		T33	6
auto[0]	auto[1]	interest[4]	6746	1			T11	32		T14	33		T27	3
auto[0]	auto[1]	interest[64]	3196	1			T11	9		T14	19		T33	16
auto[1]	auto[0]	others[0]	9747	1			T4	54		T8	38		T11	68
auto[1]	auto[0]	others[1]	1553	1			T4	9		T8	11		T11	17
auto[1]	auto[0]	others[2]	1614	1			T4	6		T8	8		T11	12
auto[1]	auto[0]	others[3]	1762	1			T4	7		T8	10		T11	12
auto[1]	auto[0]	interest[1]	1088	1			T4	3		T8	4		T11	9
auto[1]	auto[0]	interest[4]	6374	1			T4	30		T8	25		T11	41
auto[1]	auto[0]	interest[64]	3182	1			T4	17		T8	9		T11	29

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal