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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1021 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1462744978 Jun 30 04:56:47 PM PDT 24 Jun 30 04:56:55 PM PDT 24 2145223660 ps
T1022 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1237566667 Jun 30 04:57:09 PM PDT 24 Jun 30 04:57:11 PM PDT 24 41758970 ps
T149 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3032816301 Jun 30 04:56:53 PM PDT 24 Jun 30 04:56:57 PM PDT 24 551859521 ps
T1023 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2738395368 Jun 30 04:56:47 PM PDT 24 Jun 30 04:56:52 PM PDT 24 123239657 ps
T1024 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1557193118 Jun 30 04:57:10 PM PDT 24 Jun 30 04:57:11 PM PDT 24 15022654 ps
T1025 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.543464907 Jun 30 04:56:51 PM PDT 24 Jun 30 04:56:54 PM PDT 24 149894016 ps
T1026 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1547815573 Jun 30 04:57:09 PM PDT 24 Jun 30 04:57:11 PM PDT 24 79967023 ps
T111 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.419529359 Jun 30 04:56:54 PM PDT 24 Jun 30 04:56:57 PM PDT 24 375084726 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1174703146 Jun 30 04:56:44 PM PDT 24 Jun 30 04:57:07 PM PDT 24 993656245 ps
T109 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2561168527 Jun 30 04:57:08 PM PDT 24 Jun 30 04:57:11 PM PDT 24 154960198 ps
T1027 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.403284327 Jun 30 04:56:47 PM PDT 24 Jun 30 04:56:48 PM PDT 24 34454779 ps
T1028 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2513951504 Jun 30 04:57:16 PM PDT 24 Jun 30 04:57:17 PM PDT 24 28929713 ps
T181 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1123563046 Jun 30 04:56:44 PM PDT 24 Jun 30 04:56:52 PM PDT 24 287973404 ps
T1029 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1162818165 Jun 30 04:56:49 PM PDT 24 Jun 30 04:56:52 PM PDT 24 51271427 ps
T1030 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3486307369 Jun 30 04:57:17 PM PDT 24 Jun 30 04:57:18 PM PDT 24 110257749 ps
T130 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.476493249 Jun 30 04:56:42 PM PDT 24 Jun 30 04:56:44 PM PDT 24 106085008 ps
T1031 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.981316618 Jun 30 04:57:10 PM PDT 24 Jun 30 04:57:17 PM PDT 24 415780091 ps
T1032 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1589801879 Jun 30 04:56:43 PM PDT 24 Jun 30 04:56:46 PM PDT 24 176881645 ps
T1033 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2691160196 Jun 30 04:57:01 PM PDT 24 Jun 30 04:57:05 PM PDT 24 129633133 ps
T1034 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4214998253 Jun 30 04:57:08 PM PDT 24 Jun 30 04:57:11 PM PDT 24 239520414 ps
T1035 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3902956788 Jun 30 04:56:55 PM PDT 24 Jun 30 04:56:57 PM PDT 24 19092621 ps
T1036 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3304944314 Jun 30 04:56:41 PM PDT 24 Jun 30 04:56:42 PM PDT 24 16373215 ps
T151 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4124003983 Jun 30 04:56:47 PM PDT 24 Jun 30 04:56:49 PM PDT 24 96743673 ps
T1037 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1562679343 Jun 30 04:57:15 PM PDT 24 Jun 30 04:57:16 PM PDT 24 154257165 ps
T1038 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2494093020 Jun 30 04:57:16 PM PDT 24 Jun 30 04:57:18 PM PDT 24 26986269 ps
T1039 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4284724530 Jun 30 04:56:41 PM PDT 24 Jun 30 04:56:42 PM PDT 24 12016877 ps
T114 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2707191140 Jun 30 04:57:08 PM PDT 24 Jun 30 04:57:11 PM PDT 24 224267849 ps
T1040 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1751040779 Jun 30 04:56:54 PM PDT 24 Jun 30 04:56:56 PM PDT 24 77303066 ps
T150 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2986759624 Jun 30 04:56:54 PM PDT 24 Jun 30 04:57:16 PM PDT 24 4050996669 ps
T1041 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.533890634 Jun 30 04:57:15 PM PDT 24 Jun 30 04:57:16 PM PDT 24 28993145 ps
T1042 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1651744711 Jun 30 04:56:59 PM PDT 24 Jun 30 04:57:03 PM PDT 24 406234158 ps
T1043 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3166876680 Jun 30 04:57:00 PM PDT 24 Jun 30 04:57:05 PM PDT 24 46776678 ps
T1044 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2263648739 Jun 30 04:57:13 PM PDT 24 Jun 30 04:57:14 PM PDT 24 12603270 ps
T1045 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3414721457 Jun 30 04:57:01 PM PDT 24 Jun 30 04:57:05 PM PDT 24 93273739 ps
T1046 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1876796145 Jun 30 04:57:01 PM PDT 24 Jun 30 04:57:05 PM PDT 24 708961248 ps
T180 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2075659332 Jun 30 04:57:02 PM PDT 24 Jun 30 04:57:11 PM PDT 24 2011532812 ps
T1047 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3120205280 Jun 30 04:57:18 PM PDT 24 Jun 30 04:57:20 PM PDT 24 40909335 ps
T87 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3190206827 Jun 30 04:56:41 PM PDT 24 Jun 30 04:56:42 PM PDT 24 41712115 ps
T1048 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1581559131 Jun 30 04:57:16 PM PDT 24 Jun 30 04:57:18 PM PDT 24 53471841 ps
T177 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4167873144 Jun 30 04:56:55 PM PDT 24 Jun 30 04:57:08 PM PDT 24 215046579 ps
T1049 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2872297346 Jun 30 04:57:18 PM PDT 24 Jun 30 04:57:19 PM PDT 24 35851757 ps
T1050 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2106295680 Jun 30 04:57:07 PM PDT 24 Jun 30 04:57:12 PM PDT 24 481014004 ps
T116 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1972458437 Jun 30 04:56:47 PM PDT 24 Jun 30 04:56:52 PM PDT 24 63051801 ps
T1051 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3539123023 Jun 30 04:57:14 PM PDT 24 Jun 30 04:57:15 PM PDT 24 34834559 ps
T1052 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3335520946 Jun 30 04:57:13 PM PDT 24 Jun 30 04:57:15 PM PDT 24 165659490 ps
T110 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.102114726 Jun 30 04:57:07 PM PDT 24 Jun 30 04:57:12 PM PDT 24 184434198 ps
T1053 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.113551344 Jun 30 04:57:22 PM PDT 24 Jun 30 04:57:23 PM PDT 24 13357119 ps
T131 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2818071602 Jun 30 04:56:39 PM PDT 24 Jun 30 04:56:41 PM PDT 24 90400249 ps
T1054 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3783089923 Jun 30 04:57:14 PM PDT 24 Jun 30 04:57:15 PM PDT 24 37773735 ps
T1055 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4105618403 Jun 30 04:57:00 PM PDT 24 Jun 30 04:57:05 PM PDT 24 44182921 ps
T1056 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1045480096 Jun 30 04:56:54 PM PDT 24 Jun 30 04:56:59 PM PDT 24 149167603 ps
T1057 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2001508278 Jun 30 04:56:40 PM PDT 24 Jun 30 04:56:46 PM PDT 24 297309938 ps
T1058 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.833126453 Jun 30 04:57:15 PM PDT 24 Jun 30 04:57:16 PM PDT 24 35449813 ps
T1059 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1936033208 Jun 30 04:57:06 PM PDT 24 Jun 30 04:57:10 PM PDT 24 535807408 ps
T179 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3927329560 Jun 30 04:57:01 PM PDT 24 Jun 30 04:57:10 PM PDT 24 294737580 ps
T175 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.871786467 Jun 30 04:56:59 PM PDT 24 Jun 30 04:57:05 PM PDT 24 822307770 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.706169644 Jun 30 04:56:48 PM PDT 24 Jun 30 04:57:27 PM PDT 24 3600224510 ps
T1061 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2122394961 Jun 30 04:57:08 PM PDT 24 Jun 30 04:57:13 PM PDT 24 164353472 ps
T1062 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3885733704 Jun 30 04:57:16 PM PDT 24 Jun 30 04:57:17 PM PDT 24 15030746 ps
T1063 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2302596211 Jun 30 04:57:22 PM PDT 24 Jun 30 04:57:23 PM PDT 24 19711715 ps
T1064 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.821326428 Jun 30 04:56:49 PM PDT 24 Jun 30 04:56:50 PM PDT 24 15708008 ps
T1065 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.243995042 Jun 30 04:57:01 PM PDT 24 Jun 30 04:57:07 PM PDT 24 270420045 ps
T1066 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1073942838 Jun 30 04:57:00 PM PDT 24 Jun 30 04:57:05 PM PDT 24 860217223 ps
T1067 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1286913664 Jun 30 04:56:48 PM PDT 24 Jun 30 04:56:50 PM PDT 24 31091587 ps
T1068 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3981161529 Jun 30 04:57:20 PM PDT 24 Jun 30 04:57:22 PM PDT 24 16656270 ps
T1069 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1226850403 Jun 30 04:57:01 PM PDT 24 Jun 30 04:57:04 PM PDT 24 13567555 ps
T1070 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2700802926 Jun 30 04:57:00 PM PDT 24 Jun 30 04:57:03 PM PDT 24 14419101 ps
T1071 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2280933506 Jun 30 04:57:00 PM PDT 24 Jun 30 04:57:02 PM PDT 24 11636912 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3442290128 Jun 30 04:56:47 PM PDT 24 Jun 30 04:56:51 PM PDT 24 44138122 ps
T1073 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.792475499 Jun 30 04:57:01 PM PDT 24 Jun 30 04:57:04 PM PDT 24 27424737 ps
T1074 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.929034132 Jun 30 04:56:56 PM PDT 24 Jun 30 04:57:09 PM PDT 24 190846941 ps
T1075 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.48790250 Jun 30 04:57:07 PM PDT 24 Jun 30 04:57:20 PM PDT 24 202622822 ps
T1076 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.567897758 Jun 30 04:56:40 PM PDT 24 Jun 30 04:56:41 PM PDT 24 98177006 ps
T1077 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1551155372 Jun 30 04:57:08 PM PDT 24 Jun 30 04:57:11 PM PDT 24 52681583 ps
T1078 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4166130549 Jun 30 04:57:10 PM PDT 24 Jun 30 04:57:19 PM PDT 24 1142765335 ps
T1079 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.369124739 Jun 30 04:56:53 PM PDT 24 Jun 30 04:56:55 PM PDT 24 121852722 ps
T1080 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1137460640 Jun 30 04:57:18 PM PDT 24 Jun 30 04:57:19 PM PDT 24 16338757 ps
T1081 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.634240897 Jun 30 04:57:18 PM PDT 24 Jun 30 04:57:20 PM PDT 24 11196525 ps
T1082 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1478317052 Jun 30 04:57:08 PM PDT 24 Jun 30 04:57:12 PM PDT 24 40695607 ps
T1083 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2748934520 Jun 30 04:56:48 PM PDT 24 Jun 30 04:57:24 PM PDT 24 1069887325 ps
T1084 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2365027760 Jun 30 04:57:08 PM PDT 24 Jun 30 04:57:10 PM PDT 24 13447484 ps
T88 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.660877648 Jun 30 04:57:00 PM PDT 24 Jun 30 04:57:02 PM PDT 24 214619215 ps
T1085 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1077896805 Jun 30 04:57:09 PM PDT 24 Jun 30 04:57:11 PM PDT 24 256406283 ps
T1086 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.440363201 Jun 30 04:56:48 PM PDT 24 Jun 30 04:56:50 PM PDT 24 244257736 ps
T1087 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3466818902 Jun 30 04:57:02 PM PDT 24 Jun 30 04:57:07 PM PDT 24 424061217 ps
T1088 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2925742183 Jun 30 04:57:00 PM PDT 24 Jun 30 04:57:04 PM PDT 24 887926208 ps
T1089 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2915387806 Jun 30 04:56:54 PM PDT 24 Jun 30 04:56:56 PM PDT 24 14730972 ps
T1090 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2771959918 Jun 30 04:57:11 PM PDT 24 Jun 30 04:57:19 PM PDT 24 301159048 ps
T1091 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2536077726 Jun 30 04:56:49 PM PDT 24 Jun 30 04:56:51 PM PDT 24 12419944 ps
T1092 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.878156346 Jun 30 04:56:41 PM PDT 24 Jun 30 04:56:42 PM PDT 24 13942632 ps
T1093 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1311392437 Jun 30 04:56:56 PM PDT 24 Jun 30 04:56:58 PM PDT 24 28321461 ps
T1094 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2526578328 Jun 30 04:56:48 PM PDT 24 Jun 30 04:57:01 PM PDT 24 938841094 ps
T1095 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3220578535 Jun 30 04:57:09 PM PDT 24 Jun 30 04:57:10 PM PDT 24 20071815 ps
T1096 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3396169762 Jun 30 04:56:59 PM PDT 24 Jun 30 04:57:16 PM PDT 24 1396105279 ps
T1097 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.383971341 Jun 30 04:57:00 PM PDT 24 Jun 30 04:57:02 PM PDT 24 151977708 ps
T1098 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1406678027 Jun 30 04:57:10 PM PDT 24 Jun 30 04:57:15 PM PDT 24 64720797 ps
T1099 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3549221242 Jun 30 04:57:01 PM PDT 24 Jun 30 04:57:05 PM PDT 24 164299210 ps
T1100 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.623718265 Jun 30 04:56:47 PM PDT 24 Jun 30 04:56:49 PM PDT 24 36253992 ps
T1101 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1044090574 Jun 30 04:57:10 PM PDT 24 Jun 30 04:57:13 PM PDT 24 99108946 ps
T1102 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.852232627 Jun 30 04:57:01 PM PDT 24 Jun 30 04:57:04 PM PDT 24 27594066 ps
T1103 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.420144506 Jun 30 04:56:49 PM PDT 24 Jun 30 04:56:52 PM PDT 24 234305487 ps
T182 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2155646206 Jun 30 04:57:03 PM PDT 24 Jun 30 04:57:26 PM PDT 24 944136748 ps
T1104 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.804711030 Jun 30 04:57:15 PM PDT 24 Jun 30 04:57:17 PM PDT 24 17890521 ps
T1105 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4004900371 Jun 30 04:57:02 PM PDT 24 Jun 30 04:57:06 PM PDT 24 119608614 ps
T1106 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2531546689 Jun 30 04:57:13 PM PDT 24 Jun 30 04:57:16 PM PDT 24 118106482 ps
T1107 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.122325352 Jun 30 04:56:48 PM PDT 24 Jun 30 04:56:52 PM PDT 24 70825152 ps
T1108 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4006841142 Jun 30 04:57:02 PM PDT 24 Jun 30 04:57:06 PM PDT 24 143528917 ps
T1109 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3909492447 Jun 30 04:57:18 PM PDT 24 Jun 30 04:57:19 PM PDT 24 44686236 ps
T1110 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2133618175 Jun 30 04:56:53 PM PDT 24 Jun 30 04:57:01 PM PDT 24 2861816849 ps
T1111 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3509159469 Jun 30 04:56:47 PM PDT 24 Jun 30 04:56:48 PM PDT 24 42425950 ps
T1112 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3712985701 Jun 30 04:56:47 PM PDT 24 Jun 30 04:56:49 PM PDT 24 88996686 ps
T1113 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.400589049 Jun 30 04:56:57 PM PDT 24 Jun 30 04:57:06 PM PDT 24 406547777 ps
T1114 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2319203730 Jun 30 04:57:07 PM PDT 24 Jun 30 04:57:09 PM PDT 24 75322576 ps
T1115 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2362660343 Jun 30 04:57:01 PM PDT 24 Jun 30 04:57:05 PM PDT 24 262606339 ps
T1116 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3553769372 Jun 30 04:57:12 PM PDT 24 Jun 30 04:57:15 PM PDT 24 80294744 ps
T1117 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3338005300 Jun 30 04:57:02 PM PDT 24 Jun 30 04:57:05 PM PDT 24 24301108 ps
T1118 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3216434274 Jun 30 04:57:18 PM PDT 24 Jun 30 04:57:19 PM PDT 24 59035635 ps
T1119 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1916896668 Jun 30 04:56:54 PM PDT 24 Jun 30 04:56:58 PM PDT 24 96814672 ps
T1120 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.186286060 Jun 30 04:57:10 PM PDT 24 Jun 30 04:57:14 PM PDT 24 142261007 ps
T1121 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.108180542 Jun 30 04:57:08 PM PDT 24 Jun 30 04:57:10 PM PDT 24 55727253 ps
T1122 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.42124240 Jun 30 04:56:54 PM PDT 24 Jun 30 04:56:58 PM PDT 24 332685674 ps
T1123 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3878162411 Jun 30 04:57:07 PM PDT 24 Jun 30 04:57:12 PM PDT 24 529826160 ps
T1124 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4057944926 Jun 30 04:57:00 PM PDT 24 Jun 30 04:57:03 PM PDT 24 29505651 ps
T1125 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3400945052 Jun 30 04:56:50 PM PDT 24 Jun 30 04:56:59 PM PDT 24 631871907 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2651884744 Jun 30 04:56:41 PM PDT 24 Jun 30 04:56:43 PM PDT 24 75113794 ps
T1127 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3263500429 Jun 30 04:57:16 PM PDT 24 Jun 30 04:57:17 PM PDT 24 37669652 ps
T1128 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3432880794 Jun 30 04:57:00 PM PDT 24 Jun 30 04:57:04 PM PDT 24 111739365 ps
T178 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3084901244 Jun 30 04:57:08 PM PDT 24 Jun 30 04:57:21 PM PDT 24 200282359 ps
T1129 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3373390217 Jun 30 04:57:10 PM PDT 24 Jun 30 04:57:11 PM PDT 24 17050999 ps
T1130 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1232339178 Jun 30 04:56:54 PM PDT 24 Jun 30 04:56:58 PM PDT 24 196747270 ps

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1747922238
Short name T4
Test name
Test status
Simulation time 108365708407 ps
CPU time 246.47 seconds
Started Jun 30 05:29:50 PM PDT 24
Finished Jun 30 05:33:57 PM PDT 24
Peak memory 266720 kb
Host smart-4257752d-3a03-45fc-9ee4-782f0db5387b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747922238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1747922238
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.345700511
Short name T14
Test name
Test status
Simulation time 15023799474 ps
CPU time 98.03 seconds
Started Jun 30 05:32:09 PM PDT 24
Finished Jun 30 05:33:47 PM PDT 24
Peak memory 265644 kb
Host smart-d35ac3a6-7fcc-43d8-859d-9cf3ebf70bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345700511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.345700511
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1760571079
Short name T98
Test name
Test status
Simulation time 3760336697 ps
CPU time 13.44 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:23 PM PDT 24
Peak memory 215200 kb
Host smart-1d81d2b2-99d7-43b1-85eb-a492a063458d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760571079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1760571079
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1017957372
Short name T17
Test name
Test status
Simulation time 36857407367 ps
CPU time 519.29 seconds
Started Jun 30 05:32:36 PM PDT 24
Finished Jun 30 05:41:15 PM PDT 24
Peak memory 296532 kb
Host smart-3e9c3beb-1dbd-470c-a2e3-ef3ec1fbe5eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017957372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1017957372
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3860209133
Short name T21
Test name
Test status
Simulation time 70593233349 ps
CPU time 266.49 seconds
Started Jun 30 05:30:44 PM PDT 24
Finished Jun 30 05:35:12 PM PDT 24
Peak memory 273560 kb
Host smart-bd7bdcc9-331f-4227-8711-5c340c64486b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860209133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3860209133
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2883387925
Short name T71
Test name
Test status
Simulation time 18593500 ps
CPU time 0.75 seconds
Started Jun 30 05:29:19 PM PDT 24
Finished Jun 30 05:29:20 PM PDT 24
Peak memory 216628 kb
Host smart-bb076d2e-ed8f-4310-8ef9-cd9fefa3b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883387925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2883387925
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3012308634
Short name T84
Test name
Test status
Simulation time 7897154050 ps
CPU time 47.59 seconds
Started Jun 30 05:32:44 PM PDT 24
Finished Jun 30 05:33:33 PM PDT 24
Peak memory 257672 kb
Host smart-0b14684d-5577-4f4e-bbc5-4a8dd1d72c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012308634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3012308634
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.273110501
Short name T189
Test name
Test status
Simulation time 315716413726 ps
CPU time 347.97 seconds
Started Jun 30 05:32:39 PM PDT 24
Finished Jun 30 05:38:27 PM PDT 24
Peak memory 252856 kb
Host smart-35e24428-eb70-424b-a17f-e4d3437edf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273110501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.273110501
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2415867805
Short name T107
Test name
Test status
Simulation time 245627781 ps
CPU time 4.19 seconds
Started Jun 30 04:56:59 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 215512 kb
Host smart-3a9b8477-99e1-4df4-93d5-3239c9ed8a11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415867805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2415867805
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3175274048
Short name T404
Test name
Test status
Simulation time 12842547924 ps
CPU time 37.11 seconds
Started Jun 30 05:30:48 PM PDT 24
Finished Jun 30 05:31:26 PM PDT 24
Peak memory 216948 kb
Host smart-96d9aeba-715c-4c91-ab29-f5bd32b730c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175274048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3175274048
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3319962472
Short name T192
Test name
Test status
Simulation time 4352532537 ps
CPU time 94.98 seconds
Started Jun 30 05:30:44 PM PDT 24
Finished Jun 30 05:32:20 PM PDT 24
Peak memory 268632 kb
Host smart-5a1c684d-b63f-4a5e-9eb3-df74941d1c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319962472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3319962472
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.750397992
Short name T29
Test name
Test status
Simulation time 16708094 ps
CPU time 0.77 seconds
Started Jun 30 05:29:27 PM PDT 24
Finished Jun 30 05:29:28 PM PDT 24
Peak memory 205936 kb
Host smart-d1c750f1-90da-4576-8986-c7f98747513b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750397992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.750397992
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.432722605
Short name T48
Test name
Test status
Simulation time 36984293506 ps
CPU time 290.9 seconds
Started Jun 30 05:32:23 PM PDT 24
Finished Jun 30 05:37:14 PM PDT 24
Peak memory 251088 kb
Host smart-b97198bf-fd5f-4475-a710-46086268873a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432722605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.432722605
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2126819554
Short name T42
Test name
Test status
Simulation time 317659555 ps
CPU time 3.87 seconds
Started Jun 30 05:31:11 PM PDT 24
Finished Jun 30 05:31:15 PM PDT 24
Peak memory 219752 kb
Host smart-c215961f-8b8d-421f-b0f2-ce67a2d98417
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2126819554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2126819554
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2173373200
Short name T191
Test name
Test status
Simulation time 135845619386 ps
CPU time 449.81 seconds
Started Jun 30 05:29:58 PM PDT 24
Finished Jun 30 05:37:29 PM PDT 24
Peak memory 264492 kb
Host smart-812659c3-8f41-49dd-b322-4a16fed5d4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173373200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2173373200
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1687138193
Short name T55
Test name
Test status
Simulation time 5489882914 ps
CPU time 95.5 seconds
Started Jun 30 05:32:59 PM PDT 24
Finished Jun 30 05:34:35 PM PDT 24
Peak memory 249788 kb
Host smart-c3815e2c-2029-4e2c-8293-1117641fc36c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687138193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1687138193
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.754883295
Short name T126
Test name
Test status
Simulation time 1168590983 ps
CPU time 20.11 seconds
Started Jun 30 04:56:41 PM PDT 24
Finished Jun 30 04:57:01 PM PDT 24
Peak memory 215348 kb
Host smart-3bcb4258-9b53-44f2-bf53-896b10a3c645
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754883295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.754883295
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3304090364
Short name T9
Test name
Test status
Simulation time 28977068780 ps
CPU time 123.7 seconds
Started Jun 30 05:31:56 PM PDT 24
Finished Jun 30 05:34:00 PM PDT 24
Peak memory 257164 kb
Host smart-252d8542-2d8a-4ad0-aa4a-33112efd1a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304090364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3304090364
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.301835347
Short name T201
Test name
Test status
Simulation time 334141502667 ps
CPU time 662.56 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:41:53 PM PDT 24
Peak memory 268616 kb
Host smart-e7fa9944-a017-490b-97c7-6ed4f58ad8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301835347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.301835347
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1975834551
Short name T11
Test name
Test status
Simulation time 4290517069 ps
CPU time 29.27 seconds
Started Jun 30 05:33:08 PM PDT 24
Finished Jun 30 05:33:37 PM PDT 24
Peak memory 217040 kb
Host smart-0694833c-a6b1-4ffa-b83b-e13c4f3f1c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975834551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1975834551
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3513864508
Short name T275
Test name
Test status
Simulation time 232037945731 ps
CPU time 437.2 seconds
Started Jun 30 05:33:02 PM PDT 24
Finished Jun 30 05:40:20 PM PDT 24
Peak memory 268928 kb
Host smart-c2e508ac-e979-4c7c-84b8-f0137e1ca527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513864508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3513864508
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1208450880
Short name T72
Test name
Test status
Simulation time 73795489 ps
CPU time 1.1 seconds
Started Jun 30 05:29:21 PM PDT 24
Finished Jun 30 05:29:23 PM PDT 24
Peak memory 236368 kb
Host smart-6a3ff886-1539-4993-8146-2a0575246b1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208450880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1208450880
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3270558818
Short name T241
Test name
Test status
Simulation time 154328149568 ps
CPU time 649.14 seconds
Started Jun 30 05:32:02 PM PDT 24
Finished Jun 30 05:42:52 PM PDT 24
Peak memory 273644 kb
Host smart-e75713df-bc7e-4772-af51-bd1fdc6581f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270558818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3270558818
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.703670594
Short name T46
Test name
Test status
Simulation time 99757498131 ps
CPU time 343.81 seconds
Started Jun 30 05:30:01 PM PDT 24
Finished Jun 30 05:35:45 PM PDT 24
Peak memory 257888 kb
Host smart-d5dbff58-c105-4f38-9451-5e29f3aa5ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703670594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.703670594
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2776020683
Short name T39
Test name
Test status
Simulation time 68339581551 ps
CPU time 481.57 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:37:53 PM PDT 24
Peak memory 255660 kb
Host smart-004dbbdc-febf-41b3-8647-595b78f3d1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776020683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2776020683
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1992976489
Short name T100
Test name
Test status
Simulation time 293365845 ps
CPU time 13 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:14 PM PDT 24
Peak memory 215184 kb
Host smart-c7cfe0d9-d73b-42f4-bc55-0122c84f1d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992976489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1992976489
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3913379532
Short name T85
Test name
Test status
Simulation time 32698587431 ps
CPU time 317.33 seconds
Started Jun 30 05:30:32 PM PDT 24
Finished Jun 30 05:35:49 PM PDT 24
Peak memory 252340 kb
Host smart-642fc7da-ed3b-421d-b1f2-63da210c81c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913379532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3913379532
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1696807588
Short name T321
Test name
Test status
Simulation time 8576244348 ps
CPU time 58.49 seconds
Started Jun 30 05:32:05 PM PDT 24
Finished Jun 30 05:33:04 PM PDT 24
Peak memory 225436 kb
Host smart-d72b01f8-92ee-44a0-aff3-57846907d034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696807588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1696807588
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.102114726
Short name T110
Test name
Test status
Simulation time 184434198 ps
CPU time 4.14 seconds
Started Jun 30 04:57:07 PM PDT 24
Finished Jun 30 04:57:12 PM PDT 24
Peak memory 215320 kb
Host smart-c7fb0dfe-75e8-4330-85bf-ec7e14a96422
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102114726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.102114726
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2459317404
Short name T315
Test name
Test status
Simulation time 751526027 ps
CPU time 13.22 seconds
Started Jun 30 05:30:00 PM PDT 24
Finished Jun 30 05:30:14 PM PDT 24
Peak memory 225032 kb
Host smart-9ca6e1ee-95cb-45ca-9858-ca7ae24af778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459317404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2459317404
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.233224687
Short name T278
Test name
Test status
Simulation time 6144085943 ps
CPU time 145.29 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:32:31 PM PDT 24
Peak memory 282652 kb
Host smart-14419595-0a03-4cec-bca4-db0b14151393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233224687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.233224687
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1452908759
Short name T343
Test name
Test status
Simulation time 5946243593 ps
CPU time 16.31 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:31:07 PM PDT 24
Peak memory 216884 kb
Host smart-153d572d-3daa-4d55-a4c3-40f473dc2a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452908759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1452908759
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2914456618
Short name T169
Test name
Test status
Simulation time 14757642995 ps
CPU time 145.58 seconds
Started Jun 30 05:29:27 PM PDT 24
Finished Jun 30 05:31:53 PM PDT 24
Peak memory 253308 kb
Host smart-478c13ee-ede4-4790-9126-4c3aeaebeb6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914456618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2914456618
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3041671601
Short name T313
Test name
Test status
Simulation time 390370731 ps
CPU time 11.08 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:30:17 PM PDT 24
Peak memory 233220 kb
Host smart-037f1544-4375-4f88-a018-3c3319278d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041671601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3041671601
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.383196811
Short name T49
Test name
Test status
Simulation time 173961595636 ps
CPU time 431.17 seconds
Started Jun 30 05:33:01 PM PDT 24
Finished Jun 30 05:40:13 PM PDT 24
Peak memory 257268 kb
Host smart-7275cbb8-6e7a-42c3-a1bc-98ef151138c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383196811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.383196811
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3084901244
Short name T178
Test name
Test status
Simulation time 200282359 ps
CPU time 12.63 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:21 PM PDT 24
Peak memory 215268 kb
Host smart-798c2c4e-2c0e-4fa0-a183-b6c3da8f5123
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084901244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3084901244
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2106913293
Short name T196
Test name
Test status
Simulation time 118859981643 ps
CPU time 314.58 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:37:03 PM PDT 24
Peak memory 269056 kb
Host smart-822fc590-77e6-410a-8174-94e1aa7ee568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106913293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2106913293
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3947681408
Short name T295
Test name
Test status
Simulation time 7005195870 ps
CPU time 46.38 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:32:35 PM PDT 24
Peak memory 249688 kb
Host smart-df81df91-7085-421a-9003-28f2903c2977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947681408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3947681408
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1854316737
Short name T19
Test name
Test status
Simulation time 1998736797 ps
CPU time 31.18 seconds
Started Jun 30 05:32:37 PM PDT 24
Finished Jun 30 05:33:09 PM PDT 24
Peak memory 225104 kb
Host smart-505ca135-2e70-4d9b-b47c-4a1dbd0da3fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854316737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1854316737
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4193380737
Short name T280
Test name
Test status
Simulation time 85965290036 ps
CPU time 853.29 seconds
Started Jun 30 05:29:45 PM PDT 24
Finished Jun 30 05:43:59 PM PDT 24
Peak memory 273100 kb
Host smart-3a90a722-d22e-4890-b0e7-41de0b7f0389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193380737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4193380737
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.926732773
Short name T307
Test name
Test status
Simulation time 1913434350 ps
CPU time 11.24 seconds
Started Jun 30 05:29:59 PM PDT 24
Finished Jun 30 05:30:12 PM PDT 24
Peak memory 233812 kb
Host smart-1ba61677-8578-4ba8-a637-c55040bf20ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926732773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.926732773
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1599356913
Short name T209
Test name
Test status
Simulation time 1019152999 ps
CPU time 10.36 seconds
Started Jun 30 05:30:34 PM PDT 24
Finished Jun 30 05:30:44 PM PDT 24
Peak memory 233264 kb
Host smart-d184205e-1707-443e-921c-57d721476619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599356913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1599356913
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.347172203
Short name T792
Test name
Test status
Simulation time 3470766545 ps
CPU time 71.16 seconds
Started Jun 30 05:30:20 PM PDT 24
Finished Jun 30 05:31:32 PM PDT 24
Peak memory 252196 kb
Host smart-68c854a6-40e1-4f58-8287-2c779a8ac887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347172203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.347172203
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.744231527
Short name T227
Test name
Test status
Simulation time 16644725022 ps
CPU time 184.53 seconds
Started Jun 30 05:30:51 PM PDT 24
Finished Jun 30 05:33:57 PM PDT 24
Peak memory 251028 kb
Host smart-09cee2cb-2e3a-47ee-adaf-26dd0335664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744231527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.744231527
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2839316621
Short name T215
Test name
Test status
Simulation time 142231007123 ps
CPU time 413.92 seconds
Started Jun 30 05:30:00 PM PDT 24
Finished Jun 30 05:36:55 PM PDT 24
Peak memory 266332 kb
Host smart-5dfc1960-a0f8-4eb9-91f0-9d91fcb8cc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839316621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2839316621
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3190206827
Short name T87
Test name
Test status
Simulation time 41712115 ps
CPU time 1.34 seconds
Started Jun 30 04:56:41 PM PDT 24
Finished Jun 30 04:56:42 PM PDT 24
Peak memory 207140 kb
Host smart-b128436c-6bb0-4f35-8d4b-b83b6d1eb0d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190206827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3190206827
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2001508278
Short name T1057
Test name
Test status
Simulation time 297309938 ps
CPU time 5.61 seconds
Started Jun 30 04:56:40 PM PDT 24
Finished Jun 30 04:56:46 PM PDT 24
Peak memory 215504 kb
Host smart-32c3cc2b-443f-4cd2-be46-04e5d82fe10b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001508278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
001508278
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1848054971
Short name T807
Test name
Test status
Simulation time 13660736357 ps
CPU time 137.37 seconds
Started Jun 30 05:30:01 PM PDT 24
Finished Jun 30 05:32:19 PM PDT 24
Peak memory 251596 kb
Host smart-2cd227c5-5cb8-404a-b373-5cccfd34df53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848054971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1848054971
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2960789367
Short name T1004
Test name
Test status
Simulation time 123103271 ps
CPU time 7.6 seconds
Started Jun 30 04:56:41 PM PDT 24
Finished Jun 30 04:56:49 PM PDT 24
Peak memory 215380 kb
Host smart-6176252f-1a4c-4f26-afe4-448b2f3c8b14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960789367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2960789367
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.886429631
Short name T1017
Test name
Test status
Simulation time 7239744104 ps
CPU time 36.22 seconds
Started Jun 30 04:56:43 PM PDT 24
Finished Jun 30 04:57:19 PM PDT 24
Peak memory 207224 kb
Host smart-7c6605c0-2c44-4150-86bf-0d570d0ef4d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886429631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.886429631
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1589801879
Short name T1032
Test name
Test status
Simulation time 176881645 ps
CPU time 2.59 seconds
Started Jun 30 04:56:43 PM PDT 24
Finished Jun 30 04:56:46 PM PDT 24
Peak memory 217260 kb
Host smart-b193bb27-fb70-484f-aaef-67737cb8bd39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589801879 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1589801879
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2818071602
Short name T131
Test name
Test status
Simulation time 90400249 ps
CPU time 1.92 seconds
Started Jun 30 04:56:39 PM PDT 24
Finished Jun 30 04:56:41 PM PDT 24
Peak memory 215352 kb
Host smart-30d2eac9-e88a-4890-8888-cf6d11cffb5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818071602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
818071602
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3304944314
Short name T1036
Test name
Test status
Simulation time 16373215 ps
CPU time 0.7 seconds
Started Jun 30 04:56:41 PM PDT 24
Finished Jun 30 04:56:42 PM PDT 24
Peak memory 203996 kb
Host smart-1905d53b-b016-456f-bae1-1ff32e9072a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304944314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
304944314
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.956985929
Short name T120
Test name
Test status
Simulation time 118413414 ps
CPU time 2.05 seconds
Started Jun 30 04:56:43 PM PDT 24
Finished Jun 30 04:56:46 PM PDT 24
Peak memory 215292 kb
Host smart-859c4bc9-64b6-4e09-b13b-45bf8fc7297b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956985929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.956985929
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4284724530
Short name T1039
Test name
Test status
Simulation time 12016877 ps
CPU time 0.66 seconds
Started Jun 30 04:56:41 PM PDT 24
Finished Jun 30 04:56:42 PM PDT 24
Peak memory 204052 kb
Host smart-dd501bfd-a072-4117-ba75-bd2f8c71394a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284724530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4284724530
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1956525843
Short name T1016
Test name
Test status
Simulation time 84030269 ps
CPU time 1.63 seconds
Started Jun 30 04:56:40 PM PDT 24
Finished Jun 30 04:56:42 PM PDT 24
Peak memory 215344 kb
Host smart-a9d0152b-d93a-4c8c-90b8-83176fc6bc11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956525843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1956525843
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1174703146
Short name T112
Test name
Test status
Simulation time 993656245 ps
CPU time 22.23 seconds
Started Jun 30 04:56:44 PM PDT 24
Finished Jun 30 04:57:07 PM PDT 24
Peak memory 215168 kb
Host smart-00096f07-0ec6-415b-a4ff-b21db91c9bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174703146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1174703146
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3124347867
Short name T123
Test name
Test status
Simulation time 524779085 ps
CPU time 32.45 seconds
Started Jun 30 04:56:44 PM PDT 24
Finished Jun 30 04:57:17 PM PDT 24
Peak memory 215168 kb
Host smart-de5933e6-28b5-471f-b76f-3d0b787ed54b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124347867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3124347867
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3766819328
Short name T86
Test name
Test status
Simulation time 44870345 ps
CPU time 1.34 seconds
Started Jun 30 04:56:40 PM PDT 24
Finished Jun 30 04:56:42 PM PDT 24
Peak memory 216376 kb
Host smart-05abaf59-48b0-444e-8831-f8ea64670a53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766819328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3766819328
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1162818165
Short name T1029
Test name
Test status
Simulation time 51271427 ps
CPU time 1.79 seconds
Started Jun 30 04:56:49 PM PDT 24
Finished Jun 30 04:56:52 PM PDT 24
Peak memory 215504 kb
Host smart-a91bc02e-4c9c-4e75-84ce-79e09b3e1ef9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162818165 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1162818165
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.476493249
Short name T130
Test name
Test status
Simulation time 106085008 ps
CPU time 1.79 seconds
Started Jun 30 04:56:42 PM PDT 24
Finished Jun 30 04:56:44 PM PDT 24
Peak memory 207092 kb
Host smart-4b449a87-c1e9-443c-b175-5a9773ed96aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476493249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.476493249
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.878156346
Short name T1092
Test name
Test status
Simulation time 13942632 ps
CPU time 0.73 seconds
Started Jun 30 04:56:41 PM PDT 24
Finished Jun 30 04:56:42 PM PDT 24
Peak memory 203756 kb
Host smart-843bddb1-2fc9-4e58-9106-b28ea00ca7d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878156346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.878156346
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2651884744
Short name T1126
Test name
Test status
Simulation time 75113794 ps
CPU time 1.72 seconds
Started Jun 30 04:56:41 PM PDT 24
Finished Jun 30 04:56:43 PM PDT 24
Peak memory 215260 kb
Host smart-0d585091-7af6-402b-9ff1-4cbb87dc4024
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651884744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2651884744
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.567897758
Short name T1076
Test name
Test status
Simulation time 98177006 ps
CPU time 0.67 seconds
Started Jun 30 04:56:40 PM PDT 24
Finished Jun 30 04:56:41 PM PDT 24
Peak memory 204040 kb
Host smart-808065eb-37f6-4214-a8f2-0486ed43a666
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567897758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.567897758
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2738395368
Short name T1023
Test name
Test status
Simulation time 123239657 ps
CPU time 4.14 seconds
Started Jun 30 04:56:47 PM PDT 24
Finished Jun 30 04:56:52 PM PDT 24
Peak memory 215284 kb
Host smart-1ed04ff4-3325-4a4f-baf1-8eb31399426b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738395368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2738395368
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3519283582
Short name T108
Test name
Test status
Simulation time 183089176 ps
CPU time 1.4 seconds
Started Jun 30 04:56:42 PM PDT 24
Finished Jun 30 04:56:44 PM PDT 24
Peak memory 215544 kb
Host smart-14bcf6be-11d7-4ef4-a3cd-4171428c6809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519283582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
519283582
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1123563046
Short name T181
Test name
Test status
Simulation time 287973404 ps
CPU time 7.54 seconds
Started Jun 30 04:56:44 PM PDT 24
Finished Jun 30 04:56:52 PM PDT 24
Peak memory 215228 kb
Host smart-2139d219-a5bc-483f-b354-19a35f13c8ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123563046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1123563046
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3466818902
Short name T1087
Test name
Test status
Simulation time 424061217 ps
CPU time 2.84 seconds
Started Jun 30 04:57:02 PM PDT 24
Finished Jun 30 04:57:07 PM PDT 24
Peak memory 216868 kb
Host smart-2e56e649-b946-41a0-a945-dab56bc063ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466818902 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3466818902
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4004900371
Short name T1105
Test name
Test status
Simulation time 119608614 ps
CPU time 2.14 seconds
Started Jun 30 04:57:02 PM PDT 24
Finished Jun 30 04:57:06 PM PDT 24
Peak memory 215332 kb
Host smart-f3e05cc6-f1bb-4d94-9df3-850d6a7a3378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004900371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4004900371
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2280933506
Short name T1071
Test name
Test status
Simulation time 11636912 ps
CPU time 0.74 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:02 PM PDT 24
Peak memory 203768 kb
Host smart-b222530d-59ed-47c5-a346-a80d59113965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280933506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2280933506
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2925742183
Short name T1088
Test name
Test status
Simulation time 887926208 ps
CPU time 1.99 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 215600 kb
Host smart-26beb3e7-7e26-4bd6-9f00-2f362a8ed6f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925742183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2925742183
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4105618403
Short name T1055
Test name
Test status
Simulation time 44182921 ps
CPU time 2.92 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 215468 kb
Host smart-b76558f7-8de9-4694-8b5e-fad0d663e4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105618403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4105618403
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3927329560
Short name T179
Test name
Test status
Simulation time 294737580 ps
CPU time 7.13 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:10 PM PDT 24
Peak memory 215420 kb
Host smart-534d1e5a-01f8-4a5f-8574-81ac2485be91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927329560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3927329560
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1923001646
Short name T113
Test name
Test status
Simulation time 775224854 ps
CPU time 2.62 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 216316 kb
Host smart-f2c8cf1f-3d19-4660-8bd1-3c2c508f9dd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923001646 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1923001646
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1073942838
Short name T1066
Test name
Test status
Simulation time 860217223 ps
CPU time 2.49 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 215280 kb
Host smart-4dc9b7d7-87ef-428f-9e58-ade9a6efac6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073942838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1073942838
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.852232627
Short name T1102
Test name
Test status
Simulation time 27594066 ps
CPU time 0.81 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 203804 kb
Host smart-5216d26f-d8a5-4540-bca1-863617d33dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852232627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.852232627
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.81571585
Short name T1009
Test name
Test status
Simulation time 56223825 ps
CPU time 1.68 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 216548 kb
Host smart-3873ee62-8ef5-4a7b-916e-db91e64075e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81571585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sp
i_device_same_csr_outstanding.81571585
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.551636999
Short name T101
Test name
Test status
Simulation time 7334368774 ps
CPU time 22.79 seconds
Started Jun 30 04:57:02 PM PDT 24
Finished Jun 30 04:57:26 PM PDT 24
Peak memory 215352 kb
Host smart-89095161-b0fa-46fe-98cb-35e4d77ec876
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551636999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.551636999
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.321603800
Short name T115
Test name
Test status
Simulation time 602742828 ps
CPU time 3.93 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:07 PM PDT 24
Peak memory 217748 kb
Host smart-7a1f5db4-1754-410d-83dd-05e1b3e1be0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321603800 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.321603800
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4057944926
Short name T1124
Test name
Test status
Simulation time 29505651 ps
CPU time 2.02 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:03 PM PDT 24
Peak memory 207152 kb
Host smart-e90181f0-983b-4847-8732-d14ea02a79db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057944926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4057944926
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1881060432
Short name T1014
Test name
Test status
Simulation time 51645102 ps
CPU time 0.73 seconds
Started Jun 30 04:56:59 PM PDT 24
Finished Jun 30 04:57:01 PM PDT 24
Peak memory 204128 kb
Host smart-8f79c2fc-70b9-44c7-8fd1-dcf28f2f371d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881060432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1881060432
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3338005300
Short name T1117
Test name
Test status
Simulation time 24301108 ps
CPU time 1.62 seconds
Started Jun 30 04:57:02 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 215204 kb
Host smart-2d604b74-5a7d-465f-a667-7b97b7d34bd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338005300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3338005300
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2362660343
Short name T1115
Test name
Test status
Simulation time 262606339 ps
CPU time 2.29 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 215808 kb
Host smart-47a7dc61-15fe-4c67-b644-e90741d3630a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362660343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2362660343
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2155646206
Short name T182
Test name
Test status
Simulation time 944136748 ps
CPU time 21.75 seconds
Started Jun 30 04:57:03 PM PDT 24
Finished Jun 30 04:57:26 PM PDT 24
Peak memory 215380 kb
Host smart-ac4dde8a-33d4-4f16-bc63-6edb12dd47cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155646206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2155646206
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3549221242
Short name T1099
Test name
Test status
Simulation time 164299210 ps
CPU time 1.54 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 215524 kb
Host smart-adf33ab9-645a-4082-9fa7-1830cc7c3f5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549221242 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3549221242
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2823737180
Short name T125
Test name
Test status
Simulation time 55145919 ps
CPU time 2.67 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 215244 kb
Host smart-3f67e890-5a1b-4d32-ab44-d00551d34275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823737180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2823737180
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2700802926
Short name T1070
Test name
Test status
Simulation time 14419101 ps
CPU time 0.75 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:03 PM PDT 24
Peak memory 204128 kb
Host smart-511587ed-3b56-4a3b-bb03-26a3a075f565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700802926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2700802926
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1975126058
Short name T1012
Test name
Test status
Simulation time 48710894 ps
CPU time 2.85 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:06 PM PDT 24
Peak memory 215356 kb
Host smart-50824a3b-082c-44c6-b5a7-f716b04ae5d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975126058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1975126058
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4006841142
Short name T1108
Test name
Test status
Simulation time 143528917 ps
CPU time 2.22 seconds
Started Jun 30 04:57:02 PM PDT 24
Finished Jun 30 04:57:06 PM PDT 24
Peak memory 215484 kb
Host smart-963d6a10-de37-44ca-9276-1ad9d4a2ebfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006841142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4006841142
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2075659332
Short name T180
Test name
Test status
Simulation time 2011532812 ps
CPU time 7.56 seconds
Started Jun 30 04:57:02 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 215688 kb
Host smart-beb42cdf-cb9e-48dc-a7b3-b9c9b323c51c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075659332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2075659332
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2122394961
Short name T1061
Test name
Test status
Simulation time 164353472 ps
CPU time 4.07 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:13 PM PDT 24
Peak memory 217964 kb
Host smart-3a3b0841-90df-4bd6-8890-f28f69c96c92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122394961 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2122394961
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1547815573
Short name T1026
Test name
Test status
Simulation time 79967023 ps
CPU time 1.2 seconds
Started Jun 30 04:57:09 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 215248 kb
Host smart-9b7d21c2-40c0-4b59-bf79-6d0533af702d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547815573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1547815573
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3220578535
Short name T1095
Test name
Test status
Simulation time 20071815 ps
CPU time 0.68 seconds
Started Jun 30 04:57:09 PM PDT 24
Finished Jun 30 04:57:10 PM PDT 24
Peak memory 204116 kb
Host smart-9132d257-c06d-4119-85ad-559ddb2489ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220578535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3220578535
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1551155372
Short name T1077
Test name
Test status
Simulation time 52681583 ps
CPU time 1.87 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 207064 kb
Host smart-bc474c8a-0a76-4dd2-877b-99022011ef99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551155372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1551155372
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2319203730
Short name T1114
Test name
Test status
Simulation time 75322576 ps
CPU time 1.98 seconds
Started Jun 30 04:57:07 PM PDT 24
Finished Jun 30 04:57:09 PM PDT 24
Peak memory 215500 kb
Host smart-c865d94a-d4e6-41d3-b6db-683561e8b869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319203730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2319203730
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2771959918
Short name T1090
Test name
Test status
Simulation time 301159048 ps
CPU time 7 seconds
Started Jun 30 04:57:11 PM PDT 24
Finished Jun 30 04:57:19 PM PDT 24
Peak memory 215184 kb
Host smart-6485e04e-d46e-49dd-9a3c-55c89f4faea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771959918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2771959918
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1077896805
Short name T1085
Test name
Test status
Simulation time 256406283 ps
CPU time 1.77 seconds
Started Jun 30 04:57:09 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 215360 kb
Host smart-4248f51b-4d90-429d-83f8-0eb93657e91a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077896805 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1077896805
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3326916176
Short name T127
Test name
Test status
Simulation time 56289345 ps
CPU time 1.17 seconds
Started Jun 30 04:57:07 PM PDT 24
Finished Jun 30 04:57:08 PM PDT 24
Peak memory 207144 kb
Host smart-8f3ec69c-8920-4fba-80e6-4ceb1ea6307e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326916176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3326916176
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2820572117
Short name T1003
Test name
Test status
Simulation time 15660610 ps
CPU time 0.76 seconds
Started Jun 30 04:57:09 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 203712 kb
Host smart-47f254e9-d90f-4f75-b4c0-40ecb8188d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820572117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2820572117
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3878162411
Short name T1123
Test name
Test status
Simulation time 529826160 ps
CPU time 4.24 seconds
Started Jun 30 04:57:07 PM PDT 24
Finished Jun 30 04:57:12 PM PDT 24
Peak memory 215276 kb
Host smart-6f8941fe-7457-467c-9d67-dbb3d6c06472
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878162411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3878162411
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2045864739
Short name T69
Test name
Test status
Simulation time 391145406 ps
CPU time 4.45 seconds
Started Jun 30 04:57:12 PM PDT 24
Finished Jun 30 04:57:17 PM PDT 24
Peak memory 216464 kb
Host smart-3631a7bd-7ec7-4f23-8752-dac8b608ea98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045864739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2045864739
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2106295680
Short name T1050
Test name
Test status
Simulation time 481014004 ps
CPU time 4.02 seconds
Started Jun 30 04:57:07 PM PDT 24
Finished Jun 30 04:57:12 PM PDT 24
Peak memory 217648 kb
Host smart-459cc369-ade5-41bc-9527-8d55f3fc8213
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106295680 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2106295680
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1237566667
Short name T1022
Test name
Test status
Simulation time 41758970 ps
CPU time 1.35 seconds
Started Jun 30 04:57:09 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 207124 kb
Host smart-0b896c2d-558a-45f4-81fb-0a27fcd04fc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237566667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1237566667
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.108180542
Short name T1121
Test name
Test status
Simulation time 55727253 ps
CPU time 0.7 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:10 PM PDT 24
Peak memory 203816 kb
Host smart-e844d2a6-bf51-42c2-9b26-84a13b11807d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108180542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.108180542
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3585981600
Short name T148
Test name
Test status
Simulation time 119173572 ps
CPU time 2.67 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:12 PM PDT 24
Peak memory 215352 kb
Host smart-ba8675e7-8dc4-46c7-aab9-03170a2195d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585981600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3585981600
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2707191140
Short name T114
Test name
Test status
Simulation time 224267849 ps
CPU time 2.09 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 215496 kb
Host smart-ee3af524-4e7d-4343-854e-b2a0dc287a73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707191140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2707191140
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1478317052
Short name T1082
Test name
Test status
Simulation time 40695607 ps
CPU time 2.81 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:12 PM PDT 24
Peak memory 217120 kb
Host smart-162c2886-6f16-4df5-89d4-847f55f5be8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478317052 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1478317052
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1044090574
Short name T1101
Test name
Test status
Simulation time 99108946 ps
CPU time 2.13 seconds
Started Jun 30 04:57:10 PM PDT 24
Finished Jun 30 04:57:13 PM PDT 24
Peak memory 215308 kb
Host smart-5fa2e401-0098-483a-95ec-30174634a760
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044090574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1044090574
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2365027760
Short name T1084
Test name
Test status
Simulation time 13447484 ps
CPU time 0.77 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:10 PM PDT 24
Peak memory 204112 kb
Host smart-b6b417b1-a542-4f6e-98ed-e5fed12db2b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365027760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2365027760
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4214998253
Short name T1034
Test name
Test status
Simulation time 239520414 ps
CPU time 1.82 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 215328 kb
Host smart-432d130c-dc63-4707-862c-b39eccf32289
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214998253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4214998253
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.48790250
Short name T1075
Test name
Test status
Simulation time 202622822 ps
CPU time 12.54 seconds
Started Jun 30 04:57:07 PM PDT 24
Finished Jun 30 04:57:20 PM PDT 24
Peak memory 215392 kb
Host smart-71d23a9a-6896-4c49-9ef8-f26d033bb2b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48790250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_
tl_intg_err.48790250
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1936033208
Short name T1059
Test name
Test status
Simulation time 535807408 ps
CPU time 3.45 seconds
Started Jun 30 04:57:06 PM PDT 24
Finished Jun 30 04:57:10 PM PDT 24
Peak memory 217676 kb
Host smart-68a30826-b514-4b6b-abe9-d7958ef01af7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936033208 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1936033208
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3553769372
Short name T1116
Test name
Test status
Simulation time 80294744 ps
CPU time 2.63 seconds
Started Jun 30 04:57:12 PM PDT 24
Finished Jun 30 04:57:15 PM PDT 24
Peak memory 215372 kb
Host smart-7f5b1842-90ce-408f-84a9-fa2a09807e12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553769372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3553769372
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3373390217
Short name T1129
Test name
Test status
Simulation time 17050999 ps
CPU time 0.73 seconds
Started Jun 30 04:57:10 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 204076 kb
Host smart-235e8a87-6b65-4d24-bc04-fe24ef42374e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373390217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3373390217
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1406678027
Short name T1098
Test name
Test status
Simulation time 64720797 ps
CPU time 3.93 seconds
Started Jun 30 04:57:10 PM PDT 24
Finished Jun 30 04:57:15 PM PDT 24
Peak memory 215224 kb
Host smart-39e0e167-eb92-41af-8236-db492937c399
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406678027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1406678027
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2561168527
Short name T109
Test name
Test status
Simulation time 154960198 ps
CPU time 2.73 seconds
Started Jun 30 04:57:08 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 215532 kb
Host smart-ac7ff5c0-845a-483c-b3e4-d0a8c208b6ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561168527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2561168527
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.981316618
Short name T1031
Test name
Test status
Simulation time 415780091 ps
CPU time 6.74 seconds
Started Jun 30 04:57:10 PM PDT 24
Finished Jun 30 04:57:17 PM PDT 24
Peak memory 215440 kb
Host smart-af14fa66-5807-4381-96b4-28e0d314f1a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981316618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.981316618
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1346433589
Short name T68
Test name
Test status
Simulation time 145891441 ps
CPU time 3.68 seconds
Started Jun 30 04:57:11 PM PDT 24
Finished Jun 30 04:57:15 PM PDT 24
Peak memory 217324 kb
Host smart-cf84b5ac-26b7-4c05-b880-ca8ca6c00300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346433589 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1346433589
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2745255435
Short name T119
Test name
Test status
Simulation time 37291777 ps
CPU time 1.35 seconds
Started Jun 30 04:57:07 PM PDT 24
Finished Jun 30 04:57:09 PM PDT 24
Peak memory 207020 kb
Host smart-3baf5a66-7cfa-41ff-a626-96176ce3c430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745255435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2745255435
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1381085918
Short name T1020
Test name
Test status
Simulation time 29449780 ps
CPU time 0.75 seconds
Started Jun 30 04:57:10 PM PDT 24
Finished Jun 30 04:57:12 PM PDT 24
Peak memory 203752 kb
Host smart-8f058758-d80f-4022-b419-18bbad6cb4eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381085918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1381085918
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.186286060
Short name T1120
Test name
Test status
Simulation time 142261007 ps
CPU time 3.03 seconds
Started Jun 30 04:57:10 PM PDT 24
Finished Jun 30 04:57:14 PM PDT 24
Peak memory 215324 kb
Host smart-30a1d0bd-8156-4c34-82fc-7ff326c950d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186286060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.186286060
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2531546689
Short name T1106
Test name
Test status
Simulation time 118106482 ps
CPU time 3.41 seconds
Started Jun 30 04:57:13 PM PDT 24
Finished Jun 30 04:57:16 PM PDT 24
Peak memory 216464 kb
Host smart-b2edfc86-0e5d-454a-885c-ad6b21e7a1a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531546689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2531546689
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4166130549
Short name T1078
Test name
Test status
Simulation time 1142765335 ps
CPU time 8.29 seconds
Started Jun 30 04:57:10 PM PDT 24
Finished Jun 30 04:57:19 PM PDT 24
Peak memory 215724 kb
Host smart-785460db-05f8-4fd8-b3f2-b66e368560e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166130549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4166130549
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3400945052
Short name T1125
Test name
Test status
Simulation time 631871907 ps
CPU time 8.32 seconds
Started Jun 30 04:56:50 PM PDT 24
Finished Jun 30 04:56:59 PM PDT 24
Peak memory 207048 kb
Host smart-ba186fd9-9daf-425b-b2a5-2f06ecc2c315
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400945052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3400945052
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2748934520
Short name T1083
Test name
Test status
Simulation time 1069887325 ps
CPU time 36.04 seconds
Started Jun 30 04:56:48 PM PDT 24
Finished Jun 30 04:57:24 PM PDT 24
Peak memory 215352 kb
Host smart-fb19c6f9-6884-426a-a1a8-201933aa7978
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748934520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2748934520
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1286913664
Short name T1067
Test name
Test status
Simulation time 31091587 ps
CPU time 0.95 seconds
Started Jun 30 04:56:48 PM PDT 24
Finished Jun 30 04:56:50 PM PDT 24
Peak memory 206868 kb
Host smart-e9a39b97-6bcd-47d5-9536-a744f5a01243
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286913664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1286913664
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.543464907
Short name T1025
Test name
Test status
Simulation time 149894016 ps
CPU time 2.59 seconds
Started Jun 30 04:56:51 PM PDT 24
Finished Jun 30 04:56:54 PM PDT 24
Peak memory 216604 kb
Host smart-a177b073-8325-4207-8b55-20cced36b329
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543464907 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.543464907
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.420144506
Short name T1103
Test name
Test status
Simulation time 234305487 ps
CPU time 2.32 seconds
Started Jun 30 04:56:49 PM PDT 24
Finished Jun 30 04:56:52 PM PDT 24
Peak memory 215260 kb
Host smart-d1072c16-817c-42fc-a3db-1ca0848dc5fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420144506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.420144506
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.403284327
Short name T1027
Test name
Test status
Simulation time 34454779 ps
CPU time 0.69 seconds
Started Jun 30 04:56:47 PM PDT 24
Finished Jun 30 04:56:48 PM PDT 24
Peak memory 203804 kb
Host smart-caafc208-3d01-4ae3-b80a-68d3df8d1e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403284327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.403284327
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.623718265
Short name T1100
Test name
Test status
Simulation time 36253992 ps
CPU time 1.34 seconds
Started Jun 30 04:56:47 PM PDT 24
Finished Jun 30 04:56:49 PM PDT 24
Peak memory 215280 kb
Host smart-9f4efb59-6e26-45e5-8443-b4104aa4126f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623718265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.623718265
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.821326428
Short name T1064
Test name
Test status
Simulation time 15708008 ps
CPU time 0.69 seconds
Started Jun 30 04:56:49 PM PDT 24
Finished Jun 30 04:56:50 PM PDT 24
Peak memory 203684 kb
Host smart-d9a3741d-3ce2-4ab8-abf5-cb101c49ea55
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821326428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.821326428
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.122325352
Short name T1107
Test name
Test status
Simulation time 70825152 ps
CPU time 3.8 seconds
Started Jun 30 04:56:48 PM PDT 24
Finished Jun 30 04:56:52 PM PDT 24
Peak memory 215320 kb
Host smart-49288dff-85ba-4e0e-ad24-a56df08af364
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122325352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.122325352
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3442290128
Short name T1072
Test name
Test status
Simulation time 44138122 ps
CPU time 2.65 seconds
Started Jun 30 04:56:47 PM PDT 24
Finished Jun 30 04:56:51 PM PDT 24
Peak memory 215504 kb
Host smart-acd41358-96b0-4a35-b30a-23c4b23cb2bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442290128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
442290128
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2526578328
Short name T1094
Test name
Test status
Simulation time 938841094 ps
CPU time 12.59 seconds
Started Jun 30 04:56:48 PM PDT 24
Finished Jun 30 04:57:01 PM PDT 24
Peak memory 215796 kb
Host smart-b0e3726f-4680-41e6-bff5-12f72fad30b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526578328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2526578328
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1557193118
Short name T1024
Test name
Test status
Simulation time 15022654 ps
CPU time 0.7 seconds
Started Jun 30 04:57:10 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 203808 kb
Host smart-10d5170d-c576-4032-9da6-c87b69cc7235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557193118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1557193118
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3486307369
Short name T1030
Test name
Test status
Simulation time 110257749 ps
CPU time 0.74 seconds
Started Jun 30 04:57:17 PM PDT 24
Finished Jun 30 04:57:18 PM PDT 24
Peak memory 204092 kb
Host smart-7680e77f-4b8a-43b7-ab4c-14c4b670a448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486307369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3486307369
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3981161529
Short name T1068
Test name
Test status
Simulation time 16656270 ps
CPU time 0.75 seconds
Started Jun 30 04:57:20 PM PDT 24
Finished Jun 30 04:57:22 PM PDT 24
Peak memory 203828 kb
Host smart-03a62731-22ba-4d38-8ef1-f70649f5af65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981161529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3981161529
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.113551344
Short name T1053
Test name
Test status
Simulation time 13357119 ps
CPU time 0.71 seconds
Started Jun 30 04:57:22 PM PDT 24
Finished Jun 30 04:57:23 PM PDT 24
Peak memory 203816 kb
Host smart-fb796e74-277a-4b8c-9243-c88d6ddd68d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113551344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.113551344
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2872297346
Short name T1049
Test name
Test status
Simulation time 35851757 ps
CPU time 0.71 seconds
Started Jun 30 04:57:18 PM PDT 24
Finished Jun 30 04:57:19 PM PDT 24
Peak memory 203808 kb
Host smart-6956f382-c435-44fb-8c5d-dd0b787f9060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872297346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2872297346
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1711658867
Short name T1018
Test name
Test status
Simulation time 17357296 ps
CPU time 0.75 seconds
Started Jun 30 04:57:14 PM PDT 24
Finished Jun 30 04:57:15 PM PDT 24
Peak memory 203788 kb
Host smart-273ff36d-f4a6-4503-a6ff-5c8528e1754c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711658867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1711658867
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2263648739
Short name T1044
Test name
Test status
Simulation time 12603270 ps
CPU time 0.74 seconds
Started Jun 30 04:57:13 PM PDT 24
Finished Jun 30 04:57:14 PM PDT 24
Peak memory 203796 kb
Host smart-7e8f54ba-d7ed-44cb-a156-e186ee0cffe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263648739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2263648739
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1551064173
Short name T1008
Test name
Test status
Simulation time 34481801 ps
CPU time 0.69 seconds
Started Jun 30 04:57:14 PM PDT 24
Finished Jun 30 04:57:16 PM PDT 24
Peak memory 203800 kb
Host smart-56bf90f8-f188-4009-82a3-33798d052031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551064173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1551064173
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3256064489
Short name T1005
Test name
Test status
Simulation time 12489533 ps
CPU time 0.7 seconds
Started Jun 30 04:57:17 PM PDT 24
Finished Jun 30 04:57:18 PM PDT 24
Peak memory 203588 kb
Host smart-8b284cdc-8ed0-4018-bb2c-55ff5aa79dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256064489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3256064489
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3909492447
Short name T1109
Test name
Test status
Simulation time 44686236 ps
CPU time 0.79 seconds
Started Jun 30 04:57:18 PM PDT 24
Finished Jun 30 04:57:19 PM PDT 24
Peak memory 204020 kb
Host smart-15f9f5f3-cf63-4eb9-bb17-52f95c295dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909492447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3909492447
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1645862475
Short name T128
Test name
Test status
Simulation time 423258953 ps
CPU time 7.52 seconds
Started Jun 30 04:56:48 PM PDT 24
Finished Jun 30 04:56:56 PM PDT 24
Peak memory 207176 kb
Host smart-81854190-5a3d-42f1-a9cd-d9b6f8c47152
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645862475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1645862475
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.706169644
Short name T1060
Test name
Test status
Simulation time 3600224510 ps
CPU time 37.97 seconds
Started Jun 30 04:56:48 PM PDT 24
Finished Jun 30 04:57:27 PM PDT 24
Peak memory 207296 kb
Host smart-fa39d4bb-fa31-4892-9a4c-ad1bfa9f2e4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706169644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.706169644
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2518571544
Short name T122
Test name
Test status
Simulation time 155371863 ps
CPU time 1.4 seconds
Started Jun 30 04:56:49 PM PDT 24
Finished Jun 30 04:56:52 PM PDT 24
Peak memory 215260 kb
Host smart-fe2f8acf-02d1-4237-af68-babe02fc1bb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518571544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2518571544
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1565354060
Short name T102
Test name
Test status
Simulation time 185241832 ps
CPU time 2.53 seconds
Started Jun 30 04:56:47 PM PDT 24
Finished Jun 30 04:56:51 PM PDT 24
Peak memory 216592 kb
Host smart-63e444a6-08f9-4f51-b07a-dab01af14a38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565354060 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1565354060
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4124003983
Short name T151
Test name
Test status
Simulation time 96743673 ps
CPU time 1.45 seconds
Started Jun 30 04:56:47 PM PDT 24
Finished Jun 30 04:56:49 PM PDT 24
Peak memory 207208 kb
Host smart-fcc88956-4ee6-4c01-9316-b5eed187d7c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124003983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
124003983
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3509159469
Short name T1111
Test name
Test status
Simulation time 42425950 ps
CPU time 0.7 seconds
Started Jun 30 04:56:47 PM PDT 24
Finished Jun 30 04:56:48 PM PDT 24
Peak memory 203752 kb
Host smart-7bc9d201-0c60-4cab-85c6-2864f8baed2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509159469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
509159469
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3712985701
Short name T1112
Test name
Test status
Simulation time 88996686 ps
CPU time 1.86 seconds
Started Jun 30 04:56:47 PM PDT 24
Finished Jun 30 04:56:49 PM PDT 24
Peak memory 215368 kb
Host smart-f8f3d94e-3faf-4f43-90e5-defbd76a377c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712985701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3712985701
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2536077726
Short name T1091
Test name
Test status
Simulation time 12419944 ps
CPU time 0.67 seconds
Started Jun 30 04:56:49 PM PDT 24
Finished Jun 30 04:56:51 PM PDT 24
Peak memory 203704 kb
Host smart-0d4324fc-fe81-4b26-bdcb-a827b398573b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536077726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2536077726
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.440363201
Short name T1086
Test name
Test status
Simulation time 244257736 ps
CPU time 1.83 seconds
Started Jun 30 04:56:48 PM PDT 24
Finished Jun 30 04:56:50 PM PDT 24
Peak memory 215256 kb
Host smart-0c577a04-744f-4595-ae94-bd6bb936b9eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440363201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.440363201
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1972458437
Short name T116
Test name
Test status
Simulation time 63051801 ps
CPU time 3.61 seconds
Started Jun 30 04:56:47 PM PDT 24
Finished Jun 30 04:56:52 PM PDT 24
Peak memory 215492 kb
Host smart-74a13472-461b-4a92-8f37-9bf4cfe94e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972458437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
972458437
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1462744978
Short name T1021
Test name
Test status
Simulation time 2145223660 ps
CPU time 7.71 seconds
Started Jun 30 04:56:47 PM PDT 24
Finished Jun 30 04:56:55 PM PDT 24
Peak memory 215332 kb
Host smart-6cfe1a39-8642-4469-807d-a71892a9b93e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462744978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1462744978
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1581559131
Short name T1048
Test name
Test status
Simulation time 53471841 ps
CPU time 0.75 seconds
Started Jun 30 04:57:16 PM PDT 24
Finished Jun 30 04:57:18 PM PDT 24
Peak memory 203740 kb
Host smart-6c6c8b15-ea2c-47cb-bfa0-06ce51d940a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581559131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1581559131
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3120205280
Short name T1047
Test name
Test status
Simulation time 40909335 ps
CPU time 0.78 seconds
Started Jun 30 04:57:18 PM PDT 24
Finished Jun 30 04:57:20 PM PDT 24
Peak memory 203696 kb
Host smart-64a8efa0-2da7-4d37-a0fa-0d1ce85ab7ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120205280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3120205280
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3885733704
Short name T1062
Test name
Test status
Simulation time 15030746 ps
CPU time 0.75 seconds
Started Jun 30 04:57:16 PM PDT 24
Finished Jun 30 04:57:17 PM PDT 24
Peak memory 203744 kb
Host smart-ce900e40-1e68-4197-bece-8e6b3576b0a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885733704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3885733704
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3548791732
Short name T1013
Test name
Test status
Simulation time 38033546 ps
CPU time 0.72 seconds
Started Jun 30 04:57:14 PM PDT 24
Finished Jun 30 04:57:16 PM PDT 24
Peak memory 203776 kb
Host smart-30002540-acde-4908-bf8c-f21146edc98d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548791732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3548791732
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2302596211
Short name T1063
Test name
Test status
Simulation time 19711715 ps
CPU time 0.69 seconds
Started Jun 30 04:57:22 PM PDT 24
Finished Jun 30 04:57:23 PM PDT 24
Peak memory 203816 kb
Host smart-8b3eeb94-156e-4622-9ae8-9122a10b0e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302596211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2302596211
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3335520946
Short name T1052
Test name
Test status
Simulation time 165659490 ps
CPU time 0.74 seconds
Started Jun 30 04:57:13 PM PDT 24
Finished Jun 30 04:57:15 PM PDT 24
Peak memory 203792 kb
Host smart-02d3d650-2f10-4272-aa78-78c9ea273f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335520946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3335520946
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.833126453
Short name T1058
Test name
Test status
Simulation time 35449813 ps
CPU time 0.7 seconds
Started Jun 30 04:57:15 PM PDT 24
Finished Jun 30 04:57:16 PM PDT 24
Peak memory 203716 kb
Host smart-d9c9d4d3-57b0-43c1-a52d-490f3d0011c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833126453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.833126453
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3828079760
Short name T1015
Test name
Test status
Simulation time 14955357 ps
CPU time 0.72 seconds
Started Jun 30 04:57:17 PM PDT 24
Finished Jun 30 04:57:18 PM PDT 24
Peak memory 203560 kb
Host smart-aa2c272c-b26c-4151-b317-1f6b00803281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828079760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3828079760
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.533890634
Short name T1041
Test name
Test status
Simulation time 28993145 ps
CPU time 0.72 seconds
Started Jun 30 04:57:15 PM PDT 24
Finished Jun 30 04:57:16 PM PDT 24
Peak memory 203772 kb
Host smart-7fbb85cc-9523-4ded-95b7-11796637dd40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533890634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.533890634
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2513951504
Short name T1028
Test name
Test status
Simulation time 28929713 ps
CPU time 0.76 seconds
Started Jun 30 04:57:16 PM PDT 24
Finished Jun 30 04:57:17 PM PDT 24
Peak memory 203772 kb
Host smart-e6bff6db-08e8-4f66-95a3-cc7c47754986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513951504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2513951504
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.400589049
Short name T1113
Test name
Test status
Simulation time 406547777 ps
CPU time 8.8 seconds
Started Jun 30 04:56:57 PM PDT 24
Finished Jun 30 04:57:06 PM PDT 24
Peak memory 215164 kb
Host smart-158ecaa8-ead1-491b-9a36-e991d6bb1234
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400589049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.400589049
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.929034132
Short name T1074
Test name
Test status
Simulation time 190846941 ps
CPU time 12.32 seconds
Started Jun 30 04:56:56 PM PDT 24
Finished Jun 30 04:57:09 PM PDT 24
Peak memory 206940 kb
Host smart-0a914320-19ff-4810-b33c-0b3914a9a4d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929034132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.929034132
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.660877648
Short name T88
Test name
Test status
Simulation time 214619215 ps
CPU time 1.19 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:02 PM PDT 24
Peak memory 207088 kb
Host smart-508919f4-d805-4b2d-b478-744d040bbe49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660877648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.660877648
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1232339178
Short name T1130
Test name
Test status
Simulation time 196747270 ps
CPU time 3.56 seconds
Started Jun 30 04:56:54 PM PDT 24
Finished Jun 30 04:56:58 PM PDT 24
Peak memory 218060 kb
Host smart-feeb64a4-32ce-4474-893c-a2bf90f7a10e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232339178 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1232339178
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1529363103
Short name T129
Test name
Test status
Simulation time 143972879 ps
CPU time 1.3 seconds
Started Jun 30 04:56:55 PM PDT 24
Finished Jun 30 04:56:57 PM PDT 24
Peak memory 215336 kb
Host smart-0273bdec-09bf-4b97-988a-58c23321d68d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529363103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
529363103
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3902956788
Short name T1035
Test name
Test status
Simulation time 19092621 ps
CPU time 0.74 seconds
Started Jun 30 04:56:55 PM PDT 24
Finished Jun 30 04:56:57 PM PDT 24
Peak memory 203788 kb
Host smart-2348ce9a-ea6f-4866-aa95-3658b3c658bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902956788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
902956788
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1518105761
Short name T121
Test name
Test status
Simulation time 33591236 ps
CPU time 1.25 seconds
Started Jun 30 04:56:53 PM PDT 24
Finished Jun 30 04:56:55 PM PDT 24
Peak memory 215340 kb
Host smart-82089d01-4fca-4d4a-8e14-19479e8346c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518105761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1518105761
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4294964849
Short name T1007
Test name
Test status
Simulation time 17097347 ps
CPU time 0.66 seconds
Started Jun 30 04:56:53 PM PDT 24
Finished Jun 30 04:56:54 PM PDT 24
Peak memory 203700 kb
Host smart-10cba0a3-ad99-47e0-af90-84d3168a2951
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294964849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4294964849
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3032816301
Short name T149
Test name
Test status
Simulation time 551859521 ps
CPU time 4 seconds
Started Jun 30 04:56:53 PM PDT 24
Finished Jun 30 04:56:57 PM PDT 24
Peak memory 215244 kb
Host smart-e32b5f72-2cdd-49ac-bb7f-7b745148bcca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032816301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3032816301
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4007485651
Short name T106
Test name
Test status
Simulation time 211323110 ps
CPU time 3.94 seconds
Started Jun 30 04:56:54 PM PDT 24
Finished Jun 30 04:56:59 PM PDT 24
Peak memory 215352 kb
Host smart-7a345a42-1407-4d01-82a5-608654118d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007485651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
007485651
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2133618175
Short name T1110
Test name
Test status
Simulation time 2861816849 ps
CPU time 6.95 seconds
Started Jun 30 04:56:53 PM PDT 24
Finished Jun 30 04:57:01 PM PDT 24
Peak memory 215324 kb
Host smart-5cfe03ee-5723-4c63-85a0-0ae525321b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133618175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2133618175
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2494093020
Short name T1038
Test name
Test status
Simulation time 26986269 ps
CPU time 0.7 seconds
Started Jun 30 04:57:16 PM PDT 24
Finished Jun 30 04:57:18 PM PDT 24
Peak memory 203760 kb
Host smart-7cdff3c8-9459-4000-8725-598eb0d691aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494093020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2494093020
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1562679343
Short name T1037
Test name
Test status
Simulation time 154257165 ps
CPU time 0.75 seconds
Started Jun 30 04:57:15 PM PDT 24
Finished Jun 30 04:57:16 PM PDT 24
Peak memory 204060 kb
Host smart-7ff2e9af-6536-43d7-a565-af9c3596f71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562679343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1562679343
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3216434274
Short name T1118
Test name
Test status
Simulation time 59035635 ps
CPU time 0.73 seconds
Started Jun 30 04:57:18 PM PDT 24
Finished Jun 30 04:57:19 PM PDT 24
Peak memory 204024 kb
Host smart-76d44862-d137-469a-845c-fe09d5ff83f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216434274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3216434274
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1825925245
Short name T1011
Test name
Test status
Simulation time 264039751 ps
CPU time 0.76 seconds
Started Jun 30 04:57:14 PM PDT 24
Finished Jun 30 04:57:16 PM PDT 24
Peak memory 203772 kb
Host smart-039c81c7-70a2-4835-9c9b-05a56c53cce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825925245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1825925245
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.634240897
Short name T1081
Test name
Test status
Simulation time 11196525 ps
CPU time 0.73 seconds
Started Jun 30 04:57:18 PM PDT 24
Finished Jun 30 04:57:20 PM PDT 24
Peak memory 203708 kb
Host smart-4e799964-68c8-44de-ae4a-d8ad97acc658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634240897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.634240897
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3263500429
Short name T1127
Test name
Test status
Simulation time 37669652 ps
CPU time 0.81 seconds
Started Jun 30 04:57:16 PM PDT 24
Finished Jun 30 04:57:17 PM PDT 24
Peak memory 203784 kb
Host smart-7609b25e-b6cc-4150-8633-06cb4fe849b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263500429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3263500429
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1137460640
Short name T1080
Test name
Test status
Simulation time 16338757 ps
CPU time 0.71 seconds
Started Jun 30 04:57:18 PM PDT 24
Finished Jun 30 04:57:19 PM PDT 24
Peak memory 203700 kb
Host smart-cc66100c-caf5-414a-b465-b6d41fd815df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137460640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1137460640
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3783089923
Short name T1054
Test name
Test status
Simulation time 37773735 ps
CPU time 0.73 seconds
Started Jun 30 04:57:14 PM PDT 24
Finished Jun 30 04:57:15 PM PDT 24
Peak memory 203784 kb
Host smart-546aa431-77f2-4bcc-af79-5d31ec512413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783089923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3783089923
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.804711030
Short name T1104
Test name
Test status
Simulation time 17890521 ps
CPU time 0.77 seconds
Started Jun 30 04:57:15 PM PDT 24
Finished Jun 30 04:57:17 PM PDT 24
Peak memory 203808 kb
Host smart-0795604d-e450-4ff0-880d-958626fefaf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804711030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.804711030
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3539123023
Short name T1051
Test name
Test status
Simulation time 34834559 ps
CPU time 0.7 seconds
Started Jun 30 04:57:14 PM PDT 24
Finished Jun 30 04:57:15 PM PDT 24
Peak memory 203784 kb
Host smart-a1867a75-20e8-497b-9df1-008b361c5932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539123023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3539123023
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1876796145
Short name T1046
Test name
Test status
Simulation time 708961248 ps
CPU time 1.66 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 215348 kb
Host smart-36e1844a-4ecc-4c76-a1a5-a0ac47d5d11e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876796145 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1876796145
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.369124739
Short name T1079
Test name
Test status
Simulation time 121852722 ps
CPU time 1.29 seconds
Started Jun 30 04:56:53 PM PDT 24
Finished Jun 30 04:56:55 PM PDT 24
Peak memory 215332 kb
Host smart-a8858ce5-b0a3-45be-9738-193698c67cb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369124739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.369124739
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.742290663
Short name T1019
Test name
Test status
Simulation time 22804496 ps
CPU time 0.72 seconds
Started Jun 30 04:56:53 PM PDT 24
Finished Jun 30 04:56:54 PM PDT 24
Peak memory 203800 kb
Host smart-0e84308b-d927-4b00-8e7e-45313f121a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742290663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.742290663
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2691160196
Short name T1033
Test name
Test status
Simulation time 129633133 ps
CPU time 1.92 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 215352 kb
Host smart-4d807e3d-1e3d-4484-88a3-ee65fb9881d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691160196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2691160196
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.42124240
Short name T1122
Test name
Test status
Simulation time 332685674 ps
CPU time 2.74 seconds
Started Jun 30 04:56:54 PM PDT 24
Finished Jun 30 04:56:58 PM PDT 24
Peak memory 215344 kb
Host smart-f127c240-a145-48f9-8ef4-9af37620bb04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42124240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.42124240
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2986759624
Short name T150
Test name
Test status
Simulation time 4050996669 ps
CPU time 21.78 seconds
Started Jun 30 04:56:54 PM PDT 24
Finished Jun 30 04:57:16 PM PDT 24
Peak memory 216016 kb
Host smart-2c9ef4a2-15f6-4db5-9d89-d0fbd6731969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986759624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2986759624
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1045480096
Short name T1056
Test name
Test status
Simulation time 149167603 ps
CPU time 3.87 seconds
Started Jun 30 04:56:54 PM PDT 24
Finished Jun 30 04:56:59 PM PDT 24
Peak memory 217956 kb
Host smart-1bcde719-047d-4050-8c11-bac440f89819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045480096 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1045480096
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.383971341
Short name T1097
Test name
Test status
Simulation time 151977708 ps
CPU time 1.29 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:02 PM PDT 24
Peak memory 215272 kb
Host smart-37f856bb-cff6-439f-a79a-bd5c0c419d33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383971341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.383971341
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1262664593
Short name T1010
Test name
Test status
Simulation time 141052005 ps
CPU time 0.73 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 203800 kb
Host smart-937d09ca-23b5-49d2-985e-c71553c9c003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262664593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
262664593
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1311392437
Short name T1093
Test name
Test status
Simulation time 28321461 ps
CPU time 1.68 seconds
Started Jun 30 04:56:56 PM PDT 24
Finished Jun 30 04:56:58 PM PDT 24
Peak memory 207128 kb
Host smart-f83e4417-e9ed-4669-bdb5-7e73ef3d2650
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311392437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1311392437
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1916896668
Short name T1119
Test name
Test status
Simulation time 96814672 ps
CPU time 3.28 seconds
Started Jun 30 04:56:54 PM PDT 24
Finished Jun 30 04:56:58 PM PDT 24
Peak memory 216532 kb
Host smart-f0bc191d-4251-4270-a7d9-fd383c784ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916896668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
916896668
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1152564298
Short name T176
Test name
Test status
Simulation time 643943946 ps
CPU time 15.06 seconds
Started Jun 30 04:56:55 PM PDT 24
Finished Jun 30 04:57:11 PM PDT 24
Peak memory 216712 kb
Host smart-0226934c-2e29-4ad2-ac86-9ffa4081fd49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152564298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1152564298
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2497389132
Short name T117
Test name
Test status
Simulation time 282014244 ps
CPU time 2.04 seconds
Started Jun 30 04:57:02 PM PDT 24
Finished Jun 30 04:57:06 PM PDT 24
Peak memory 216436 kb
Host smart-7577c2ac-c423-4b78-8c7e-0751ec178895
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497389132 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2497389132
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3731883850
Short name T124
Test name
Test status
Simulation time 68864357 ps
CPU time 1.31 seconds
Started Jun 30 04:56:55 PM PDT 24
Finished Jun 30 04:56:57 PM PDT 24
Peak memory 207152 kb
Host smart-651efcb1-302c-4186-bbb2-85307e4472a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731883850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
731883850
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2915387806
Short name T1089
Test name
Test status
Simulation time 14730972 ps
CPU time 0.74 seconds
Started Jun 30 04:56:54 PM PDT 24
Finished Jun 30 04:56:56 PM PDT 24
Peak memory 203796 kb
Host smart-60f6a4d2-edcf-41ce-836d-27f0f9518e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915387806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
915387806
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1751040779
Short name T1040
Test name
Test status
Simulation time 77303066 ps
CPU time 1.74 seconds
Started Jun 30 04:56:54 PM PDT 24
Finished Jun 30 04:56:56 PM PDT 24
Peak memory 215316 kb
Host smart-f825d15c-1730-4154-bdb9-e6ee60532756
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751040779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1751040779
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.419875000
Short name T70
Test name
Test status
Simulation time 339216517 ps
CPU time 2.35 seconds
Started Jun 30 04:56:54 PM PDT 24
Finished Jun 30 04:56:57 PM PDT 24
Peak memory 215516 kb
Host smart-e98d0d25-7dac-421d-a29b-fac7b1cc9906
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419875000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.419875000
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4167873144
Short name T177
Test name
Test status
Simulation time 215046579 ps
CPU time 12.74 seconds
Started Jun 30 04:56:55 PM PDT 24
Finished Jun 30 04:57:08 PM PDT 24
Peak memory 215332 kb
Host smart-f6b804a1-574e-4f00-83e7-5dad79664cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167873144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4167873144
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3166876680
Short name T1043
Test name
Test status
Simulation time 46776678 ps
CPU time 2.94 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 216916 kb
Host smart-5a183ee0-8479-4d72-81c5-cff465d48f64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166876680 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3166876680
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1651744711
Short name T1042
Test name
Test status
Simulation time 406234158 ps
CPU time 3.01 seconds
Started Jun 30 04:56:59 PM PDT 24
Finished Jun 30 04:57:03 PM PDT 24
Peak memory 215392 kb
Host smart-d120f9ea-157d-46ab-9233-e0b4ba1a3ce5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651744711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
651744711
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4117801161
Short name T1006
Test name
Test status
Simulation time 18017846 ps
CPU time 0.78 seconds
Started Jun 30 04:57:02 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 203836 kb
Host smart-2552409c-b601-4b91-a16d-04b0b6660c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117801161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4
117801161
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.792475499
Short name T1073
Test name
Test status
Simulation time 27424737 ps
CPU time 1.73 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 215288 kb
Host smart-9d72b811-d0e6-4641-b929-c6581982dbee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792475499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.792475499
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.419529359
Short name T111
Test name
Test status
Simulation time 375084726 ps
CPU time 2.29 seconds
Started Jun 30 04:56:54 PM PDT 24
Finished Jun 30 04:56:57 PM PDT 24
Peak memory 215492 kb
Host smart-02c729cb-5cb6-45fe-8483-6f9947b601ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419529359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.419529359
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3396169762
Short name T1096
Test name
Test status
Simulation time 1396105279 ps
CPU time 15.93 seconds
Started Jun 30 04:56:59 PM PDT 24
Finished Jun 30 04:57:16 PM PDT 24
Peak memory 215736 kb
Host smart-7c961343-838d-4a1c-a439-6bbbc1d11961
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396169762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3396169762
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3432880794
Short name T1128
Test name
Test status
Simulation time 111739365 ps
CPU time 1.75 seconds
Started Jun 30 04:57:00 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 215252 kb
Host smart-5309e2e3-5ed7-4f3d-aafc-c0f83aeca06d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432880794 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3432880794
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3414721457
Short name T1045
Test name
Test status
Simulation time 93273739 ps
CPU time 1.82 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 215352 kb
Host smart-c9562e83-4ecd-4e1e-94ba-b2e6e550d562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414721457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
414721457
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1226850403
Short name T1069
Test name
Test status
Simulation time 13567555 ps
CPU time 0.72 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:04 PM PDT 24
Peak memory 203804 kb
Host smart-5a7c623e-f30c-43dc-933b-60b36856098f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226850403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
226850403
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.243995042
Short name T1065
Test name
Test status
Simulation time 270420045 ps
CPU time 3.14 seconds
Started Jun 30 04:57:01 PM PDT 24
Finished Jun 30 04:57:07 PM PDT 24
Peak memory 215304 kb
Host smart-bdc8746d-e9ea-405d-b7c6-738d215b713b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243995042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.243995042
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.871786467
Short name T175
Test name
Test status
Simulation time 822307770 ps
CPU time 4.99 seconds
Started Jun 30 04:56:59 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 215624 kb
Host smart-a4dc69dd-e745-4355-a425-346e2983b27b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871786467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.871786467
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4172538472
Short name T893
Test name
Test status
Simulation time 34891598 ps
CPU time 0.77 seconds
Started Jun 30 05:29:19 PM PDT 24
Finished Jun 30 05:29:21 PM PDT 24
Peak memory 206256 kb
Host smart-daf8aad2-5cbd-4c7d-989c-9972ba501d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172538472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
172538472
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1298173903
Short name T441
Test name
Test status
Simulation time 213895843 ps
CPU time 3.05 seconds
Started Jun 30 05:29:21 PM PDT 24
Finished Jun 30 05:29:26 PM PDT 24
Peak memory 224932 kb
Host smart-5522fb3c-3a3e-433a-aab5-c0cfe566350e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298173903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1298173903
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.825770769
Short name T366
Test name
Test status
Simulation time 21043788 ps
CPU time 0.78 seconds
Started Jun 30 05:29:18 PM PDT 24
Finished Jun 30 05:29:20 PM PDT 24
Peak memory 207436 kb
Host smart-b56a4ed2-5a29-4bd2-ad36-2ad97cfe97a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825770769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.825770769
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2291869133
Short name T284
Test name
Test status
Simulation time 355307095958 ps
CPU time 437.9 seconds
Started Jun 30 05:29:22 PM PDT 24
Finished Jun 30 05:36:41 PM PDT 24
Peak memory 257192 kb
Host smart-296a9fe7-459a-4056-bf1e-a12a6514f965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291869133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2291869133
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3962642833
Short name T632
Test name
Test status
Simulation time 5775314623 ps
CPU time 92.55 seconds
Started Jun 30 05:29:21 PM PDT 24
Finished Jun 30 05:30:54 PM PDT 24
Peak memory 261216 kb
Host smart-830689e1-19d0-46ab-9535-9f5de458318b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962642833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3962642833
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1700566295
Short name T762
Test name
Test status
Simulation time 2783106688 ps
CPU time 49.6 seconds
Started Jun 30 05:29:20 PM PDT 24
Finished Jun 30 05:30:11 PM PDT 24
Peak memory 250276 kb
Host smart-39f4a558-c6ce-42ca-814c-ed27ca659709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700566295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1700566295
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3018444558
Short name T469
Test name
Test status
Simulation time 141473960 ps
CPU time 2.66 seconds
Started Jun 30 05:29:22 PM PDT 24
Finished Jun 30 05:29:26 PM PDT 24
Peak memory 233216 kb
Host smart-12ef59c9-ae09-4f0d-aa4b-80c05bdab8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018444558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3018444558
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1708653196
Short name T96
Test name
Test status
Simulation time 38787501529 ps
CPU time 154.6 seconds
Started Jun 30 05:29:22 PM PDT 24
Finished Jun 30 05:31:58 PM PDT 24
Peak memory 249700 kb
Host smart-ae2f0a15-cee4-47cd-8610-81e84e908495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708653196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1708653196
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1816728566
Short name T231
Test name
Test status
Simulation time 1704695128 ps
CPU time 17.53 seconds
Started Jun 30 05:29:22 PM PDT 24
Finished Jun 30 05:29:40 PM PDT 24
Peak memory 220872 kb
Host smart-2de28105-6f1c-4cac-964a-c4fc7b8a5d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816728566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1816728566
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.543892857
Short name T811
Test name
Test status
Simulation time 3715651485 ps
CPU time 42.08 seconds
Started Jun 30 05:29:19 PM PDT 24
Finished Jun 30 05:30:02 PM PDT 24
Peak memory 241072 kb
Host smart-3ee2ad98-d9bd-4efb-9497-6d34030ed4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543892857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.543892857
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3266029720
Short name T935
Test name
Test status
Simulation time 1749302831 ps
CPU time 3.85 seconds
Started Jun 30 05:29:20 PM PDT 24
Finished Jun 30 05:29:25 PM PDT 24
Peak memory 233108 kb
Host smart-6976df23-3ce7-4206-a0cf-99bb1e02927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266029720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3266029720
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1380610473
Short name T472
Test name
Test status
Simulation time 965489546 ps
CPU time 4.19 seconds
Started Jun 30 05:29:19 PM PDT 24
Finished Jun 30 05:29:24 PM PDT 24
Peak memory 233184 kb
Host smart-ea0edb7d-d238-4a36-8060-adb9f7124b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380610473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1380610473
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1975379276
Short name T753
Test name
Test status
Simulation time 2300386294 ps
CPU time 8.77 seconds
Started Jun 30 05:29:20 PM PDT 24
Finished Jun 30 05:29:30 PM PDT 24
Peak memory 223736 kb
Host smart-6debc679-4613-4197-9bc6-27986051d2f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1975379276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1975379276
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2566358908
Short name T159
Test name
Test status
Simulation time 59791248201 ps
CPU time 108.43 seconds
Started Jun 30 05:29:19 PM PDT 24
Finished Jun 30 05:31:08 PM PDT 24
Peak memory 249900 kb
Host smart-0285c658-9155-4b20-88de-aa2fe92aa129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566358908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2566358908
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2803329435
Short name T766
Test name
Test status
Simulation time 1293252669 ps
CPU time 17.24 seconds
Started Jun 30 05:29:19 PM PDT 24
Finished Jun 30 05:29:37 PM PDT 24
Peak memory 220928 kb
Host smart-108f87ad-abc8-4135-8f33-224dae1fc196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803329435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2803329435
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2676799613
Short name T657
Test name
Test status
Simulation time 2486583436 ps
CPU time 8.33 seconds
Started Jun 30 05:29:20 PM PDT 24
Finished Jun 30 05:29:30 PM PDT 24
Peak memory 216908 kb
Host smart-12c2a250-fc36-4335-82e1-757cf83abb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676799613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2676799613
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4217401397
Short name T573
Test name
Test status
Simulation time 152630443 ps
CPU time 3.31 seconds
Started Jun 30 05:29:21 PM PDT 24
Finished Jun 30 05:29:26 PM PDT 24
Peak memory 216808 kb
Host smart-aa5da554-24f1-4999-b31b-7a6930e5fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217401397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4217401397
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.395331770
Short name T506
Test name
Test status
Simulation time 124867488 ps
CPU time 0.88 seconds
Started Jun 30 05:29:21 PM PDT 24
Finished Jun 30 05:29:23 PM PDT 24
Peak memory 206448 kb
Host smart-6be3b129-6aa5-4b29-8667-e84310e9e02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395331770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.395331770
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.614205257
Short name T255
Test name
Test status
Simulation time 20131485995 ps
CPU time 15.33 seconds
Started Jun 30 05:29:23 PM PDT 24
Finished Jun 30 05:29:39 PM PDT 24
Peak memory 249684 kb
Host smart-c4ea21d5-03e1-4808-8830-2a684ba84246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614205257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.614205257
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2276638544
Short name T235
Test name
Test status
Simulation time 1418490755 ps
CPU time 6.92 seconds
Started Jun 30 05:29:26 PM PDT 24
Finished Jun 30 05:29:33 PM PDT 24
Peak memory 224964 kb
Host smart-36680e6d-ad5e-4b9d-b23d-655e15c5d548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276638544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2276638544
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2486690668
Short name T826
Test name
Test status
Simulation time 16094483 ps
CPU time 0.79 seconds
Started Jun 30 05:29:21 PM PDT 24
Finished Jun 30 05:29:23 PM PDT 24
Peak memory 207108 kb
Host smart-af91bd43-8902-4598-a30e-4192e6cb5990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486690668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2486690668
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3249684605
Short name T750
Test name
Test status
Simulation time 5500169378 ps
CPU time 16.2 seconds
Started Jun 30 05:29:27 PM PDT 24
Finished Jun 30 05:29:43 PM PDT 24
Peak memory 238816 kb
Host smart-b668f4a2-4211-4a2f-a5b7-f6c71e990813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249684605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3249684605
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3328280490
Short name T137
Test name
Test status
Simulation time 27720670188 ps
CPU time 79.47 seconds
Started Jun 30 05:29:27 PM PDT 24
Finished Jun 30 05:30:47 PM PDT 24
Peak memory 239016 kb
Host smart-d9237d74-2a01-4516-983f-57b265cba702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328280490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3328280490
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1512772388
Short name T54
Test name
Test status
Simulation time 18570054028 ps
CPU time 175.63 seconds
Started Jun 30 05:29:27 PM PDT 24
Finished Jun 30 05:32:23 PM PDT 24
Peak memory 266128 kb
Host smart-aeb35742-73b4-43ed-9081-0303c48fadd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512772388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1512772388
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.722756750
Short name T395
Test name
Test status
Simulation time 136726591 ps
CPU time 2.83 seconds
Started Jun 30 05:29:27 PM PDT 24
Finished Jun 30 05:29:30 PM PDT 24
Peak memory 233164 kb
Host smart-bc30319e-2219-4140-9cb2-1803ee348829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722756750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.722756750
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1328457608
Short name T824
Test name
Test status
Simulation time 7517768663 ps
CPU time 37.55 seconds
Started Jun 30 05:29:29 PM PDT 24
Finished Jun 30 05:30:06 PM PDT 24
Peak memory 238620 kb
Host smart-23194e84-bd30-4612-9888-8c516b5d42de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328457608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1328457608
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1347477105
Short name T875
Test name
Test status
Simulation time 152083458 ps
CPU time 2.87 seconds
Started Jun 30 05:29:30 PM PDT 24
Finished Jun 30 05:29:33 PM PDT 24
Peak memory 224904 kb
Host smart-bbaf6adc-bc8e-4800-a922-cddb27caf380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347477105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1347477105
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1739174485
Short name T449
Test name
Test status
Simulation time 4109032679 ps
CPU time 16.73 seconds
Started Jun 30 05:29:30 PM PDT 24
Finished Jun 30 05:29:47 PM PDT 24
Peak memory 233336 kb
Host smart-4e11f42e-010d-4210-9de5-609d4b7efece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739174485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1739174485
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2843258582
Short name T948
Test name
Test status
Simulation time 2463013751 ps
CPU time 10.56 seconds
Started Jun 30 05:29:20 PM PDT 24
Finished Jun 30 05:29:32 PM PDT 24
Peak memory 233296 kb
Host smart-79cabbef-2b2a-4994-ad2d-487319ed5eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843258582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2843258582
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.268259470
Short name T600
Test name
Test status
Simulation time 3916795429 ps
CPU time 8.22 seconds
Started Jun 30 05:29:19 PM PDT 24
Finished Jun 30 05:29:28 PM PDT 24
Peak memory 233368 kb
Host smart-8dbc0d70-8dbe-4bf2-bedd-ac108e81b9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268259470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.268259470
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3175332371
Short name T789
Test name
Test status
Simulation time 525198284 ps
CPU time 5.71 seconds
Started Jun 30 05:29:26 PM PDT 24
Finished Jun 30 05:29:32 PM PDT 24
Peak memory 219580 kb
Host smart-0c04e76b-2795-490c-a0dc-7d85953dff73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3175332371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3175332371
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3673440795
Short name T74
Test name
Test status
Simulation time 92624413 ps
CPU time 1.17 seconds
Started Jun 30 05:29:29 PM PDT 24
Finished Jun 30 05:29:31 PM PDT 24
Peak memory 236500 kb
Host smart-5825038f-c16c-4711-b17e-00567492c3bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673440795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3673440795
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.305981247
Short name T50
Test name
Test status
Simulation time 4679917247 ps
CPU time 5.85 seconds
Started Jun 30 05:29:21 PM PDT 24
Finished Jun 30 05:29:27 PM PDT 24
Peak memory 220364 kb
Host smart-3a69474d-32d0-4c91-afef-c4d134bfdd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305981247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.305981247
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3779568377
Short name T553
Test name
Test status
Simulation time 14414778286 ps
CPU time 7.94 seconds
Started Jun 30 05:29:22 PM PDT 24
Finished Jun 30 05:29:31 PM PDT 24
Peak memory 216904 kb
Host smart-4a167ee7-a35f-4e32-8fcb-231787ec6b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779568377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3779568377
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.361968756
Short name T941
Test name
Test status
Simulation time 207924268 ps
CPU time 1.28 seconds
Started Jun 30 05:29:20 PM PDT 24
Finished Jun 30 05:29:22 PM PDT 24
Peak memory 208576 kb
Host smart-8b7fe154-84a3-4118-931b-f04ad0cc6bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361968756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.361968756
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.415720613
Short name T27
Test name
Test status
Simulation time 35117393 ps
CPU time 0.81 seconds
Started Jun 30 05:29:22 PM PDT 24
Finished Jun 30 05:29:24 PM PDT 24
Peak memory 206472 kb
Host smart-7b1e5379-060c-446a-a125-a9b99d266380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415720613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.415720613
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2950906654
Short name T786
Test name
Test status
Simulation time 181756020 ps
CPU time 2.62 seconds
Started Jun 30 05:29:28 PM PDT 24
Finished Jun 30 05:29:31 PM PDT 24
Peak memory 233204 kb
Host smart-8869fcda-dedd-42e8-b778-dcada843ee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950906654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2950906654
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1134517431
Short name T359
Test name
Test status
Simulation time 44075878 ps
CPU time 0.71 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:30:09 PM PDT 24
Peak memory 205428 kb
Host smart-7a0dd401-6069-4870-a1e2-ffb97cb29bae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134517431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1134517431
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1561576639
Short name T464
Test name
Test status
Simulation time 261438772 ps
CPU time 2.37 seconds
Started Jun 30 05:29:59 PM PDT 24
Finished Jun 30 05:30:02 PM PDT 24
Peak memory 225012 kb
Host smart-5c2d540f-6af8-4ae9-8f82-2bdd80e74dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561576639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1561576639
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.183482716
Short name T425
Test name
Test status
Simulation time 44230295 ps
CPU time 0.83 seconds
Started Jun 30 05:29:58 PM PDT 24
Finished Jun 30 05:29:59 PM PDT 24
Peak memory 207408 kb
Host smart-ddd5f98a-9fd6-4e84-8933-cd22f223a70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183482716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.183482716
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1613736334
Short name T928
Test name
Test status
Simulation time 12025307677 ps
CPU time 74.98 seconds
Started Jun 30 05:29:57 PM PDT 24
Finished Jun 30 05:31:13 PM PDT 24
Peak memory 257904 kb
Host smart-d514c0bf-9018-4c80-8da8-eedfd0f73ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613736334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1613736334
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4272722092
Short name T905
Test name
Test status
Simulation time 10573574935 ps
CPU time 106.01 seconds
Started Jun 30 05:30:04 PM PDT 24
Finished Jun 30 05:31:51 PM PDT 24
Peak memory 249836 kb
Host smart-3fedc9c3-378a-4ec6-ad57-38437effe74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272722092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4272722092
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1164923667
Short name T717
Test name
Test status
Simulation time 210860688 ps
CPU time 3.64 seconds
Started Jun 30 05:30:01 PM PDT 24
Finished Jun 30 05:30:05 PM PDT 24
Peak memory 233148 kb
Host smart-44ddd4c7-1d37-4b04-b942-59a2e196da64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164923667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1164923667
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2246415244
Short name T95
Test name
Test status
Simulation time 1230264758 ps
CPU time 4.43 seconds
Started Jun 30 05:30:06 PM PDT 24
Finished Jun 30 05:30:11 PM PDT 24
Peak memory 224972 kb
Host smart-ea00856e-ea78-4683-9ad0-4276aab0a6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246415244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2246415244
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1608520323
Short name T906
Test name
Test status
Simulation time 5450803126 ps
CPU time 5.27 seconds
Started Jun 30 05:30:00 PM PDT 24
Finished Jun 30 05:30:06 PM PDT 24
Peak memory 233300 kb
Host smart-77dd0b79-5c42-41fd-87eb-b0a20ac9f749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608520323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1608520323
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.824188705
Short name T224
Test name
Test status
Simulation time 79609455157 ps
CPU time 15.41 seconds
Started Jun 30 05:29:58 PM PDT 24
Finished Jun 30 05:30:14 PM PDT 24
Peak memory 233384 kb
Host smart-5174e8e8-603a-4f60-bcc1-e37975e2aa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824188705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.824188705
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.978498145
Short name T409
Test name
Test status
Simulation time 4970746227 ps
CPU time 8.61 seconds
Started Jun 30 05:29:58 PM PDT 24
Finished Jun 30 05:30:08 PM PDT 24
Peak memory 223056 kb
Host smart-9bec7451-f118-42ab-8e60-5c8854d8e544
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=978498145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.978498145
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4001369611
Short name T568
Test name
Test status
Simulation time 4066403297 ps
CPU time 23.23 seconds
Started Jun 30 05:30:00 PM PDT 24
Finished Jun 30 05:30:24 PM PDT 24
Peak memory 218908 kb
Host smart-7eda8cca-4a03-4be1-8ca3-41514ae38220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001369611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4001369611
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.449612255
Short name T971
Test name
Test status
Simulation time 1852506015 ps
CPU time 5.68 seconds
Started Jun 30 05:29:59 PM PDT 24
Finished Jun 30 05:30:05 PM PDT 24
Peak memory 216764 kb
Host smart-3cd9421c-a65d-4ecd-9f61-3227120b252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449612255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.449612255
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3952999843
Short name T613
Test name
Test status
Simulation time 359738854 ps
CPU time 1.25 seconds
Started Jun 30 05:30:00 PM PDT 24
Finished Jun 30 05:30:02 PM PDT 24
Peak memory 208460 kb
Host smart-55f445dd-0cf7-49ce-a501-9e1c862798f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952999843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3952999843
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4121887254
Short name T841
Test name
Test status
Simulation time 187107465 ps
CPU time 0.88 seconds
Started Jun 30 05:30:02 PM PDT 24
Finished Jun 30 05:30:03 PM PDT 24
Peak memory 206448 kb
Host smart-6d4c3a0e-e8e5-478f-bb11-5522f8bc9bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121887254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4121887254
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2959317527
Short name T245
Test name
Test status
Simulation time 1364232461 ps
CPU time 10.21 seconds
Started Jun 30 05:29:58 PM PDT 24
Finished Jun 30 05:30:09 PM PDT 24
Peak memory 233140 kb
Host smart-3fdd0448-d823-4c16-b99b-a0874802ea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959317527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2959317527
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3925879330
Short name T784
Test name
Test status
Simulation time 27211036 ps
CPU time 0.69 seconds
Started Jun 30 05:30:03 PM PDT 24
Finished Jun 30 05:30:04 PM PDT 24
Peak memory 205376 kb
Host smart-8109286d-5dfc-41e1-8b85-50469143acbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925879330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3925879330
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2400173639
Short name T591
Test name
Test status
Simulation time 116610794 ps
CPU time 2.91 seconds
Started Jun 30 05:30:04 PM PDT 24
Finished Jun 30 05:30:08 PM PDT 24
Peak memory 233200 kb
Host smart-bb21f474-40a6-40a2-b380-611c5a587439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400173639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2400173639
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4019133201
Short name T82
Test name
Test status
Simulation time 17067942 ps
CPU time 0.82 seconds
Started Jun 30 05:30:04 PM PDT 24
Finished Jun 30 05:30:05 PM PDT 24
Peak memory 207064 kb
Host smart-deae9b55-01d7-433a-8f81-b46687be9ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019133201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4019133201
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.677269590
Short name T228
Test name
Test status
Simulation time 431440236 ps
CPU time 7.33 seconds
Started Jun 30 05:30:10 PM PDT 24
Finished Jun 30 05:30:17 PM PDT 24
Peak memory 224996 kb
Host smart-e6ec32c4-2eaf-4944-9a4a-2bb101a2a961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677269590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.677269590
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.182972330
Short name T530
Test name
Test status
Simulation time 41307130885 ps
CPU time 46.12 seconds
Started Jun 30 05:30:06 PM PDT 24
Finished Jun 30 05:30:53 PM PDT 24
Peak memory 225312 kb
Host smart-fa51a6fb-6884-47de-bf0e-d110012530db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182972330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.182972330
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.645295249
Short name T628
Test name
Test status
Simulation time 3173599716 ps
CPU time 28.52 seconds
Started Jun 30 05:30:04 PM PDT 24
Finished Jun 30 05:30:33 PM PDT 24
Peak memory 225196 kb
Host smart-b467fe61-ff4d-4187-a2e2-aa01a05ceda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645295249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.645295249
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1048308157
Short name T642
Test name
Test status
Simulation time 23933596388 ps
CPU time 184.78 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:33:11 PM PDT 24
Peak memory 253232 kb
Host smart-80313c9f-6f56-45c8-82e3-cb8d39dacecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048308157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1048308157
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1454635327
Short name T376
Test name
Test status
Simulation time 35711412 ps
CPU time 2.48 seconds
Started Jun 30 05:30:04 PM PDT 24
Finished Jun 30 05:30:07 PM PDT 24
Peak memory 233244 kb
Host smart-1e80449f-273f-4f66-98af-59863e5fbeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454635327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1454635327
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4028346751
Short name T758
Test name
Test status
Simulation time 86961278760 ps
CPU time 198.11 seconds
Started Jun 30 05:30:08 PM PDT 24
Finished Jun 30 05:33:27 PM PDT 24
Peak memory 235488 kb
Host smart-911eaf8d-574d-4424-a45a-2cdf7880b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028346751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4028346751
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2237345223
Short name T775
Test name
Test status
Simulation time 3320879306 ps
CPU time 6.99 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:30:15 PM PDT 24
Peak memory 241468 kb
Host smart-e26d6c74-afcb-4a98-b680-e90dd345d7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237345223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2237345223
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.281531114
Short name T867
Test name
Test status
Simulation time 6269200928 ps
CPU time 4.18 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:30:10 PM PDT 24
Peak memory 225036 kb
Host smart-f52a802e-66e0-45b5-83f5-afb44ea90ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281531114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.281531114
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.825276911
Short name T418
Test name
Test status
Simulation time 1928274381 ps
CPU time 5.57 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:30:11 PM PDT 24
Peak memory 223156 kb
Host smart-0d11dbbe-ed0c-4a9a-80c5-9f921bd5f13c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=825276911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.825276911
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.245738277
Short name T23
Test name
Test status
Simulation time 178105848 ps
CPU time 1 seconds
Started Jun 30 05:30:02 PM PDT 24
Finished Jun 30 05:30:04 PM PDT 24
Peak memory 207216 kb
Host smart-f7ecc48b-fa79-4177-911b-53896e5358a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245738277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.245738277
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.4071825873
Short name T848
Test name
Test status
Simulation time 18430081701 ps
CPU time 26.04 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:30:34 PM PDT 24
Peak memory 216912 kb
Host smart-910e6fc0-fbfa-4fc5-9e4f-fbd55df36d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071825873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4071825873
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.865521279
Short name T378
Test name
Test status
Simulation time 680240430 ps
CPU time 3.45 seconds
Started Jun 30 05:30:09 PM PDT 24
Finished Jun 30 05:30:13 PM PDT 24
Peak memory 216780 kb
Host smart-282294b7-1c67-4494-80a2-5300ce21a451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865521279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.865521279
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2883579506
Short name T711
Test name
Test status
Simulation time 152337052 ps
CPU time 3.5 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:30:12 PM PDT 24
Peak memory 216744 kb
Host smart-034f4072-f707-4aec-8177-a2d7e490dd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883579506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2883579506
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3080216653
Short name T679
Test name
Test status
Simulation time 13497355 ps
CPU time 0.73 seconds
Started Jun 30 05:30:04 PM PDT 24
Finished Jun 30 05:30:05 PM PDT 24
Peak memory 206128 kb
Host smart-f6535520-2cc7-4b82-9ed0-fab305189051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080216653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3080216653
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3076046051
Short name T877
Test name
Test status
Simulation time 485931037 ps
CPU time 6.2 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:30:14 PM PDT 24
Peak memory 220356 kb
Host smart-c960bb1d-4839-4531-96fd-17a285b1cded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076046051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3076046051
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.501954615
Short name T872
Test name
Test status
Simulation time 31297445 ps
CPU time 0.69 seconds
Started Jun 30 05:30:11 PM PDT 24
Finished Jun 30 05:30:12 PM PDT 24
Peak memory 205972 kb
Host smart-69d49457-8045-4361-a8f6-c963df4b444d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501954615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.501954615
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3607024307
Short name T544
Test name
Test status
Simulation time 68601051 ps
CPU time 3.02 seconds
Started Jun 30 05:30:06 PM PDT 24
Finished Jun 30 05:30:10 PM PDT 24
Peak memory 233196 kb
Host smart-334633ad-3dab-4050-ba4b-52ef3e98b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607024307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3607024307
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.330929601
Short name T614
Test name
Test status
Simulation time 57217754 ps
CPU time 0.77 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:30:07 PM PDT 24
Peak memory 205980 kb
Host smart-3a3dd745-85ae-4282-b64a-8a9894c966be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330929601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.330929601
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3493878344
Short name T281
Test name
Test status
Simulation time 68491112162 ps
CPU time 287.04 seconds
Started Jun 30 05:30:08 PM PDT 24
Finished Jun 30 05:34:56 PM PDT 24
Peak memory 254172 kb
Host smart-ced6f81d-d55d-4302-b2ef-ca07f9bcefbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493878344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3493878344
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2967405063
Short name T630
Test name
Test status
Simulation time 180381180929 ps
CPU time 131.03 seconds
Started Jun 30 05:30:11 PM PDT 24
Finished Jun 30 05:32:22 PM PDT 24
Peak memory 249976 kb
Host smart-36bba885-e710-4a8c-88e1-45c12d852f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967405063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2967405063
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2599429204
Short name T838
Test name
Test status
Simulation time 15867232319 ps
CPU time 83.69 seconds
Started Jun 30 05:30:13 PM PDT 24
Finished Jun 30 05:31:38 PM PDT 24
Peak memory 261420 kb
Host smart-421559ec-1acd-4b45-931b-a00bf659a26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599429204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2599429204
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.771841826
Short name T145
Test name
Test status
Simulation time 424148231 ps
CPU time 10.74 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:30:17 PM PDT 24
Peak memory 249616 kb
Host smart-680a427c-15f0-411d-8e11-c569ea2c3baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771841826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.771841826
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2982426209
Short name T726
Test name
Test status
Simulation time 5915832861 ps
CPU time 78.84 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:31:27 PM PDT 24
Peak memory 253556 kb
Host smart-8c890a42-fa57-472f-9120-32788cab3d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982426209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2982426209
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2985973248
Short name T658
Test name
Test status
Simulation time 73369471 ps
CPU time 2.35 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:30:08 PM PDT 24
Peak memory 224876 kb
Host smart-1a492495-6f48-4c14-8b7e-89d3ae3a7621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985973248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2985973248
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3582032061
Short name T162
Test name
Test status
Simulation time 46070289582 ps
CPU time 64.26 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:31:10 PM PDT 24
Peak memory 238200 kb
Host smart-909fb4d8-b088-4b64-9ed9-3bdf47df1f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582032061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3582032061
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1505487106
Short name T207
Test name
Test status
Simulation time 3057882236 ps
CPU time 10.35 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:30:18 PM PDT 24
Peak memory 225148 kb
Host smart-45107514-efed-4393-8c4a-e11971c035fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505487106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1505487106
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2231042856
Short name T929
Test name
Test status
Simulation time 386657882 ps
CPU time 3.64 seconds
Started Jun 30 05:30:04 PM PDT 24
Finished Jun 30 05:30:08 PM PDT 24
Peak memory 225044 kb
Host smart-325bdec6-d4ee-461d-9af7-4a94e4c3b6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231042856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2231042856
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1418864120
Short name T747
Test name
Test status
Simulation time 527464988 ps
CPU time 6.25 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:30:14 PM PDT 24
Peak memory 223060 kb
Host smart-2675cc33-4fa3-4fae-ac8d-d19ad7f749a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1418864120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1418864120
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1404838891
Short name T296
Test name
Test status
Simulation time 237400705908 ps
CPU time 438.22 seconds
Started Jun 30 05:30:17 PM PDT 24
Finished Jun 30 05:37:36 PM PDT 24
Peak memory 273536 kb
Host smart-62979416-52a6-4c1b-b051-49c9a3f2d952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404838891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1404838891
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1023640931
Short name T710
Test name
Test status
Simulation time 2946851554 ps
CPU time 12.31 seconds
Started Jun 30 05:30:04 PM PDT 24
Finished Jun 30 05:30:17 PM PDT 24
Peak memory 216996 kb
Host smart-e30d0d62-62d7-4ac1-b705-10fee7bef102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023640931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1023640931
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.770138219
Short name T981
Test name
Test status
Simulation time 907177843 ps
CPU time 6.63 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:30:15 PM PDT 24
Peak memory 216848 kb
Host smart-8b4ec7fc-0d47-4588-95ae-7967fa9248e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770138219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.770138219
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1011268868
Short name T388
Test name
Test status
Simulation time 34801113 ps
CPU time 0.68 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:30:09 PM PDT 24
Peak memory 205220 kb
Host smart-1247668c-3a0d-4072-80a7-e693eb6dea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011268868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1011268868
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2737348905
Short name T860
Test name
Test status
Simulation time 312991599 ps
CPU time 0.96 seconds
Started Jun 30 05:30:07 PM PDT 24
Finished Jun 30 05:30:09 PM PDT 24
Peak memory 206480 kb
Host smart-b8f30f55-1c9b-4078-ba5e-46b87aa2fb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737348905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2737348905
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.139647652
Short name T976
Test name
Test status
Simulation time 28978303894 ps
CPU time 25.8 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:30:31 PM PDT 24
Peak memory 241548 kb
Host smart-aed015dc-88b5-4379-ad77-a203f24c722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139647652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.139647652
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1997100518
Short name T342
Test name
Test status
Simulation time 35516289 ps
CPU time 0.74 seconds
Started Jun 30 05:30:21 PM PDT 24
Finished Jun 30 05:30:22 PM PDT 24
Peak memory 205388 kb
Host smart-409e6ab8-c677-472a-8633-921ba041b149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997100518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1997100518
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1590436130
Short name T741
Test name
Test status
Simulation time 84453491 ps
CPU time 2.36 seconds
Started Jun 30 05:30:10 PM PDT 24
Finished Jun 30 05:30:13 PM PDT 24
Peak memory 224932 kb
Host smart-ee404932-7acb-4e37-8ee3-a18e5a204c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590436130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1590436130
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3005509092
Short name T983
Test name
Test status
Simulation time 35137514 ps
CPU time 0.82 seconds
Started Jun 30 05:30:14 PM PDT 24
Finished Jun 30 05:30:15 PM PDT 24
Peak memory 207032 kb
Host smart-4ff26360-7f07-4f37-8504-76fb28148ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005509092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3005509092
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.41224291
Short name T744
Test name
Test status
Simulation time 11435893806 ps
CPU time 53.32 seconds
Started Jun 30 05:30:13 PM PDT 24
Finished Jun 30 05:31:07 PM PDT 24
Peak memory 249724 kb
Host smart-9eb3cd6e-24e9-4e02-9f65-0171036aa1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41224291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.41224291
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2189844476
Short name T785
Test name
Test status
Simulation time 2238717207 ps
CPU time 50.03 seconds
Started Jun 30 05:30:21 PM PDT 24
Finished Jun 30 05:31:12 PM PDT 24
Peak memory 252260 kb
Host smart-ce6407a1-3a20-44f8-91c8-e46bea8938ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189844476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2189844476
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2072940665
Short name T731
Test name
Test status
Simulation time 219480077 ps
CPU time 3.28 seconds
Started Jun 30 05:30:12 PM PDT 24
Finished Jun 30 05:30:16 PM PDT 24
Peak memory 233932 kb
Host smart-4906c637-8f32-4a96-8e58-0efcf731de2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072940665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2072940665
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2723379483
Short name T220
Test name
Test status
Simulation time 43506057968 ps
CPU time 176.62 seconds
Started Jun 30 05:30:11 PM PDT 24
Finished Jun 30 05:33:08 PM PDT 24
Peak memory 255896 kb
Host smart-907fcd75-51f0-458b-8b49-a23fdf10cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723379483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2723379483
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1277715765
Short name T103
Test name
Test status
Simulation time 60384957 ps
CPU time 2.27 seconds
Started Jun 30 05:30:11 PM PDT 24
Finished Jun 30 05:30:14 PM PDT 24
Peak memory 233020 kb
Host smart-2b26c719-611c-4523-bb71-e32d2a5872b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277715765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1277715765
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4233501974
Short name T923
Test name
Test status
Simulation time 13509803755 ps
CPU time 43.26 seconds
Started Jun 30 05:30:12 PM PDT 24
Finished Jun 30 05:30:56 PM PDT 24
Peak memory 225144 kb
Host smart-c92e318a-c79c-4324-8f26-7e1921fdf3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233501974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4233501974
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3517333194
Short name T263
Test name
Test status
Simulation time 134487758 ps
CPU time 3.34 seconds
Started Jun 30 05:30:12 PM PDT 24
Finished Jun 30 05:30:15 PM PDT 24
Peak memory 233112 kb
Host smart-74677294-7c6e-4f54-88be-08c026648b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517333194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3517333194
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3469284690
Short name T416
Test name
Test status
Simulation time 193509043 ps
CPU time 2.49 seconds
Started Jun 30 05:30:17 PM PDT 24
Finished Jun 30 05:30:20 PM PDT 24
Peak memory 224960 kb
Host smart-7d2da0dd-30d5-412d-bd21-d6bbca3cf48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469284690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3469284690
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2708299962
Short name T390
Test name
Test status
Simulation time 3933423399 ps
CPU time 9.52 seconds
Started Jun 30 05:30:13 PM PDT 24
Finished Jun 30 05:30:23 PM PDT 24
Peak memory 222188 kb
Host smart-7a4dfffe-d07f-4c2d-8165-aa6b12e8e689
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2708299962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2708299962
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.884417622
Short name T680
Test name
Test status
Simulation time 272265581869 ps
CPU time 420.25 seconds
Started Jun 30 05:30:19 PM PDT 24
Finished Jun 30 05:37:20 PM PDT 24
Peak memory 273924 kb
Host smart-373c1e65-03fb-46a6-a19c-ef9dbbab928c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884417622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.884417622
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3779449284
Short name T500
Test name
Test status
Simulation time 3727629170 ps
CPU time 4.44 seconds
Started Jun 30 05:30:13 PM PDT 24
Finished Jun 30 05:30:18 PM PDT 24
Peak memory 217232 kb
Host smart-d7418cbf-fab5-4bcf-9455-e67b5286408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779449284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3779449284
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3611248970
Short name T1001
Test name
Test status
Simulation time 1130699835 ps
CPU time 4.97 seconds
Started Jun 30 05:30:14 PM PDT 24
Finished Jun 30 05:30:19 PM PDT 24
Peak memory 216812 kb
Host smart-e2967a59-dabc-47de-aceb-e21a9f61d6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611248970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3611248970
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2498762096
Short name T738
Test name
Test status
Simulation time 99735827 ps
CPU time 2.12 seconds
Started Jun 30 05:30:10 PM PDT 24
Finished Jun 30 05:30:13 PM PDT 24
Peak memory 216724 kb
Host smart-a87d9e61-df78-40d3-9249-7d966e7eacd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498762096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2498762096
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3884958306
Short name T166
Test name
Test status
Simulation time 403616732 ps
CPU time 0.95 seconds
Started Jun 30 05:30:12 PM PDT 24
Finished Jun 30 05:30:13 PM PDT 24
Peak memory 206460 kb
Host smart-aa9cd8da-8099-4d8f-a027-4cafc0dc7621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884958306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3884958306
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2667203962
Short name T903
Test name
Test status
Simulation time 9967308234 ps
CPU time 17.48 seconds
Started Jun 30 05:30:12 PM PDT 24
Finished Jun 30 05:30:30 PM PDT 24
Peak memory 241432 kb
Host smart-02c079ab-c553-4584-b038-d6e62f8f7bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667203962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2667203962
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3985573172
Short name T537
Test name
Test status
Simulation time 89127655 ps
CPU time 0.73 seconds
Started Jun 30 05:30:28 PM PDT 24
Finished Jun 30 05:30:29 PM PDT 24
Peak memory 206152 kb
Host smart-ddb5200e-32b8-4990-bd29-580617c03c81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985573172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3985573172
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1134199582
Short name T842
Test name
Test status
Simulation time 84918891 ps
CPU time 3.26 seconds
Started Jun 30 05:30:24 PM PDT 24
Finished Jun 30 05:30:27 PM PDT 24
Peak memory 233132 kb
Host smart-8ae3d3c1-06e2-46bf-80d7-24617c5f95e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134199582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1134199582
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1547621259
Short name T545
Test name
Test status
Simulation time 32700825 ps
CPU time 0.83 seconds
Started Jun 30 05:30:21 PM PDT 24
Finished Jun 30 05:30:22 PM PDT 24
Peak memory 207300 kb
Host smart-87ced477-fb48-44d4-a003-beb9b0b9f3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547621259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1547621259
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1783729125
Short name T47
Test name
Test status
Simulation time 57657348779 ps
CPU time 78.7 seconds
Started Jun 30 05:30:25 PM PDT 24
Finished Jun 30 05:31:44 PM PDT 24
Peak memory 254100 kb
Host smart-62bba13c-d79f-43a4-b3be-364e32171c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783729125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1783729125
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1117944221
Short name T686
Test name
Test status
Simulation time 21118312665 ps
CPU time 81.64 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:31:57 PM PDT 24
Peak memory 257812 kb
Host smart-c9e81bd7-e778-4fd4-8796-5865f85463b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117944221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1117944221
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3195849361
Short name T233
Test name
Test status
Simulation time 90192969227 ps
CPU time 201.66 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:33:57 PM PDT 24
Peak memory 250748 kb
Host smart-e3664505-2d51-480e-9fbc-c99a044d32b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195849361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3195849361
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1857326449
Short name T358
Test name
Test status
Simulation time 169598443 ps
CPU time 6.11 seconds
Started Jun 30 05:30:20 PM PDT 24
Finished Jun 30 05:30:27 PM PDT 24
Peak memory 255192 kb
Host smart-ee59125c-3df1-4671-b048-20646d02172e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857326449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1857326449
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3166497635
Short name T943
Test name
Test status
Simulation time 4281455441 ps
CPU time 52.71 seconds
Started Jun 30 05:30:19 PM PDT 24
Finished Jun 30 05:31:13 PM PDT 24
Peak memory 253392 kb
Host smart-7c85c8e4-4d12-4ed1-9f18-7564c141858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166497635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3166497635
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1404172104
Short name T554
Test name
Test status
Simulation time 7782443347 ps
CPU time 14.52 seconds
Started Jun 30 05:30:24 PM PDT 24
Finished Jun 30 05:30:38 PM PDT 24
Peak memory 233336 kb
Host smart-a8be2792-83ea-4c7d-ac41-5b7ba33f0fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404172104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1404172104
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.277356040
Short name T200
Test name
Test status
Simulation time 18584904693 ps
CPU time 68.4 seconds
Started Jun 30 05:30:20 PM PDT 24
Finished Jun 30 05:31:29 PM PDT 24
Peak memory 249476 kb
Host smart-217d4e35-9bc0-4e4d-95ea-8a723020e5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277356040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.277356040
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3936505859
Short name T670
Test name
Test status
Simulation time 1349008691 ps
CPU time 4.13 seconds
Started Jun 30 05:30:24 PM PDT 24
Finished Jun 30 05:30:28 PM PDT 24
Peak memory 224984 kb
Host smart-351e2d9d-f399-4b44-b493-c7df957b3a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936505859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3936505859
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1533786465
Short name T742
Test name
Test status
Simulation time 9961226778 ps
CPU time 29.31 seconds
Started Jun 30 05:30:19 PM PDT 24
Finished Jun 30 05:30:49 PM PDT 24
Peak memory 249444 kb
Host smart-f8a35e7d-7b44-4cb2-a4de-9756de58725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533786465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1533786465
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.866132092
Short name T995
Test name
Test status
Simulation time 1823015613 ps
CPU time 5.78 seconds
Started Jun 30 05:30:19 PM PDT 24
Finished Jun 30 05:30:26 PM PDT 24
Peak memory 221072 kb
Host smart-b8951c94-4a60-4c4f-93fe-693f5d9589c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=866132092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.866132092
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2576408037
Short name T16
Test name
Test status
Simulation time 127157931 ps
CPU time 1.12 seconds
Started Jun 30 05:30:27 PM PDT 24
Finished Jun 30 05:30:29 PM PDT 24
Peak memory 208160 kb
Host smart-e5ee9e86-98bf-49b1-a5a7-1d6f86683823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576408037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2576408037
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2243337505
Short name T327
Test name
Test status
Simulation time 8687419241 ps
CPU time 18.53 seconds
Started Jun 30 05:30:19 PM PDT 24
Finished Jun 30 05:30:38 PM PDT 24
Peak memory 216964 kb
Host smart-bbee1554-6263-4cee-b4b7-1a182e9c5af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243337505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2243337505
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3920056364
Short name T646
Test name
Test status
Simulation time 61630610354 ps
CPU time 16.09 seconds
Started Jun 30 05:30:20 PM PDT 24
Finished Jun 30 05:30:37 PM PDT 24
Peak memory 217900 kb
Host smart-6f4e8a65-ff0b-4da8-bbd4-a641272321c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920056364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3920056364
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1440804409
Short name T448
Test name
Test status
Simulation time 1456472232 ps
CPU time 1.8 seconds
Started Jun 30 05:30:21 PM PDT 24
Finished Jun 30 05:30:23 PM PDT 24
Peak memory 216716 kb
Host smart-e487ea4a-6c37-4176-a3d4-2ecf78ff6c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440804409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1440804409
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.222646675
Short name T926
Test name
Test status
Simulation time 34450282 ps
CPU time 0.81 seconds
Started Jun 30 05:30:21 PM PDT 24
Finished Jun 30 05:30:22 PM PDT 24
Peak memory 206476 kb
Host smart-3e875bbd-dffd-4530-8e12-dd2ac29c90cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222646675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.222646675
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3301695248
Short name T853
Test name
Test status
Simulation time 499775723 ps
CPU time 8.32 seconds
Started Jun 30 05:30:19 PM PDT 24
Finished Jun 30 05:30:28 PM PDT 24
Peak memory 233124 kb
Host smart-b5223776-8a01-4881-be09-605ee0306e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301695248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3301695248
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.339308354
Short name T397
Test name
Test status
Simulation time 23094443 ps
CPU time 0.72 seconds
Started Jun 30 05:30:27 PM PDT 24
Finished Jun 30 05:30:28 PM PDT 24
Peak memory 205956 kb
Host smart-808cd040-cefb-42a1-8ca2-63e614f92dc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339308354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.339308354
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2744261742
Short name T547
Test name
Test status
Simulation time 470470433 ps
CPU time 3.51 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:39 PM PDT 24
Peak memory 233164 kb
Host smart-7db610d7-df30-4cfe-9384-aaabc3a01270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744261742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2744261742
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.240007844
Short name T737
Test name
Test status
Simulation time 26418225 ps
CPU time 0.82 seconds
Started Jun 30 05:30:25 PM PDT 24
Finished Jun 30 05:30:26 PM PDT 24
Peak memory 207384 kb
Host smart-8417e972-652e-4338-8ff5-77d269aeaf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240007844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.240007844
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3986493561
Short name T901
Test name
Test status
Simulation time 13162819692 ps
CPU time 53.74 seconds
Started Jun 30 05:30:36 PM PDT 24
Finished Jun 30 05:31:31 PM PDT 24
Peak memory 251768 kb
Host smart-09c069c5-1ece-436e-837f-f9f670261432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986493561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3986493561
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3394044776
Short name T136
Test name
Test status
Simulation time 3875645098 ps
CPU time 92.7 seconds
Started Jun 30 05:30:28 PM PDT 24
Finished Jun 30 05:32:01 PM PDT 24
Peak memory 266268 kb
Host smart-8a3cf33d-3b5c-4ebd-9eb9-0bc00968be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394044776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3394044776
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2085293251
Short name T52
Test name
Test status
Simulation time 24397320548 ps
CPU time 77.41 seconds
Started Jun 30 05:30:28 PM PDT 24
Finished Jun 30 05:31:45 PM PDT 24
Peak memory 241660 kb
Host smart-c9f94396-a866-417f-9254-5866e2b1321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085293251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2085293251
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2142532324
Short name T857
Test name
Test status
Simulation time 836178671 ps
CPU time 15.09 seconds
Started Jun 30 05:30:26 PM PDT 24
Finished Jun 30 05:30:41 PM PDT 24
Peak memory 237848 kb
Host smart-2079e9ee-81f2-4ed1-99fc-3e1ef6f03b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142532324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2142532324
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1849434921
Short name T183
Test name
Test status
Simulation time 17015682204 ps
CPU time 124 seconds
Started Jun 30 05:30:37 PM PDT 24
Finished Jun 30 05:32:41 PM PDT 24
Peak memory 249664 kb
Host smart-5c247619-f0f5-4507-be6d-ef0acd93deb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849434921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1849434921
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3218525910
Short name T622
Test name
Test status
Simulation time 152689747 ps
CPU time 4.01 seconds
Started Jun 30 05:30:27 PM PDT 24
Finished Jun 30 05:30:31 PM PDT 24
Peak memory 225044 kb
Host smart-1a09a9fd-db4d-46e2-8416-b446c1107674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218525910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3218525910
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1012476129
Short name T917
Test name
Test status
Simulation time 1266175875 ps
CPU time 19.1 seconds
Started Jun 30 05:30:26 PM PDT 24
Finished Jun 30 05:30:46 PM PDT 24
Peak memory 225192 kb
Host smart-6c030fff-4951-4a7f-8fe1-1323cc2e7ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012476129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1012476129
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2328599495
Short name T958
Test name
Test status
Simulation time 862969112 ps
CPU time 6.49 seconds
Started Jun 30 05:30:28 PM PDT 24
Finished Jun 30 05:30:35 PM PDT 24
Peak memory 233428 kb
Host smart-aecae355-118c-43e0-a34c-02bb92cca072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328599495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2328599495
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2824961672
Short name T211
Test name
Test status
Simulation time 1684880640 ps
CPU time 10.27 seconds
Started Jun 30 05:30:26 PM PDT 24
Finished Jun 30 05:30:37 PM PDT 24
Peak memory 240292 kb
Host smart-a48d670f-de34-4b2e-8efe-c4826fdad283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824961672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2824961672
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3451234504
Short name T763
Test name
Test status
Simulation time 2698283773 ps
CPU time 6 seconds
Started Jun 30 05:30:25 PM PDT 24
Finished Jun 30 05:30:32 PM PDT 24
Peak memory 223720 kb
Host smart-59ecc3c0-1015-4335-88e0-a728a873ddd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3451234504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3451234504
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2688445771
Short name T135
Test name
Test status
Simulation time 2703883897 ps
CPU time 40.58 seconds
Started Jun 30 05:30:27 PM PDT 24
Finished Jun 30 05:31:08 PM PDT 24
Peak memory 256672 kb
Host smart-cc81fe50-13c0-4a53-8442-1a1ed4f621de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688445771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2688445771
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1675795529
Short name T523
Test name
Test status
Simulation time 7537362908 ps
CPU time 27.9 seconds
Started Jun 30 05:30:28 PM PDT 24
Finished Jun 30 05:30:56 PM PDT 24
Peak memory 216876 kb
Host smart-2c733bd3-1273-442d-bae9-a188a180650f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675795529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1675795529
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.250608459
Short name T337
Test name
Test status
Simulation time 11006048 ps
CPU time 0.71 seconds
Started Jun 30 05:30:26 PM PDT 24
Finished Jun 30 05:30:27 PM PDT 24
Peak memory 206164 kb
Host smart-94df8861-3c6b-453a-8e1b-3d4b93339a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250608459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.250608459
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1702248173
Short name T571
Test name
Test status
Simulation time 68281457 ps
CPU time 1.21 seconds
Started Jun 30 05:30:27 PM PDT 24
Finished Jun 30 05:30:29 PM PDT 24
Peak memory 216788 kb
Host smart-2d76752d-ce6f-4754-80d8-697f46a1c9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702248173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1702248173
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.4140172389
Short name T89
Test name
Test status
Simulation time 208075762 ps
CPU time 0.84 seconds
Started Jun 30 05:30:25 PM PDT 24
Finished Jun 30 05:30:26 PM PDT 24
Peak memory 206824 kb
Host smart-398e0700-a6ab-4874-8564-7ce88fd4fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140172389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4140172389
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3625930958
Short name T507
Test name
Test status
Simulation time 1885675574 ps
CPU time 7.18 seconds
Started Jun 30 05:30:37 PM PDT 24
Finished Jun 30 05:30:44 PM PDT 24
Peak memory 239156 kb
Host smart-22b586b3-1f87-4292-8cf7-f6837b67a6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625930958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3625930958
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.607246358
Short name T755
Test name
Test status
Simulation time 43458996 ps
CPU time 0.68 seconds
Started Jun 30 05:30:32 PM PDT 24
Finished Jun 30 05:30:33 PM PDT 24
Peak memory 206212 kb
Host smart-99181b99-c816-4f5e-985c-c6482754c4c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607246358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.607246358
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.9749226
Short name T770
Test name
Test status
Simulation time 2429865473 ps
CPU time 5.53 seconds
Started Jun 30 05:30:33 PM PDT 24
Finished Jun 30 05:30:39 PM PDT 24
Peak memory 225096 kb
Host smart-9308c4e4-2dc7-4f0c-9188-9978949c0cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9749226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.9749226
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3262997745
Short name T795
Test name
Test status
Simulation time 59795415 ps
CPU time 0.77 seconds
Started Jun 30 05:30:27 PM PDT 24
Finished Jun 30 05:30:28 PM PDT 24
Peak memory 207116 kb
Host smart-22cfa4d7-1457-4e15-8da6-3b26bc5716fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262997745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3262997745
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2170204940
Short name T301
Test name
Test status
Simulation time 1889486926 ps
CPU time 8.25 seconds
Started Jun 30 05:30:37 PM PDT 24
Finished Jun 30 05:30:46 PM PDT 24
Peak memory 234052 kb
Host smart-555b4a74-9a35-443e-b0c5-f53a03be4f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170204940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2170204940
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2667938866
Short name T858
Test name
Test status
Simulation time 98557569386 ps
CPU time 66.08 seconds
Started Jun 30 05:30:36 PM PDT 24
Finished Jun 30 05:31:43 PM PDT 24
Peak memory 241668 kb
Host smart-14c6ae28-a833-4b3b-81bf-625da7fbcbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667938866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2667938866
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3254521781
Short name T316
Test name
Test status
Simulation time 1624233019 ps
CPU time 11.32 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:47 PM PDT 24
Peak memory 225040 kb
Host smart-7a36392d-3928-4b09-9605-38f4254be804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254521781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3254521781
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2013765328
Short name T535
Test name
Test status
Simulation time 20459724640 ps
CPU time 148.9 seconds
Started Jun 30 05:30:34 PM PDT 24
Finished Jun 30 05:33:04 PM PDT 24
Peak memory 254084 kb
Host smart-b37dbb0e-c565-40c7-8faf-e7ca36f08211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013765328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2013765328
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3355517687
Short name T336
Test name
Test status
Simulation time 376746642 ps
CPU time 7.97 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:44 PM PDT 24
Peak memory 240956 kb
Host smart-ba47876a-52d5-4a8a-9705-8ba1e7713763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355517687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3355517687
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1551075568
Short name T908
Test name
Test status
Simulation time 172448666 ps
CPU time 2.14 seconds
Started Jun 30 05:30:33 PM PDT 24
Finished Jun 30 05:30:35 PM PDT 24
Peak memory 225196 kb
Host smart-b579d226-aa09-4aeb-8d33-4e12a9429d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551075568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1551075568
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3638543268
Short name T871
Test name
Test status
Simulation time 17312739543 ps
CPU time 26.61 seconds
Started Jun 30 05:30:36 PM PDT 24
Finished Jun 30 05:31:03 PM PDT 24
Peak memory 234784 kb
Host smart-331bf7cc-e780-43ad-b1f0-095a66814277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638543268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3638543268
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1217353798
Short name T823
Test name
Test status
Simulation time 577013055 ps
CPU time 3.82 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:40 PM PDT 24
Peak memory 223796 kb
Host smart-1890a614-4c9b-4a65-a324-d80469238b76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1217353798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1217353798
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.261635360
Short name T34
Test name
Test status
Simulation time 15379557674 ps
CPU time 148.32 seconds
Started Jun 30 05:30:32 PM PDT 24
Finished Jun 30 05:33:01 PM PDT 24
Peak memory 249992 kb
Host smart-7a4929c2-0103-4c6c-8117-140d53e1992e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261635360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.261635360
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1486013239
Short name T325
Test name
Test status
Simulation time 4964848716 ps
CPU time 23.14 seconds
Started Jun 30 05:30:33 PM PDT 24
Finished Jun 30 05:30:56 PM PDT 24
Peak memory 216896 kb
Host smart-90b68f2e-bab5-41b5-a0af-745a5ef74676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486013239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1486013239
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1598848871
Short name T532
Test name
Test status
Simulation time 1001781927 ps
CPU time 4.46 seconds
Started Jun 30 05:30:34 PM PDT 24
Finished Jun 30 05:30:39 PM PDT 24
Peak memory 216800 kb
Host smart-5832da4d-4031-4038-97fb-456ba59b3965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598848871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1598848871
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1184604305
Short name T852
Test name
Test status
Simulation time 47609992 ps
CPU time 0.86 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:36 PM PDT 24
Peak memory 206976 kb
Host smart-46208474-04fe-445c-9d60-619f954bad86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184604305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1184604305
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.26224564
Short name T973
Test name
Test status
Simulation time 282802427 ps
CPU time 1.16 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:37 PM PDT 24
Peak memory 207492 kb
Host smart-628d9def-ef8d-4bea-96fb-c9893c0c3b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26224564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.26224564
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1254254927
Short name T53
Test name
Test status
Simulation time 514608598 ps
CPU time 5.88 seconds
Started Jun 30 05:30:33 PM PDT 24
Finished Jun 30 05:30:40 PM PDT 24
Peak memory 233212 kb
Host smart-4cd27d45-0f80-4412-9544-2fd36c337729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254254927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1254254927
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1414445692
Short name T859
Test name
Test status
Simulation time 32872305 ps
CPU time 0.74 seconds
Started Jun 30 05:30:39 PM PDT 24
Finished Jun 30 05:30:41 PM PDT 24
Peak memory 205364 kb
Host smart-e7cba0e4-4360-408c-81e6-7c1958003f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414445692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1414445692
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1382914863
Short name T677
Test name
Test status
Simulation time 3928602803 ps
CPU time 9.5 seconds
Started Jun 30 05:30:36 PM PDT 24
Finished Jun 30 05:30:47 PM PDT 24
Peak memory 233328 kb
Host smart-8820402b-bb2e-4d60-80a1-5850f0e9ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382914863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1382914863
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3565585784
Short name T381
Test name
Test status
Simulation time 53726389 ps
CPU time 0.75 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:37 PM PDT 24
Peak memory 206076 kb
Host smart-bd072850-c18e-4749-a87c-e4ce074c4c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565585784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3565585784
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1354243436
Short name T43
Test name
Test status
Simulation time 13448382193 ps
CPU time 100.78 seconds
Started Jun 30 05:30:43 PM PDT 24
Finished Jun 30 05:32:25 PM PDT 24
Peak memory 257316 kb
Host smart-b5ef2d4b-623d-4353-a558-82a3bb9eb277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354243436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1354243436
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3301719702
Short name T938
Test name
Test status
Simulation time 26469582892 ps
CPU time 31.79 seconds
Started Jun 30 05:30:44 PM PDT 24
Finished Jun 30 05:31:17 PM PDT 24
Peak memory 241612 kb
Host smart-f7ddbee0-2132-49ca-b737-8027d348834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301719702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3301719702
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1121304666
Short name T133
Test name
Test status
Simulation time 37440978953 ps
CPU time 171.65 seconds
Started Jun 30 05:30:41 PM PDT 24
Finished Jun 30 05:33:34 PM PDT 24
Peak memory 255004 kb
Host smart-94b9e9b1-645c-4597-a2da-545bf96328a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121304666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1121304666
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2516528413
Short name T944
Test name
Test status
Simulation time 919947792 ps
CPU time 6.59 seconds
Started Jun 30 05:30:42 PM PDT 24
Finished Jun 30 05:30:50 PM PDT 24
Peak memory 233188 kb
Host smart-9c8be59e-0860-4c31-8b84-9090a7c48686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516528413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2516528413
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1853935870
Short name T372
Test name
Test status
Simulation time 22936663 ps
CPU time 0.77 seconds
Started Jun 30 05:30:42 PM PDT 24
Finished Jun 30 05:30:45 PM PDT 24
Peak memory 216392 kb
Host smart-57fbe99e-5862-4b60-8ab6-5aebba7a12d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853935870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1853935870
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.341211936
Short name T988
Test name
Test status
Simulation time 6493225172 ps
CPU time 36.46 seconds
Started Jun 30 05:30:33 PM PDT 24
Finished Jun 30 05:31:10 PM PDT 24
Peak memory 225168 kb
Host smart-9948c84d-3b83-4a10-b57c-f4cc4bd26b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341211936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.341211936
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1743016946
Short name T458
Test name
Test status
Simulation time 60079571 ps
CPU time 2.34 seconds
Started Jun 30 05:30:34 PM PDT 24
Finished Jun 30 05:30:37 PM PDT 24
Peak memory 232892 kb
Host smart-0a1f6551-a9cb-4654-9523-737f6be02749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743016946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1743016946
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1619890218
Short name T511
Test name
Test status
Simulation time 2365531122 ps
CPU time 5.05 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:41 PM PDT 24
Peak memory 225092 kb
Host smart-80513a26-83a2-4eb4-a667-fd306ad549b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619890218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1619890218
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1601067692
Short name T440
Test name
Test status
Simulation time 1915793259 ps
CPU time 5.75 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:42 PM PDT 24
Peak memory 240808 kb
Host smart-e85ca9c2-e84b-49b7-a834-0e1ae680873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601067692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1601067692
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2739943032
Short name T167
Test name
Test status
Simulation time 157673113 ps
CPU time 4.68 seconds
Started Jun 30 05:30:42 PM PDT 24
Finished Jun 30 05:30:48 PM PDT 24
Peak memory 223616 kb
Host smart-572cf34d-82b1-40eb-b696-06163f2da843
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2739943032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2739943032
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1158399323
Short name T528
Test name
Test status
Simulation time 44607367002 ps
CPU time 406.71 seconds
Started Jun 30 05:30:43 PM PDT 24
Finished Jun 30 05:37:32 PM PDT 24
Peak memory 268896 kb
Host smart-5b5e0b2f-eb45-4080-8302-50616f257581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158399323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1158399323
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.803652684
Short name T8
Test name
Test status
Simulation time 6738464290 ps
CPU time 14.03 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:50 PM PDT 24
Peak memory 217056 kb
Host smart-2b7600d4-e970-4681-b92b-c77e41b1db54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803652684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.803652684
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3840156363
Short name T444
Test name
Test status
Simulation time 11861663920 ps
CPU time 22.64 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:58 PM PDT 24
Peak memory 216908 kb
Host smart-8e9ab0b1-da17-41f6-9d4c-f4495b86ef14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840156363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3840156363
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3766383523
Short name T471
Test name
Test status
Simulation time 61863206 ps
CPU time 3.61 seconds
Started Jun 30 05:30:35 PM PDT 24
Finished Jun 30 05:30:40 PM PDT 24
Peak memory 216772 kb
Host smart-e8619a4c-258b-46f1-8171-77347eaea7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766383523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3766383523
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2670598073
Short name T526
Test name
Test status
Simulation time 20451414 ps
CPU time 0.7 seconds
Started Jun 30 05:30:33 PM PDT 24
Finished Jun 30 05:30:34 PM PDT 24
Peak memory 206068 kb
Host smart-c128ccea-de27-4281-a00f-56b03f05a806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670598073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2670598073
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2102000561
Short name T638
Test name
Test status
Simulation time 7235722005 ps
CPU time 14.43 seconds
Started Jun 30 05:30:37 PM PDT 24
Finished Jun 30 05:30:52 PM PDT 24
Peak memory 233068 kb
Host smart-9939e1a5-0d03-4a0f-9385-27567fd3f6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102000561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2102000561
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1162762559
Short name T814
Test name
Test status
Simulation time 36512138 ps
CPU time 0.7 seconds
Started Jun 30 05:30:41 PM PDT 24
Finished Jun 30 05:30:43 PM PDT 24
Peak memory 206276 kb
Host smart-5d475187-6aac-46d4-8c47-974e0770f9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162762559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1162762559
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4022826800
Short name T466
Test name
Test status
Simulation time 379367752 ps
CPU time 7.34 seconds
Started Jun 30 05:30:40 PM PDT 24
Finished Jun 30 05:30:48 PM PDT 24
Peak memory 233132 kb
Host smart-1d3cfc0f-3d78-41d7-ba4b-678d7d14586e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022826800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4022826800
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3385508671
Short name T67
Test name
Test status
Simulation time 35868115 ps
CPU time 0.77 seconds
Started Jun 30 05:30:42 PM PDT 24
Finished Jun 30 05:30:45 PM PDT 24
Peak memory 206004 kb
Host smart-cd650357-00a8-46c4-b4b0-be6a666722c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385508671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3385508671
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3820652501
Short name T964
Test name
Test status
Simulation time 19933685352 ps
CPU time 200.37 seconds
Started Jun 30 05:30:44 PM PDT 24
Finished Jun 30 05:34:06 PM PDT 24
Peak memory 253884 kb
Host smart-68f33804-bbda-4daf-a86e-af9663564642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820652501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3820652501
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.944040170
Short name T35
Test name
Test status
Simulation time 19992013525 ps
CPU time 92.91 seconds
Started Jun 30 05:30:48 PM PDT 24
Finished Jun 30 05:32:22 PM PDT 24
Peak memory 257984 kb
Host smart-8b077a8f-2989-4892-9aa8-8009e1b99d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944040170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.944040170
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.528546025
Short name T616
Test name
Test status
Simulation time 3148964463 ps
CPU time 44.18 seconds
Started Jun 30 05:30:41 PM PDT 24
Finished Jun 30 05:31:27 PM PDT 24
Peak memory 233316 kb
Host smart-64a3cae3-ab3c-4e17-a3b3-fcfe4c641b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528546025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.528546025
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.70582250
Short name T633
Test name
Test status
Simulation time 1752640213 ps
CPU time 8.84 seconds
Started Jun 30 05:30:42 PM PDT 24
Finished Jun 30 05:30:52 PM PDT 24
Peak memory 240944 kb
Host smart-9ad8082b-e91a-4d9a-9aea-1a4284dd273d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70582250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.70582250
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.435558040
Short name T212
Test name
Test status
Simulation time 53276093 ps
CPU time 2.67 seconds
Started Jun 30 05:30:42 PM PDT 24
Finished Jun 30 05:30:46 PM PDT 24
Peak memory 224924 kb
Host smart-75476f47-218f-4c64-b15f-91e653ace058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435558040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.435558040
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2948790493
Short name T719
Test name
Test status
Simulation time 528595795 ps
CPU time 8.18 seconds
Started Jun 30 05:30:40 PM PDT 24
Finished Jun 30 05:30:48 PM PDT 24
Peak memory 233236 kb
Host smart-c543f149-aba3-42c6-a04e-9a461b38e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948790493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2948790493
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2736472944
Short name T772
Test name
Test status
Simulation time 24169635456 ps
CPU time 16.2 seconds
Started Jun 30 05:30:41 PM PDT 24
Finished Jun 30 05:30:58 PM PDT 24
Peak memory 236292 kb
Host smart-a8135da3-0644-4b5d-b01c-855741c750c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736472944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2736472944
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2807212108
Short name T495
Test name
Test status
Simulation time 521668262 ps
CPU time 6.24 seconds
Started Jun 30 05:30:42 PM PDT 24
Finished Jun 30 05:30:50 PM PDT 24
Peak memory 225032 kb
Host smart-c9150f32-4c65-4f09-ae42-e3f7a734b7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807212108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2807212108
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2009979195
Short name T984
Test name
Test status
Simulation time 3775880233 ps
CPU time 14.38 seconds
Started Jun 30 05:30:42 PM PDT 24
Finished Jun 30 05:30:58 PM PDT 24
Peak memory 221504 kb
Host smart-0a43ceac-dab1-4891-9990-bdfecd081d1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2009979195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2009979195
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2574191062
Short name T874
Test name
Test status
Simulation time 4625126713 ps
CPU time 24.13 seconds
Started Jun 30 05:30:48 PM PDT 24
Finished Jun 30 05:31:13 PM PDT 24
Peak memory 216924 kb
Host smart-0e0e0415-2bb3-4326-8726-2602bc55375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574191062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2574191062
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1492350743
Short name T578
Test name
Test status
Simulation time 700062612 ps
CPU time 4.87 seconds
Started Jun 30 05:30:45 PM PDT 24
Finished Jun 30 05:30:50 PM PDT 24
Peak memory 216760 kb
Host smart-5f41dc8d-e93d-4f26-ac03-8ed81cf869c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492350743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1492350743
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1991842686
Short name T31
Test name
Test status
Simulation time 1765426954 ps
CPU time 4.31 seconds
Started Jun 30 05:30:46 PM PDT 24
Finished Jun 30 05:30:51 PM PDT 24
Peak memory 216772 kb
Host smart-08198e7d-c351-44ea-bd6b-7c616f0e903d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991842686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1991842686
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1722227656
Short name T588
Test name
Test status
Simulation time 70414808 ps
CPU time 0.84 seconds
Started Jun 30 05:30:41 PM PDT 24
Finished Jun 30 05:30:43 PM PDT 24
Peak memory 206472 kb
Host smart-3f1d5e3a-1788-4095-9572-1101f059c1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722227656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1722227656
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1247260139
Short name T601
Test name
Test status
Simulation time 12424747049 ps
CPU time 43.39 seconds
Started Jun 30 05:30:40 PM PDT 24
Finished Jun 30 05:31:24 PM PDT 24
Peak memory 241332 kb
Host smart-0f9aad49-582f-4f12-a8be-70b56f411986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247260139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1247260139
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4117621854
Short name T415
Test name
Test status
Simulation time 13525092 ps
CPU time 0.72 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:30:52 PM PDT 24
Peak memory 205928 kb
Host smart-ef23c7ae-0a63-4303-bcf6-412ea98c1c42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117621854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4117621854
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3991522138
Short name T497
Test name
Test status
Simulation time 460752230 ps
CPU time 4.47 seconds
Started Jun 30 05:30:43 PM PDT 24
Finished Jun 30 05:30:49 PM PDT 24
Peak memory 224960 kb
Host smart-2d7639be-a056-4c5e-8536-b9f19d201472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991522138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3991522138
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2109363744
Short name T524
Test name
Test status
Simulation time 135365528 ps
CPU time 0.86 seconds
Started Jun 30 05:30:42 PM PDT 24
Finished Jun 30 05:30:45 PM PDT 24
Peak memory 207300 kb
Host smart-55fe4450-1c94-4c79-a5ea-6acde8771451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109363744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2109363744
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2080764124
Short name T203
Test name
Test status
Simulation time 55536608439 ps
CPU time 135.27 seconds
Started Jun 30 05:30:48 PM PDT 24
Finished Jun 30 05:33:05 PM PDT 24
Peak memory 257036 kb
Host smart-792f41de-1c91-46f6-845b-c315f2777136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080764124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2080764124
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1691964483
Short name T223
Test name
Test status
Simulation time 27390943249 ps
CPU time 306 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:35:56 PM PDT 24
Peak memory 249792 kb
Host smart-a095381d-5fc5-4511-a30b-8710d058f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691964483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1691964483
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3950410119
Short name T932
Test name
Test status
Simulation time 1661599919 ps
CPU time 9.4 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:30:59 PM PDT 24
Peak memory 224964 kb
Host smart-10c5ac2b-b49b-4508-9eac-b1207e77b93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950410119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3950410119
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3423891227
Short name T703
Test name
Test status
Simulation time 81145472844 ps
CPU time 272.2 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:35:24 PM PDT 24
Peak memory 251360 kb
Host smart-431805a5-c036-4e44-a7b9-dd0e0a329795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423891227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3423891227
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.569602769
Short name T894
Test name
Test status
Simulation time 5232066345 ps
CPU time 16.9 seconds
Started Jun 30 05:30:41 PM PDT 24
Finished Jun 30 05:30:59 PM PDT 24
Peak memory 233332 kb
Host smart-35c66542-c3ce-44be-a551-b0fa7e77c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569602769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.569602769
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.811105627
Short name T335
Test name
Test status
Simulation time 593521814 ps
CPU time 9.65 seconds
Started Jun 30 05:30:40 PM PDT 24
Finished Jun 30 05:30:51 PM PDT 24
Peak memory 233180 kb
Host smart-0e4953b9-a871-4015-8942-55e3523d9508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811105627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.811105627
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2353984038
Short name T300
Test name
Test status
Simulation time 4850000185 ps
CPU time 16.73 seconds
Started Jun 30 05:30:48 PM PDT 24
Finished Jun 30 05:31:05 PM PDT 24
Peak memory 234356 kb
Host smart-0b80a92b-ba8d-41cf-b38a-d215392db3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353984038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2353984038
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2468561650
Short name T333
Test name
Test status
Simulation time 293570381 ps
CPU time 2.44 seconds
Started Jun 30 05:30:40 PM PDT 24
Finished Jun 30 05:30:44 PM PDT 24
Peak memory 224508 kb
Host smart-40a1efd3-9ab4-4788-abc3-7623527cd0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468561650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2468561650
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.840583292
Short name T450
Test name
Test status
Simulation time 140026861 ps
CPU time 4.28 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:30:56 PM PDT 24
Peak memory 220700 kb
Host smart-84aa753b-c84e-4e88-9a99-f5ddda522718
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=840583292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.840583292
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.334250687
Short name T580
Test name
Test status
Simulation time 22151631752 ps
CPU time 47.61 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:31:39 PM PDT 24
Peak memory 225196 kb
Host smart-0396125e-19d7-408a-996f-41efc082f674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334250687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.334250687
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1028642541
Short name T328
Test name
Test status
Simulation time 8569971764 ps
CPU time 28.33 seconds
Started Jun 30 05:30:43 PM PDT 24
Finished Jun 30 05:31:13 PM PDT 24
Peak memory 220800 kb
Host smart-13c990c6-c721-446d-877c-753572e31641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028642541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1028642541
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3036560083
Short name T367
Test name
Test status
Simulation time 17799785504 ps
CPU time 10.5 seconds
Started Jun 30 05:30:40 PM PDT 24
Finished Jun 30 05:30:51 PM PDT 24
Peak memory 216900 kb
Host smart-0c4eaef4-2514-48ff-9242-4b4d37fd231a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036560083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3036560083
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3731731198
Short name T645
Test name
Test status
Simulation time 32062873 ps
CPU time 1.12 seconds
Started Jun 30 05:30:43 PM PDT 24
Finished Jun 30 05:30:46 PM PDT 24
Peak memory 208308 kb
Host smart-9f0b0625-d9a4-4be5-b36f-107f6113b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731731198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3731731198
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1324668064
Short name T593
Test name
Test status
Simulation time 33577189 ps
CPU time 0.8 seconds
Started Jun 30 05:30:44 PM PDT 24
Finished Jun 30 05:30:46 PM PDT 24
Peak memory 206472 kb
Host smart-302b4ce1-6472-4370-a4d5-1d391c9bfd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324668064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1324668064
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.4187372894
Short name T996
Test name
Test status
Simulation time 2209650449 ps
CPU time 8.99 seconds
Started Jun 30 05:30:40 PM PDT 24
Finished Jun 30 05:30:50 PM PDT 24
Peak memory 241496 kb
Host smart-f25de61b-61d2-45fe-8ffb-7bfa9f8975ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187372894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4187372894
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.180051721
Short name T394
Test name
Test status
Simulation time 43435534 ps
CPU time 0.75 seconds
Started Jun 30 05:29:35 PM PDT 24
Finished Jun 30 05:29:36 PM PDT 24
Peak memory 205924 kb
Host smart-cff39b93-ef8b-4d5c-a91d-d8153653d73f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180051721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.180051721
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3290647557
Short name T465
Test name
Test status
Simulation time 1630327773 ps
CPU time 16.24 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:29:53 PM PDT 24
Peak memory 233184 kb
Host smart-712d8b90-c925-471f-a254-d13f7a529f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290647557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3290647557
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.188167459
Short name T28
Test name
Test status
Simulation time 77583996 ps
CPU time 0.78 seconds
Started Jun 30 05:29:27 PM PDT 24
Finished Jun 30 05:29:28 PM PDT 24
Peak memory 206080 kb
Host smart-b6ab7e08-b6cc-4f0d-92ae-f5d2f6073da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188167459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.188167459
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3892666970
Short name T697
Test name
Test status
Simulation time 9213272108 ps
CPU time 119.02 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:31:35 PM PDT 24
Peak memory 258156 kb
Host smart-8a6f78ed-4599-46c2-bde8-b3315a67321a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892666970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3892666970
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.606199244
Short name T729
Test name
Test status
Simulation time 2468107025 ps
CPU time 58.91 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:30:35 PM PDT 24
Peak memory 256652 kb
Host smart-d27e36fa-d621-4e84-8106-b18d8936c742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606199244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.606199244
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1143946006
Short name T277
Test name
Test status
Simulation time 29161284811 ps
CPU time 319.65 seconds
Started Jun 30 05:29:37 PM PDT 24
Finished Jun 30 05:34:57 PM PDT 24
Peak memory 256720 kb
Host smart-84405bc4-6cab-448b-9700-f411eedd185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143946006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1143946006
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2897210597
Short name T809
Test name
Test status
Simulation time 2248440279 ps
CPU time 38.22 seconds
Started Jun 30 05:29:34 PM PDT 24
Finished Jun 30 05:30:13 PM PDT 24
Peak memory 241572 kb
Host smart-1e75bf73-b2f8-4390-aefa-f730709407fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897210597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2897210597
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1450481250
Short name T184
Test name
Test status
Simulation time 3373085368 ps
CPU time 46.72 seconds
Started Jun 30 05:29:37 PM PDT 24
Finished Jun 30 05:30:24 PM PDT 24
Peak memory 249732 kb
Host smart-1c909d13-291c-4b39-a65e-c7f293d955b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450481250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1450481250
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2815378275
Short name T773
Test name
Test status
Simulation time 2230946640 ps
CPU time 6.31 seconds
Started Jun 30 05:29:34 PM PDT 24
Finished Jun 30 05:29:41 PM PDT 24
Peak memory 225124 kb
Host smart-3468b7a3-b449-4d5d-90ce-dccc7a1e1344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815378275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2815378275
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2538969190
Short name T801
Test name
Test status
Simulation time 14738784410 ps
CPU time 55.63 seconds
Started Jun 30 05:29:34 PM PDT 24
Finished Jun 30 05:30:30 PM PDT 24
Peak memory 240568 kb
Host smart-b9b3eec3-2c38-4d26-b408-f0e6c94490ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538969190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2538969190
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.710878537
Short name T439
Test name
Test status
Simulation time 596046376 ps
CPU time 2.8 seconds
Started Jun 30 05:29:38 PM PDT 24
Finished Jun 30 05:29:41 PM PDT 24
Peak memory 225028 kb
Host smart-a48938f5-c1d5-44e8-8e76-f77842db4626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710878537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
710878537
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1202149062
Short name T819
Test name
Test status
Simulation time 1152946321 ps
CPU time 6.22 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:29:43 PM PDT 24
Peak memory 225032 kb
Host smart-c4f27885-7048-4408-b973-1e0b2423c843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202149062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1202149062
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3042331244
Short name T787
Test name
Test status
Simulation time 2244019856 ps
CPU time 6.37 seconds
Started Jun 30 05:29:38 PM PDT 24
Finished Jun 30 05:29:45 PM PDT 24
Peak memory 223444 kb
Host smart-8aeda518-dc0b-494b-b81e-e68d176c8fa9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3042331244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3042331244
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3095572093
Short name T18
Test name
Test status
Simulation time 129488357 ps
CPU time 0.96 seconds
Started Jun 30 05:29:35 PM PDT 24
Finished Jun 30 05:29:36 PM PDT 24
Peak memory 236972 kb
Host smart-e72fb397-753a-4ffd-8a79-e780b7df116b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095572093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3095572093
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1793252194
Short name T140
Test name
Test status
Simulation time 17394572184 ps
CPU time 268.24 seconds
Started Jun 30 05:29:37 PM PDT 24
Finished Jun 30 05:34:06 PM PDT 24
Peak memory 282024 kb
Host smart-173dd13b-7170-4bac-ad32-3b69080a2fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793252194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1793252194
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1199044102
Short name T793
Test name
Test status
Simulation time 5428507393 ps
CPU time 19.91 seconds
Started Jun 30 05:29:26 PM PDT 24
Finished Jun 30 05:29:46 PM PDT 24
Peak memory 220864 kb
Host smart-1696f601-3e88-49ee-83e4-1866c4815415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199044102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1199044102
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2207183080
Short name T602
Test name
Test status
Simulation time 833425479 ps
CPU time 4.47 seconds
Started Jun 30 05:29:27 PM PDT 24
Finished Jun 30 05:29:31 PM PDT 24
Peak memory 216728 kb
Host smart-a34d1743-cc80-435a-93ad-19e3c194e0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207183080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2207183080
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4180146321
Short name T702
Test name
Test status
Simulation time 355376175 ps
CPU time 1.6 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:29:38 PM PDT 24
Peak memory 216828 kb
Host smart-2324f7a0-e4ee-4826-8def-d16417ea8f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180146321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4180146321
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.661792430
Short name T796
Test name
Test status
Simulation time 171287178 ps
CPU time 1.02 seconds
Started Jun 30 05:29:28 PM PDT 24
Finished Jun 30 05:29:29 PM PDT 24
Peak memory 206452 kb
Host smart-e919c4b6-1d5f-43de-bb27-fc426fbd318d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661792430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.661792430
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3679707863
Short name T525
Test name
Test status
Simulation time 4667272635 ps
CPU time 13.81 seconds
Started Jun 30 05:29:34 PM PDT 24
Finished Jun 30 05:29:48 PM PDT 24
Peak memory 233352 kb
Host smart-1a3ddbc2-ad00-4c10-9789-c275c664052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679707863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3679707863
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1834359540
Short name T389
Test name
Test status
Simulation time 15169382 ps
CPU time 0.75 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:30:51 PM PDT 24
Peak memory 205364 kb
Host smart-5740d4d2-9fcd-422f-887b-30ff96222e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834359540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1834359540
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2252508962
Short name T709
Test name
Test status
Simulation time 187600136 ps
CPU time 2.02 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:30:52 PM PDT 24
Peak memory 224776 kb
Host smart-fd44bcd9-b87e-494e-8722-74c050c55cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252508962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2252508962
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1402562280
Short name T684
Test name
Test status
Simulation time 16667403 ps
CPU time 0.79 seconds
Started Jun 30 05:30:48 PM PDT 24
Finished Jun 30 05:30:50 PM PDT 24
Peak memory 207424 kb
Host smart-407304b2-580b-4deb-851f-b85d7b4882fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402562280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1402562280
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1138859078
Short name T208
Test name
Test status
Simulation time 326802529630 ps
CPU time 204.14 seconds
Started Jun 30 05:30:48 PM PDT 24
Finished Jun 30 05:34:13 PM PDT 24
Peak memory 250004 kb
Host smart-8d32616b-9ebe-4237-9fee-78dcea4f6a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138859078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1138859078
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2239902415
Short name T997
Test name
Test status
Simulation time 18047150543 ps
CPU time 163.74 seconds
Started Jun 30 05:30:48 PM PDT 24
Finished Jun 30 05:33:32 PM PDT 24
Peak memory 257720 kb
Host smart-db26517a-2e5d-46d4-abf4-2286aae8e16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239902415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2239902415
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2994438292
Short name T76
Test name
Test status
Simulation time 11296627959 ps
CPU time 35.34 seconds
Started Jun 30 05:30:51 PM PDT 24
Finished Jun 30 05:31:27 PM PDT 24
Peak memory 235376 kb
Host smart-0ff12475-d287-4d8a-b817-5236f42edd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994438292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2994438292
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1628620560
Short name T919
Test name
Test status
Simulation time 30271484808 ps
CPU time 216.48 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:34:26 PM PDT 24
Peak memory 265908 kb
Host smart-477a7242-4e75-4055-a6d3-fcd63a6b570f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628620560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1628620560
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1036686181
Short name T890
Test name
Test status
Simulation time 1227852757 ps
CPU time 11.91 seconds
Started Jun 30 05:30:48 PM PDT 24
Finished Jun 30 05:31:00 PM PDT 24
Peak memory 221300 kb
Host smart-f11c6366-126d-4f3d-a275-4765bb951007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036686181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1036686181
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3258437557
Short name T558
Test name
Test status
Simulation time 13111447262 ps
CPU time 39.8 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:31:29 PM PDT 24
Peak memory 235512 kb
Host smart-a85a59ec-ac69-4e35-86c8-59642c10bda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258437557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3258437557
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2390685102
Short name T991
Test name
Test status
Simulation time 8231599769 ps
CPU time 24.91 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:31:16 PM PDT 24
Peak memory 233304 kb
Host smart-9112f24f-e819-48d3-b9a0-f4b2e9ad29d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390685102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2390685102
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.972127177
Short name T565
Test name
Test status
Simulation time 349592788 ps
CPU time 2.92 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:30:53 PM PDT 24
Peak memory 219412 kb
Host smart-1f00009e-d4a5-4966-9b88-5d5987b47025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972127177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.972127177
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1761386092
Short name T962
Test name
Test status
Simulation time 10578460752 ps
CPU time 8.16 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:30:58 PM PDT 24
Peak memory 223596 kb
Host smart-fca858f5-a22b-43ce-8885-a55e093bbda3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1761386092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1761386092
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3381627435
Short name T933
Test name
Test status
Simulation time 131520905062 ps
CPU time 680.85 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:42:12 PM PDT 24
Peak memory 273776 kb
Host smart-b45c4d36-c119-43ff-9c56-e53f09c85059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381627435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3381627435
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.914567464
Short name T457
Test name
Test status
Simulation time 11589933392 ps
CPU time 21.88 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:31:12 PM PDT 24
Peak memory 217184 kb
Host smart-3156de08-49fd-491b-a4e7-054d9baad4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914567464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.914567464
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4092777776
Short name T982
Test name
Test status
Simulation time 974412652 ps
CPU time 6.57 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:30:58 PM PDT 24
Peak memory 216792 kb
Host smart-ea69894b-a8d9-4544-b2ff-e6138238e73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092777776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4092777776
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2128225111
Short name T678
Test name
Test status
Simulation time 900888569 ps
CPU time 6.22 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:30:57 PM PDT 24
Peak memory 216836 kb
Host smart-d83dde5b-997e-466d-8012-da479c8e131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128225111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2128225111
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1185657504
Short name T414
Test name
Test status
Simulation time 53999801 ps
CPU time 0.86 seconds
Started Jun 30 05:30:46 PM PDT 24
Finished Jun 30 05:30:48 PM PDT 24
Peak memory 206436 kb
Host smart-f754330b-7b0c-475a-bdd2-825cc87a30f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185657504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1185657504
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1402487294
Short name T475
Test name
Test status
Simulation time 361566642 ps
CPU time 5.07 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:30:55 PM PDT 24
Peak memory 233112 kb
Host smart-2a4a75cc-18fb-4016-8e8d-9eb93b55f880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402487294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1402487294
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4216961054
Short name T10
Test name
Test status
Simulation time 13983221 ps
CPU time 0.71 seconds
Started Jun 30 05:30:56 PM PDT 24
Finished Jun 30 05:30:58 PM PDT 24
Peak memory 205888 kb
Host smart-f4c4279b-1181-479c-af0b-25a5576fbb78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216961054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4216961054
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2235190964
Short name T891
Test name
Test status
Simulation time 1316699538 ps
CPU time 4.64 seconds
Started Jun 30 05:30:54 PM PDT 24
Finished Jun 30 05:30:59 PM PDT 24
Peak memory 224976 kb
Host smart-fd971b7a-c05e-445f-8a64-0592414e0d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235190964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2235190964
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.662997275
Short name T660
Test name
Test status
Simulation time 63876191 ps
CPU time 0.77 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:30:52 PM PDT 24
Peak memory 206052 kb
Host smart-680fb71d-7fad-42e4-9f96-f3a4abbb3bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662997275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.662997275
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3375205567
Short name T413
Test name
Test status
Simulation time 11892737267 ps
CPU time 68.32 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:32:00 PM PDT 24
Peak memory 251048 kb
Host smart-d262a2ad-a92d-4d28-8a3a-5d635a17d487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375205567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3375205567
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1033032027
Short name T454
Test name
Test status
Simulation time 148916065990 ps
CPU time 187.03 seconds
Started Jun 30 05:30:51 PM PDT 24
Finished Jun 30 05:33:59 PM PDT 24
Peak memory 249812 kb
Host smart-d6488428-b312-4f7c-bede-171ece349c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033032027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1033032027
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4168430763
Short name T417
Test name
Test status
Simulation time 18870448658 ps
CPU time 205.84 seconds
Started Jun 30 05:30:54 PM PDT 24
Finished Jun 30 05:34:20 PM PDT 24
Peak memory 256268 kb
Host smart-0f0318ee-b4ce-4783-a7ab-62f4df98166d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168430763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4168430763
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1922886339
Short name T147
Test name
Test status
Simulation time 5516936358 ps
CPU time 52.3 seconds
Started Jun 30 05:30:51 PM PDT 24
Finished Jun 30 05:31:44 PM PDT 24
Peak memory 238400 kb
Host smart-a9a92ffc-0f85-41d6-8b35-ef16292d9b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922886339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1922886339
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.768257519
Short name T666
Test name
Test status
Simulation time 7292526804 ps
CPU time 58.66 seconds
Started Jun 30 05:30:54 PM PDT 24
Finished Jun 30 05:31:53 PM PDT 24
Peak memory 249736 kb
Host smart-35f19e40-799e-45c3-bc1c-62214853668b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768257519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.768257519
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.463876365
Short name T99
Test name
Test status
Simulation time 9113322422 ps
CPU time 17.86 seconds
Started Jun 30 05:30:49 PM PDT 24
Finished Jun 30 05:31:08 PM PDT 24
Peak memory 225076 kb
Host smart-2078511c-f653-410d-939a-15bc59dbee16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463876365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.463876365
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1575133004
Short name T377
Test name
Test status
Simulation time 6454662569 ps
CPU time 56.94 seconds
Started Jun 30 05:30:51 PM PDT 24
Finished Jun 30 05:31:49 PM PDT 24
Peak memory 233296 kb
Host smart-a834b20c-7ba7-4cdd-9d23-420688540e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575133004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1575133004
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3438988261
Short name T261
Test name
Test status
Simulation time 7464410482 ps
CPU time 8.81 seconds
Started Jun 30 05:30:51 PM PDT 24
Finished Jun 30 05:31:01 PM PDT 24
Peak memory 225136 kb
Host smart-b20fa52f-0339-4c16-b224-f0a7c7df08c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438988261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3438988261
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.755214076
Short name T594
Test name
Test status
Simulation time 1950297633 ps
CPU time 8.17 seconds
Started Jun 30 05:30:51 PM PDT 24
Finished Jun 30 05:31:00 PM PDT 24
Peak memory 233200 kb
Host smart-3561a30d-5073-46a0-b839-0ab83af1e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755214076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.755214076
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3903733445
Short name T671
Test name
Test status
Simulation time 1326337622 ps
CPU time 9.7 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:31:01 PM PDT 24
Peak memory 223304 kb
Host smart-95cae671-85d2-43b8-b700-950ab21d1a22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3903733445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3903733445
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.523929320
Short name T155
Test name
Test status
Simulation time 36463481687 ps
CPU time 135.59 seconds
Started Jun 30 05:30:57 PM PDT 24
Finished Jun 30 05:33:13 PM PDT 24
Peak memory 254852 kb
Host smart-4d4c1e55-5385-4f71-9c54-6f23fe1ed2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523929320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.523929320
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.985172177
Short name T790
Test name
Test status
Simulation time 110180034 ps
CPU time 1.19 seconds
Started Jun 30 05:30:48 PM PDT 24
Finished Jun 30 05:30:49 PM PDT 24
Peak memory 216800 kb
Host smart-d2681036-467a-4230-bdf8-0504f48c38de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985172177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.985172177
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1331496137
Short name T371
Test name
Test status
Simulation time 22314491 ps
CPU time 0.71 seconds
Started Jun 30 05:30:47 PM PDT 24
Finished Jun 30 05:30:48 PM PDT 24
Peak memory 206436 kb
Host smart-5856c289-c2c0-4312-88e6-c877184c1e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331496137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1331496137
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.808931198
Short name T250
Test name
Test status
Simulation time 9195943978 ps
CPU time 10.77 seconds
Started Jun 30 05:30:50 PM PDT 24
Finished Jun 30 05:31:02 PM PDT 24
Peak memory 236132 kb
Host smart-d5defeae-5c2d-4ea5-a1f6-13e234241f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808931198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.808931198
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2653062219
Short name T531
Test name
Test status
Simulation time 17537551 ps
CPU time 0.71 seconds
Started Jun 30 05:30:56 PM PDT 24
Finished Jun 30 05:30:58 PM PDT 24
Peak memory 205924 kb
Host smart-73c60bae-746e-4f0e-aee9-cf523340acc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653062219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2653062219
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2261019132
Short name T870
Test name
Test status
Simulation time 982949175 ps
CPU time 12.76 seconds
Started Jun 30 05:30:57 PM PDT 24
Finished Jun 30 05:31:11 PM PDT 24
Peak memory 225000 kb
Host smart-33b6538c-7a84-4329-bb08-a88c91eadfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261019132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2261019132
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.880375176
Short name T461
Test name
Test status
Simulation time 15147926 ps
CPU time 0.82 seconds
Started Jun 30 05:30:55 PM PDT 24
Finished Jun 30 05:30:56 PM PDT 24
Peak memory 207124 kb
Host smart-ad687dd4-4232-482f-a621-fce0e760e840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880375176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.880375176
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3004356303
Short name T428
Test name
Test status
Simulation time 25244557266 ps
CPU time 91.82 seconds
Started Jun 30 05:30:59 PM PDT 24
Finished Jun 30 05:32:31 PM PDT 24
Peak memory 254852 kb
Host smart-2e59645f-23b2-4eb8-a5b6-18751ce0ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004356303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3004356303
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3213956950
Short name T837
Test name
Test status
Simulation time 9057904326 ps
CPU time 48.79 seconds
Started Jun 30 05:30:56 PM PDT 24
Finished Jun 30 05:31:46 PM PDT 24
Peak memory 249888 kb
Host smart-f1c3293d-40a2-4f73-9829-e07a7c7ead51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213956950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3213956950
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2187164328
Short name T193
Test name
Test status
Simulation time 15714637224 ps
CPU time 155.68 seconds
Started Jun 30 05:31:00 PM PDT 24
Finished Jun 30 05:33:37 PM PDT 24
Peak memory 265976 kb
Host smart-b4467235-372d-4ae8-9f88-e3f2e6e8ef01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187164328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2187164328
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1952503142
Short name T590
Test name
Test status
Simulation time 1251824888 ps
CPU time 8.63 seconds
Started Jun 30 05:30:56 PM PDT 24
Finished Jun 30 05:31:05 PM PDT 24
Peak memory 224980 kb
Host smart-47356ab4-12c3-4faf-92ad-f36c619de149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952503142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1952503142
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.252942104
Short name T170
Test name
Test status
Simulation time 1844447237 ps
CPU time 33.06 seconds
Started Jun 30 05:30:56 PM PDT 24
Finished Jun 30 05:31:30 PM PDT 24
Peak memory 249616 kb
Host smart-987bde8c-3d13-411c-9fb8-36adb9d58e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252942104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.252942104
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3451112720
Short name T226
Test name
Test status
Simulation time 2661536891 ps
CPU time 8.34 seconds
Started Jun 30 05:30:55 PM PDT 24
Finished Jun 30 05:31:04 PM PDT 24
Peak memory 225116 kb
Host smart-68108d75-c9eb-4cf5-b2f1-d4e5607d6874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451112720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3451112720
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3583199345
Short name T61
Test name
Test status
Simulation time 50173387368 ps
CPU time 67.18 seconds
Started Jun 30 05:30:55 PM PDT 24
Finished Jun 30 05:32:02 PM PDT 24
Peak memory 237696 kb
Host smart-0e9afbbd-e228-4d3d-9473-7a4d8972ff2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583199345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3583199345
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1563839683
Short name T718
Test name
Test status
Simulation time 8027443764 ps
CPU time 9.42 seconds
Started Jun 30 05:30:56 PM PDT 24
Finished Jun 30 05:31:07 PM PDT 24
Peak memory 233292 kb
Host smart-145f8fc4-a064-4987-beb7-994856abd117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563839683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1563839683
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1330775052
Short name T953
Test name
Test status
Simulation time 8164771782 ps
CPU time 20.94 seconds
Started Jun 30 05:31:02 PM PDT 24
Finished Jun 30 05:31:23 PM PDT 24
Peak memory 233300 kb
Host smart-2330b02d-de15-4fe2-85ac-8876740406f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330775052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1330775052
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1669231141
Short name T423
Test name
Test status
Simulation time 1979791230 ps
CPU time 17.83 seconds
Started Jun 30 05:31:01 PM PDT 24
Finished Jun 30 05:31:20 PM PDT 24
Peak memory 219388 kb
Host smart-9d9eb5d4-fac2-4a86-8f19-9b35a085d83e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1669231141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1669231141
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3356174889
Short name T552
Test name
Test status
Simulation time 6573115857 ps
CPU time 107.04 seconds
Started Jun 30 05:30:56 PM PDT 24
Finished Jun 30 05:32:44 PM PDT 24
Peak memory 251072 kb
Host smart-6892f3bc-1069-46e2-8190-da305131ac9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356174889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3356174889
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.744046917
Short name T319
Test name
Test status
Simulation time 2598285939 ps
CPU time 3.05 seconds
Started Jun 30 05:31:01 PM PDT 24
Finished Jun 30 05:31:05 PM PDT 24
Peak memory 217136 kb
Host smart-dd8e0404-447e-45bc-adaf-ac4c42f469f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744046917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.744046917
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3530320320
Short name T357
Test name
Test status
Simulation time 887450651 ps
CPU time 3.68 seconds
Started Jun 30 05:30:57 PM PDT 24
Finished Jun 30 05:31:02 PM PDT 24
Peak memory 216828 kb
Host smart-b0f55048-11eb-44a6-bde7-19a39e3c0007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530320320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3530320320
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2411877768
Short name T488
Test name
Test status
Simulation time 242761455 ps
CPU time 2.25 seconds
Started Jun 30 05:31:01 PM PDT 24
Finished Jun 30 05:31:03 PM PDT 24
Peak memory 216840 kb
Host smart-ac0fa402-eba4-4153-993d-a6ae082e6167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411877768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2411877768
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3033068038
Short name T607
Test name
Test status
Simulation time 39568535 ps
CPU time 0.8 seconds
Started Jun 30 05:31:02 PM PDT 24
Finished Jun 30 05:31:03 PM PDT 24
Peak memory 206460 kb
Host smart-d7896d13-0a78-4858-8d93-48ebbc07ef51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033068038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3033068038
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2510874968
Short name T636
Test name
Test status
Simulation time 4026579927 ps
CPU time 4.25 seconds
Started Jun 30 05:30:56 PM PDT 24
Finished Jun 30 05:31:01 PM PDT 24
Peak memory 225068 kb
Host smart-74ac1005-064f-4689-b489-cd5d0ba2b575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510874968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2510874968
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4156030962
Short name T351
Test name
Test status
Simulation time 34922112 ps
CPU time 0.72 seconds
Started Jun 30 05:31:08 PM PDT 24
Finished Jun 30 05:31:09 PM PDT 24
Peak memory 205300 kb
Host smart-b11951c3-06c1-439f-acef-f54bcadf8d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156030962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4156030962
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3648187060
Short name T979
Test name
Test status
Simulation time 2571546514 ps
CPU time 9.04 seconds
Started Jun 30 05:31:05 PM PDT 24
Finished Jun 30 05:31:14 PM PDT 24
Peak memory 225072 kb
Host smart-40a877fb-459c-42c7-a91c-e9ea725566c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648187060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3648187060
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.677839158
Short name T487
Test name
Test status
Simulation time 14376559 ps
CPU time 0.75 seconds
Started Jun 30 05:31:00 PM PDT 24
Finished Jun 30 05:31:01 PM PDT 24
Peak memory 206400 kb
Host smart-fcfc48a3-72f1-4cda-9c3b-dc063fb4cd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677839158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.677839158
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3770397015
Short name T194
Test name
Test status
Simulation time 47093768614 ps
CPU time 380.2 seconds
Started Jun 30 05:31:03 PM PDT 24
Finished Jun 30 05:37:23 PM PDT 24
Peak memory 263116 kb
Host smart-b44b4496-5a23-4ea1-9d3e-616e2344e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770397015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3770397015
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2040858932
Short name T285
Test name
Test status
Simulation time 12310716924 ps
CPU time 170.88 seconds
Started Jun 30 05:31:05 PM PDT 24
Finished Jun 30 05:33:57 PM PDT 24
Peak memory 267924 kb
Host smart-c55724ff-acf8-41b7-8dd5-d17183a35d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040858932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2040858932
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1152088443
Short name T174
Test name
Test status
Simulation time 1528161356 ps
CPU time 36.45 seconds
Started Jun 30 05:31:06 PM PDT 24
Finished Jun 30 05:31:43 PM PDT 24
Peak memory 250912 kb
Host smart-30979fed-df59-45fe-b5ef-53edcbef8523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152088443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1152088443
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1378694913
Short name T909
Test name
Test status
Simulation time 318489999 ps
CPU time 5.56 seconds
Started Jun 30 05:31:06 PM PDT 24
Finished Jun 30 05:31:12 PM PDT 24
Peak memory 225004 kb
Host smart-6d8b116e-1fcd-479e-8c0e-7f0bb2394b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378694913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1378694913
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3360252125
Short name T510
Test name
Test status
Simulation time 2772551924 ps
CPU time 24.42 seconds
Started Jun 30 05:31:07 PM PDT 24
Finished Jun 30 05:31:32 PM PDT 24
Peak memory 249732 kb
Host smart-b85fdfeb-7636-4063-ac3c-3730b7af9837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360252125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3360252125
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1426434508
Short name T598
Test name
Test status
Simulation time 133283832 ps
CPU time 2.99 seconds
Started Jun 30 05:31:05 PM PDT 24
Finished Jun 30 05:31:09 PM PDT 24
Peak memory 224928 kb
Host smart-7d4c351e-2a91-405d-b210-8d587579c74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426434508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1426434508
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2524781155
Short name T825
Test name
Test status
Simulation time 336675805 ps
CPU time 4.36 seconds
Started Jun 30 05:31:03 PM PDT 24
Finished Jun 30 05:31:08 PM PDT 24
Peak memory 233152 kb
Host smart-a31a9e38-9033-4366-a6a0-eff6efab2e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524781155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2524781155
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2545280371
Short name T361
Test name
Test status
Simulation time 291584039 ps
CPU time 2.2 seconds
Started Jun 30 05:31:05 PM PDT 24
Finished Jun 30 05:31:07 PM PDT 24
Peak memory 223680 kb
Host smart-8be476fa-10bf-4bdf-9a65-ec25e6fe4bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545280371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2545280371
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3418827542
Short name T623
Test name
Test status
Simulation time 14429879237 ps
CPU time 8.76 seconds
Started Jun 30 05:31:06 PM PDT 24
Finished Jun 30 05:31:15 PM PDT 24
Peak memory 225144 kb
Host smart-79729c96-b98d-478e-9434-b35b62388c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418827542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3418827542
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1558516066
Short name T832
Test name
Test status
Simulation time 604457187 ps
CPU time 8.3 seconds
Started Jun 30 05:31:02 PM PDT 24
Finished Jun 30 05:31:11 PM PDT 24
Peak memory 222604 kb
Host smart-eb647555-5dd6-494b-90bb-7db8fa280673
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1558516066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1558516066
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.54359223
Short name T728
Test name
Test status
Simulation time 226048869 ps
CPU time 1.08 seconds
Started Jun 30 05:31:08 PM PDT 24
Finished Jun 30 05:31:10 PM PDT 24
Peak memory 207388 kb
Host smart-a903481b-9cba-4d85-84d9-6e724eed1f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54359223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress
_all.54359223
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.32699781
Short name T965
Test name
Test status
Simulation time 16419244826 ps
CPU time 22.67 seconds
Started Jun 30 05:31:00 PM PDT 24
Finished Jun 30 05:31:23 PM PDT 24
Peak memory 216924 kb
Host smart-45d9ec92-f2a7-4b85-a81a-954baeaf726f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32699781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.32699781
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1879006174
Short name T603
Test name
Test status
Simulation time 1565791544 ps
CPU time 4.14 seconds
Started Jun 30 05:30:59 PM PDT 24
Finished Jun 30 05:31:04 PM PDT 24
Peak memory 216960 kb
Host smart-8db89fc0-8733-431d-b6e9-e9309379d716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879006174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1879006174
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2995922704
Short name T584
Test name
Test status
Simulation time 289585170 ps
CPU time 7.85 seconds
Started Jun 30 05:30:56 PM PDT 24
Finished Jun 30 05:31:04 PM PDT 24
Peak memory 216840 kb
Host smart-0bd8a172-d87e-4bd0-808e-860bcff707dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995922704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2995922704
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3144434777
Short name T761
Test name
Test status
Simulation time 12144153 ps
CPU time 0.69 seconds
Started Jun 30 05:30:57 PM PDT 24
Finished Jun 30 05:30:58 PM PDT 24
Peak memory 206136 kb
Host smart-adbd69a6-2d23-49d9-a097-492b06ce4ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144434777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3144434777
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1805668801
Short name T249
Test name
Test status
Simulation time 991472438 ps
CPU time 5.46 seconds
Started Jun 30 05:31:07 PM PDT 24
Finished Jun 30 05:31:13 PM PDT 24
Peak memory 233124 kb
Host smart-1349ad63-ee69-462e-8199-34595602e193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805668801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1805668801
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3776341580
Short name T410
Test name
Test status
Simulation time 11243312 ps
CPU time 0.73 seconds
Started Jun 30 05:31:10 PM PDT 24
Finished Jun 30 05:31:12 PM PDT 24
Peak memory 205360 kb
Host smart-efe7b282-9222-4fab-8d1a-b9393762c4a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776341580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3776341580
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.350638690
Short name T431
Test name
Test status
Simulation time 983151419 ps
CPU time 3.38 seconds
Started Jun 30 05:31:09 PM PDT 24
Finished Jun 30 05:31:13 PM PDT 24
Peak memory 233204 kb
Host smart-da3ff36d-7ee3-424d-9599-ff99c83324c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350638690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.350638690
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3581876596
Short name T599
Test name
Test status
Simulation time 39634409 ps
CPU time 0.77 seconds
Started Jun 30 05:31:03 PM PDT 24
Finished Jun 30 05:31:04 PM PDT 24
Peak memory 206608 kb
Host smart-749ef0b1-999b-4ea8-8c9d-923b9386807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581876596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3581876596
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3048752159
Short name T6
Test name
Test status
Simulation time 14285856236 ps
CPU time 52.31 seconds
Started Jun 30 05:31:09 PM PDT 24
Finished Jun 30 05:32:03 PM PDT 24
Peak memory 241492 kb
Host smart-55777a1c-20c9-4119-9a1b-fb316c764f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048752159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3048752159
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2493361740
Short name T834
Test name
Test status
Simulation time 42328548231 ps
CPU time 109.35 seconds
Started Jun 30 05:31:10 PM PDT 24
Finished Jun 30 05:33:00 PM PDT 24
Peak memory 241660 kb
Host smart-0fc618ea-2c37-4bcc-a9e0-b6a2f2a7b6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493361740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2493361740
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3320480164
Short name T221
Test name
Test status
Simulation time 32460508716 ps
CPU time 88.35 seconds
Started Jun 30 05:31:11 PM PDT 24
Finished Jun 30 05:32:40 PM PDT 24
Peak memory 257908 kb
Host smart-05d8de9a-a7ce-4dc5-a43f-61880d6d59f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320480164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3320480164
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2216431496
Short name T626
Test name
Test status
Simulation time 130453835 ps
CPU time 5.92 seconds
Started Jun 30 05:31:12 PM PDT 24
Finished Jun 30 05:31:18 PM PDT 24
Peak memory 241604 kb
Host smart-c0d489c3-87d3-4b2d-8469-3dacff39ed6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216431496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2216431496
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3233838445
Short name T865
Test name
Test status
Simulation time 7998370686 ps
CPU time 105.53 seconds
Started Jun 30 05:31:10 PM PDT 24
Finished Jun 30 05:32:57 PM PDT 24
Peak memory 249764 kb
Host smart-8d603c86-d717-466d-92b9-a19f5e8c6b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233838445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3233838445
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3515548818
Short name T354
Test name
Test status
Simulation time 1256464179 ps
CPU time 4.98 seconds
Started Jun 30 05:31:02 PM PDT 24
Finished Jun 30 05:31:08 PM PDT 24
Peak memory 233172 kb
Host smart-9a48680a-6094-41c5-93e3-840993fd63c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515548818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3515548818
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1515777642
Short name T247
Test name
Test status
Simulation time 14340609493 ps
CPU time 123.43 seconds
Started Jun 30 05:31:03 PM PDT 24
Finished Jun 30 05:33:07 PM PDT 24
Peak memory 251420 kb
Host smart-6990e086-7e23-4f3e-ba1f-70bee39d9098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515777642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1515777642
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2618128596
Short name T682
Test name
Test status
Simulation time 2935746038 ps
CPU time 5.92 seconds
Started Jun 30 05:31:04 PM PDT 24
Finished Jun 30 05:31:11 PM PDT 24
Peak memory 233244 kb
Host smart-9cac0dfa-6f42-4670-a069-1943206747ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618128596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2618128596
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3096115858
Short name T802
Test name
Test status
Simulation time 318952467 ps
CPU time 3.63 seconds
Started Jun 30 05:31:07 PM PDT 24
Finished Jun 30 05:31:11 PM PDT 24
Peak memory 225040 kb
Host smart-3e71aae4-02c0-42f4-b920-42e720020407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096115858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3096115858
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.235338455
Short name T276
Test name
Test status
Simulation time 21213449772 ps
CPU time 96.62 seconds
Started Jun 30 05:31:10 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 253552 kb
Host smart-7f5f7ad7-5cab-4dba-bf60-bb11f13a25ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235338455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.235338455
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1530160123
Short name T570
Test name
Test status
Simulation time 1739983932 ps
CPU time 16.65 seconds
Started Jun 30 05:31:03 PM PDT 24
Finished Jun 30 05:31:20 PM PDT 24
Peak memory 216792 kb
Host smart-d4c9a5e4-4549-4d30-a9c3-9ac3ab48577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530160123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1530160123
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3551914482
Short name T699
Test name
Test status
Simulation time 1225683796 ps
CPU time 2.43 seconds
Started Jun 30 05:31:06 PM PDT 24
Finished Jun 30 05:31:08 PM PDT 24
Peak memory 216744 kb
Host smart-4d0f592f-fbd8-480f-a9bd-83aa5dd97634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551914482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3551914482
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1445946276
Short name T918
Test name
Test status
Simulation time 119724016 ps
CPU time 0.92 seconds
Started Jun 30 05:31:06 PM PDT 24
Finished Jun 30 05:31:08 PM PDT 24
Peak memory 207404 kb
Host smart-2615a24c-5bf3-4e3f-a592-1cde72c847cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445946276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1445946276
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2847703053
Short name T866
Test name
Test status
Simulation time 29072690 ps
CPU time 0.81 seconds
Started Jun 30 05:31:05 PM PDT 24
Finished Jun 30 05:31:06 PM PDT 24
Peak memory 206452 kb
Host smart-d3183eab-a405-4b8e-885b-34e8c8a6ba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847703053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2847703053
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3567873503
Short name T270
Test name
Test status
Simulation time 5007589759 ps
CPU time 6.22 seconds
Started Jun 30 05:31:09 PM PDT 24
Finished Jun 30 05:31:15 PM PDT 24
Peak memory 233300 kb
Host smart-b1f2ab81-6f88-4212-9495-d6eb854253ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567873503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3567873503
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2994711680
Short name T434
Test name
Test status
Simulation time 37698224 ps
CPU time 0.72 seconds
Started Jun 30 05:31:19 PM PDT 24
Finished Jun 30 05:31:20 PM PDT 24
Peak memory 205380 kb
Host smart-9077822a-6799-4f67-af46-7678bb059148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994711680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2994711680
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3759001797
Short name T363
Test name
Test status
Simulation time 463478256 ps
CPU time 5 seconds
Started Jun 30 05:31:19 PM PDT 24
Finished Jun 30 05:31:25 PM PDT 24
Peak memory 224976 kb
Host smart-2014f4ba-f537-435b-bd6e-ff9296355964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759001797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3759001797
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1519326791
Short name T1002
Test name
Test status
Simulation time 53985540 ps
CPU time 0.8 seconds
Started Jun 30 05:31:09 PM PDT 24
Finished Jun 30 05:31:10 PM PDT 24
Peak memory 207076 kb
Host smart-fc56db7e-b647-4541-9944-45cc6d1266a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519326791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1519326791
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4081685139
Short name T303
Test name
Test status
Simulation time 5106073704 ps
CPU time 81.47 seconds
Started Jun 30 05:31:17 PM PDT 24
Finished Jun 30 05:32:39 PM PDT 24
Peak memory 249756 kb
Host smart-56d67a0b-8e65-440f-8521-f8ba879b221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081685139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4081685139
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1183418427
Short name T288
Test name
Test status
Simulation time 73995888264 ps
CPU time 741.68 seconds
Started Jun 30 05:31:18 PM PDT 24
Finished Jun 30 05:43:41 PM PDT 24
Peak memory 267888 kb
Host smart-75ebaeb5-35ab-43e5-bbf3-4f706574db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183418427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1183418427
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1121933551
Short name T266
Test name
Test status
Simulation time 4241719962 ps
CPU time 35.97 seconds
Started Jun 30 05:31:17 PM PDT 24
Finished Jun 30 05:31:53 PM PDT 24
Peak memory 225260 kb
Host smart-519190b9-4536-4bbb-8328-0ddd6e65ad8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121933551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1121933551
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3560557279
Short name T217
Test name
Test status
Simulation time 1286482163 ps
CPU time 21.93 seconds
Started Jun 30 05:31:21 PM PDT 24
Finished Jun 30 05:31:43 PM PDT 24
Peak memory 249824 kb
Host smart-05f1efb7-ed74-4f73-92ae-bb1a95aa6e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560557279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3560557279
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.475349620
Short name T884
Test name
Test status
Simulation time 172561297888 ps
CPU time 170 seconds
Started Jun 30 05:31:20 PM PDT 24
Finished Jun 30 05:34:11 PM PDT 24
Peak memory 266116 kb
Host smart-737566a6-4c3d-4f96-ae4b-0e5616853a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475349620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.475349620
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.595639426
Short name T765
Test name
Test status
Simulation time 417902538 ps
CPU time 6.45 seconds
Started Jun 30 05:31:11 PM PDT 24
Finished Jun 30 05:31:18 PM PDT 24
Peak memory 233172 kb
Host smart-856e0b4e-0b8a-4cd3-99e8-3e072c6cdf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595639426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.595639426
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.597672068
Short name T743
Test name
Test status
Simulation time 12506689121 ps
CPU time 40.59 seconds
Started Jun 30 05:31:17 PM PDT 24
Finished Jun 30 05:31:58 PM PDT 24
Peak memory 233344 kb
Host smart-2aa89924-be03-41fa-a45f-c9679fca0dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597672068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.597672068
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1830602246
Short name T259
Test name
Test status
Simulation time 286728319 ps
CPU time 2.82 seconds
Started Jun 30 05:31:11 PM PDT 24
Finished Jun 30 05:31:14 PM PDT 24
Peak memory 233248 kb
Host smart-7d91dd54-0829-4e62-bfcc-ec70d6a67638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830602246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1830602246
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.127720101
Short name T886
Test name
Test status
Simulation time 3137609802 ps
CPU time 11.39 seconds
Started Jun 30 05:31:11 PM PDT 24
Finished Jun 30 05:31:23 PM PDT 24
Peak memory 225116 kb
Host smart-7360b30f-a04e-43ea-b954-1026df3266c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127720101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.127720101
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1338736043
Short name T803
Test name
Test status
Simulation time 128908304 ps
CPU time 4.31 seconds
Started Jun 30 05:31:18 PM PDT 24
Finished Jun 30 05:31:23 PM PDT 24
Peak memory 223104 kb
Host smart-47bd4b6f-0e09-44df-81ff-2b25d6767fe1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1338736043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1338736043
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1323796321
Short name T289
Test name
Test status
Simulation time 100314003457 ps
CPU time 301.36 seconds
Started Jun 30 05:31:17 PM PDT 24
Finished Jun 30 05:36:19 PM PDT 24
Peak memory 264532 kb
Host smart-36632256-6657-4ad9-a978-277d27303340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323796321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1323796321
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2314554580
Short name T608
Test name
Test status
Simulation time 68732595 ps
CPU time 0.75 seconds
Started Jun 30 05:31:09 PM PDT 24
Finished Jun 30 05:31:11 PM PDT 24
Peak memory 206556 kb
Host smart-d7d39280-fc02-44aa-9c2f-d10817c75146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314554580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2314554580
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2508235221
Short name T483
Test name
Test status
Simulation time 927307561 ps
CPU time 6.81 seconds
Started Jun 30 05:31:09 PM PDT 24
Finished Jun 30 05:31:17 PM PDT 24
Peak memory 216764 kb
Host smart-f6729314-fea9-4294-8257-1e6ecf7e47b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508235221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2508235221
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.947113982
Short name T676
Test name
Test status
Simulation time 210283050 ps
CPU time 8.36 seconds
Started Jun 30 05:31:11 PM PDT 24
Finished Jun 30 05:31:20 PM PDT 24
Peak memory 216736 kb
Host smart-077462db-fa83-4392-af0a-1ae66cae3516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947113982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.947113982
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.538373901
Short name T804
Test name
Test status
Simulation time 28615615 ps
CPU time 0.81 seconds
Started Jun 30 05:31:09 PM PDT 24
Finished Jun 30 05:31:10 PM PDT 24
Peak memory 206476 kb
Host smart-5eff0529-8aed-41fa-96a8-1406a3c73832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538373901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.538373901
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2123983754
Short name T916
Test name
Test status
Simulation time 4494883128 ps
CPU time 18.02 seconds
Started Jun 30 05:31:20 PM PDT 24
Finished Jun 30 05:31:39 PM PDT 24
Peak memory 233352 kb
Host smart-dfc19bf2-5d4b-4972-bd64-b08bd586b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123983754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2123983754
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.303353667
Short name T360
Test name
Test status
Simulation time 44013162 ps
CPU time 0.75 seconds
Started Jun 30 05:31:25 PM PDT 24
Finished Jun 30 05:31:26 PM PDT 24
Peak memory 205332 kb
Host smart-21c59083-c271-4877-af24-915d8c7f98eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303353667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.303353667
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1270758592
Short name T855
Test name
Test status
Simulation time 2848548131 ps
CPU time 8.08 seconds
Started Jun 30 05:31:17 PM PDT 24
Finished Jun 30 05:31:26 PM PDT 24
Peak memory 233304 kb
Host smart-0c17d369-cb35-479c-aa75-0721160ac2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270758592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1270758592
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1191272312
Short name T516
Test name
Test status
Simulation time 67966426 ps
CPU time 0.79 seconds
Started Jun 30 05:31:19 PM PDT 24
Finished Jun 30 05:31:20 PM PDT 24
Peak memory 206008 kb
Host smart-daf03acb-b030-4233-b0e6-75f210dec322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191272312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1191272312
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3159842188
Short name T165
Test name
Test status
Simulation time 9443888192 ps
CPU time 34.2 seconds
Started Jun 30 05:31:25 PM PDT 24
Finished Jun 30 05:32:00 PM PDT 24
Peak memory 236432 kb
Host smart-bab2026d-c417-4de7-b70c-72cb455ed6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159842188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3159842188
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4148321973
Short name T960
Test name
Test status
Simulation time 2833817864 ps
CPU time 35.65 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:32:03 PM PDT 24
Peak memory 249596 kb
Host smart-3b1f810d-ab8d-4522-993f-01d3f504d965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148321973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4148321973
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1415918015
Short name T287
Test name
Test status
Simulation time 4180270664 ps
CPU time 59.44 seconds
Started Jun 30 05:31:28 PM PDT 24
Finished Jun 30 05:32:28 PM PDT 24
Peak memory 240752 kb
Host smart-2d58526f-044c-45e6-9270-c16b427c4eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415918015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1415918015
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1749480795
Short name T143
Test name
Test status
Simulation time 4501702162 ps
CPU time 53.6 seconds
Started Jun 30 05:31:18 PM PDT 24
Finished Jun 30 05:32:12 PM PDT 24
Peak memory 249652 kb
Host smart-7678f8c7-857c-4105-af79-6136327e0072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749480795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1749480795
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.649099427
Short name T782
Test name
Test status
Simulation time 1703361535 ps
CPU time 41.62 seconds
Started Jun 30 05:31:19 PM PDT 24
Finished Jun 30 05:32:02 PM PDT 24
Peak memory 257752 kb
Host smart-ba7a83e7-b072-4e53-8606-636b8addfc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649099427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.649099427
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2731550085
Short name T271
Test name
Test status
Simulation time 209816634 ps
CPU time 5.37 seconds
Started Jun 30 05:31:19 PM PDT 24
Finished Jun 30 05:31:25 PM PDT 24
Peak memory 220268 kb
Host smart-883ceacb-fc3e-4846-8923-16fa6df93305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731550085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2731550085
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1200857322
Short name T80
Test name
Test status
Simulation time 27942225 ps
CPU time 2.15 seconds
Started Jun 30 05:31:18 PM PDT 24
Finished Jun 30 05:31:20 PM PDT 24
Peak memory 225036 kb
Host smart-cc1aa792-148f-4909-8d9d-81af873fa68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200857322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1200857322
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3834564572
Short name T970
Test name
Test status
Simulation time 6296631851 ps
CPU time 20.24 seconds
Started Jun 30 05:31:18 PM PDT 24
Finished Jun 30 05:31:39 PM PDT 24
Peak memory 241164 kb
Host smart-0df7c3c2-85c5-4312-807b-7ad3ef9911ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834564572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3834564572
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2588040022
Short name T481
Test name
Test status
Simulation time 77825798 ps
CPU time 2.11 seconds
Started Jun 30 05:31:18 PM PDT 24
Finished Jun 30 05:31:21 PM PDT 24
Peak memory 223824 kb
Host smart-24eb6e61-9158-475d-80d5-066671708fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588040022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2588040022
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.287846332
Short name T513
Test name
Test status
Simulation time 360749996 ps
CPU time 7.2 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:31:34 PM PDT 24
Peak memory 222640 kb
Host smart-c0bf84eb-b986-4372-88be-39762597dcbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=287846332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.287846332
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2685710940
Short name T990
Test name
Test status
Simulation time 41705763525 ps
CPU time 369.8 seconds
Started Jun 30 05:31:30 PM PDT 24
Finished Jun 30 05:37:40 PM PDT 24
Peak memory 264760 kb
Host smart-9c1a9b02-2612-437c-8955-abdb72314b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685710940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2685710940
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3563896389
Short name T619
Test name
Test status
Simulation time 6622237903 ps
CPU time 21.22 seconds
Started Jun 30 05:31:20 PM PDT 24
Finished Jun 30 05:31:42 PM PDT 24
Peak memory 216964 kb
Host smart-d5ca9a7e-0864-4604-941a-a0b152f9b1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563896389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3563896389
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2918567787
Short name T705
Test name
Test status
Simulation time 1027067595 ps
CPU time 4.02 seconds
Started Jun 30 05:31:20 PM PDT 24
Finished Jun 30 05:31:24 PM PDT 24
Peak memory 216764 kb
Host smart-309468e5-fda4-4250-bd7b-d7654526b601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918567787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2918567787
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.212978824
Short name T927
Test name
Test status
Simulation time 539282894 ps
CPU time 4.2 seconds
Started Jun 30 05:31:17 PM PDT 24
Finished Jun 30 05:31:21 PM PDT 24
Peak memory 216752 kb
Host smart-149c91e7-18e9-4bfb-858e-2830fc46c9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212978824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.212978824
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3219889539
Short name T57
Test name
Test status
Simulation time 81397999 ps
CPU time 0.93 seconds
Started Jun 30 05:31:18 PM PDT 24
Finished Jun 30 05:31:20 PM PDT 24
Peak memory 206420 kb
Host smart-7333bd1e-8ba2-4764-babf-5e2c5ec9958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219889539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3219889539
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2240930384
Short name T641
Test name
Test status
Simulation time 1689996768 ps
CPU time 5.97 seconds
Started Jun 30 05:31:19 PM PDT 24
Finished Jun 30 05:31:26 PM PDT 24
Peak memory 233168 kb
Host smart-ad305097-b6ce-4384-899c-cf106a9b8902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240930384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2240930384
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2085711860
Short name T999
Test name
Test status
Simulation time 22521256 ps
CPU time 0.74 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:31:28 PM PDT 24
Peak memory 205944 kb
Host smart-03ba2ce6-c1db-44d8-b15a-f56b73d739cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085711860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2085711860
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3624880648
Short name T998
Test name
Test status
Simulation time 292665141 ps
CPU time 2.12 seconds
Started Jun 30 05:31:25 PM PDT 24
Finished Jun 30 05:31:28 PM PDT 24
Peak memory 224928 kb
Host smart-c333d4c7-5edf-4f90-89f9-810e351ea9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624880648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3624880648
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3206206551
Short name T346
Test name
Test status
Simulation time 14566237 ps
CPU time 0.74 seconds
Started Jun 30 05:31:30 PM PDT 24
Finished Jun 30 05:31:31 PM PDT 24
Peak memory 207452 kb
Host smart-c8eedb4e-89b7-483d-9b9d-a3e13e3c9580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206206551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3206206551
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2883433082
Short name T25
Test name
Test status
Simulation time 1097223935 ps
CPU time 22.03 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:31:49 PM PDT 24
Peak memory 237392 kb
Host smart-af7ef627-4d72-42b0-93d9-3902ecdb7b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883433082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2883433082
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.510734923
Short name T36
Test name
Test status
Simulation time 14481391882 ps
CPU time 122.77 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:33:30 PM PDT 24
Peak memory 253064 kb
Host smart-3fcc3304-010d-4df7-a81b-8c7f17e755c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510734923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.510734923
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1902624324
Short name T240
Test name
Test status
Simulation time 41175229838 ps
CPU time 363.55 seconds
Started Jun 30 05:31:30 PM PDT 24
Finished Jun 30 05:37:34 PM PDT 24
Peak memory 266268 kb
Host smart-72c55fd4-4218-424a-8eab-80071ff8da4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902624324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1902624324
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.932219435
Short name T163
Test name
Test status
Simulation time 1539107274 ps
CPU time 12.36 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:31:40 PM PDT 24
Peak memory 241392 kb
Host smart-f921c1f8-9a05-439e-b741-3783d1f7e3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932219435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.932219435
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.863195588
Short name T959
Test name
Test status
Simulation time 2982662824 ps
CPU time 31.36 seconds
Started Jun 30 05:31:25 PM PDT 24
Finished Jun 30 05:31:57 PM PDT 24
Peak memory 241580 kb
Host smart-6f7a05eb-c09c-441d-a04b-a6bb4184f544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863195588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.863195588
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3836373862
Short name T969
Test name
Test status
Simulation time 142368941 ps
CPU time 4.2 seconds
Started Jun 30 05:31:25 PM PDT 24
Finished Jun 30 05:31:30 PM PDT 24
Peak memory 233224 kb
Host smart-979781ad-00bc-4f77-8a06-4776fc3e3d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836373862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3836373862
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.360298146
Short name T963
Test name
Test status
Simulation time 242204622 ps
CPU time 7.41 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:31:35 PM PDT 24
Peak memory 241048 kb
Host smart-464914d7-cb99-41f3-9099-514eb69ede99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360298146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.360298146
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3263311197
Short name T518
Test name
Test status
Simulation time 394773628 ps
CPU time 2.42 seconds
Started Jun 30 05:31:28 PM PDT 24
Finished Jun 30 05:31:31 PM PDT 24
Peak memory 224516 kb
Host smart-4185c463-8601-4c0f-8402-7acf2c186957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263311197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3263311197
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2835526485
Short name T951
Test name
Test status
Simulation time 75965349 ps
CPU time 2.24 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:31:29 PM PDT 24
Peak memory 224512 kb
Host smart-21ba5116-c619-44a3-aafd-0ca58c6258d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835526485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2835526485
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1360670911
Short name T735
Test name
Test status
Simulation time 636435149 ps
CPU time 9.39 seconds
Started Jun 30 05:31:29 PM PDT 24
Finished Jun 30 05:31:38 PM PDT 24
Peak memory 220516 kb
Host smart-3ff4b99b-c981-45ce-8b45-cbf650b64fc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1360670911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1360670911
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1645308515
Short name T132
Test name
Test status
Simulation time 101607227961 ps
CPU time 281.69 seconds
Started Jun 30 05:31:24 PM PDT 24
Finished Jun 30 05:36:07 PM PDT 24
Peak memory 265252 kb
Host smart-9525ff5a-692f-4fe4-8213-82e64b21aac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645308515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1645308515
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1291396414
Short name T514
Test name
Test status
Simulation time 6782535511 ps
CPU time 36.06 seconds
Started Jun 30 05:31:27 PM PDT 24
Finished Jun 30 05:32:04 PM PDT 24
Peak memory 216940 kb
Host smart-9dec0760-96dd-43d3-8019-3bccbdd10bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291396414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1291396414
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.171682207
Short name T348
Test name
Test status
Simulation time 3238812995 ps
CPU time 8.63 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:31:36 PM PDT 24
Peak memory 217140 kb
Host smart-a6daa389-6dbc-4969-824c-a51aa86af4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171682207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.171682207
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.517806384
Short name T978
Test name
Test status
Simulation time 69001514 ps
CPU time 1.85 seconds
Started Jun 30 05:31:27 PM PDT 24
Finished Jun 30 05:31:30 PM PDT 24
Peak memory 216840 kb
Host smart-5e062e60-b9bc-4d25-a5f8-51cb9a7c7a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517806384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.517806384
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4129632049
Short name T30
Test name
Test status
Simulation time 197856706 ps
CPU time 0.84 seconds
Started Jun 30 05:31:25 PM PDT 24
Finished Jun 30 05:31:27 PM PDT 24
Peak memory 206468 kb
Host smart-988bfa61-b2de-4b17-9757-9720c7f01f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129632049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4129632049
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.880213792
Short name T199
Test name
Test status
Simulation time 178224802 ps
CPU time 3.06 seconds
Started Jun 30 05:31:24 PM PDT 24
Finished Jun 30 05:31:28 PM PDT 24
Peak memory 224948 kb
Host smart-3910128d-657c-459d-b8b5-4921f900b89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880213792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.880213792
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3537496657
Short name T576
Test name
Test status
Simulation time 21767090 ps
CPU time 0.75 seconds
Started Jun 30 05:31:35 PM PDT 24
Finished Jun 30 05:31:37 PM PDT 24
Peak memory 205848 kb
Host smart-c154e54a-54c9-47f7-9938-9a93f70e8697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537496657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3537496657
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.263273921
Short name T236
Test name
Test status
Simulation time 112010693 ps
CPU time 2.62 seconds
Started Jun 30 05:31:28 PM PDT 24
Finished Jun 30 05:31:31 PM PDT 24
Peak memory 219344 kb
Host smart-74680237-a668-4a0b-972d-58ad7a2c5859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263273921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.263273921
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1197565941
Short name T79
Test name
Test status
Simulation time 12905904 ps
CPU time 0.77 seconds
Started Jun 30 05:31:28 PM PDT 24
Finished Jun 30 05:31:29 PM PDT 24
Peak memory 206068 kb
Host smart-d3274e62-cd72-442e-a0c0-8dae95fcde43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197565941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1197565941
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3146009502
Short name T195
Test name
Test status
Simulation time 10807477310 ps
CPU time 73.15 seconds
Started Jun 30 05:31:34 PM PDT 24
Finished Jun 30 05:32:48 PM PDT 24
Peak memory 255492 kb
Host smart-477f9a41-24c1-40b5-bc15-bd82fc0ee0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146009502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3146009502
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2404364541
Short name T332
Test name
Test status
Simulation time 13557971831 ps
CPU time 153.09 seconds
Started Jun 30 05:31:33 PM PDT 24
Finished Jun 30 05:34:07 PM PDT 24
Peak memory 250820 kb
Host smart-293fa42d-09c2-4fc9-af83-fc1aff3ff8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404364541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2404364541
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.430773789
Short name T900
Test name
Test status
Simulation time 63429634019 ps
CPU time 312.87 seconds
Started Jun 30 05:31:34 PM PDT 24
Finished Jun 30 05:36:48 PM PDT 24
Peak memory 249884 kb
Host smart-f162194b-9587-42a2-9270-35cd4b3a321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430773789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.430773789
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4024406289
Short name T931
Test name
Test status
Simulation time 269249445 ps
CPU time 3.01 seconds
Started Jun 30 05:31:34 PM PDT 24
Finished Jun 30 05:31:38 PM PDT 24
Peak memory 224996 kb
Host smart-fee4caff-f655-49da-99ab-fda35b1c481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024406289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4024406289
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1409464576
Short name T661
Test name
Test status
Simulation time 18383445523 ps
CPU time 139.81 seconds
Started Jun 30 05:31:34 PM PDT 24
Finished Jun 30 05:33:55 PM PDT 24
Peak memory 257924 kb
Host smart-7a219d8b-dc77-4862-8c1b-f74a20218761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409464576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1409464576
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1722395248
Short name T214
Test name
Test status
Simulation time 2618605769 ps
CPU time 9.24 seconds
Started Jun 30 05:31:25 PM PDT 24
Finished Jun 30 05:31:36 PM PDT 24
Peak memory 225128 kb
Host smart-85e2fc59-9260-4baa-9d70-6301373dc989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722395248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1722395248
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1759120017
Short name T504
Test name
Test status
Simulation time 37583737145 ps
CPU time 50.41 seconds
Started Jun 30 05:31:25 PM PDT 24
Finished Jun 30 05:32:16 PM PDT 24
Peak memory 233252 kb
Host smart-fe3e8df7-7c64-4628-a2f8-b578fc526fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759120017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1759120017
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.247597390
Short name T701
Test name
Test status
Simulation time 355609677 ps
CPU time 4.36 seconds
Started Jun 30 05:31:25 PM PDT 24
Finished Jun 30 05:31:31 PM PDT 24
Peak memory 224976 kb
Host smart-8f3614f7-d73b-41cd-bda2-14a06c43f063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247597390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.247597390
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2505142440
Short name T380
Test name
Test status
Simulation time 14995720927 ps
CPU time 9.97 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:31:37 PM PDT 24
Peak memory 225156 kb
Host smart-70d961d7-a283-4367-a9cd-654436c8af0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505142440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2505142440
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2541152237
Short name T443
Test name
Test status
Simulation time 1910219137 ps
CPU time 7.21 seconds
Started Jun 30 05:31:35 PM PDT 24
Finished Jun 30 05:31:43 PM PDT 24
Peak memory 223516 kb
Host smart-e72b9aff-7f3a-4be3-8e5b-59b11ba4c73c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2541152237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2541152237
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.445426162
Short name T22
Test name
Test status
Simulation time 6342941717 ps
CPU time 91.96 seconds
Started Jun 30 05:31:33 PM PDT 24
Finished Jun 30 05:33:06 PM PDT 24
Peak memory 255056 kb
Host smart-e4df5780-4fa6-4f38-a4f9-31d46f0355bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445426162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.445426162
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3303124882
Short name T322
Test name
Test status
Simulation time 5432533809 ps
CPU time 15.59 seconds
Started Jun 30 05:31:28 PM PDT 24
Finished Jun 30 05:31:44 PM PDT 24
Peak memory 216960 kb
Host smart-dfe6c4e0-49e9-468a-980a-8720ea1b1440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303124882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3303124882
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1697184984
Short name T91
Test name
Test status
Simulation time 3732645224 ps
CPU time 7.04 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:31:35 PM PDT 24
Peak memory 216904 kb
Host smart-0c8c57a1-92ed-4de7-b530-0f54b91fb474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697184984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1697184984
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.529224773
Short name T12
Test name
Test status
Simulation time 66479871 ps
CPU time 1.18 seconds
Started Jun 30 05:31:26 PM PDT 24
Finished Jun 30 05:31:28 PM PDT 24
Peak memory 217068 kb
Host smart-77765673-87fa-4169-bea6-91895c0a5c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529224773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.529224773
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.196484895
Short name T708
Test name
Test status
Simulation time 19194766 ps
CPU time 0.72 seconds
Started Jun 30 05:31:30 PM PDT 24
Finished Jun 30 05:31:31 PM PDT 24
Peak memory 206496 kb
Host smart-b51a44fb-d309-49c6-b58f-42013641dee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196484895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.196484895
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.955415403
Short name T856
Test name
Test status
Simulation time 291856071 ps
CPU time 5.46 seconds
Started Jun 30 05:31:24 PM PDT 24
Finished Jun 30 05:31:30 PM PDT 24
Peak memory 239716 kb
Host smart-6def280f-406d-4707-8a69-0de7ae6ccdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955415403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.955415403
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3527529611
Short name T400
Test name
Test status
Simulation time 14464341 ps
CPU time 0.73 seconds
Started Jun 30 05:31:36 PM PDT 24
Finished Jun 30 05:31:37 PM PDT 24
Peak memory 205940 kb
Host smart-43df73c7-c636-47a0-a1af-a746a1d5674d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527529611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3527529611
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3947784683
Short name T794
Test name
Test status
Simulation time 1099073001 ps
CPU time 5.58 seconds
Started Jun 30 05:31:35 PM PDT 24
Finished Jun 30 05:31:41 PM PDT 24
Peak memory 224956 kb
Host smart-ddbda296-7542-4604-a774-71c48e84b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947784683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3947784683
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.426770270
Short name T895
Test name
Test status
Simulation time 14730891 ps
CPU time 0.83 seconds
Started Jun 30 05:31:35 PM PDT 24
Finished Jun 30 05:31:36 PM PDT 24
Peak memory 207120 kb
Host smart-325873d7-d3a3-4180-8cc2-a28fe82985a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426770270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.426770270
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1381726115
Short name T204
Test name
Test status
Simulation time 35342427520 ps
CPU time 149.48 seconds
Started Jun 30 05:31:33 PM PDT 24
Finished Jun 30 05:34:03 PM PDT 24
Peak memory 255756 kb
Host smart-997ac782-95f6-4dde-8d71-f900a113cc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381726115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1381726115
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3670105415
Short name T83
Test name
Test status
Simulation time 69461294596 ps
CPU time 269.94 seconds
Started Jun 30 05:31:33 PM PDT 24
Finished Jun 30 05:36:04 PM PDT 24
Peak memory 270012 kb
Host smart-3097f5b7-c016-4a02-b3ec-7e4106c9730e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670105415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3670105415
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2001698532
Short name T611
Test name
Test status
Simulation time 2604935521 ps
CPU time 58.84 seconds
Started Jun 30 05:31:35 PM PDT 24
Finished Jun 30 05:32:35 PM PDT 24
Peak memory 252472 kb
Host smart-70658104-1411-4d14-a0bc-09f2030255ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001698532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2001698532
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.435098350
Short name T308
Test name
Test status
Simulation time 12181024431 ps
CPU time 24.21 seconds
Started Jun 30 05:31:33 PM PDT 24
Finished Jun 30 05:31:57 PM PDT 24
Peak memory 249744 kb
Host smart-b124e700-f13e-467b-9881-f199f910519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435098350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.435098350
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2219424552
Short name T173
Test name
Test status
Simulation time 104310155456 ps
CPU time 206.4 seconds
Started Jun 30 05:31:35 PM PDT 24
Finished Jun 30 05:35:02 PM PDT 24
Peak memory 257464 kb
Host smart-abcd3e16-230f-4442-9b51-5c5ff2631d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219424552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2219424552
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1791605911
Short name T597
Test name
Test status
Simulation time 2107581567 ps
CPU time 13.3 seconds
Started Jun 30 05:31:35 PM PDT 24
Finished Jun 30 05:31:48 PM PDT 24
Peak memory 233144 kb
Host smart-bfe8bb41-dc2b-47bc-bed2-533a344e8125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791605911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1791605911
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3266161511
Short name T462
Test name
Test status
Simulation time 186295657708 ps
CPU time 148.46 seconds
Started Jun 30 05:31:32 PM PDT 24
Finished Jun 30 05:34:01 PM PDT 24
Peak memory 234304 kb
Host smart-65bdb3a2-da1b-47d8-8d5b-dc0c59225d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266161511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3266161511
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.93515256
Short name T987
Test name
Test status
Simulation time 13483239315 ps
CPU time 13.21 seconds
Started Jun 30 05:31:35 PM PDT 24
Finished Jun 30 05:31:49 PM PDT 24
Peak memory 237148 kb
Host smart-434cb9ac-8bfd-436a-991c-5942d3bac804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93515256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.93515256
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2576905510
Short name T268
Test name
Test status
Simulation time 4690015571 ps
CPU time 5.82 seconds
Started Jun 30 05:31:33 PM PDT 24
Finished Jun 30 05:31:39 PM PDT 24
Peak memory 225072 kb
Host smart-b766e87b-7c19-4fb5-97d9-0c90afa0070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576905510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2576905510
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4180049556
Short name T144
Test name
Test status
Simulation time 1682696603 ps
CPU time 6.97 seconds
Started Jun 30 05:31:34 PM PDT 24
Finished Jun 30 05:31:41 PM PDT 24
Peak memory 222920 kb
Host smart-ec2f93af-2dfc-43fa-a2b9-21ffe195e34b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4180049556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4180049556
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2448331146
Short name T911
Test name
Test status
Simulation time 190105936 ps
CPU time 1.01 seconds
Started Jun 30 05:31:32 PM PDT 24
Finished Jun 30 05:31:34 PM PDT 24
Peak memory 208332 kb
Host smart-ea4ab899-0ea3-4924-9456-ceec4cc47c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448331146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2448331146
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.23818630
Short name T620
Test name
Test status
Simulation time 2555297540 ps
CPU time 16.47 seconds
Started Jun 30 05:31:33 PM PDT 24
Finished Jun 30 05:31:50 PM PDT 24
Peak memory 217080 kb
Host smart-504a517b-6114-461e-ac29-bff8d91d54ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23818630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.23818630
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4179457055
Short name T90
Test name
Test status
Simulation time 5203331679 ps
CPU time 7.3 seconds
Started Jun 30 05:31:34 PM PDT 24
Finished Jun 30 05:31:42 PM PDT 24
Peak memory 216884 kb
Host smart-80e9e86a-b9b6-4ecf-90fc-5d050cd53fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179457055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4179457055
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1414403568
Short name T652
Test name
Test status
Simulation time 387514776 ps
CPU time 2.4 seconds
Started Jun 30 05:31:32 PM PDT 24
Finished Jun 30 05:31:35 PM PDT 24
Peak memory 216780 kb
Host smart-b12e53a2-933d-4936-9c13-7d24905172f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414403568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1414403568
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3604958648
Short name T643
Test name
Test status
Simulation time 99302023 ps
CPU time 0.82 seconds
Started Jun 30 05:31:33 PM PDT 24
Finished Jun 30 05:31:34 PM PDT 24
Peak memory 206460 kb
Host smart-7fdb66f7-6777-4299-93a1-4f4a6af1fb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604958648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3604958648
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3243535175
Short name T437
Test name
Test status
Simulation time 126591743 ps
CPU time 2.65 seconds
Started Jun 30 05:31:34 PM PDT 24
Finished Jun 30 05:31:37 PM PDT 24
Peak memory 224724 kb
Host smart-3830e9e2-92e7-46d8-9db8-edbb2e016704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243535175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3243535175
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3581739499
Short name T644
Test name
Test status
Simulation time 16639639 ps
CPU time 0.72 seconds
Started Jun 30 05:29:46 PM PDT 24
Finished Jun 30 05:29:47 PM PDT 24
Peak memory 205392 kb
Host smart-48f31b0c-211c-4958-abf9-77138de44983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581739499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
581739499
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2915563224
Short name T828
Test name
Test status
Simulation time 47194506 ps
CPU time 2.87 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:29:40 PM PDT 24
Peak memory 233148 kb
Host smart-6b2f7125-a3a4-44d6-bc20-38bd420cf4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915563224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2915563224
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2087109958
Short name T681
Test name
Test status
Simulation time 16588748 ps
CPU time 0.79 seconds
Started Jun 30 05:29:35 PM PDT 24
Finished Jun 30 05:29:36 PM PDT 24
Peak memory 206028 kb
Host smart-2c611eb6-d043-4b2e-902d-848e8f649fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087109958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2087109958
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.849072209
Short name T302
Test name
Test status
Simulation time 4801945096 ps
CPU time 67.93 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:30:53 PM PDT 24
Peak memory 256696 kb
Host smart-27d27eb0-1fbc-4f9e-b371-8e96d733c276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849072209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.849072209
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1969850080
Short name T225
Test name
Test status
Simulation time 10946877384 ps
CPU time 112.04 seconds
Started Jun 30 05:29:42 PM PDT 24
Finished Jun 30 05:31:35 PM PDT 24
Peak memory 249888 kb
Host smart-4c94da5f-cfdb-4df1-adcd-22ce4eb785b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969850080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1969850080
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.633084451
Short name T774
Test name
Test status
Simulation time 8185324062 ps
CPU time 143.54 seconds
Started Jun 30 05:29:48 PM PDT 24
Finished Jun 30 05:32:12 PM PDT 24
Peak memory 273712 kb
Host smart-0d4a06de-6dbb-4fa4-9987-688d5d1436c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633084451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
633084451
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3502508540
Short name T309
Test name
Test status
Simulation time 7426370793 ps
CPU time 23.19 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:29:59 PM PDT 24
Peak memory 233580 kb
Host smart-7b177683-d08b-42af-924d-de59ad264aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502508540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3502508540
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2688285336
Short name T596
Test name
Test status
Simulation time 12894289 ps
CPU time 0.8 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:29:46 PM PDT 24
Peak memory 216424 kb
Host smart-9a429a44-2b69-4fd6-9ef7-c6b553d30923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688285336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2688285336
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.50250788
Short name T97
Test name
Test status
Simulation time 2596291490 ps
CPU time 14.99 seconds
Started Jun 30 05:29:35 PM PDT 24
Finished Jun 30 05:29:51 PM PDT 24
Peak memory 225172 kb
Host smart-6bd618cb-b2b0-4a13-a294-e79df228c4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50250788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.50250788
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2021924225
Short name T213
Test name
Test status
Simulation time 9244755188 ps
CPU time 10.31 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:29:47 PM PDT 24
Peak memory 233296 kb
Host smart-2534b676-cb0b-48a7-a251-1244aa0a439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021924225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2021924225
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1962931848
Short name T262
Test name
Test status
Simulation time 51249095 ps
CPU time 2.86 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:29:39 PM PDT 24
Peak memory 233228 kb
Host smart-8043712d-e1c1-4109-a34d-d5d55648e1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962931848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1962931848
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.405860435
Short name T412
Test name
Test status
Simulation time 196480228 ps
CPU time 2.58 seconds
Started Jun 30 05:29:34 PM PDT 24
Finished Jun 30 05:29:37 PM PDT 24
Peak memory 233140 kb
Host smart-e6f0a694-19c2-4f1c-a4a2-00136d3e5558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405860435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.405860435
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2007091831
Short name T582
Test name
Test status
Simulation time 406986948 ps
CPU time 4.2 seconds
Started Jun 30 05:29:49 PM PDT 24
Finished Jun 30 05:29:54 PM PDT 24
Peak memory 223644 kb
Host smart-b599e990-597f-4c6f-a844-d113c7f3b6c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2007091831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2007091831
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3115797358
Short name T20
Test name
Test status
Simulation time 108744571 ps
CPU time 1.13 seconds
Started Jun 30 05:29:42 PM PDT 24
Finished Jun 30 05:29:44 PM PDT 24
Peak memory 236960 kb
Host smart-bfbc4e53-676a-4799-ad89-23940141d62b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115797358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3115797358
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3716784651
Short name T156
Test name
Test status
Simulation time 21672286038 ps
CPU time 90.57 seconds
Started Jun 30 05:29:48 PM PDT 24
Finished Jun 30 05:31:19 PM PDT 24
Peak memory 252060 kb
Host smart-193252b3-d9a5-4932-8177-74075a3e9077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716784651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3716784651
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2365979627
Short name T317
Test name
Test status
Simulation time 2900669634 ps
CPU time 13.28 seconds
Started Jun 30 05:29:35 PM PDT 24
Finished Jun 30 05:29:49 PM PDT 24
Peak memory 216892 kb
Host smart-e54b3875-b104-4efe-bff3-a75a5fe8e685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365979627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2365979627
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.299187038
Short name T604
Test name
Test status
Simulation time 3080011702 ps
CPU time 5.66 seconds
Started Jun 30 05:29:37 PM PDT 24
Finished Jun 30 05:29:43 PM PDT 24
Peak memory 216888 kb
Host smart-35b1e7fa-1ace-40a8-9833-b0524b37ca22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299187038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.299187038
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1604770820
Short name T401
Test name
Test status
Simulation time 442525363 ps
CPU time 3.38 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:29:40 PM PDT 24
Peak memory 216792 kb
Host smart-df79f9a8-2e59-4331-9d69-55ab3325a017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604770820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1604770820
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.431248982
Short name T736
Test name
Test status
Simulation time 58113582 ps
CPU time 0.85 seconds
Started Jun 30 05:29:36 PM PDT 24
Finished Jun 30 05:29:38 PM PDT 24
Peak memory 206460 kb
Host smart-8f834694-02f0-4d69-b50b-825fd94082a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431248982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.431248982
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1949535191
Short name T505
Test name
Test status
Simulation time 689953843 ps
CPU time 5.52 seconds
Started Jun 30 05:29:34 PM PDT 24
Finished Jun 30 05:29:40 PM PDT 24
Peak memory 233124 kb
Host smart-defdd9ba-4d40-4384-95c1-c84e60608d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949535191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1949535191
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2492537545
Short name T476
Test name
Test status
Simulation time 48200043 ps
CPU time 0.76 seconds
Started Jun 30 05:31:42 PM PDT 24
Finished Jun 30 05:31:44 PM PDT 24
Peak memory 205952 kb
Host smart-3374f5ec-8b11-402e-8002-6e253de82d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492537545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2492537545
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2445146124
Short name T273
Test name
Test status
Simulation time 595803327 ps
CPU time 2.23 seconds
Started Jun 30 05:31:40 PM PDT 24
Finished Jun 30 05:31:43 PM PDT 24
Peak memory 224912 kb
Host smart-b50ae7dc-92da-43ad-9e52-3f47fffbc8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445146124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2445146124
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2470342150
Short name T407
Test name
Test status
Simulation time 16589009 ps
CPU time 0.78 seconds
Started Jun 30 05:31:53 PM PDT 24
Finished Jun 30 05:31:55 PM PDT 24
Peak memory 207372 kb
Host smart-49b526a6-5075-4ad6-a2b6-e5b4661a54bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470342150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2470342150
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3844292554
Short name T186
Test name
Test status
Simulation time 56207346704 ps
CPU time 56.31 seconds
Started Jun 30 05:31:47 PM PDT 24
Finished Jun 30 05:32:44 PM PDT 24
Peak memory 238200 kb
Host smart-4b028a3c-a69a-4943-b2ac-83858f3fef31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844292554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3844292554
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3430724562
Short name T669
Test name
Test status
Simulation time 3880643491 ps
CPU time 65.14 seconds
Started Jun 30 05:31:44 PM PDT 24
Finished Jun 30 05:32:50 PM PDT 24
Peak memory 252928 kb
Host smart-be789d10-f7f5-485e-b928-f6a33a6d9c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430724562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3430724562
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.4011689308
Short name T206
Test name
Test status
Simulation time 635967738786 ps
CPU time 527.66 seconds
Started Jun 30 05:31:44 PM PDT 24
Finished Jun 30 05:40:32 PM PDT 24
Peak memory 255940 kb
Host smart-6a12ac5f-0673-428e-98f2-912abbc976f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011689308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.4011689308
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1667141094
Short name T764
Test name
Test status
Simulation time 9796293514 ps
CPU time 31.21 seconds
Started Jun 30 05:31:42 PM PDT 24
Finished Jun 30 05:32:13 PM PDT 24
Peak memory 233328 kb
Host smart-372b5726-99fb-4ca2-b697-37a8a085a84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667141094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1667141094
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1378305322
Short name T675
Test name
Test status
Simulation time 18483544270 ps
CPU time 62.29 seconds
Started Jun 30 05:31:42 PM PDT 24
Finished Jun 30 05:32:46 PM PDT 24
Peak memory 256852 kb
Host smart-29edf80f-5cad-4528-8204-436803a621e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378305322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1378305322
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4069630877
Short name T379
Test name
Test status
Simulation time 108760093 ps
CPU time 2.14 seconds
Started Jun 30 05:31:41 PM PDT 24
Finished Jun 30 05:31:44 PM PDT 24
Peak memory 224796 kb
Host smart-7297e4f8-c813-4108-853f-ad5598dc6f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069630877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4069630877
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3763763025
Short name T899
Test name
Test status
Simulation time 9495883050 ps
CPU time 22.08 seconds
Started Jun 30 05:31:39 PM PDT 24
Finished Jun 30 05:32:02 PM PDT 24
Peak memory 239344 kb
Host smart-2c7485cd-507c-4a3b-b116-b60b6d55e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763763025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3763763025
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4088302330
Short name T930
Test name
Test status
Simulation time 2667959606 ps
CPU time 7.46 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:31:55 PM PDT 24
Peak memory 233528 kb
Host smart-23a87afd-53ed-42f1-9364-73cb74b21648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088302330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4088302330
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4073792207
Short name T760
Test name
Test status
Simulation time 2592736309 ps
CPU time 6.37 seconds
Started Jun 30 05:31:39 PM PDT 24
Finished Jun 30 05:31:46 PM PDT 24
Peak memory 233296 kb
Host smart-07c665ab-82ff-4c95-aee2-796b214ec1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073792207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4073792207
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.147692020
Short name T563
Test name
Test status
Simulation time 868256950 ps
CPU time 4.33 seconds
Started Jun 30 05:31:46 PM PDT 24
Finished Jun 30 05:31:51 PM PDT 24
Peak memory 219792 kb
Host smart-d92cb477-caec-4003-abb3-0d80db252037
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=147692020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.147692020
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4152832741
Short name T157
Test name
Test status
Simulation time 52757310 ps
CPU time 0.98 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:31:49 PM PDT 24
Peak memory 207092 kb
Host smart-e995f202-a4ed-43b9-91d4-5b7af046302b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152832741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4152832741
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3634871856
Short name T63
Test name
Test status
Simulation time 6437518090 ps
CPU time 38.04 seconds
Started Jun 30 05:31:43 PM PDT 24
Finished Jun 30 05:32:21 PM PDT 24
Peak memory 217004 kb
Host smart-1b489a68-351c-43ee-8e49-7ba14fc9b9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634871856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3634871856
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.475409030
Short name T503
Test name
Test status
Simulation time 1843510596 ps
CPU time 11.33 seconds
Started Jun 30 05:31:40 PM PDT 24
Finished Jun 30 05:31:52 PM PDT 24
Peak memory 216780 kb
Host smart-a3d87de1-ecff-4317-89c9-9a1a65a30167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475409030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.475409030
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.628725406
Short name T888
Test name
Test status
Simulation time 204101711 ps
CPU time 7.29 seconds
Started Jun 30 05:31:40 PM PDT 24
Finished Jun 30 05:31:47 PM PDT 24
Peak memory 216836 kb
Host smart-10050ad9-c9e3-4ca3-a61a-702a3cf7e87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628725406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.628725406
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1098689434
Short name T426
Test name
Test status
Simulation time 332848810 ps
CPU time 0.98 seconds
Started Jun 30 05:31:41 PM PDT 24
Finished Jun 30 05:31:42 PM PDT 24
Peak memory 206712 kb
Host smart-0d9a46a5-03e1-49a4-bb7d-62875f55b194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098689434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1098689434
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.238229969
Short name T662
Test name
Test status
Simulation time 41791859 ps
CPU time 2.34 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:31:51 PM PDT 24
Peak memory 233148 kb
Host smart-846818e5-bca8-4c5b-b10b-e6e1452bf3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238229969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.238229969
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3666654876
Short name T833
Test name
Test status
Simulation time 13490032 ps
CPU time 0.7 seconds
Started Jun 30 05:31:47 PM PDT 24
Finished Jun 30 05:31:48 PM PDT 24
Peak memory 205360 kb
Host smart-3318e946-6901-4cff-a550-985cefe0edb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666654876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3666654876
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1422559541
Short name T924
Test name
Test status
Simulation time 9845953959 ps
CPU time 27.45 seconds
Started Jun 30 05:31:43 PM PDT 24
Finished Jun 30 05:32:11 PM PDT 24
Peak memory 233244 kb
Host smart-b83847c1-b73e-48c3-9773-3fa8c300d560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422559541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1422559541
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.88246530
Short name T365
Test name
Test status
Simulation time 17822689 ps
CPU time 0.78 seconds
Started Jun 30 05:31:46 PM PDT 24
Finished Jun 30 05:31:47 PM PDT 24
Peak memory 207404 kb
Host smart-66941a47-be54-4988-bd37-c25e4e9b374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88246530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.88246530
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.744496426
Short name T727
Test name
Test status
Simulation time 112790061045 ps
CPU time 206.59 seconds
Started Jun 30 05:31:50 PM PDT 24
Finished Jun 30 05:35:17 PM PDT 24
Peak memory 250740 kb
Host smart-c21bf661-4b88-4144-9b37-9d63ecf4b654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744496426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.744496426
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3147728770
Short name T687
Test name
Test status
Simulation time 99059727904 ps
CPU time 168.3 seconds
Started Jun 30 05:31:49 PM PDT 24
Finished Jun 30 05:34:38 PM PDT 24
Peak memory 254348 kb
Host smart-87c54580-4486-4a7a-89b2-c0f4cb23627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147728770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3147728770
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.339063902
Short name T232
Test name
Test status
Simulation time 7272062399 ps
CPU time 26.48 seconds
Started Jun 30 05:31:49 PM PDT 24
Finished Jun 30 05:32:16 PM PDT 24
Peak memory 249832 kb
Host smart-c855891f-d180-48a9-9bd9-5de54c564d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339063902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.339063902
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4169026575
Short name T791
Test name
Test status
Simulation time 1630429002 ps
CPU time 9.34 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:31:59 PM PDT 24
Peak memory 235572 kb
Host smart-8b96a541-e5bd-4f1f-b99d-b22eafb1603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169026575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4169026575
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1662385760
Short name T234
Test name
Test status
Simulation time 37503457885 ps
CPU time 259.5 seconds
Started Jun 30 05:31:49 PM PDT 24
Finished Jun 30 05:36:10 PM PDT 24
Peak memory 263556 kb
Host smart-a82e5f1a-7330-4c96-ac9b-bf9580410148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662385760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1662385760
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2907615945
Short name T561
Test name
Test status
Simulation time 1392625794 ps
CPU time 5.58 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:31:54 PM PDT 24
Peak memory 224936 kb
Host smart-dfaf96d3-133f-4534-9873-d9307148cfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907615945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2907615945
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1743444238
Short name T813
Test name
Test status
Simulation time 113366281 ps
CPU time 3.48 seconds
Started Jun 30 05:31:42 PM PDT 24
Finished Jun 30 05:31:46 PM PDT 24
Peak memory 225020 kb
Host smart-53a23027-eec9-4dca-8b79-2d15deef2e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743444238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1743444238
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2386730153
Short name T283
Test name
Test status
Simulation time 1781546499 ps
CPU time 8.08 seconds
Started Jun 30 05:31:40 PM PDT 24
Finished Jun 30 05:31:48 PM PDT 24
Peak memory 233232 kb
Host smart-e868aad5-e752-4eb7-a728-7e11ba6c0741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386730153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2386730153
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.861072738
Short name T406
Test name
Test status
Simulation time 5327238568 ps
CPU time 7.41 seconds
Started Jun 30 05:31:39 PM PDT 24
Finished Jun 30 05:31:46 PM PDT 24
Peak memory 229764 kb
Host smart-36176c1b-3952-4316-bbe2-3cc44b71259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861072738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.861072738
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1586132370
Short name T800
Test name
Test status
Simulation time 974171095 ps
CPU time 5.63 seconds
Started Jun 30 05:31:51 PM PDT 24
Finished Jun 30 05:31:57 PM PDT 24
Peak memory 223580 kb
Host smart-0c1feeaa-5f5a-4bf4-b86d-027952bcbfe0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1586132370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1586132370
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4162027007
Short name T323
Test name
Test status
Simulation time 30501876285 ps
CPU time 38.12 seconds
Started Jun 30 05:31:44 PM PDT 24
Finished Jun 30 05:32:23 PM PDT 24
Peak memory 216908 kb
Host smart-b39a477f-c0ba-4384-bbd8-65f239a71eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162027007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4162027007
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4004440021
Short name T59
Test name
Test status
Simulation time 27051435780 ps
CPU time 17.15 seconds
Started Jun 30 05:31:41 PM PDT 24
Finished Jun 30 05:31:59 PM PDT 24
Peak memory 216900 kb
Host smart-d5a4b55b-722c-4406-8fd7-e49aa0e5eeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004440021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4004440021
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2171461867
Short name T330
Test name
Test status
Simulation time 265710358 ps
CPU time 2.08 seconds
Started Jun 30 05:31:43 PM PDT 24
Finished Jun 30 05:31:46 PM PDT 24
Peak memory 216748 kb
Host smart-9dcae1f7-3e44-4aae-8180-c87ad3799a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171461867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2171461867
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4037155953
Short name T557
Test name
Test status
Simulation time 28481329 ps
CPU time 0.85 seconds
Started Jun 30 05:31:42 PM PDT 24
Finished Jun 30 05:31:43 PM PDT 24
Peak memory 206448 kb
Host smart-7425308a-3f1b-4a29-81ec-cfed555af3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037155953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4037155953
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3692397717
Short name T820
Test name
Test status
Simulation time 76283468 ps
CPU time 2.44 seconds
Started Jun 30 05:31:43 PM PDT 24
Finished Jun 30 05:31:46 PM PDT 24
Peak memory 224984 kb
Host smart-291ce841-6386-4dd6-8afc-ad520062833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692397717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3692397717
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1235234435
Short name T659
Test name
Test status
Simulation time 23610426 ps
CPU time 0.74 seconds
Started Jun 30 05:31:50 PM PDT 24
Finished Jun 30 05:31:51 PM PDT 24
Peak memory 205344 kb
Host smart-745ea145-fbd9-4ed0-808e-5484c1d58192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235234435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1235234435
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.708598409
Short name T617
Test name
Test status
Simulation time 342218260 ps
CPU time 5.62 seconds
Started Jun 30 05:31:52 PM PDT 24
Finished Jun 30 05:31:58 PM PDT 24
Peak memory 233016 kb
Host smart-5c92dc54-658d-4ddd-9ba0-b32835b4f2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708598409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.708598409
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.146780723
Short name T66
Test name
Test status
Simulation time 137795733 ps
CPU time 0.79 seconds
Started Jun 30 05:31:49 PM PDT 24
Finished Jun 30 05:31:50 PM PDT 24
Peak memory 207096 kb
Host smart-5b350198-44ea-4e84-8ed0-ba5479106c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146780723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.146780723
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3835905388
Short name T651
Test name
Test status
Simulation time 31980582864 ps
CPU time 57.98 seconds
Started Jun 30 05:31:47 PM PDT 24
Finished Jun 30 05:32:46 PM PDT 24
Peak memory 257876 kb
Host smart-03935d27-e4be-4052-aecd-65b2187c2024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835905388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3835905388
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1227708414
Short name T460
Test name
Test status
Simulation time 18230767841 ps
CPU time 149.15 seconds
Started Jun 30 05:31:52 PM PDT 24
Finished Jun 30 05:34:21 PM PDT 24
Peak memory 252896 kb
Host smart-e9bcd3d2-b714-41c7-abfc-a5df0f378acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227708414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1227708414
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3067356363
Short name T986
Test name
Test status
Simulation time 489716694 ps
CPU time 4.92 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:31:54 PM PDT 24
Peak memory 224980 kb
Host smart-156f9402-466d-4cda-a7e4-902014f26c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067356363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3067356363
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2819357960
Short name T305
Test name
Test status
Simulation time 122115665703 ps
CPU time 195.21 seconds
Started Jun 30 05:31:51 PM PDT 24
Finished Jun 30 05:35:07 PM PDT 24
Peak memory 253216 kb
Host smart-e6ba01dc-7b6f-48bb-9482-3e2795f9732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819357960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2819357960
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.80932994
Short name T688
Test name
Test status
Simulation time 2148094049 ps
CPU time 21.05 seconds
Started Jun 30 05:31:52 PM PDT 24
Finished Jun 30 05:32:13 PM PDT 24
Peak memory 225060 kb
Host smart-dc6262fa-4346-4031-aa21-2b6988471da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80932994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.80932994
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2635588489
Short name T218
Test name
Test status
Simulation time 691779675 ps
CPU time 12.32 seconds
Started Jun 30 05:31:50 PM PDT 24
Finished Jun 30 05:32:03 PM PDT 24
Peak memory 233176 kb
Host smart-e91235af-8ed2-4f11-8511-667539ded3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635588489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2635588489
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2885972140
Short name T925
Test name
Test status
Simulation time 287513988 ps
CPU time 5.81 seconds
Started Jun 30 05:31:51 PM PDT 24
Finished Jun 30 05:31:57 PM PDT 24
Peak memory 233108 kb
Host smart-4d02589f-4b83-4a05-89be-6c000dfd7692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885972140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2885972140
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1424753369
Short name T592
Test name
Test status
Simulation time 228969573 ps
CPU time 3.49 seconds
Started Jun 30 05:31:49 PM PDT 24
Finished Jun 30 05:31:53 PM PDT 24
Peak memory 233156 kb
Host smart-eaaf083b-4cd0-4cbf-b185-552df0b09d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424753369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1424753369
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4199157663
Short name T810
Test name
Test status
Simulation time 1210001632 ps
CPU time 7.08 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:31:56 PM PDT 24
Peak memory 219944 kb
Host smart-7d3691af-a8c2-4538-9fb1-86f32a1f7ae5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4199157663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4199157663
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2419192902
Short name T134
Test name
Test status
Simulation time 90860427902 ps
CPU time 226.26 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:35:35 PM PDT 24
Peak memory 270216 kb
Host smart-de551df8-750c-45ec-b671-8bdbab386b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419192902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2419192902
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3783965259
Short name T817
Test name
Test status
Simulation time 4440538295 ps
CPU time 9 seconds
Started Jun 30 05:31:49 PM PDT 24
Finished Jun 30 05:31:59 PM PDT 24
Peak memory 217140 kb
Host smart-2106cc77-a00c-4749-bc4f-b36df6255a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783965259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3783965259
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.963605774
Short name T341
Test name
Test status
Simulation time 11755464319 ps
CPU time 16.88 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:32:06 PM PDT 24
Peak memory 216944 kb
Host smart-b0440aeb-0ca5-43e3-ab7e-8cd2ceda29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963605774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.963605774
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1073351210
Short name T435
Test name
Test status
Simulation time 501268156 ps
CPU time 2.7 seconds
Started Jun 30 05:31:50 PM PDT 24
Finished Jun 30 05:31:54 PM PDT 24
Peak memory 216764 kb
Host smart-31f50739-2519-4ead-a87e-e2ef8e0cb82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073351210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1073351210
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3958751138
Short name T392
Test name
Test status
Simulation time 17654322 ps
CPU time 0.73 seconds
Started Jun 30 05:31:51 PM PDT 24
Finished Jun 30 05:31:52 PM PDT 24
Peak memory 206444 kb
Host smart-8a28cbf8-f589-4f3d-aade-d5f977a4c1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958751138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3958751138
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2627544674
Short name T812
Test name
Test status
Simulation time 834693986 ps
CPU time 5.07 seconds
Started Jun 30 05:31:52 PM PDT 24
Finished Jun 30 05:31:58 PM PDT 24
Peak memory 249624 kb
Host smart-3cb1f366-7fe7-4546-b675-6425134760e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627544674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2627544674
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3643040196
Short name T915
Test name
Test status
Simulation time 81388440 ps
CPU time 0.77 seconds
Started Jun 30 05:32:04 PM PDT 24
Finished Jun 30 05:32:05 PM PDT 24
Peak memory 205376 kb
Host smart-8fc6b6b4-ec49-4ffa-b8f4-025c8d5f5a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643040196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3643040196
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3772508783
Short name T655
Test name
Test status
Simulation time 2204327603 ps
CPU time 6.05 seconds
Started Jun 30 05:31:56 PM PDT 24
Finished Jun 30 05:32:03 PM PDT 24
Peak memory 225136 kb
Host smart-e10ad12c-3ad9-40ce-a990-44fff93cde00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772508783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3772508783
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2794004460
Short name T653
Test name
Test status
Simulation time 23843569 ps
CPU time 0.74 seconds
Started Jun 30 05:31:49 PM PDT 24
Finished Jun 30 05:31:51 PM PDT 24
Peak memory 206072 kb
Host smart-449e1990-c682-4503-9609-8d138f124a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794004460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2794004460
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.420998630
Short name T822
Test name
Test status
Simulation time 43102641693 ps
CPU time 90.57 seconds
Started Jun 30 05:31:56 PM PDT 24
Finished Jun 30 05:33:27 PM PDT 24
Peak memory 266116 kb
Host smart-ba3857f3-f0a1-42c0-82ea-452351c001e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420998630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.420998630
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4247533398
Short name T139
Test name
Test status
Simulation time 12523247388 ps
CPU time 37.64 seconds
Started Jun 30 05:31:57 PM PDT 24
Finished Jun 30 05:32:35 PM PDT 24
Peak memory 238216 kb
Host smart-1e071259-c4fb-47a8-91ba-14a913aa234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247533398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4247533398
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3306973467
Short name T432
Test name
Test status
Simulation time 12759159164 ps
CPU time 129.24 seconds
Started Jun 30 05:31:56 PM PDT 24
Finished Jun 30 05:34:06 PM PDT 24
Peak memory 241664 kb
Host smart-75f99261-3517-4205-9876-35649107c9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306973467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3306973467
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3485300443
Short name T821
Test name
Test status
Simulation time 4410921571 ps
CPU time 68.58 seconds
Started Jun 30 05:32:02 PM PDT 24
Finished Jun 30 05:33:11 PM PDT 24
Peak memory 249392 kb
Host smart-58aaa5d6-5911-4d5a-a981-5ae8325344e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485300443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3485300443
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4252367166
Short name T210
Test name
Test status
Simulation time 6684796529 ps
CPU time 25.85 seconds
Started Jun 30 05:31:52 PM PDT 24
Finished Jun 30 05:32:19 PM PDT 24
Peak memory 225100 kb
Host smart-afed9ce3-c557-4ab6-a57c-b6afc249a0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252367166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4252367166
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3541852882
Short name T989
Test name
Test status
Simulation time 9032067247 ps
CPU time 38.76 seconds
Started Jun 30 05:31:51 PM PDT 24
Finished Jun 30 05:32:30 PM PDT 24
Peak memory 233288 kb
Host smart-74804308-2fc5-44ba-8d88-cbb00d335da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541852882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3541852882
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.4146814711
Short name T293
Test name
Test status
Simulation time 2910580580 ps
CPU time 11.04 seconds
Started Jun 30 05:31:49 PM PDT 24
Finished Jun 30 05:32:01 PM PDT 24
Peak memory 233248 kb
Host smart-6107d694-371b-41db-bb84-6499207b46de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146814711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.4146814711
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2011737618
Short name T451
Test name
Test status
Simulation time 4546262761 ps
CPU time 13.34 seconds
Started Jun 30 05:31:52 PM PDT 24
Finished Jun 30 05:32:06 PM PDT 24
Peak memory 233304 kb
Host smart-12643df0-e184-469e-8b20-8f615a7ceebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011737618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2011737618
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3508747155
Short name T424
Test name
Test status
Simulation time 1926980467 ps
CPU time 9.11 seconds
Started Jun 30 05:32:02 PM PDT 24
Finished Jun 30 05:32:11 PM PDT 24
Peak memory 220792 kb
Host smart-f1517584-d772-4fa6-b9a7-2d2985500684
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3508747155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3508747155
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.4102024154
Short name T56
Test name
Test status
Simulation time 35589495010 ps
CPU time 91.39 seconds
Started Jun 30 05:31:57 PM PDT 24
Finished Jun 30 05:33:29 PM PDT 24
Peak memory 272152 kb
Host smart-6785f37d-0947-4f53-9808-c7ddddae5811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102024154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.4102024154
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.137444085
Short name T912
Test name
Test status
Simulation time 1000266051 ps
CPU time 3.5 seconds
Started Jun 30 05:31:49 PM PDT 24
Finished Jun 30 05:31:53 PM PDT 24
Peak memory 216784 kb
Host smart-2ce68df1-ec11-45a0-bd3e-17aad5e84210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137444085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.137444085
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2735667474
Short name T910
Test name
Test status
Simulation time 23304457200 ps
CPU time 19.7 seconds
Started Jun 30 05:31:51 PM PDT 24
Finished Jun 30 05:32:11 PM PDT 24
Peak memory 216924 kb
Host smart-698b2c2f-fe39-4320-97e2-a0eb871f2e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735667474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2735667474
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3787638930
Short name T32
Test name
Test status
Simulation time 73518958 ps
CPU time 1.34 seconds
Started Jun 30 05:31:52 PM PDT 24
Finished Jun 30 05:31:54 PM PDT 24
Peak memory 216800 kb
Host smart-3aed3ff3-e478-4355-8913-5eb4d85d2c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787638930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3787638930
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2070702375
Short name T589
Test name
Test status
Simulation time 71739148 ps
CPU time 0.91 seconds
Started Jun 30 05:31:48 PM PDT 24
Finished Jun 30 05:31:50 PM PDT 24
Peak memory 206440 kb
Host smart-890c2934-ac1f-4cf1-8e9f-1f8f2763a33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070702375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2070702375
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3374032845
Short name T942
Test name
Test status
Simulation time 219216895 ps
CPU time 2.72 seconds
Started Jun 30 05:32:02 PM PDT 24
Finished Jun 30 05:32:06 PM PDT 24
Peak memory 224400 kb
Host smart-9052ad5f-1c06-4a0f-9b35-3da444f5a816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374032845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3374032845
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1055450414
Short name T968
Test name
Test status
Simulation time 157279593 ps
CPU time 0.71 seconds
Started Jun 30 05:32:05 PM PDT 24
Finished Jun 30 05:32:06 PM PDT 24
Peak memory 205928 kb
Host smart-d390d417-e80c-44db-9438-5e6a00bdc68c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055450414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1055450414
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2554974293
Short name T605
Test name
Test status
Simulation time 80887221 ps
CPU time 2.41 seconds
Started Jun 30 05:31:59 PM PDT 24
Finished Jun 30 05:32:02 PM PDT 24
Peak memory 224952 kb
Host smart-1f6f4eab-4a38-4d3f-b0bd-406a14e64b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554974293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2554974293
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4277510878
Short name T349
Test name
Test status
Simulation time 21323828 ps
CPU time 0.78 seconds
Started Jun 30 05:31:58 PM PDT 24
Finished Jun 30 05:31:59 PM PDT 24
Peak memory 206296 kb
Host smart-777e616f-eac5-40c2-9688-4a99f862bb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277510878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4277510878
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3184425654
Short name T863
Test name
Test status
Simulation time 60108444444 ps
CPU time 43.14 seconds
Started Jun 30 05:31:56 PM PDT 24
Finished Jun 30 05:32:40 PM PDT 24
Peak memory 238036 kb
Host smart-c977fb38-2318-4c25-86f1-666b81ce2685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184425654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3184425654
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.947387600
Short name T496
Test name
Test status
Simulation time 1358554200 ps
CPU time 6.8 seconds
Started Jun 30 05:31:58 PM PDT 24
Finished Jun 30 05:32:06 PM PDT 24
Peak memory 225256 kb
Host smart-fb91941c-19de-4043-983e-49e889c8962e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947387600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.947387600
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2338507737
Short name T286
Test name
Test status
Simulation time 25516570687 ps
CPU time 260.34 seconds
Started Jun 30 05:32:04 PM PDT 24
Finished Jun 30 05:36:24 PM PDT 24
Peak memory 270220 kb
Host smart-77e783ef-9674-44be-a8b7-1b46f87a7b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338507737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2338507737
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.826826742
Short name T40
Test name
Test status
Simulation time 499938261 ps
CPU time 5.76 seconds
Started Jun 30 05:32:01 PM PDT 24
Finished Jun 30 05:32:07 PM PDT 24
Peak memory 233212 kb
Host smart-a4683204-ec36-4744-bd93-5c9dd77a8a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826826742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.826826742
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3601572521
Short name T954
Test name
Test status
Simulation time 7172536837 ps
CPU time 29.88 seconds
Started Jun 30 05:31:55 PM PDT 24
Finished Jun 30 05:32:25 PM PDT 24
Peak memory 254336 kb
Host smart-643b4b15-6cc3-4133-9850-b74e735c20ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601572521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3601572521
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1302644468
Short name T779
Test name
Test status
Simulation time 947676479 ps
CPU time 4.35 seconds
Started Jun 30 05:32:00 PM PDT 24
Finished Jun 30 05:32:05 PM PDT 24
Peak memory 224584 kb
Host smart-d0681209-1c8a-43bf-9820-b2120098d3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302644468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1302644468
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1394633600
Short name T272
Test name
Test status
Simulation time 12715430482 ps
CPU time 34.52 seconds
Started Jun 30 05:31:57 PM PDT 24
Finished Jun 30 05:32:32 PM PDT 24
Peak memory 241376 kb
Host smart-ec3146c1-5ae0-4b16-8d7d-d0982331920e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394633600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1394633600
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.196523820
Short name T754
Test name
Test status
Simulation time 1830881663 ps
CPU time 5.22 seconds
Started Jun 30 05:32:00 PM PDT 24
Finished Jun 30 05:32:06 PM PDT 24
Peak memory 233860 kb
Host smart-157b9a6b-6d57-4a1f-9730-5742e33ba670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196523820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.196523820
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.400444471
Short name T356
Test name
Test status
Simulation time 89756640 ps
CPU time 2.07 seconds
Started Jun 30 05:31:59 PM PDT 24
Finished Jun 30 05:32:01 PM PDT 24
Peak memory 224776 kb
Host smart-ee30e23e-882a-40c4-a5b2-84bf075b7261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400444471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.400444471
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1658607896
Short name T647
Test name
Test status
Simulation time 86564423 ps
CPU time 3.51 seconds
Started Jun 30 05:32:02 PM PDT 24
Finished Jun 30 05:32:07 PM PDT 24
Peak memory 223244 kb
Host smart-21ef98b0-dea4-4948-9a96-c0e0a9a91dd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1658607896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1658607896
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2367505862
Short name T320
Test name
Test status
Simulation time 8722395287 ps
CPU time 14.23 seconds
Started Jun 30 05:31:56 PM PDT 24
Finished Jun 30 05:32:11 PM PDT 24
Peak memory 217240 kb
Host smart-053f70bb-e88f-44e6-a4a8-4db2f6ecf211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367505862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2367505862
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.539988320
Short name T33
Test name
Test status
Simulation time 1758702025 ps
CPU time 5.24 seconds
Started Jun 30 05:31:56 PM PDT 24
Finished Jun 30 05:32:01 PM PDT 24
Peak memory 216688 kb
Host smart-19f18e27-9581-44da-b748-c78879d7f65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539988320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.539988320
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.34581075
Short name T541
Test name
Test status
Simulation time 120067449 ps
CPU time 2.12 seconds
Started Jun 30 05:32:01 PM PDT 24
Finished Jun 30 05:32:03 PM PDT 24
Peak memory 216780 kb
Host smart-e4e45b3c-6069-46e2-a0de-1e231e7aa4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34581075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.34581075
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1649020651
Short name T350
Test name
Test status
Simulation time 11428642 ps
CPU time 0.73 seconds
Started Jun 30 05:31:54 PM PDT 24
Finished Jun 30 05:31:55 PM PDT 24
Peak memory 206100 kb
Host smart-6b49525a-8531-43c0-91db-ca34459088bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649020651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1649020651
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.999337721
Short name T574
Test name
Test status
Simulation time 4707323296 ps
CPU time 19.37 seconds
Started Jun 30 05:31:56 PM PDT 24
Finished Jun 30 05:32:17 PM PDT 24
Peak memory 225116 kb
Host smart-cff60fef-0981-4b39-9ba6-d3a7decbc79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999337721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.999337721
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.674506187
Short name T815
Test name
Test status
Simulation time 10774555 ps
CPU time 0.7 seconds
Started Jun 30 05:32:05 PM PDT 24
Finished Jun 30 05:32:06 PM PDT 24
Peak memory 205916 kb
Host smart-f653fc70-3df7-46f9-b688-f3f303cf13af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674506187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.674506187
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2424662992
Short name T257
Test name
Test status
Simulation time 734705519 ps
CPU time 6.43 seconds
Started Jun 30 05:32:04 PM PDT 24
Finished Jun 30 05:32:11 PM PDT 24
Peak memory 224960 kb
Host smart-58c491c1-0714-40b1-bf43-257f3f042a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424662992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2424662992
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1420050865
Short name T362
Test name
Test status
Simulation time 18153664 ps
CPU time 0.82 seconds
Started Jun 30 05:32:04 PM PDT 24
Finished Jun 30 05:32:05 PM PDT 24
Peak memory 207324 kb
Host smart-9210467d-ba5e-44e4-ad2c-b82fb6710c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420050865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1420050865
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3316228395
Short name T606
Test name
Test status
Simulation time 7971757318 ps
CPU time 68.1 seconds
Started Jun 30 05:32:05 PM PDT 24
Finished Jun 30 05:33:14 PM PDT 24
Peak memory 257912 kb
Host smart-d8a4fcef-afc9-40f5-b3ee-efd11a6518b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316228395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3316228395
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3952190590
Short name T861
Test name
Test status
Simulation time 74330184634 ps
CPU time 56.52 seconds
Started Jun 30 05:32:02 PM PDT 24
Finished Jun 30 05:33:00 PM PDT 24
Peak memory 250832 kb
Host smart-51e9aa2a-c5ba-413f-9527-0a9b6996a12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952190590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3952190590
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2833442756
Short name T37
Test name
Test status
Simulation time 9582913806 ps
CPU time 58.17 seconds
Started Jun 30 05:32:02 PM PDT 24
Finished Jun 30 05:33:01 PM PDT 24
Peak memory 249844 kb
Host smart-bb7b8431-29d7-47b4-b3dc-cc6b1721977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833442756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2833442756
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3463120762
Short name T311
Test name
Test status
Simulation time 1590598074 ps
CPU time 24.32 seconds
Started Jun 30 05:32:04 PM PDT 24
Finished Jun 30 05:32:29 PM PDT 24
Peak memory 249492 kb
Host smart-fb85cae5-de07-4606-8392-bb10343c770d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463120762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3463120762
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.114030552
Short name T197
Test name
Test status
Simulation time 5381900153 ps
CPU time 99.53 seconds
Started Jun 30 05:32:04 PM PDT 24
Finished Jun 30 05:33:44 PM PDT 24
Peak memory 274288 kb
Host smart-7658ac58-f674-4d57-be8b-9872c56064cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114030552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.114030552
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2171550366
Short name T254
Test name
Test status
Simulation time 13803169384 ps
CPU time 9.97 seconds
Started Jun 30 05:32:03 PM PDT 24
Finished Jun 30 05:32:13 PM PDT 24
Peak memory 233244 kb
Host smart-19a3a8d1-6ff8-439b-ba4d-8e09c5d75dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171550366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2171550366
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2866996976
Short name T639
Test name
Test status
Simulation time 12106659002 ps
CPU time 15.45 seconds
Started Jun 30 05:32:03 PM PDT 24
Finished Jun 30 05:32:19 PM PDT 24
Peak memory 225156 kb
Host smart-cec87b52-e066-46ec-a4d6-e3bce466d318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866996976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2866996976
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2388512647
Short name T520
Test name
Test status
Simulation time 72927389 ps
CPU time 2.42 seconds
Started Jun 30 05:32:02 PM PDT 24
Finished Jun 30 05:32:05 PM PDT 24
Peak memory 233176 kb
Host smart-dc306122-d1fa-4755-8cc8-4fb6e317466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388512647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2388512647
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1670213659
Short name T739
Test name
Test status
Simulation time 4377951710 ps
CPU time 6.4 seconds
Started Jun 30 05:32:05 PM PDT 24
Finished Jun 30 05:32:12 PM PDT 24
Peak memory 233528 kb
Host smart-51c96f9b-14f2-4c84-aa19-91f17992d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670213659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1670213659
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3699107631
Short name T3
Test name
Test status
Simulation time 420042503 ps
CPU time 7.7 seconds
Started Jun 30 05:32:04 PM PDT 24
Finished Jun 30 05:32:12 PM PDT 24
Peak memory 219884 kb
Host smart-176d0c22-bfa1-4586-a9c1-a79ee85e2899
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3699107631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3699107631
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2468384877
Short name T522
Test name
Test status
Simulation time 1406599932 ps
CPU time 10.61 seconds
Started Jun 30 05:32:05 PM PDT 24
Finished Jun 30 05:32:16 PM PDT 24
Peak memory 217016 kb
Host smart-663848ae-9b03-4b1d-b175-8a900c0a39f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468384877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2468384877
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2479018085
Short name T836
Test name
Test status
Simulation time 3085395675 ps
CPU time 9.36 seconds
Started Jun 30 05:32:04 PM PDT 24
Finished Jun 30 05:32:14 PM PDT 24
Peak memory 216956 kb
Host smart-f599bb34-f68b-49e1-99a4-a392465a4714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479018085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2479018085
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1890253620
Short name T384
Test name
Test status
Simulation time 906105335 ps
CPU time 3.76 seconds
Started Jun 30 05:32:05 PM PDT 24
Finished Jun 30 05:32:09 PM PDT 24
Peak memory 216764 kb
Host smart-ed772503-f90a-4dbf-9284-05325f3bcb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890253620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1890253620
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4263776691
Short name T347
Test name
Test status
Simulation time 49510644 ps
CPU time 0.77 seconds
Started Jun 30 05:32:03 PM PDT 24
Finished Jun 30 05:32:04 PM PDT 24
Peak memory 206376 kb
Host smart-351493e1-b6e8-44fb-8bc5-997aa2f5f29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263776691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4263776691
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.905161990
Short name T251
Test name
Test status
Simulation time 1677476996 ps
CPU time 3.98 seconds
Started Jun 30 05:32:06 PM PDT 24
Finished Jun 30 05:32:10 PM PDT 24
Peak memory 233164 kb
Host smart-9879976f-deb3-489a-be79-42cf90d5a8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905161990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.905161990
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.454118169
Short name T345
Test name
Test status
Simulation time 12681512 ps
CPU time 0.71 seconds
Started Jun 30 05:32:12 PM PDT 24
Finished Jun 30 05:32:13 PM PDT 24
Peak memory 205392 kb
Host smart-45dbe20d-813a-4795-ba6a-08752d670fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454118169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.454118169
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.657184294
Short name T94
Test name
Test status
Simulation time 234165171 ps
CPU time 2.58 seconds
Started Jun 30 05:32:12 PM PDT 24
Finished Jun 30 05:32:15 PM PDT 24
Peak memory 224964 kb
Host smart-920cb09a-3f94-4d33-92ec-9840ebfb2f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657184294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.657184294
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.767580804
Short name T902
Test name
Test status
Simulation time 55382936 ps
CPU time 0.83 seconds
Started Jun 30 05:32:07 PM PDT 24
Finished Jun 30 05:32:08 PM PDT 24
Peak memory 207428 kb
Host smart-4ceb5b67-c00f-4bae-aa1b-e36a53c6d786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767580804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.767580804
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3453050559
Short name T171
Test name
Test status
Simulation time 6393762983 ps
CPU time 37.58 seconds
Started Jun 30 05:32:10 PM PDT 24
Finished Jun 30 05:32:48 PM PDT 24
Peak memory 249732 kb
Host smart-d3c5f662-f0ab-4e98-a32a-bf5ac72e2401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453050559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3453050559
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3758920473
Short name T474
Test name
Test status
Simulation time 22010032251 ps
CPU time 130.14 seconds
Started Jun 30 05:32:09 PM PDT 24
Finished Jun 30 05:34:20 PM PDT 24
Peak memory 258008 kb
Host smart-10df85a7-5cbc-4018-8ed3-0a9d4de48b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758920473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3758920473
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.440647066
Short name T515
Test name
Test status
Simulation time 24934227875 ps
CPU time 43.68 seconds
Started Jun 30 05:32:09 PM PDT 24
Finished Jun 30 05:32:53 PM PDT 24
Peak memory 225292 kb
Host smart-94aa3426-b08a-4feb-817b-e0f912258a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440647066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.440647066
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1953120260
Short name T649
Test name
Test status
Simulation time 3559480831 ps
CPU time 15.98 seconds
Started Jun 30 05:32:13 PM PDT 24
Finished Jun 30 05:32:29 PM PDT 24
Peak memory 225152 kb
Host smart-684a3f64-63be-4e0f-8ec6-a045b66ca2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953120260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1953120260
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1706676151
Short name T898
Test name
Test status
Simulation time 48414395298 ps
CPU time 179.02 seconds
Started Jun 30 05:32:09 PM PDT 24
Finished Jun 30 05:35:09 PM PDT 24
Peak memory 253880 kb
Host smart-df339399-f8d7-4e34-9a9c-9e9db888029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706676151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1706676151
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.215242410
Short name T913
Test name
Test status
Simulation time 93363039 ps
CPU time 3.79 seconds
Started Jun 30 05:32:10 PM PDT 24
Finished Jun 30 05:32:14 PM PDT 24
Peak memory 233136 kb
Host smart-36210d1e-629f-4c63-a5a4-178c09c3b65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215242410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.215242410
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.496956937
Short name T634
Test name
Test status
Simulation time 614725132 ps
CPU time 8.23 seconds
Started Jun 30 05:32:10 PM PDT 24
Finished Jun 30 05:32:19 PM PDT 24
Peak memory 225024 kb
Host smart-dcbd8e20-ffeb-4740-8218-ff8f335b296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496956937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.496956937
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1875217368
Short name T635
Test name
Test status
Simulation time 553183161 ps
CPU time 4.05 seconds
Started Jun 30 05:32:12 PM PDT 24
Finished Jun 30 05:32:17 PM PDT 24
Peak memory 225008 kb
Host smart-7104f0bf-5a33-4722-8b95-9c19107ab5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875217368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1875217368
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1384376157
Short name T548
Test name
Test status
Simulation time 95197232 ps
CPU time 2.39 seconds
Started Jun 30 05:32:10 PM PDT 24
Finished Jun 30 05:32:13 PM PDT 24
Peak memory 224828 kb
Host smart-0a76f658-4c40-4e00-9478-df15392839d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384376157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1384376157
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3466146197
Short name T579
Test name
Test status
Simulation time 1374452754 ps
CPU time 5.56 seconds
Started Jun 30 05:32:09 PM PDT 24
Finished Jun 30 05:32:15 PM PDT 24
Peak memory 219300 kb
Host smart-2da570ef-c744-43c2-b53c-aa7e3b6224f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3466146197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3466146197
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2892681126
Short name T445
Test name
Test status
Simulation time 1531578733 ps
CPU time 9.25 seconds
Started Jun 30 05:32:04 PM PDT 24
Finished Jun 30 05:32:14 PM PDT 24
Peak memory 216800 kb
Host smart-b40737a1-04f5-4190-9588-79fb994fc9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892681126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2892681126
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2135943259
Short name T624
Test name
Test status
Simulation time 10006085563 ps
CPU time 14.26 seconds
Started Jun 30 05:32:02 PM PDT 24
Finished Jun 30 05:32:17 PM PDT 24
Peak memory 216872 kb
Host smart-ebf37cdc-24d9-42a9-9e9c-822c4dbced55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135943259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2135943259
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.800073085
Short name T58
Test name
Test status
Simulation time 346098553 ps
CPU time 1.15 seconds
Started Jun 30 05:32:09 PM PDT 24
Finished Jun 30 05:32:10 PM PDT 24
Peak memory 216580 kb
Host smart-4c1a1205-4405-4c82-a6f7-32b74bd8efb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800073085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.800073085
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2302406351
Short name T625
Test name
Test status
Simulation time 71771706 ps
CPU time 1.04 seconds
Started Jun 30 05:32:06 PM PDT 24
Finished Jun 30 05:32:08 PM PDT 24
Peak memory 207488 kb
Host smart-fadf42c6-232b-48c6-a26a-91d9362acbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302406351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2302406351
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2317824496
Short name T897
Test name
Test status
Simulation time 5877672510 ps
CPU time 21.35 seconds
Started Jun 30 05:32:10 PM PDT 24
Finished Jun 30 05:32:31 PM PDT 24
Peak memory 233256 kb
Host smart-4908d3eb-9ad2-490d-ab4e-a4bcd15b6ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317824496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2317824496
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2759610731
Short name T879
Test name
Test status
Simulation time 141631397 ps
CPU time 0.71 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:32:18 PM PDT 24
Peak memory 205928 kb
Host smart-29b22975-fb8d-496b-ac67-1b0f06a374bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759610731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2759610731
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.704827854
Short name T239
Test name
Test status
Simulation time 783149612 ps
CPU time 4.21 seconds
Started Jun 30 05:32:13 PM PDT 24
Finished Jun 30 05:32:17 PM PDT 24
Peak memory 224936 kb
Host smart-210277dd-f1ce-4ba3-b2e8-2690b6f83ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704827854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.704827854
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3402756218
Short name T393
Test name
Test status
Simulation time 36455865 ps
CPU time 0.84 seconds
Started Jun 30 05:32:13 PM PDT 24
Finished Jun 30 05:32:15 PM PDT 24
Peak memory 207132 kb
Host smart-22851264-896c-4075-b028-c651c0e13ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402756218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3402756218
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3476859349
Short name T847
Test name
Test status
Simulation time 12058648 ps
CPU time 0.75 seconds
Started Jun 30 05:32:16 PM PDT 24
Finished Jun 30 05:32:18 PM PDT 24
Peak memory 216416 kb
Host smart-6f486831-6faf-457c-b86d-013061ee2cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476859349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3476859349
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.751845997
Short name T673
Test name
Test status
Simulation time 14095565895 ps
CPU time 128.73 seconds
Started Jun 30 05:32:16 PM PDT 24
Finished Jun 30 05:34:26 PM PDT 24
Peak memory 250248 kb
Host smart-08a20e67-3e55-42df-982f-8c4bb23df02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751845997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.751845997
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.126724486
Short name T707
Test name
Test status
Simulation time 6503215165 ps
CPU time 116.23 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:34:14 PM PDT 24
Peak memory 258024 kb
Host smart-543d80f5-5d5c-4479-8966-78fa3697bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126724486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.126724486
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3663631346
Short name T716
Test name
Test status
Simulation time 278001897 ps
CPU time 7.01 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:32:24 PM PDT 24
Peak memory 241324 kb
Host smart-646e4489-c7f4-46b0-8eb6-48a32c819302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663631346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3663631346
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3525583669
Short name T433
Test name
Test status
Simulation time 746659024 ps
CPU time 4.59 seconds
Started Jun 30 05:32:13 PM PDT 24
Finished Jun 30 05:32:18 PM PDT 24
Peak memory 224968 kb
Host smart-5c494fe7-4643-47e5-9238-24d8cb7d1661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525583669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3525583669
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.271736628
Short name T64
Test name
Test status
Simulation time 54413688034 ps
CPU time 106.98 seconds
Started Jun 30 05:32:13 PM PDT 24
Finished Jun 30 05:34:01 PM PDT 24
Peak memory 249484 kb
Host smart-88c9a07a-78f4-40ef-af96-bd867ee19152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271736628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.271736628
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2179552347
Short name T733
Test name
Test status
Simulation time 11733196515 ps
CPU time 9.53 seconds
Started Jun 30 05:32:09 PM PDT 24
Finished Jun 30 05:32:19 PM PDT 24
Peak memory 225100 kb
Host smart-1a13bed5-05d8-457b-8aac-d5a22b472174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179552347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2179552347
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3068739108
Short name T499
Test name
Test status
Simulation time 307910463 ps
CPU time 2.79 seconds
Started Jun 30 05:32:09 PM PDT 24
Finished Jun 30 05:32:12 PM PDT 24
Peak memory 225020 kb
Host smart-ad65c474-830a-48c4-b8d9-46d987d4422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068739108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3068739108
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2627244163
Short name T656
Test name
Test status
Simulation time 2271830912 ps
CPU time 11.79 seconds
Started Jun 30 05:32:20 PM PDT 24
Finished Jun 30 05:32:32 PM PDT 24
Peak memory 223292 kb
Host smart-a7fd1bbe-020d-403a-9c1e-2c63ccfe9f89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2627244163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2627244163
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.625273802
Short name T839
Test name
Test status
Simulation time 97878305746 ps
CPU time 184.34 seconds
Started Jun 30 05:32:16 PM PDT 24
Finished Jun 30 05:35:20 PM PDT 24
Peak memory 258032 kb
Host smart-976b0b2b-2cdc-4ef8-9f32-bdd6ab134462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625273802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.625273802
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.910596028
Short name T966
Test name
Test status
Simulation time 69500865771 ps
CPU time 44.16 seconds
Started Jun 30 05:32:10 PM PDT 24
Finished Jun 30 05:32:55 PM PDT 24
Peak memory 217052 kb
Host smart-2f29f670-cd8e-450a-b9be-edf14c6a9b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910596028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.910596028
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1342002738
Short name T543
Test name
Test status
Simulation time 1809264485 ps
CPU time 3.31 seconds
Started Jun 30 05:32:08 PM PDT 24
Finished Jun 30 05:32:12 PM PDT 24
Peak memory 216832 kb
Host smart-d391fca9-dc3d-45f8-aa48-a1a157cd6b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342002738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1342002738
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.4190835282
Short name T374
Test name
Test status
Simulation time 730638146 ps
CPU time 1.38 seconds
Started Jun 30 05:32:13 PM PDT 24
Finished Jun 30 05:32:15 PM PDT 24
Peak memory 216780 kb
Host smart-bc33c744-6f15-460f-a3c4-960db64d0cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190835282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4190835282
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2795255940
Short name T353
Test name
Test status
Simulation time 210955355 ps
CPU time 0.89 seconds
Started Jun 30 05:32:13 PM PDT 24
Finished Jun 30 05:32:15 PM PDT 24
Peak memory 206496 kb
Host smart-3988d29e-de0d-4e90-adf6-78c97674ae07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795255940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2795255940
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3701241620
Short name T949
Test name
Test status
Simulation time 7765491900 ps
CPU time 30.12 seconds
Started Jun 30 05:32:09 PM PDT 24
Finished Jun 30 05:32:40 PM PDT 24
Peak memory 249996 kb
Host smart-22af5191-7deb-4732-b440-a475b702f07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701241620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3701241620
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3544930309
Short name T757
Test name
Test status
Simulation time 53281522 ps
CPU time 0.75 seconds
Started Jun 30 05:32:23 PM PDT 24
Finished Jun 30 05:32:25 PM PDT 24
Peak memory 206260 kb
Host smart-5a685a82-2e15-45d3-9e8b-920cca4a2a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544930309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3544930309
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1288226379
Short name T883
Test name
Test status
Simulation time 104900629 ps
CPU time 2.43 seconds
Started Jun 30 05:32:16 PM PDT 24
Finished Jun 30 05:32:19 PM PDT 24
Peak memory 224928 kb
Host smart-d0be4cc7-2e32-4658-9d5a-3c5bbb81dd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288226379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1288226379
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.549632625
Short name T398
Test name
Test status
Simulation time 52103285 ps
CPU time 0.76 seconds
Started Jun 30 05:32:16 PM PDT 24
Finished Jun 30 05:32:18 PM PDT 24
Peak memory 207088 kb
Host smart-eab275bb-85ea-402d-a748-89a9c1c69e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549632625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.549632625
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2145100402
Short name T581
Test name
Test status
Simulation time 107266719676 ps
CPU time 158.48 seconds
Started Jun 30 05:32:22 PM PDT 24
Finished Jun 30 05:35:01 PM PDT 24
Peak memory 251092 kb
Host smart-8823f0d1-0fa4-4ef0-a394-74712ba07df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145100402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2145100402
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3711069422
Short name T260
Test name
Test status
Simulation time 6235334395 ps
CPU time 79.01 seconds
Started Jun 30 05:32:24 PM PDT 24
Finished Jun 30 05:33:44 PM PDT 24
Peak memory 263052 kb
Host smart-20a67f8e-eb1f-4c04-8259-344faced22aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711069422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3711069422
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3381977246
Short name T876
Test name
Test status
Simulation time 21865363638 ps
CPU time 206.35 seconds
Started Jun 30 05:32:23 PM PDT 24
Finished Jun 30 05:35:49 PM PDT 24
Peak memory 258024 kb
Host smart-d73e13c2-72a5-42c1-988d-b630247bc64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381977246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3381977246
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3251216284
Short name T314
Test name
Test status
Simulation time 350074143 ps
CPU time 5.53 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:32:23 PM PDT 24
Peak memory 224944 kb
Host smart-22e847e4-6649-4d28-a886-053562182885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251216284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3251216284
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4126813385
Short name T446
Test name
Test status
Simulation time 17241861493 ps
CPU time 125.82 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:34:24 PM PDT 24
Peak memory 249740 kb
Host smart-fd2448ff-8cfc-4689-a679-fa1d8118d5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126813385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4126813385
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3854330869
Short name T243
Test name
Test status
Simulation time 182862015 ps
CPU time 5.25 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:32:23 PM PDT 24
Peak memory 228976 kb
Host smart-7066e8a8-1f6e-498c-848c-bcfbe65f43b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854330869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3854330869
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1142579677
Short name T564
Test name
Test status
Simulation time 245346172 ps
CPU time 6.55 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:32:24 PM PDT 24
Peak memory 233144 kb
Host smart-d208a9b1-5e8a-4f7b-aa8f-048698cf6414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142579677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1142579677
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2478851221
Short name T5
Test name
Test status
Simulation time 907649697 ps
CPU time 7.28 seconds
Started Jun 30 05:32:16 PM PDT 24
Finished Jun 30 05:32:25 PM PDT 24
Peak memory 233192 kb
Host smart-3df417fc-0144-4c89-af4b-4868765377f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478851221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2478851221
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3023727732
Short name T843
Test name
Test status
Simulation time 966619639 ps
CPU time 3.61 seconds
Started Jun 30 05:32:16 PM PDT 24
Finished Jun 30 05:32:20 PM PDT 24
Peak memory 224976 kb
Host smart-f2045396-7fd2-4f33-9b9a-7eea3eda3df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023727732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3023727732
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4226008614
Short name T142
Test name
Test status
Simulation time 1502213775 ps
CPU time 12.57 seconds
Started Jun 30 05:32:28 PM PDT 24
Finished Jun 30 05:32:40 PM PDT 24
Peak memory 223124 kb
Host smart-53716504-101f-4454-8f2f-6cf71b528a44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4226008614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4226008614
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3129835203
Short name T648
Test name
Test status
Simulation time 127744548 ps
CPU time 1.1 seconds
Started Jun 30 05:32:23 PM PDT 24
Finished Jun 30 05:32:25 PM PDT 24
Peak memory 208312 kb
Host smart-005828d2-e51a-4340-8ba8-80527c552166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129835203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3129835203
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.639557877
Short name T621
Test name
Test status
Simulation time 1156117095 ps
CPU time 5.69 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:32:23 PM PDT 24
Peak memory 217004 kb
Host smart-1bca9e9e-4fb0-487f-983a-db215e31280b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639557877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.639557877
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.196053274
Short name T840
Test name
Test status
Simulation time 4636848330 ps
CPU time 7.63 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:32:26 PM PDT 24
Peak memory 216968 kb
Host smart-aee86ba5-cced-4a4b-9833-be9977d460ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196053274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.196053274
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1925140331
Short name T781
Test name
Test status
Simulation time 666819619 ps
CPU time 1.57 seconds
Started Jun 30 05:32:18 PM PDT 24
Finished Jun 30 05:32:21 PM PDT 24
Peak memory 217084 kb
Host smart-5b749940-320c-432b-ad57-91bb82a22f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925140331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1925140331
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1819931305
Short name T694
Test name
Test status
Simulation time 28965276 ps
CPU time 0.79 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:32:18 PM PDT 24
Peak memory 206476 kb
Host smart-3c6cd936-5a93-4989-a3e9-0be2f4ca11cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819931305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1819931305
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3166192989
Short name T690
Test name
Test status
Simulation time 4299235463 ps
CPU time 11.85 seconds
Started Jun 30 05:32:17 PM PDT 24
Finished Jun 30 05:32:30 PM PDT 24
Peak memory 225072 kb
Host smart-604aa3d8-0411-4bc2-94b6-f39fdda93ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166192989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3166192989
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2041145550
Short name T405
Test name
Test status
Simulation time 33915356 ps
CPU time 0.7 seconds
Started Jun 30 05:32:25 PM PDT 24
Finished Jun 30 05:32:26 PM PDT 24
Peak memory 206316 kb
Host smart-11f1c9cf-d8f2-47c7-ae00-0d0c24cf4f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041145550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2041145550
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3595770120
Short name T244
Test name
Test status
Simulation time 2503776654 ps
CPU time 6.76 seconds
Started Jun 30 05:32:26 PM PDT 24
Finished Jun 30 05:32:33 PM PDT 24
Peak memory 225088 kb
Host smart-94bd8a28-e0f8-4124-b525-97e6e3ce2780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595770120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3595770120
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.275106260
Short name T609
Test name
Test status
Simulation time 31163742 ps
CPU time 0.77 seconds
Started Jun 30 05:32:23 PM PDT 24
Finished Jun 30 05:32:25 PM PDT 24
Peak memory 207072 kb
Host smart-e29a2e2d-9151-4d45-94f8-4ae37711de6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275106260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.275106260
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3642652852
Short name T222
Test name
Test status
Simulation time 307543627435 ps
CPU time 573.6 seconds
Started Jun 30 05:32:28 PM PDT 24
Finished Jun 30 05:42:01 PM PDT 24
Peak memory 254064 kb
Host smart-c48efba2-efe4-45f2-a7ad-4137f283d6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642652852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3642652852
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.91216408
Short name T957
Test name
Test status
Simulation time 53482751293 ps
CPU time 265.69 seconds
Started Jun 30 05:32:24 PM PDT 24
Finished Jun 30 05:36:50 PM PDT 24
Peak memory 257996 kb
Host smart-7d3c3388-8c7b-4b03-a783-67f7380d0743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91216408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.91216408
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3231357745
Short name T498
Test name
Test status
Simulation time 27861848325 ps
CPU time 156.28 seconds
Started Jun 30 05:32:24 PM PDT 24
Finished Jun 30 05:35:01 PM PDT 24
Peak memory 254520 kb
Host smart-1a54e6fc-1e82-4d13-b513-f73fc606f4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231357745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3231357745
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.764286351
Short name T714
Test name
Test status
Simulation time 517206040 ps
CPU time 3.35 seconds
Started Jun 30 05:32:21 PM PDT 24
Finished Jun 30 05:32:24 PM PDT 24
Peak memory 233228 kb
Host smart-3df1b791-e12b-4d5f-b906-4831e73ec2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764286351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.764286351
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.847923392
Short name T723
Test name
Test status
Simulation time 117452894 ps
CPU time 2.46 seconds
Started Jun 30 05:32:22 PM PDT 24
Finished Jun 30 05:32:25 PM PDT 24
Peak memory 227412 kb
Host smart-fb663329-b8dd-4e92-8813-45b0b1449395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847923392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.847923392
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4190142042
Short name T808
Test name
Test status
Simulation time 7244429170 ps
CPU time 64.17 seconds
Started Jun 30 05:32:24 PM PDT 24
Finished Jun 30 05:33:29 PM PDT 24
Peak memory 225076 kb
Host smart-acbb9b4f-be3b-41fd-8e35-17390fadd60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190142042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4190142042
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.985985682
Short name T78
Test name
Test status
Simulation time 13444846180 ps
CPU time 4.06 seconds
Started Jun 30 05:32:26 PM PDT 24
Finished Jun 30 05:32:30 PM PDT 24
Peak memory 225140 kb
Host smart-d400e3f8-5be6-4f07-ac9c-75ffc4dc7100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985985682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.985985682
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2623465649
Short name T105
Test name
Test status
Simulation time 375896027 ps
CPU time 7.26 seconds
Started Jun 30 05:32:23 PM PDT 24
Finished Jun 30 05:32:31 PM PDT 24
Peak memory 225012 kb
Host smart-3b36791d-dc7c-4e8d-b99c-8138db8da6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623465649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2623465649
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.947157369
Short name T41
Test name
Test status
Simulation time 157783158 ps
CPU time 4.18 seconds
Started Jun 30 05:32:24 PM PDT 24
Finished Jun 30 05:32:28 PM PDT 24
Peak memory 219364 kb
Host smart-f212de97-651c-4261-85db-b7ea012e18c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=947157369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.947157369
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2977011672
Short name T154
Test name
Test status
Simulation time 148292446528 ps
CPU time 339.32 seconds
Started Jun 30 05:32:25 PM PDT 24
Finished Jun 30 05:38:05 PM PDT 24
Peak memory 240940 kb
Host smart-025414db-ba14-4617-9df4-2152f4ee8670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977011672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2977011672
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1922406460
Short name T627
Test name
Test status
Simulation time 8513262567 ps
CPU time 3.17 seconds
Started Jun 30 05:32:22 PM PDT 24
Finished Jun 30 05:32:25 PM PDT 24
Peak memory 218008 kb
Host smart-80061fd0-b47a-4988-a9a1-8a785ff008c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922406460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1922406460
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3112338022
Short name T386
Test name
Test status
Simulation time 12242627354 ps
CPU time 15.79 seconds
Started Jun 30 05:32:22 PM PDT 24
Finished Jun 30 05:32:38 PM PDT 24
Peak memory 216928 kb
Host smart-8df12755-3b58-4e64-af76-26663784cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112338022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3112338022
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1289560914
Short name T369
Test name
Test status
Simulation time 247619306 ps
CPU time 2.91 seconds
Started Jun 30 05:32:23 PM PDT 24
Finished Jun 30 05:32:27 PM PDT 24
Peak memory 216840 kb
Host smart-00f797e2-7388-405a-91c6-e03875cb95fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289560914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1289560914
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2545115553
Short name T730
Test name
Test status
Simulation time 123218314 ps
CPU time 0.73 seconds
Started Jun 30 05:32:24 PM PDT 24
Finished Jun 30 05:32:26 PM PDT 24
Peak memory 206436 kb
Host smart-cc24b89d-5c05-4787-9174-dfb23d93a5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545115553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2545115553
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4253057494
Short name T610
Test name
Test status
Simulation time 886970429 ps
CPU time 7.61 seconds
Started Jun 30 05:32:24 PM PDT 24
Finished Jun 30 05:32:33 PM PDT 24
Peak memory 235688 kb
Host smart-6aed0005-4f35-4924-91a9-4564893860c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253057494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4253057494
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3791214875
Short name T827
Test name
Test status
Simulation time 24184050 ps
CPU time 0.72 seconds
Started Jun 30 05:29:46 PM PDT 24
Finished Jun 30 05:29:48 PM PDT 24
Peak memory 205976 kb
Host smart-a6372b17-3478-4337-804e-a6dd533fe5c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791214875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
791214875
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2184740198
Short name T352
Test name
Test status
Simulation time 293342132 ps
CPU time 4.76 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:29:49 PM PDT 24
Peak memory 233164 kb
Host smart-f286ba75-1842-4231-947c-92e64f797fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184740198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2184740198
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3959533285
Short name T698
Test name
Test status
Simulation time 71549384 ps
CPU time 0.76 seconds
Started Jun 30 05:29:42 PM PDT 24
Finished Jun 30 05:29:43 PM PDT 24
Peak memory 206420 kb
Host smart-e01df2f9-7838-4a8d-8307-5e9865c79ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959533285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3959533285
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1482145353
Short name T595
Test name
Test status
Simulation time 4752336111 ps
CPU time 74.16 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:30:59 PM PDT 24
Peak memory 249740 kb
Host smart-a4ecb8db-9f18-45ec-9115-d6b873a7ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482145353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1482145353
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4135836213
Short name T818
Test name
Test status
Simulation time 11964290955 ps
CPU time 172.23 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:32:37 PM PDT 24
Peak memory 255460 kb
Host smart-2eb2443a-ad45-4f80-8429-17a4808a4885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135836213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4135836213
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3743825613
Short name T331
Test name
Test status
Simulation time 112838563598 ps
CPU time 43.69 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:30:29 PM PDT 24
Peak memory 249096 kb
Host smart-221b6a82-07f5-4da6-9387-c86c30e2dc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743825613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3743825613
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3200159569
Short name T312
Test name
Test status
Simulation time 2451823906 ps
CPU time 30.35 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:30:15 PM PDT 24
Peak memory 234448 kb
Host smart-eb458269-e1b8-4b6c-a522-074c876191ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200159569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3200159569
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3852193593
Short name T752
Test name
Test status
Simulation time 8973613133 ps
CPU time 15.17 seconds
Started Jun 30 05:29:48 PM PDT 24
Finished Jun 30 05:30:04 PM PDT 24
Peak memory 225120 kb
Host smart-41aa56a0-a9ba-49a5-a6df-713ecbec3213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852193593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3852193593
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1736383340
Short name T269
Test name
Test status
Simulation time 65651674 ps
CPU time 2.98 seconds
Started Jun 30 05:29:46 PM PDT 24
Finished Jun 30 05:29:49 PM PDT 24
Peak memory 233168 kb
Host smart-3a10ba82-c3f5-4694-9cc0-8e285ae93451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736383340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1736383340
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2933490348
Short name T881
Test name
Test status
Simulation time 656375022 ps
CPU time 11.41 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:29:56 PM PDT 24
Peak memory 241048 kb
Host smart-af83ad0e-f312-4921-af80-44205da268e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933490348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2933490348
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2047510973
Short name T689
Test name
Test status
Simulation time 49666030390 ps
CPU time 22.87 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:30:08 PM PDT 24
Peak memory 233316 kb
Host smart-3e7d07b3-e30e-4a51-8462-66072df1b63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047510973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2047510973
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3051242680
Short name T749
Test name
Test status
Simulation time 24355674427 ps
CPU time 18.87 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:30:03 PM PDT 24
Peak memory 225124 kb
Host smart-0c49cfe5-286a-4897-829c-953922de248f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051242680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3051242680
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2794581513
Short name T569
Test name
Test status
Simulation time 583456786 ps
CPU time 4.37 seconds
Started Jun 30 05:29:45 PM PDT 24
Finished Jun 30 05:29:50 PM PDT 24
Peak memory 223844 kb
Host smart-ce070a69-ebe3-41b0-b23d-4e846354b24c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2794581513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2794581513
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3017324324
Short name T73
Test name
Test status
Simulation time 67579691 ps
CPU time 1 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:29:45 PM PDT 24
Peak memory 236904 kb
Host smart-0c35d3bf-ae82-43c3-af2b-df87fe4d74f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017324324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3017324324
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1577145214
Short name T152
Test name
Test status
Simulation time 43374986467 ps
CPU time 137.64 seconds
Started Jun 30 05:29:48 PM PDT 24
Finished Jun 30 05:32:07 PM PDT 24
Peak memory 252192 kb
Host smart-5a06885c-afd6-493e-8abf-1c9b371109f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577145214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1577145214
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3604696929
Short name T683
Test name
Test status
Simulation time 34791268961 ps
CPU time 44.2 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:30:28 PM PDT 24
Peak memory 216880 kb
Host smart-815e606d-2d9d-4a51-ae28-cedf14f833e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604696929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3604696929
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1852398666
Short name T672
Test name
Test status
Simulation time 4987698866 ps
CPU time 14.08 seconds
Started Jun 30 05:29:46 PM PDT 24
Finished Jun 30 05:30:01 PM PDT 24
Peak memory 216952 kb
Host smart-7866f585-3aa3-4172-9e4c-db8823788540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852398666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1852398666
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1494868354
Short name T396
Test name
Test status
Simulation time 153959142 ps
CPU time 3.5 seconds
Started Jun 30 05:29:45 PM PDT 24
Finished Jun 30 05:29:49 PM PDT 24
Peak memory 216784 kb
Host smart-7bb73a26-75c4-439e-81e6-dd70f39fa572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494868354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1494868354
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.330456867
Short name T501
Test name
Test status
Simulation time 21166418 ps
CPU time 0.77 seconds
Started Jun 30 05:29:47 PM PDT 24
Finished Jun 30 05:29:48 PM PDT 24
Peak memory 206488 kb
Host smart-f1bfc21d-eb6b-4f37-a659-624ef33d4e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330456867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.330456867
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4284239424
Short name T447
Test name
Test status
Simulation time 815126534 ps
CPU time 9.81 seconds
Started Jun 30 05:29:48 PM PDT 24
Finished Jun 30 05:29:58 PM PDT 24
Peak memory 225036 kb
Host smart-bab336f5-799a-4bc8-a47c-4d25f245c891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284239424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4284239424
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2570184491
Short name T338
Test name
Test status
Simulation time 54554533 ps
CPU time 0.73 seconds
Started Jun 30 05:32:32 PM PDT 24
Finished Jun 30 05:32:34 PM PDT 24
Peak memory 206240 kb
Host smart-ec394552-ffbd-4e64-ab84-32cf1d279a33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570184491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2570184491
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1601114505
Short name T13
Test name
Test status
Simulation time 170874429 ps
CPU time 3.57 seconds
Started Jun 30 05:32:35 PM PDT 24
Finished Jun 30 05:32:39 PM PDT 24
Peak memory 225032 kb
Host smart-4c5ef339-5d1c-4592-8ebc-640078d5f723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601114505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1601114505
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1162106837
Short name T740
Test name
Test status
Simulation time 22869695 ps
CPU time 0.87 seconds
Started Jun 30 05:32:25 PM PDT 24
Finished Jun 30 05:32:26 PM PDT 24
Peak memory 207372 kb
Host smart-626e44ce-0e71-47fc-8472-4b5c1f17be24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162106837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1162106837
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3799133612
Short name T845
Test name
Test status
Simulation time 57673691369 ps
CPU time 207.95 seconds
Started Jun 30 05:32:31 PM PDT 24
Finished Jun 30 05:36:00 PM PDT 24
Peak memory 251512 kb
Host smart-3d1220da-242d-41cf-b818-772ba4831b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799133612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3799133612
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3454031329
Short name T490
Test name
Test status
Simulation time 2536258950 ps
CPU time 46.23 seconds
Started Jun 30 05:32:31 PM PDT 24
Finished Jun 30 05:33:19 PM PDT 24
Peak memory 249608 kb
Host smart-1d8acbad-9b9e-4599-b50f-ff3840459d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454031329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3454031329
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2539536717
Short name T198
Test name
Test status
Simulation time 8383900421 ps
CPU time 58.97 seconds
Started Jun 30 05:32:29 PM PDT 24
Finished Jun 30 05:33:28 PM PDT 24
Peak memory 249828 kb
Host smart-76f0d60d-32c2-4278-b1ea-65036c276dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539536717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2539536717
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1658803184
Short name T756
Test name
Test status
Simulation time 366901393 ps
CPU time 5.27 seconds
Started Jun 30 05:32:31 PM PDT 24
Finished Jun 30 05:32:38 PM PDT 24
Peak memory 233232 kb
Host smart-5b0a0185-5fb0-49e2-87a5-d38be08fca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658803184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1658803184
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3765706208
Short name T713
Test name
Test status
Simulation time 8516931185 ps
CPU time 33.38 seconds
Started Jun 30 05:32:32 PM PDT 24
Finished Jun 30 05:33:06 PM PDT 24
Peak memory 249720 kb
Host smart-c6a09c64-37b3-4bf7-980d-3e29cb605572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765706208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3765706208
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3591182276
Short name T585
Test name
Test status
Simulation time 3145745054 ps
CPU time 5.08 seconds
Started Jun 30 05:32:30 PM PDT 24
Finished Jun 30 05:32:36 PM PDT 24
Peak memory 233360 kb
Host smart-a5f4150a-d179-4b0f-8127-c92df3534628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591182276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3591182276
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1195794396
Short name T216
Test name
Test status
Simulation time 5070032709 ps
CPU time 5.62 seconds
Started Jun 30 05:32:31 PM PDT 24
Finished Jun 30 05:32:38 PM PDT 24
Peak memory 233232 kb
Host smart-ba5af029-a0b5-4538-bf3d-f8db0ce70609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195794396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1195794396
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3290519788
Short name T700
Test name
Test status
Simulation time 1621788660 ps
CPU time 5.74 seconds
Started Jun 30 05:32:36 PM PDT 24
Finished Jun 30 05:32:42 PM PDT 24
Peak memory 233228 kb
Host smart-dad749a1-3a69-463c-ab55-13f36a0d10ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290519788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3290519788
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.521894376
Short name T783
Test name
Test status
Simulation time 133941511 ps
CPU time 2.49 seconds
Started Jun 30 05:32:35 PM PDT 24
Finished Jun 30 05:32:37 PM PDT 24
Peak memory 233344 kb
Host smart-11ef232b-812d-4fef-895d-8ac9b190eeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521894376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.521894376
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1447733324
Short name T560
Test name
Test status
Simulation time 1229263086 ps
CPU time 11.84 seconds
Started Jun 30 05:32:32 PM PDT 24
Finished Jun 30 05:32:44 PM PDT 24
Peak memory 221032 kb
Host smart-c4f7ec49-b6b6-4791-9ad2-40bc7ab83e2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1447733324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1447733324
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4013869655
Short name T279
Test name
Test status
Simulation time 4089531382 ps
CPU time 66.92 seconds
Started Jun 30 05:32:31 PM PDT 24
Finished Jun 30 05:33:38 PM PDT 24
Peak memory 250320 kb
Host smart-c19f0dbd-f1bf-4006-a998-04d96d69d2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013869655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4013869655
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4261516536
Short name T329
Test name
Test status
Simulation time 3069917839 ps
CPU time 21.9 seconds
Started Jun 30 05:32:32 PM PDT 24
Finished Jun 30 05:32:54 PM PDT 24
Peak memory 220844 kb
Host smart-1009c6c7-77b9-4c89-88eb-33a59c01c672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261516536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4261516536
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3943243991
Short name T572
Test name
Test status
Simulation time 1608202021 ps
CPU time 8.77 seconds
Started Jun 30 05:32:26 PM PDT 24
Finished Jun 30 05:32:35 PM PDT 24
Peak memory 216820 kb
Host smart-c623deba-6cd6-4fe8-8c08-e19c0cc7d468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943243991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3943243991
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3652980707
Short name T491
Test name
Test status
Simulation time 135306317 ps
CPU time 0.95 seconds
Started Jun 30 05:32:30 PM PDT 24
Finished Jun 30 05:32:31 PM PDT 24
Peak memory 208156 kb
Host smart-f73fabbd-b8db-4961-bbab-3d88c317607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652980707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3652980707
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2889118376
Short name T769
Test name
Test status
Simulation time 77636549 ps
CPU time 0.95 seconds
Started Jun 30 05:32:34 PM PDT 24
Finished Jun 30 05:32:36 PM PDT 24
Peak memory 206664 kb
Host smart-edd85ffd-33e1-434e-8688-a78ce8cbb23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889118376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2889118376
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2920029713
Short name T534
Test name
Test status
Simulation time 25311925033 ps
CPU time 17.43 seconds
Started Jun 30 05:32:32 PM PDT 24
Finished Jun 30 05:32:50 PM PDT 24
Peak memory 225124 kb
Host smart-39d37243-4ad6-4212-86bb-f49647da8ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920029713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2920029713
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2345070921
Short name T715
Test name
Test status
Simulation time 16495904 ps
CPU time 0.73 seconds
Started Jun 30 05:32:36 PM PDT 24
Finished Jun 30 05:32:37 PM PDT 24
Peak memory 205420 kb
Host smart-e171d1a5-d396-4fd0-b20b-8b93b675f078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345070921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2345070921
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2705676
Short name T1
Test name
Test status
Simulation time 208685045 ps
CPU time 2.29 seconds
Started Jun 30 05:32:36 PM PDT 24
Finished Jun 30 05:32:39 PM PDT 24
Peak memory 233204 kb
Host smart-36da6654-a557-49d8-9f90-1cdfb1d0ef28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2705676
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1966030089
Short name T493
Test name
Test status
Simulation time 43070278 ps
CPU time 0.77 seconds
Started Jun 30 05:32:30 PM PDT 24
Finished Jun 30 05:32:32 PM PDT 24
Peak memory 206080 kb
Host smart-2c7b78c0-764d-4ad8-808f-d3f3ca9b5889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966030089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1966030089
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1064354756
Short name T538
Test name
Test status
Simulation time 25365645956 ps
CPU time 161.03 seconds
Started Jun 30 05:32:37 PM PDT 24
Finished Jun 30 05:35:19 PM PDT 24
Peak memory 258124 kb
Host smart-8fe64c09-e834-4c5e-a58f-e4d7f1c9dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064354756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1064354756
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4160254137
Short name T294
Test name
Test status
Simulation time 55560797288 ps
CPU time 144.12 seconds
Started Jun 30 05:32:44 PM PDT 24
Finished Jun 30 05:35:09 PM PDT 24
Peak memory 256400 kb
Host smart-08cdf140-888d-40f2-a0cd-02a34b7129af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160254137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4160254137
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3391840764
Short name T265
Test name
Test status
Simulation time 299715874532 ps
CPU time 497.17 seconds
Started Jun 30 05:32:43 PM PDT 24
Finished Jun 30 05:41:01 PM PDT 24
Peak memory 255308 kb
Host smart-7d250e8b-dfb5-4cf1-95d0-3b09368b6c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391840764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3391840764
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.567939306
Short name T882
Test name
Test status
Simulation time 516366289 ps
CPU time 4.72 seconds
Started Jun 30 05:32:39 PM PDT 24
Finished Jun 30 05:32:44 PM PDT 24
Peak memory 225032 kb
Host smart-4850aa78-d5b6-42bb-9175-41999c0b71fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567939306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.567939306
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1825495500
Short name T972
Test name
Test status
Simulation time 220056821456 ps
CPU time 373.18 seconds
Started Jun 30 05:32:37 PM PDT 24
Finished Jun 30 05:38:51 PM PDT 24
Peak memory 249740 kb
Host smart-4ff7933f-7c83-48c4-9af9-3e4a18ff520b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825495500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1825495500
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2638833653
Short name T1000
Test name
Test status
Simulation time 671556517 ps
CPU time 5.31 seconds
Started Jun 30 05:32:32 PM PDT 24
Finished Jun 30 05:32:38 PM PDT 24
Peak memory 233152 kb
Host smart-1c025a7c-fbcc-4c62-a93b-8f17ac5aed89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638833653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2638833653
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4206354478
Short name T484
Test name
Test status
Simulation time 1788304377 ps
CPU time 17.47 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:33:03 PM PDT 24
Peak memory 239452 kb
Host smart-57c30686-bd04-4cc4-ba0c-0384b2ed636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206354478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4206354478
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3858169135
Short name T492
Test name
Test status
Simulation time 15304026628 ps
CPU time 5.27 seconds
Started Jun 30 05:32:33 PM PDT 24
Finished Jun 30 05:32:38 PM PDT 24
Peak memory 233312 kb
Host smart-e24fe72e-5efd-46ce-8c99-017e7bbf9ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858169135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3858169135
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4193109081
Short name T237
Test name
Test status
Simulation time 10584458041 ps
CPU time 8.71 seconds
Started Jun 30 05:32:32 PM PDT 24
Finished Jun 30 05:32:42 PM PDT 24
Peak memory 233352 kb
Host smart-efeeb04c-7557-46b3-8747-f762364f299f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193109081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4193109081
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1199379394
Short name T382
Test name
Test status
Simulation time 169347789 ps
CPU time 3.95 seconds
Started Jun 30 05:32:43 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 220536 kb
Host smart-10b47107-c159-4e18-aa18-5ad2ad2b0a9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1199379394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1199379394
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2609998148
Short name T326
Test name
Test status
Simulation time 27326186020 ps
CPU time 39.04 seconds
Started Jun 30 05:32:31 PM PDT 24
Finished Jun 30 05:33:10 PM PDT 24
Peak memory 217020 kb
Host smart-e41a1498-7b18-4477-9c6a-13aa5b427596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609998148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2609998148
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.516191025
Short name T550
Test name
Test status
Simulation time 755384630 ps
CPU time 5.29 seconds
Started Jun 30 05:32:31 PM PDT 24
Finished Jun 30 05:32:37 PM PDT 24
Peak memory 216824 kb
Host smart-beaf3301-916c-4f3c-ab18-deee47bb4843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516191025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.516191025
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1737782518
Short name T51
Test name
Test status
Simulation time 350108948 ps
CPU time 3.97 seconds
Started Jun 30 05:32:31 PM PDT 24
Finished Jun 30 05:32:36 PM PDT 24
Peak memory 216748 kb
Host smart-7d5e0d58-b811-47eb-89dd-b7366da03021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737782518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1737782518
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3501941258
Short name T955
Test name
Test status
Simulation time 26226132 ps
CPU time 0.82 seconds
Started Jun 30 05:32:35 PM PDT 24
Finished Jun 30 05:32:36 PM PDT 24
Peak memory 206672 kb
Host smart-08a66542-0187-400a-a44e-245bfc829825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501941258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3501941258
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4208970189
Short name T849
Test name
Test status
Simulation time 9128258203 ps
CPU time 9.9 seconds
Started Jun 30 05:32:36 PM PDT 24
Finished Jun 30 05:32:46 PM PDT 24
Peak memory 225076 kb
Host smart-22081847-f745-4ccf-bd1c-e665e7ec7aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208970189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4208970189
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2310357374
Short name T562
Test name
Test status
Simulation time 14890724 ps
CPU time 0.78 seconds
Started Jun 30 05:32:44 PM PDT 24
Finished Jun 30 05:32:46 PM PDT 24
Peak memory 206152 kb
Host smart-5965006b-0726-44ea-bd17-e5a1bc602a24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310357374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2310357374
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1744469733
Short name T846
Test name
Test status
Simulation time 118824251 ps
CPU time 3.7 seconds
Started Jun 30 05:32:38 PM PDT 24
Finished Jun 30 05:32:42 PM PDT 24
Peak memory 233176 kb
Host smart-8d8df9f6-eaf2-474e-8c91-d0bdf3c6d9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744469733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1744469733
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2528544227
Short name T748
Test name
Test status
Simulation time 55014002 ps
CPU time 0.77 seconds
Started Jun 30 05:32:36 PM PDT 24
Finished Jun 30 05:32:37 PM PDT 24
Peak memory 207428 kb
Host smart-6b728316-fa0c-45bc-9341-38db4db0b5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528544227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2528544227
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3279444504
Short name T299
Test name
Test status
Simulation time 379430908708 ps
CPU time 325.67 seconds
Started Jun 30 05:32:36 PM PDT 24
Finished Jun 30 05:38:02 PM PDT 24
Peak memory 253516 kb
Host smart-e0620e56-2b68-4c08-851e-bb639a7202a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279444504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3279444504
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2609775500
Short name T706
Test name
Test status
Simulation time 3601973385 ps
CPU time 81.3 seconds
Started Jun 30 05:32:39 PM PDT 24
Finished Jun 30 05:34:01 PM PDT 24
Peak memory 258032 kb
Host smart-a9632307-a5fd-4a82-890b-3f42f1cc07de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609775500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2609775500
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.598779679
Short name T402
Test name
Test status
Simulation time 253636696 ps
CPU time 2.97 seconds
Started Jun 30 05:32:43 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 219376 kb
Host smart-b5ef9fbe-7292-48f0-90b7-474715193d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598779679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.598779679
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2086326691
Short name T253
Test name
Test status
Simulation time 2697950163 ps
CPU time 6.9 seconds
Started Jun 30 05:32:39 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 233356 kb
Host smart-adfad5e1-d37f-4d41-b188-fa1d5177b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086326691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2086326691
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2554793149
Short name T248
Test name
Test status
Simulation time 61563552280 ps
CPU time 56.9 seconds
Started Jun 30 05:32:38 PM PDT 24
Finished Jun 30 05:33:36 PM PDT 24
Peak memory 241240 kb
Host smart-5e3727de-de53-4aa5-96f5-4b11af4246e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554793149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2554793149
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4264460048
Short name T373
Test name
Test status
Simulation time 631404436 ps
CPU time 7.4 seconds
Started Jun 30 05:32:35 PM PDT 24
Finished Jun 30 05:32:43 PM PDT 24
Peak memory 233216 kb
Host smart-8c2cf5dc-318f-45d2-af98-d127ac153fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264460048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4264460048
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.432792247
Short name T468
Test name
Test status
Simulation time 2657697031 ps
CPU time 11.15 seconds
Started Jun 30 05:32:46 PM PDT 24
Finished Jun 30 05:32:58 PM PDT 24
Peak memory 233224 kb
Host smart-ce93e35f-205d-47f0-b504-9103dbb07f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432792247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.432792247
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3364961055
Short name T551
Test name
Test status
Simulation time 212432213 ps
CPU time 6.18 seconds
Started Jun 30 05:32:36 PM PDT 24
Finished Jun 30 05:32:42 PM PDT 24
Peak memory 223652 kb
Host smart-9646f4bc-e070-4d4e-abce-b38cb598eaf6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3364961055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3364961055
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.596913978
Short name T453
Test name
Test status
Simulation time 28183554175 ps
CPU time 40.11 seconds
Started Jun 30 05:32:36 PM PDT 24
Finished Jun 30 05:33:16 PM PDT 24
Peak memory 221624 kb
Host smart-d3c52787-ee6c-46ad-9949-5a55e77c8511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596913978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.596913978
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1698986210
Short name T566
Test name
Test status
Simulation time 870440099 ps
CPU time 1.97 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 208276 kb
Host smart-8024648b-b60e-44fb-b315-e8c432bf680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698986210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1698986210
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4174904821
Short name T751
Test name
Test status
Simulation time 71218714 ps
CPU time 1.53 seconds
Started Jun 30 05:32:44 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 216724 kb
Host smart-280aa144-2d91-43a8-af10-41c824bd1c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174904821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4174904821
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3546330147
Short name T583
Test name
Test status
Simulation time 33316063 ps
CPU time 0.77 seconds
Started Jun 30 05:32:38 PM PDT 24
Finished Jun 30 05:32:39 PM PDT 24
Peak memory 206420 kb
Host smart-6fe96d7b-cb62-48cc-9a0f-f0f221cf0b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546330147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3546330147
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1771766031
Short name T399
Test name
Test status
Simulation time 5015000294 ps
CPU time 9.75 seconds
Started Jun 30 05:32:38 PM PDT 24
Finished Jun 30 05:32:49 PM PDT 24
Peak memory 233276 kb
Host smart-8be6b53f-2b3e-4d3c-aac4-9d59d017392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771766031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1771766031
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3753443990
Short name T980
Test name
Test status
Simulation time 14877698 ps
CPU time 0.71 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 205936 kb
Host smart-337308dd-63da-4834-8c55-56c726fa6ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753443990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3753443990
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1335760435
Short name T185
Test name
Test status
Simulation time 90816578 ps
CPU time 3.12 seconds
Started Jun 30 05:32:44 PM PDT 24
Finished Jun 30 05:32:48 PM PDT 24
Peak memory 233200 kb
Host smart-6fe7eb37-20f8-4e08-84c0-69214071bc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335760435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1335760435
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2418968719
Short name T640
Test name
Test status
Simulation time 15302159 ps
CPU time 0.77 seconds
Started Jun 30 05:32:37 PM PDT 24
Finished Jun 30 05:32:38 PM PDT 24
Peak memory 207416 kb
Host smart-eff3a786-eb28-47ef-8f45-04f66acb3585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418968719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2418968719
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3100638946
Short name T559
Test name
Test status
Simulation time 2140485073 ps
CPU time 21.86 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:33:08 PM PDT 24
Peak memory 233200 kb
Host smart-0ed908d9-0c2e-4982-8e02-0965f69fdb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100638946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3100638946
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2859673591
Short name T546
Test name
Test status
Simulation time 7977876937 ps
CPU time 29.44 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:33:15 PM PDT 24
Peak memory 241504 kb
Host smart-4e63f738-0867-40c7-95d6-2ffa129badd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859673591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2859673591
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3834671039
Short name T612
Test name
Test status
Simulation time 7413148370 ps
CPU time 57.47 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:33:44 PM PDT 24
Peak memory 241672 kb
Host smart-e92bc520-4514-46f4-9c66-e1d5f8b9cde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834671039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3834671039
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2824627623
Short name T160
Test name
Test status
Simulation time 503597992 ps
CPU time 5.59 seconds
Started Jun 30 05:32:44 PM PDT 24
Finished Jun 30 05:32:50 PM PDT 24
Peak memory 238556 kb
Host smart-f77dc14a-b061-499f-94fe-8dd65259ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824627623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2824627623
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2958003136
Short name T947
Test name
Test status
Simulation time 4396029801 ps
CPU time 63.16 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:33:49 PM PDT 24
Peak memory 253296 kb
Host smart-9f5f9653-bb9d-4dfb-b413-eb682e6a7332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958003136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2958003136
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2776868635
Short name T419
Test name
Test status
Simulation time 46742114 ps
CPU time 2.41 seconds
Started Jun 30 05:32:43 PM PDT 24
Finished Jun 30 05:32:46 PM PDT 24
Peak memory 233004 kb
Host smart-e4ac7c57-5fac-4a85-afc0-513405dccd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776868635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2776868635
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1341391021
Short name T667
Test name
Test status
Simulation time 1429540506 ps
CPU time 21.75 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:33:07 PM PDT 24
Peak memory 250320 kb
Host smart-292fedac-b374-4da6-9362-1e8f4d75d77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341391021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1341391021
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4286744334
Short name T291
Test name
Test status
Simulation time 2761243702 ps
CPU time 10.29 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:32:56 PM PDT 24
Peak memory 236376 kb
Host smart-07d51605-0189-4e0f-b9e8-df19bbddf26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286744334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4286744334
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1768767161
Short name T664
Test name
Test status
Simulation time 234058264 ps
CPU time 5.23 seconds
Started Jun 30 05:32:42 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 233132 kb
Host smart-99483620-fc54-4c89-8747-8d955164efcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768767161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1768767161
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3458428472
Short name T862
Test name
Test status
Simulation time 7689537383 ps
CPU time 15.57 seconds
Started Jun 30 05:32:42 PM PDT 24
Finished Jun 30 05:32:58 PM PDT 24
Peak memory 224148 kb
Host smart-dc824e6f-f5a6-416c-9387-a820465eb03d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3458428472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3458428472
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3689668773
Short name T306
Test name
Test status
Simulation time 404007090227 ps
CPU time 908.82 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:47:55 PM PDT 24
Peak memory 283168 kb
Host smart-fde1fe39-a0e1-4af0-b4e8-817ed11d68d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689668773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3689668773
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.919766418
Short name T318
Test name
Test status
Simulation time 9885760593 ps
CPU time 25.57 seconds
Started Jun 30 05:32:44 PM PDT 24
Finished Jun 30 05:33:11 PM PDT 24
Peak memory 216904 kb
Host smart-2199fcae-02a5-45f6-a808-249bc1f66fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919766418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.919766418
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1166773807
Short name T521
Test name
Test status
Simulation time 7906863049 ps
CPU time 6.22 seconds
Started Jun 30 05:32:38 PM PDT 24
Finished Jun 30 05:32:45 PM PDT 24
Peak memory 216896 kb
Host smart-3e51b232-4ac4-4198-8d16-228e71464904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166773807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1166773807
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4118160857
Short name T485
Test name
Test status
Simulation time 45818743 ps
CPU time 1.33 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 216776 kb
Host smart-e5656e85-42fb-46c9-a6e8-472e1f733f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118160857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4118160857
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3352368919
Short name T436
Test name
Test status
Simulation time 39030724 ps
CPU time 0.7 seconds
Started Jun 30 05:32:43 PM PDT 24
Finished Jun 30 05:32:44 PM PDT 24
Peak memory 206108 kb
Host smart-f96ed439-9d14-4140-9625-c9ea2140a457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352368919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3352368919
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1781821276
Short name T383
Test name
Test status
Simulation time 218802490 ps
CPU time 2.71 seconds
Started Jun 30 05:32:43 PM PDT 24
Finished Jun 30 05:32:46 PM PDT 24
Peak memory 224940 kb
Host smart-9365e486-d084-451b-94f2-e8d4865a9bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781821276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1781821276
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2653095849
Short name T482
Test name
Test status
Simulation time 51853380 ps
CPU time 0.75 seconds
Started Jun 30 05:32:59 PM PDT 24
Finished Jun 30 05:33:00 PM PDT 24
Peak memory 205268 kb
Host smart-cb31bfef-b3e7-4da4-9fd9-cae3f2579b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653095849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2653095849
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1092444511
Short name T65
Test name
Test status
Simulation time 61070721 ps
CPU time 3.65 seconds
Started Jun 30 05:32:50 PM PDT 24
Finished Jun 30 05:32:54 PM PDT 24
Peak memory 233228 kb
Host smart-1cf467bc-deeb-4be9-b9cb-1c4255ac90e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092444511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1092444511
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2288413116
Short name T777
Test name
Test status
Simulation time 53710270 ps
CPU time 0.78 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 207076 kb
Host smart-7ba912a6-53db-4f5e-9100-7dc23d977fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288413116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2288413116
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3422651093
Short name T486
Test name
Test status
Simulation time 40332297420 ps
CPU time 127.49 seconds
Started Jun 30 05:32:54 PM PDT 24
Finished Jun 30 05:35:02 PM PDT 24
Peak memory 250912 kb
Host smart-7e9a5d00-00f9-4ff7-90e4-9b39d8d16b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422651093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3422651093
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1767089455
Short name T480
Test name
Test status
Simulation time 192824651221 ps
CPU time 424.18 seconds
Started Jun 30 05:32:53 PM PDT 24
Finished Jun 30 05:39:57 PM PDT 24
Peak memory 254416 kb
Host smart-778bd6f6-a1a1-46a5-a918-cd6eb4c104e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767089455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1767089455
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3469000031
Short name T946
Test name
Test status
Simulation time 3076722959 ps
CPU time 25.06 seconds
Started Jun 30 05:32:52 PM PDT 24
Finished Jun 30 05:33:18 PM PDT 24
Peak memory 218316 kb
Host smart-14724562-b50c-4451-a909-d831ba5ed82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469000031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3469000031
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.941125484
Short name T994
Test name
Test status
Simulation time 2789354603 ps
CPU time 46.05 seconds
Started Jun 30 05:32:50 PM PDT 24
Finished Jun 30 05:33:37 PM PDT 24
Peak memory 239732 kb
Host smart-f0d9e9bd-3370-4b44-8775-101087818bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941125484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.941125484
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.135740307
Short name T463
Test name
Test status
Simulation time 34513348075 ps
CPU time 31.24 seconds
Started Jun 30 05:32:51 PM PDT 24
Finished Jun 30 05:33:23 PM PDT 24
Peak memory 249748 kb
Host smart-a6b4189e-563f-41c7-be9c-18bf6d79dc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135740307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.135740307
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3782549572
Short name T93
Test name
Test status
Simulation time 1984356312 ps
CPU time 8.55 seconds
Started Jun 30 05:32:53 PM PDT 24
Finished Jun 30 05:33:02 PM PDT 24
Peak memory 233212 kb
Host smart-39b3c0f0-f2be-4020-b110-71e85859a2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782549572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3782549572
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.316163806
Short name T993
Test name
Test status
Simulation time 322098063 ps
CPU time 3.78 seconds
Started Jun 30 05:32:59 PM PDT 24
Finished Jun 30 05:33:04 PM PDT 24
Peak memory 233120 kb
Host smart-df46c6c5-664f-4cc1-8531-d06e20db5aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316163806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.316163806
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3811298929
Short name T258
Test name
Test status
Simulation time 2965296220 ps
CPU time 11.77 seconds
Started Jun 30 05:32:50 PM PDT 24
Finished Jun 30 05:33:02 PM PDT 24
Peak memory 233320 kb
Host smart-2fbbc78e-1b2e-47ca-8bef-a6436655e339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811298929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3811298929
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1215404876
Short name T187
Test name
Test status
Simulation time 2494279068 ps
CPU time 6.58 seconds
Started Jun 30 05:32:49 PM PDT 24
Finished Jun 30 05:32:56 PM PDT 24
Peak memory 241044 kb
Host smart-7dc3d115-17da-4efa-85e1-4074470e1e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215404876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1215404876
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3595808065
Short name T479
Test name
Test status
Simulation time 4087044533 ps
CPU time 12.83 seconds
Started Jun 30 05:32:51 PM PDT 24
Finished Jun 30 05:33:05 PM PDT 24
Peak memory 223616 kb
Host smart-a4bfdd82-165d-4d56-a72a-bbf5f4e0018b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3595808065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3595808065
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3065790911
Short name T830
Test name
Test status
Simulation time 66112172 ps
CPU time 1.1 seconds
Started Jun 30 05:32:51 PM PDT 24
Finished Jun 30 05:32:53 PM PDT 24
Peak memory 207492 kb
Host smart-1c32aaa1-5ab9-404c-8ae9-84b5fa45ea85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065790911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3065790911
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2269496780
Short name T961
Test name
Test status
Simulation time 15674580191 ps
CPU time 39.78 seconds
Started Jun 30 05:32:44 PM PDT 24
Finished Jun 30 05:33:24 PM PDT 24
Peak memory 216904 kb
Host smart-974984fb-c0f1-4f68-bf4c-6d270b568cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269496780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2269496780
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1051518123
Short name T555
Test name
Test status
Simulation time 533213144 ps
CPU time 2.05 seconds
Started Jun 30 05:32:42 PM PDT 24
Finished Jun 30 05:32:45 PM PDT 24
Peak memory 208304 kb
Host smart-90b755a0-69c6-4181-ba54-ab32bbc88831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051518123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1051518123
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4087855977
Short name T368
Test name
Test status
Simulation time 49122070 ps
CPU time 0.68 seconds
Started Jun 30 05:32:49 PM PDT 24
Finished Jun 30 05:32:50 PM PDT 24
Peak memory 206164 kb
Host smart-5d797d93-1f71-4554-8970-7031417df49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087855977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4087855977
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1092987801
Short name T494
Test name
Test status
Simulation time 38679106 ps
CPU time 0.76 seconds
Started Jun 30 05:32:45 PM PDT 24
Finished Jun 30 05:32:47 PM PDT 24
Peak memory 206468 kb
Host smart-0619a4e9-dee5-4231-b3cb-049ab680dbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092987801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1092987801
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2374152599
Short name T408
Test name
Test status
Simulation time 4857811228 ps
CPU time 16.08 seconds
Started Jun 30 05:32:51 PM PDT 24
Finished Jun 30 05:33:07 PM PDT 24
Peak memory 233264 kb
Host smart-1540cfc7-46b0-4b24-9dc6-fde5ea48e28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374152599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2374152599
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1587131608
Short name T339
Test name
Test status
Simulation time 61830138 ps
CPU time 0.82 seconds
Started Jun 30 05:33:02 PM PDT 24
Finished Jun 30 05:33:04 PM PDT 24
Peak memory 206184 kb
Host smart-164a692c-cec9-4985-9978-c92fb22d4d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587131608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1587131608
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3288699199
Short name T24
Test name
Test status
Simulation time 230558397 ps
CPU time 4.87 seconds
Started Jun 30 05:32:50 PM PDT 24
Finished Jun 30 05:32:55 PM PDT 24
Peak memory 225036 kb
Host smart-9356a5d0-a5eb-484b-be08-cf9f7e9ceebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288699199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3288699199
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3458379893
Short name T370
Test name
Test status
Simulation time 15258763 ps
CPU time 0.76 seconds
Started Jun 30 05:32:50 PM PDT 24
Finished Jun 30 05:32:52 PM PDT 24
Peak memory 206448 kb
Host smart-8bf0f94c-a66e-4d2e-a2e8-dfc60412acb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458379893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3458379893
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3741774883
Short name T745
Test name
Test status
Simulation time 72518381195 ps
CPU time 79.31 seconds
Started Jun 30 05:32:52 PM PDT 24
Finished Jun 30 05:34:12 PM PDT 24
Peak memory 238812 kb
Host smart-5316c086-8c40-4000-bcea-b27a5067b605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741774883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3741774883
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.188528694
Short name T674
Test name
Test status
Simulation time 17180579368 ps
CPU time 155.42 seconds
Started Jun 30 05:32:57 PM PDT 24
Finished Jun 30 05:35:32 PM PDT 24
Peak memory 241620 kb
Host smart-7f17b998-4f75-46ed-ad85-d5476f13fe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188528694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.188528694
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1511846396
Short name T529
Test name
Test status
Simulation time 165590386 ps
CPU time 3.66 seconds
Started Jun 30 05:32:50 PM PDT 24
Finished Jun 30 05:32:55 PM PDT 24
Peak memory 233948 kb
Host smart-2317adb9-07ea-417e-a5da-2ad7855d6fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511846396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1511846396
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3787218307
Short name T831
Test name
Test status
Simulation time 11258417304 ps
CPU time 77.24 seconds
Started Jun 30 05:32:51 PM PDT 24
Finished Jun 30 05:34:09 PM PDT 24
Peak memory 225128 kb
Host smart-f61df400-4fec-4166-b371-4a040b7aa255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787218307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3787218307
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2765973139
Short name T242
Test name
Test status
Simulation time 831675547 ps
CPU time 6.12 seconds
Started Jun 30 05:32:51 PM PDT 24
Finished Jun 30 05:32:58 PM PDT 24
Peak memory 224968 kb
Host smart-d07236e7-a334-463f-88f3-a038a90fe460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765973139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2765973139
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2219773658
Short name T44
Test name
Test status
Simulation time 20964789465 ps
CPU time 50.08 seconds
Started Jun 30 05:32:52 PM PDT 24
Finished Jun 30 05:33:43 PM PDT 24
Peak memory 233280 kb
Host smart-a29c4612-07bb-40f5-aa10-b06c21fe1f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219773658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2219773658
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3037075682
Short name T264
Test name
Test status
Simulation time 126116348 ps
CPU time 2.76 seconds
Started Jun 30 05:32:50 PM PDT 24
Finished Jun 30 05:32:53 PM PDT 24
Peak memory 224924 kb
Host smart-7cf4c9da-e96a-4d58-a19d-3e056e4eb030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037075682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3037075682
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2628852930
Short name T734
Test name
Test status
Simulation time 109475736 ps
CPU time 2.34 seconds
Started Jun 30 05:32:51 PM PDT 24
Finished Jun 30 05:32:54 PM PDT 24
Peak memory 224960 kb
Host smart-0491fa16-4c29-448f-95c4-569edbdddd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628852930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2628852930
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2346861128
Short name T692
Test name
Test status
Simulation time 2345157736 ps
CPU time 6.94 seconds
Started Jun 30 05:32:53 PM PDT 24
Finished Jun 30 05:33:00 PM PDT 24
Peak memory 219980 kb
Host smart-7729c9ad-873c-4552-9620-85ed86f31b11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2346861128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2346861128
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3912889911
Short name T205
Test name
Test status
Simulation time 6846993235 ps
CPU time 100.31 seconds
Started Jun 30 05:32:57 PM PDT 24
Finished Jun 30 05:34:37 PM PDT 24
Peak memory 241628 kb
Host smart-33a82fc9-6cb1-4d05-92bd-b5e200c7c662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912889911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3912889911
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3639066409
Short name T618
Test name
Test status
Simulation time 16917058799 ps
CPU time 27.25 seconds
Started Jun 30 05:32:52 PM PDT 24
Finished Jun 30 05:33:20 PM PDT 24
Peak memory 216884 kb
Host smart-6dea1ae0-ea87-4dc1-ac4e-84199bf551fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639066409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3639066409
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2832977071
Short name T60
Test name
Test status
Simulation time 4593282287 ps
CPU time 12.56 seconds
Started Jun 30 05:32:51 PM PDT 24
Finished Jun 30 05:33:04 PM PDT 24
Peak memory 216912 kb
Host smart-825e2a0c-e4df-4c2a-ab1d-6106ff7298a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832977071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2832977071
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.47514490
Short name T637
Test name
Test status
Simulation time 26115936 ps
CPU time 1.11 seconds
Started Jun 30 05:32:50 PM PDT 24
Finished Jun 30 05:32:52 PM PDT 24
Peak memory 208320 kb
Host smart-4fc58802-e569-4bc6-b573-59e3bd846c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47514490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.47514490
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3392359429
Short name T438
Test name
Test status
Simulation time 82358459 ps
CPU time 0.97 seconds
Started Jun 30 05:32:51 PM PDT 24
Finished Jun 30 05:32:52 PM PDT 24
Peak memory 206460 kb
Host smart-eebb0947-bb34-4597-af9b-ea26828b8b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392359429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3392359429
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.72807750
Short name T164
Test name
Test status
Simulation time 98302853 ps
CPU time 2.83 seconds
Started Jun 30 05:32:52 PM PDT 24
Finished Jun 30 05:32:55 PM PDT 24
Peak memory 224812 kb
Host smart-32d730a5-3a14-4443-a338-d91ca1388191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72807750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.72807750
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.671248911
Short name T26
Test name
Test status
Simulation time 35222176 ps
CPU time 0.71 seconds
Started Jun 30 05:32:59 PM PDT 24
Finished Jun 30 05:33:01 PM PDT 24
Peak memory 205352 kb
Host smart-6f0bb8f9-74ad-4ab3-a752-90d59256804e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671248911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.671248911
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1994543656
Short name T693
Test name
Test status
Simulation time 2614760577 ps
CPU time 8.68 seconds
Started Jun 30 05:32:59 PM PDT 24
Finished Jun 30 05:33:08 PM PDT 24
Peak memory 225108 kb
Host smart-f9889fd5-ef2d-46a3-8561-4de5e2595a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994543656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1994543656
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1085996898
Short name T771
Test name
Test status
Simulation time 16339430 ps
CPU time 0.78 seconds
Started Jun 30 05:33:01 PM PDT 24
Finished Jun 30 05:33:02 PM PDT 24
Peak memory 207424 kb
Host smart-3ee36ed3-30d7-4980-940b-1adc36c2878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085996898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1085996898
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1477065754
Short name T663
Test name
Test status
Simulation time 7658278464 ps
CPU time 12.64 seconds
Started Jun 30 05:33:00 PM PDT 24
Finished Jun 30 05:33:13 PM PDT 24
Peak memory 225164 kb
Host smart-ada84661-285e-41bf-abb0-c2f6bb279ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477065754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1477065754
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1409029306
Short name T230
Test name
Test status
Simulation time 14330724269 ps
CPU time 57.13 seconds
Started Jun 30 05:32:56 PM PDT 24
Finished Jun 30 05:33:53 PM PDT 24
Peak memory 241632 kb
Host smart-09aa3da2-f03c-4cbc-b6c5-c37b692118db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409029306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1409029306
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3566296960
Short name T732
Test name
Test status
Simulation time 5077555829 ps
CPU time 29.09 seconds
Started Jun 30 05:32:56 PM PDT 24
Finished Jun 30 05:33:26 PM PDT 24
Peak memory 233340 kb
Host smart-dae76590-3f52-4b8c-8ee5-a44eab24400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566296960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3566296960
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.913558756
Short name T45
Test name
Test status
Simulation time 57394998129 ps
CPU time 413.96 seconds
Started Jun 30 05:32:59 PM PDT 24
Finished Jun 30 05:39:54 PM PDT 24
Peak memory 262504 kb
Host smart-0cbbab8e-49e8-42e0-a841-255cff67ddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913558756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.913558756
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1352215580
Short name T985
Test name
Test status
Simulation time 182160576 ps
CPU time 4.5 seconds
Started Jun 30 05:32:58 PM PDT 24
Finished Jun 30 05:33:03 PM PDT 24
Peak memory 224932 kb
Host smart-35915fbe-5552-49e3-a2ab-90890a33268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352215580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1352215580
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1543241041
Short name T62
Test name
Test status
Simulation time 10107845791 ps
CPU time 12.91 seconds
Started Jun 30 05:32:58 PM PDT 24
Finished Jun 30 05:33:11 PM PDT 24
Peak memory 233368 kb
Host smart-5833b5be-05e8-4a4b-8146-b79c8f368e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543241041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1543241041
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3146200050
Short name T542
Test name
Test status
Simulation time 640929346 ps
CPU time 3.69 seconds
Started Jun 30 05:32:57 PM PDT 24
Finished Jun 30 05:33:01 PM PDT 24
Peak memory 233160 kb
Host smart-6bec0730-397c-49f7-bf81-2397915979e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146200050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3146200050
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3815115686
Short name T907
Test name
Test status
Simulation time 644702555 ps
CPU time 4.37 seconds
Started Jun 30 05:33:01 PM PDT 24
Finished Jun 30 05:33:06 PM PDT 24
Peak memory 225024 kb
Host smart-108f15db-64ad-4a20-a922-fffd1fd4e4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815115686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3815115686
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3424533570
Short name T889
Test name
Test status
Simulation time 1321596390 ps
CPU time 5.81 seconds
Started Jun 30 05:33:00 PM PDT 24
Finished Jun 30 05:33:06 PM PDT 24
Peak memory 222596 kb
Host smart-3e8e3cb7-2a2a-4087-8a2f-1c2dbe251b29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3424533570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3424533570
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3203122048
Short name T473
Test name
Test status
Simulation time 14670664248 ps
CPU time 41.31 seconds
Started Jun 30 05:32:57 PM PDT 24
Finished Jun 30 05:33:39 PM PDT 24
Peak memory 217236 kb
Host smart-5895280f-e0fb-432d-b513-33f9ad41d474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203122048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3203122048
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4145267844
Short name T92
Test name
Test status
Simulation time 1242499537 ps
CPU time 6.93 seconds
Started Jun 30 05:32:57 PM PDT 24
Finished Jun 30 05:33:05 PM PDT 24
Peak memory 216812 kb
Host smart-15fc18ff-53da-4009-a56d-15b4ac8e4ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145267844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4145267844
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.895342974
Short name T844
Test name
Test status
Simulation time 63797581 ps
CPU time 1.27 seconds
Started Jun 30 05:32:58 PM PDT 24
Finished Jun 30 05:32:59 PM PDT 24
Peak memory 208340 kb
Host smart-cc2d22b4-6885-4aed-b44f-838f4d5e0cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895342974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.895342974
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1886863205
Short name T355
Test name
Test status
Simulation time 250596981 ps
CPU time 0.93 seconds
Started Jun 30 05:33:01 PM PDT 24
Finished Jun 30 05:33:02 PM PDT 24
Peak memory 206696 kb
Host smart-ef3c9968-9024-4bd2-8530-aee616789ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886863205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1886863205
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1623218346
Short name T797
Test name
Test status
Simulation time 19738971218 ps
CPU time 18.15 seconds
Started Jun 30 05:32:57 PM PDT 24
Finished Jun 30 05:33:16 PM PDT 24
Peak memory 249292 kb
Host smart-17afac34-6e2c-47a5-a8bb-7de41008d0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623218346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1623218346
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3844955575
Short name T2
Test name
Test status
Simulation time 31379008 ps
CPU time 0.72 seconds
Started Jun 30 05:33:04 PM PDT 24
Finished Jun 30 05:33:06 PM PDT 24
Peak memory 206208 kb
Host smart-2d04893d-c573-4aed-8f81-35722c40a748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844955575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3844955575
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3932162670
Short name T489
Test name
Test status
Simulation time 306654496 ps
CPU time 2.71 seconds
Started Jun 30 05:33:04 PM PDT 24
Finished Jun 30 05:33:08 PM PDT 24
Peak memory 224908 kb
Host smart-2f9679ca-3537-4d36-b7c1-85b7d34b7eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932162670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3932162670
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1691448976
Short name T429
Test name
Test status
Simulation time 18252382 ps
CPU time 0.83 seconds
Started Jun 30 05:33:02 PM PDT 24
Finished Jun 30 05:33:04 PM PDT 24
Peak memory 207660 kb
Host smart-ebc1c392-0e7e-496d-8378-18c921503f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691448976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1691448976
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1040830137
Short name T290
Test name
Test status
Simulation time 78706691734 ps
CPU time 295.25 seconds
Started Jun 30 05:33:06 PM PDT 24
Finished Jun 30 05:38:02 PM PDT 24
Peak memory 249716 kb
Host smart-b07692b1-4eeb-4781-90d5-f11a1416cbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040830137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1040830137
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3376879148
Short name T878
Test name
Test status
Simulation time 68089298808 ps
CPU time 132.5 seconds
Started Jun 30 05:33:03 PM PDT 24
Finished Jun 30 05:35:17 PM PDT 24
Peak memory 264228 kb
Host smart-37a22148-1b56-4c0f-b940-2a3de99b2a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376879148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3376879148
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.766545209
Short name T780
Test name
Test status
Simulation time 41202369984 ps
CPU time 119.04 seconds
Started Jun 30 05:33:03 PM PDT 24
Finished Jun 30 05:35:03 PM PDT 24
Peak memory 254888 kb
Host smart-b704ba97-d465-412b-9b82-4fe74ba70b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766545209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.766545209
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3661039405
Short name T517
Test name
Test status
Simulation time 4011970961 ps
CPU time 23.79 seconds
Started Jun 30 05:33:05 PM PDT 24
Finished Jun 30 05:33:30 PM PDT 24
Peak memory 238468 kb
Host smart-b0da0ad5-ef5f-4858-aae6-53d3c28555a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661039405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3661039405
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2294171211
Short name T934
Test name
Test status
Simulation time 127985096866 ps
CPU time 114.17 seconds
Started Jun 30 05:33:04 PM PDT 24
Finished Jun 30 05:34:59 PM PDT 24
Peak memory 249712 kb
Host smart-30fb9f46-50e0-4f7e-8192-357e9170e455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294171211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2294171211
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2903567041
Short name T202
Test name
Test status
Simulation time 308586415 ps
CPU time 7.68 seconds
Started Jun 30 05:33:02 PM PDT 24
Finished Jun 30 05:33:12 PM PDT 24
Peak memory 233188 kb
Host smart-c2ff0f77-4812-443a-bae3-aba114eea6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903567041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2903567041
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.321537434
Short name T104
Test name
Test status
Simulation time 58176043351 ps
CPU time 72.46 seconds
Started Jun 30 05:33:03 PM PDT 24
Finished Jun 30 05:34:17 PM PDT 24
Peak memory 234524 kb
Host smart-0fcebb34-baec-42cb-b10f-9f14c41ac179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321537434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.321537434
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.332357304
Short name T724
Test name
Test status
Simulation time 37521830461 ps
CPU time 25.76 seconds
Started Jun 30 05:33:04 PM PDT 24
Finished Jun 30 05:33:31 PM PDT 24
Peak memory 241408 kb
Host smart-ac9c2bac-ca9e-4ff9-ae25-be144404d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332357304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.332357304
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.467807219
Short name T502
Test name
Test status
Simulation time 35318025 ps
CPU time 2.57 seconds
Started Jun 30 05:33:02 PM PDT 24
Finished Jun 30 05:33:07 PM PDT 24
Peak memory 232956 kb
Host smart-eeec3c25-2c3c-4953-b132-a1b4a76a2791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467807219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.467807219
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3149211819
Short name T146
Test name
Test status
Simulation time 96538759 ps
CPU time 4.1 seconds
Started Jun 30 05:33:05 PM PDT 24
Finished Jun 30 05:33:10 PM PDT 24
Peak memory 223472 kb
Host smart-6eab31f2-6112-414b-b6a9-f603bd156cee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3149211819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3149211819
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3929879035
Short name T556
Test name
Test status
Simulation time 204268542 ps
CPU time 1.05 seconds
Started Jun 30 05:33:05 PM PDT 24
Finished Jun 30 05:33:07 PM PDT 24
Peak memory 207732 kb
Host smart-b71e24d4-028c-4fbe-8ee2-24d99d974b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929879035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3929879035
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1894696063
Short name T631
Test name
Test status
Simulation time 2808273075 ps
CPU time 25.73 seconds
Started Jun 30 05:32:57 PM PDT 24
Finished Jun 30 05:33:23 PM PDT 24
Peak memory 217156 kb
Host smart-61b43c3a-8154-4f7f-a2be-75a2b739cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894696063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1894696063
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2304356923
Short name T385
Test name
Test status
Simulation time 3012103452 ps
CPU time 6.15 seconds
Started Jun 30 05:32:57 PM PDT 24
Finished Jun 30 05:33:04 PM PDT 24
Peak memory 216948 kb
Host smart-41c47165-a6f7-4ee8-afa2-97b798ddc701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304356923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2304356923
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.278690551
Short name T691
Test name
Test status
Simulation time 119094463 ps
CPU time 2.01 seconds
Started Jun 30 05:33:02 PM PDT 24
Finished Jun 30 05:33:05 PM PDT 24
Peak memory 216872 kb
Host smart-0ba5841f-a334-4773-8993-0c523a771d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278690551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.278690551
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3262215446
Short name T615
Test name
Test status
Simulation time 71769226 ps
CPU time 0.95 seconds
Started Jun 30 05:32:58 PM PDT 24
Finished Jun 30 05:32:59 PM PDT 24
Peak memory 206476 kb
Host smart-e572109c-f6d4-4110-8c8e-e331811bdbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262215446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3262215446
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.363500868
Short name T219
Test name
Test status
Simulation time 2659438783 ps
CPU time 11.85 seconds
Started Jun 30 05:33:04 PM PDT 24
Finished Jun 30 05:33:17 PM PDT 24
Peak memory 249672 kb
Host smart-b1be3139-4202-4c67-a177-bc4c67007038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363500868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.363500868
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1609395479
Short name T936
Test name
Test status
Simulation time 14858740 ps
CPU time 0.71 seconds
Started Jun 30 05:33:14 PM PDT 24
Finished Jun 30 05:33:15 PM PDT 24
Peak memory 205384 kb
Host smart-cee3f15d-dadb-4749-bb31-459377feb54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609395479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1609395479
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1900003780
Short name T161
Test name
Test status
Simulation time 2937452608 ps
CPU time 15.26 seconds
Started Jun 30 05:33:04 PM PDT 24
Finished Jun 30 05:33:20 PM PDT 24
Peak memory 233324 kb
Host smart-5be0e871-fd84-42ba-85a4-fd359d248488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900003780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1900003780
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2653331376
Short name T768
Test name
Test status
Simulation time 36163526 ps
CPU time 0.77 seconds
Started Jun 30 05:33:02 PM PDT 24
Finished Jun 30 05:33:05 PM PDT 24
Peak memory 207084 kb
Host smart-9fc191de-f99c-4481-8f06-f408022e7c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653331376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2653331376
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.880547752
Short name T81
Test name
Test status
Simulation time 9043684942 ps
CPU time 85.46 seconds
Started Jun 30 05:33:11 PM PDT 24
Finished Jun 30 05:34:37 PM PDT 24
Peak memory 249704 kb
Host smart-1b12bbd7-0818-40aa-a460-22f7fe23669e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880547752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.880547752
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.907102953
Short name T138
Test name
Test status
Simulation time 9390940922 ps
CPU time 84.02 seconds
Started Jun 30 05:33:15 PM PDT 24
Finished Jun 30 05:34:39 PM PDT 24
Peak memory 234676 kb
Host smart-c7bd0f54-0bcf-48d6-b729-de399210f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907102953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.907102953
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1437756219
Short name T172
Test name
Test status
Simulation time 22590442341 ps
CPU time 154.71 seconds
Started Jun 30 05:33:11 PM PDT 24
Finished Jun 30 05:35:47 PM PDT 24
Peak memory 252776 kb
Host smart-f441dd15-d759-4d4b-9a12-35cacbd14623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437756219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1437756219
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1551924641
Short name T722
Test name
Test status
Simulation time 155197425 ps
CPU time 5.59 seconds
Started Jun 30 05:33:11 PM PDT 24
Finished Jun 30 05:33:18 PM PDT 24
Peak memory 233180 kb
Host smart-81adffa3-90ab-4ab6-a64c-ce0d00ee9aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551924641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1551924641
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.822018924
Short name T945
Test name
Test status
Simulation time 43519891067 ps
CPU time 169.37 seconds
Started Jun 30 05:33:13 PM PDT 24
Finished Jun 30 05:36:02 PM PDT 24
Peak memory 260988 kb
Host smart-7039c4d7-31c9-4131-8c0a-2069282324bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822018924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.822018924
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1202607624
Short name T229
Test name
Test status
Simulation time 145245863 ps
CPU time 3.03 seconds
Started Jun 30 05:33:03 PM PDT 24
Finished Jun 30 05:33:08 PM PDT 24
Peak memory 224968 kb
Host smart-dab5e5ed-9531-439a-b4f4-5974ec70ec8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202607624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1202607624
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.255499379
Short name T75
Test name
Test status
Simulation time 2462097404 ps
CPU time 31.02 seconds
Started Jun 30 05:33:03 PM PDT 24
Finished Jun 30 05:33:36 PM PDT 24
Peak memory 233220 kb
Host smart-397b5ae0-86c1-46d5-94e6-40bffe2152f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255499379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.255499379
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2108203023
Short name T38
Test name
Test status
Simulation time 32440124 ps
CPU time 2.71 seconds
Started Jun 30 05:33:05 PM PDT 24
Finished Jun 30 05:33:09 PM PDT 24
Peak memory 232964 kb
Host smart-cc2c0dfb-0080-4c55-a33c-98aa047dfca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108203023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2108203023
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2613119717
Short name T403
Test name
Test status
Simulation time 1662870133 ps
CPU time 11.07 seconds
Started Jun 30 05:33:02 PM PDT 24
Finished Jun 30 05:33:15 PM PDT 24
Peak memory 225044 kb
Host smart-b63da3b9-42f5-4fb0-b41a-159a60e6f971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613119717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2613119717
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2680667829
Short name T427
Test name
Test status
Simulation time 5200230852 ps
CPU time 16.65 seconds
Started Jun 30 05:33:13 PM PDT 24
Finished Jun 30 05:33:30 PM PDT 24
Peak memory 223240 kb
Host smart-781408f8-6253-4eaa-b01a-a5615b24de3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2680667829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2680667829
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2658812201
Short name T292
Test name
Test status
Simulation time 580337123730 ps
CPU time 682.12 seconds
Started Jun 30 05:33:13 PM PDT 24
Finished Jun 30 05:44:36 PM PDT 24
Peak memory 266588 kb
Host smart-d304ebc3-e3f2-474d-a8e3-d494e694cb46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658812201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2658812201
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.922583347
Short name T452
Test name
Test status
Simulation time 1251464324 ps
CPU time 3.94 seconds
Started Jun 30 05:33:04 PM PDT 24
Finished Jun 30 05:33:10 PM PDT 24
Peak memory 216784 kb
Host smart-1267a627-7e7e-484f-bbb7-76b153a980f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922583347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.922583347
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2678779603
Short name T459
Test name
Test status
Simulation time 108438006 ps
CPU time 2.22 seconds
Started Jun 30 05:33:02 PM PDT 24
Finished Jun 30 05:33:06 PM PDT 24
Peak memory 216836 kb
Host smart-563a1ade-425d-4901-833c-db5167f7e1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678779603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2678779603
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2677328342
Short name T430
Test name
Test status
Simulation time 126257616 ps
CPU time 0.92 seconds
Started Jun 30 05:33:03 PM PDT 24
Finished Jun 30 05:33:05 PM PDT 24
Peak memory 206444 kb
Host smart-a9205d90-b1a2-4854-a3fa-2ee7345ea501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677328342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2677328342
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1373740888
Short name T519
Test name
Test status
Simulation time 256934134 ps
CPU time 5.08 seconds
Started Jun 30 05:33:08 PM PDT 24
Finished Jun 30 05:33:13 PM PDT 24
Peak memory 233196 kb
Host smart-ab2f234c-06c8-42a8-b40a-d3e270f9d792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373740888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1373740888
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.286198708
Short name T509
Test name
Test status
Simulation time 21013071 ps
CPU time 0.72 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:33:19 PM PDT 24
Peak memory 205936 kb
Host smart-7666aee0-7a27-4b8d-9e84-2aef5165b245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286198708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.286198708
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4020151802
Short name T650
Test name
Test status
Simulation time 439474717 ps
CPU time 2.26 seconds
Started Jun 30 05:33:15 PM PDT 24
Finished Jun 30 05:33:18 PM PDT 24
Peak memory 224288 kb
Host smart-9aa6877c-8b90-4daf-b4fd-5cda13792198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020151802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4020151802
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.80548083
Short name T788
Test name
Test status
Simulation time 17772188 ps
CPU time 0.8 seconds
Started Jun 30 05:33:14 PM PDT 24
Finished Jun 30 05:33:15 PM PDT 24
Peak memory 207412 kb
Host smart-e725824b-19d4-4c85-bb5d-04d40bfe04c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80548083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.80548083
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3667443027
Short name T721
Test name
Test status
Simulation time 7482591929 ps
CPU time 46.86 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:34:05 PM PDT 24
Peak memory 257904 kb
Host smart-179b9366-0304-481a-8cf4-2d88791adcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667443027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3667443027
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3732845126
Short name T298
Test name
Test status
Simulation time 127332662510 ps
CPU time 277.25 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:37:55 PM PDT 24
Peak memory 257308 kb
Host smart-e17b6e7e-bd31-4e6a-928c-452fd65b80be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732845126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3732845126
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1107498815
Short name T188
Test name
Test status
Simulation time 25827300146 ps
CPU time 149.92 seconds
Started Jun 30 05:33:17 PM PDT 24
Finished Jun 30 05:35:47 PM PDT 24
Peak memory 256140 kb
Host smart-5db33acc-e0e9-4fda-a866-ef09284a52a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107498815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1107498815
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.758496001
Short name T118
Test name
Test status
Simulation time 216169184 ps
CPU time 2.76 seconds
Started Jun 30 05:33:13 PM PDT 24
Finished Jun 30 05:33:16 PM PDT 24
Peak memory 233176 kb
Host smart-e4ed5264-14ce-4aee-abb4-45a331a7e8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758496001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.758496001
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2897377105
Short name T304
Test name
Test status
Simulation time 67024863685 ps
CPU time 112.71 seconds
Started Jun 30 05:33:14 PM PDT 24
Finished Jun 30 05:35:07 PM PDT 24
Peak memory 250276 kb
Host smart-c3e18728-5dfd-4a34-bdf7-492e5a5f5202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897377105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2897377105
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4046703898
Short name T778
Test name
Test status
Simulation time 404869821 ps
CPU time 6.19 seconds
Started Jun 30 05:33:14 PM PDT 24
Finished Jun 30 05:33:21 PM PDT 24
Peak memory 224932 kb
Host smart-888a3661-c444-4fd7-a6c7-8fd5ea729378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046703898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4046703898
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1882094186
Short name T252
Test name
Test status
Simulation time 14055731869 ps
CPU time 80.32 seconds
Started Jun 30 05:33:10 PM PDT 24
Finished Jun 30 05:34:31 PM PDT 24
Peak memory 233288 kb
Host smart-d404a963-4126-484e-966a-56481253dbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882094186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1882094186
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1937018612
Short name T654
Test name
Test status
Simulation time 3697599847 ps
CPU time 15.01 seconds
Started Jun 30 05:33:15 PM PDT 24
Finished Jun 30 05:33:31 PM PDT 24
Peak memory 239944 kb
Host smart-e9117c57-34b4-428d-9c83-9b0b92d63321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937018612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1937018612
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3339087865
Short name T892
Test name
Test status
Simulation time 501448862 ps
CPU time 5.17 seconds
Started Jun 30 05:33:11 PM PDT 24
Finished Jun 30 05:33:16 PM PDT 24
Peak memory 225024 kb
Host smart-1444ace7-e075-4e51-9274-9d8d31d6cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339087865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3339087865
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2287131897
Short name T776
Test name
Test status
Simulation time 1298950742 ps
CPU time 12.4 seconds
Started Jun 30 05:33:16 PM PDT 24
Finished Jun 30 05:33:29 PM PDT 24
Peak memory 220964 kb
Host smart-0f1aea40-55f9-4cc7-9ba8-f0fe0dfddabc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2287131897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2287131897
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1872436330
Short name T153
Test name
Test status
Simulation time 3526529744 ps
CPU time 27.42 seconds
Started Jun 30 05:33:18 PM PDT 24
Finished Jun 30 05:33:46 PM PDT 24
Peak memory 237504 kb
Host smart-c7c3c8bb-b039-4de8-b0b7-b30944272e19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872436330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1872436330
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3065755606
Short name T720
Test name
Test status
Simulation time 5335263337 ps
CPU time 26.63 seconds
Started Jun 30 05:33:09 PM PDT 24
Finished Jun 30 05:33:36 PM PDT 24
Peak memory 217088 kb
Host smart-301acf3f-bb81-42d1-b69d-326ebe1a2153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065755606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3065755606
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.677271300
Short name T587
Test name
Test status
Simulation time 18809007927 ps
CPU time 14.51 seconds
Started Jun 30 05:33:11 PM PDT 24
Finished Jun 30 05:33:27 PM PDT 24
Peak memory 218216 kb
Host smart-6ad9febb-7a36-4c4e-ad53-ab5eab903ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677271300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.677271300
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3081284369
Short name T478
Test name
Test status
Simulation time 340750874 ps
CPU time 2.54 seconds
Started Jun 30 05:33:15 PM PDT 24
Finished Jun 30 05:33:18 PM PDT 24
Peak memory 216004 kb
Host smart-18cceb4f-9d12-4817-9f34-fdf9c871e7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081284369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3081284369
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3796384872
Short name T939
Test name
Test status
Simulation time 210938391 ps
CPU time 0.87 seconds
Started Jun 30 05:33:12 PM PDT 24
Finished Jun 30 05:33:13 PM PDT 24
Peak memory 206444 kb
Host smart-29ef40bb-b38e-4c65-851f-eed5d094ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796384872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3796384872
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4263319079
Short name T868
Test name
Test status
Simulation time 1758556937 ps
CPU time 4.79 seconds
Started Jun 30 05:33:13 PM PDT 24
Finished Jun 30 05:33:18 PM PDT 24
Peak memory 225012 kb
Host smart-d4f75cc0-c93f-4f9d-826b-78e052e61dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263319079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4263319079
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.237954107
Short name T344
Test name
Test status
Simulation time 32966687 ps
CPU time 0.72 seconds
Started Jun 30 05:29:50 PM PDT 24
Finished Jun 30 05:29:51 PM PDT 24
Peak memory 205996 kb
Host smart-fc059a37-46a3-458d-8541-2ac8b389c0eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237954107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.237954107
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2308068685
Short name T885
Test name
Test status
Simulation time 126906919 ps
CPU time 2.31 seconds
Started Jun 30 05:29:43 PM PDT 24
Finished Jun 30 05:29:46 PM PDT 24
Peak memory 224888 kb
Host smart-958b438d-f429-4168-b850-e950bb0067c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308068685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2308068685
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1989240617
Short name T364
Test name
Test status
Simulation time 30212676 ps
CPU time 0.79 seconds
Started Jun 30 05:29:45 PM PDT 24
Finished Jun 30 05:29:46 PM PDT 24
Peak memory 206636 kb
Host smart-f6e70d7d-8127-475b-8cf6-445fb90bdf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989240617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1989240617
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1271715823
Short name T873
Test name
Test status
Simulation time 70438879744 ps
CPU time 133.69 seconds
Started Jun 30 05:29:43 PM PDT 24
Finished Jun 30 05:31:58 PM PDT 24
Peak memory 249744 kb
Host smart-e2e596f3-dd80-4ec4-8312-f10f5ec3dc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271715823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1271715823
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2842868733
Short name T190
Test name
Test status
Simulation time 11839852300 ps
CPU time 150.59 seconds
Started Jun 30 05:29:47 PM PDT 24
Finished Jun 30 05:32:19 PM PDT 24
Peak memory 249856 kb
Host smart-0d054340-1918-4c6d-b0c9-dd2f6c59d184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842868733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2842868733
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3420936263
Short name T310
Test name
Test status
Simulation time 8241935989 ps
CPU time 21.32 seconds
Started Jun 30 05:29:45 PM PDT 24
Finished Jun 30 05:30:07 PM PDT 24
Peak memory 236164 kb
Host smart-aebdb48a-4679-4e89-acfa-b9f27cc8b391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420936263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3420936263
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2616474360
Short name T725
Test name
Test status
Simulation time 3617674610 ps
CPU time 79.29 seconds
Started Jun 30 05:29:48 PM PDT 24
Finished Jun 30 05:31:08 PM PDT 24
Peak memory 257020 kb
Host smart-800af4cb-73c2-43cc-9c9a-756dfa604c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616474360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2616474360
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3742799347
Short name T829
Test name
Test status
Simulation time 578520988 ps
CPU time 4.93 seconds
Started Jun 30 05:29:48 PM PDT 24
Finished Jun 30 05:29:53 PM PDT 24
Peak memory 224952 kb
Host smart-ab579af9-7f0f-46e6-9e1a-6a5e3e44d09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742799347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3742799347
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1329426439
Short name T246
Test name
Test status
Simulation time 11436812656 ps
CPU time 32.17 seconds
Started Jun 30 05:29:48 PM PDT 24
Finished Jun 30 05:30:21 PM PDT 24
Peak memory 241020 kb
Host smart-80068a88-d7e1-4670-be8c-cf9d36b19328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329426439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1329426439
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3285416423
Short name T704
Test name
Test status
Simulation time 675158634 ps
CPU time 6.39 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:29:59 PM PDT 24
Peak memory 225036 kb
Host smart-7fd9e1c2-04b5-4ba4-8e18-624e7b584b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285416423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3285416423
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2576501320
Short name T455
Test name
Test status
Simulation time 16127724388 ps
CPU time 11.08 seconds
Started Jun 30 05:29:48 PM PDT 24
Finished Jun 30 05:29:59 PM PDT 24
Peak memory 225088 kb
Host smart-e6bbc549-7084-418c-9e3f-79feadff66ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576501320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2576501320
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.786817880
Short name T141
Test name
Test status
Simulation time 771652373 ps
CPU time 11.41 seconds
Started Jun 30 05:29:45 PM PDT 24
Finished Jun 30 05:29:57 PM PDT 24
Peak memory 222564 kb
Host smart-362b8e9d-fd96-4e55-a138-d5fcd975d30e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=786817880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.786817880
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.386623595
Short name T158
Test name
Test status
Simulation time 7174795266 ps
CPU time 67.54 seconds
Started Jun 30 05:29:45 PM PDT 24
Finished Jun 30 05:30:53 PM PDT 24
Peak memory 234744 kb
Host smart-27a2f0de-5be6-4c38-8e8c-df2bba8bccc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386623595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.386623595
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.4155840813
Short name T575
Test name
Test status
Simulation time 3055275721 ps
CPU time 30.77 seconds
Started Jun 30 05:29:47 PM PDT 24
Finished Jun 30 05:30:18 PM PDT 24
Peak memory 216952 kb
Host smart-b2d517e9-7e10-4d6c-9e81-77c9732bf6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155840813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4155840813
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1183819155
Short name T420
Test name
Test status
Simulation time 2519498216 ps
CPU time 7.49 seconds
Started Jun 30 05:29:42 PM PDT 24
Finished Jun 30 05:29:50 PM PDT 24
Peak memory 216928 kb
Host smart-a5c445fd-26df-4dab-9e5c-0b5f23e19c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183819155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1183819155
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2934368332
Short name T835
Test name
Test status
Simulation time 258658238 ps
CPU time 10.63 seconds
Started Jun 30 05:29:44 PM PDT 24
Finished Jun 30 05:29:55 PM PDT 24
Peak memory 216812 kb
Host smart-b1b31a7e-98f8-4aca-8232-33b9b19e45d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934368332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2934368332
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.804522325
Short name T391
Test name
Test status
Simulation time 108914859 ps
CPU time 0.9 seconds
Started Jun 30 05:29:46 PM PDT 24
Finished Jun 30 05:29:48 PM PDT 24
Peak memory 206952 kb
Host smart-ea4fa3a7-cee7-4383-b5f0-dc60f1ccb597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804522325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.804522325
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.246004765
Short name T508
Test name
Test status
Simulation time 232848557 ps
CPU time 4.88 seconds
Started Jun 30 05:29:43 PM PDT 24
Finished Jun 30 05:29:48 PM PDT 24
Peak memory 233100 kb
Host smart-fc0a9cf6-42fe-4d74-9232-ea0087f0b9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246004765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.246004765
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1511733904
Short name T411
Test name
Test status
Simulation time 34974375 ps
CPU time 0.75 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:29:53 PM PDT 24
Peak memory 205952 kb
Host smart-6ec71839-e3a8-4434-b9fd-893ea6ea5014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511733904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
511733904
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3880342970
Short name T470
Test name
Test status
Simulation time 1020704285 ps
CPU time 10.15 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:30:02 PM PDT 24
Peak memory 233140 kb
Host smart-07c2c378-7175-49f7-a17b-8f9736e088d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880342970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3880342970
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.191483023
Short name T759
Test name
Test status
Simulation time 115132322 ps
CPU time 0.8 seconds
Started Jun 30 05:29:53 PM PDT 24
Finished Jun 30 05:29:54 PM PDT 24
Peak memory 207660 kb
Host smart-88df6764-56cd-481a-9097-9231644c29cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191483023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.191483023
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1070008000
Short name T586
Test name
Test status
Simulation time 55455432 ps
CPU time 1.01 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:29:53 PM PDT 24
Peak memory 216556 kb
Host smart-2a6e26ff-eda8-45a3-8e68-726cdae43ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070008000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1070008000
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2122618237
Short name T922
Test name
Test status
Simulation time 53963003344 ps
CPU time 468.6 seconds
Started Jun 30 05:29:50 PM PDT 24
Finished Jun 30 05:37:39 PM PDT 24
Peak memory 258656 kb
Host smart-0bfa81bd-dd18-4622-8e21-f8609b05101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122618237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2122618237
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2951985266
Short name T77
Test name
Test status
Simulation time 1201957121 ps
CPU time 17.1 seconds
Started Jun 30 05:29:55 PM PDT 24
Finished Jun 30 05:30:13 PM PDT 24
Peak memory 225428 kb
Host smart-3ca9c850-4f44-49a2-97de-89a341bb202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951985266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2951985266
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2391890794
Short name T696
Test name
Test status
Simulation time 48011056975 ps
CPU time 172.19 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:32:44 PM PDT 24
Peak memory 249736 kb
Host smart-6bd9482d-6c15-49cc-b9c0-e60def788375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391890794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2391890794
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2908629020
Short name T456
Test name
Test status
Simulation time 8659237744 ps
CPU time 23.12 seconds
Started Jun 30 05:29:49 PM PDT 24
Finished Jun 30 05:30:12 PM PDT 24
Peak memory 233280 kb
Host smart-1fc7dba4-63ac-4062-96b1-621448654954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908629020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2908629020
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1887286046
Short name T940
Test name
Test status
Simulation time 25630623816 ps
CPU time 53.92 seconds
Started Jun 30 05:29:50 PM PDT 24
Finished Jun 30 05:30:44 PM PDT 24
Peak memory 249680 kb
Host smart-f82db56d-1cf1-4fb0-9c9d-e4229e2f4725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887286046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1887286046
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2900737597
Short name T477
Test name
Test status
Simulation time 34694312 ps
CPU time 2.31 seconds
Started Jun 30 05:29:55 PM PDT 24
Finished Jun 30 05:29:58 PM PDT 24
Peak memory 232972 kb
Host smart-7581cafe-61ca-48e6-87ec-e82bc2f1e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900737597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2900737597
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4078576540
Short name T806
Test name
Test status
Simulation time 8736018576 ps
CPU time 24.43 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:30:16 PM PDT 24
Peak memory 225148 kb
Host smart-a10c7e4a-ba25-45e7-9ef6-694ecfe8533b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078576540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4078576540
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1134405420
Short name T952
Test name
Test status
Simulation time 506885620 ps
CPU time 8.74 seconds
Started Jun 30 05:29:50 PM PDT 24
Finished Jun 30 05:29:59 PM PDT 24
Peak memory 223652 kb
Host smart-c9e82bb5-b818-49b6-b83f-2115509e0f19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1134405420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1134405420
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3282950753
Short name T805
Test name
Test status
Simulation time 45083091831 ps
CPU time 100.49 seconds
Started Jun 30 05:29:55 PM PDT 24
Finished Jun 30 05:31:36 PM PDT 24
Peak memory 234836 kb
Host smart-9ae42b3b-2943-424c-b5ae-e69ee67796d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282950753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3282950753
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3213077800
Short name T324
Test name
Test status
Simulation time 2514881399 ps
CPU time 8.51 seconds
Started Jun 30 05:29:50 PM PDT 24
Finished Jun 30 05:29:59 PM PDT 24
Peak memory 216944 kb
Host smart-2f4d3087-e53d-4092-95cc-58581ce551ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213077800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3213077800
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.386835792
Short name T668
Test name
Test status
Simulation time 7991898276 ps
CPU time 19.13 seconds
Started Jun 30 05:29:53 PM PDT 24
Finished Jun 30 05:30:13 PM PDT 24
Peak memory 216904 kb
Host smart-31039c73-9cf7-42ef-8e39-ef5510ef4214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386835792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.386835792
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1483715163
Short name T512
Test name
Test status
Simulation time 458231582 ps
CPU time 1.69 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:29:54 PM PDT 24
Peak memory 216768 kb
Host smart-9ea120c6-42fa-4c02-8154-d1871924af7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483715163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1483715163
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1441487890
Short name T665
Test name
Test status
Simulation time 21715883 ps
CPU time 0.68 seconds
Started Jun 30 05:29:54 PM PDT 24
Finished Jun 30 05:29:55 PM PDT 24
Peak memory 206128 kb
Host smart-419ffbd3-9dc8-4ecd-b4e4-6b4129a177f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441487890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1441487890
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4249851714
Short name T746
Test name
Test status
Simulation time 154862427 ps
CPU time 2.7 seconds
Started Jun 30 05:29:53 PM PDT 24
Finished Jun 30 05:29:56 PM PDT 24
Peak memory 233260 kb
Host smart-49fffc7a-10a3-4a4e-aa26-9dbff4bc09dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249851714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4249851714
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.789145175
Short name T767
Test name
Test status
Simulation time 23236524 ps
CPU time 0.71 seconds
Started Jun 30 05:29:57 PM PDT 24
Finished Jun 30 05:29:58 PM PDT 24
Peak memory 205956 kb
Host smart-01b7cfb5-fa10-48c3-8b1e-bba300d489f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789145175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.789145175
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4201130758
Short name T256
Test name
Test status
Simulation time 209513259 ps
CPU time 3.51 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:29:55 PM PDT 24
Peak memory 233216 kb
Host smart-d153c3c4-a49f-4271-8cfd-d5cfa06a663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201130758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4201130758
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3541250983
Short name T956
Test name
Test status
Simulation time 93129055 ps
CPU time 0.78 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:29:53 PM PDT 24
Peak memory 206096 kb
Host smart-b5053909-89f0-40ef-9f03-78e02cdd0cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541250983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3541250983
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1273107796
Short name T921
Test name
Test status
Simulation time 6696210138 ps
CPU time 74.53 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:31:07 PM PDT 24
Peak memory 257064 kb
Host smart-4d52f084-6be6-4a82-8b64-8b66fae685c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273107796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1273107796
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1984236550
Short name T282
Test name
Test status
Simulation time 19226738844 ps
CPU time 23.51 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:30:16 PM PDT 24
Peak memory 249104 kb
Host smart-f35aa547-5466-4917-ae60-73edd1d592a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984236550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1984236550
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3409932489
Short name T387
Test name
Test status
Simulation time 1206341403 ps
CPU time 6.33 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:29:59 PM PDT 24
Peak memory 241396 kb
Host smart-6a720e10-7ee7-40ef-8481-5ac67e2248f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409932489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3409932489
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3360594819
Short name T297
Test name
Test status
Simulation time 15550814336 ps
CPU time 102.71 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:31:35 PM PDT 24
Peak memory 237724 kb
Host smart-3e474358-7442-4c4d-bec9-3f67ee339ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360594819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3360594819
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3464676038
Short name T567
Test name
Test status
Simulation time 2117542835 ps
CPU time 10.19 seconds
Started Jun 30 05:29:52 PM PDT 24
Finished Jun 30 05:30:03 PM PDT 24
Peak memory 233144 kb
Host smart-5073f7f4-706d-4bd4-baa9-d4911e4e7c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464676038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3464676038
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3952728155
Short name T7
Test name
Test status
Simulation time 7775824409 ps
CPU time 12.23 seconds
Started Jun 30 05:29:52 PM PDT 24
Finished Jun 30 05:30:05 PM PDT 24
Peak memory 236740 kb
Host smart-17ae3254-14ec-448b-8048-cae6f7f68d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952728155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3952728155
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2688363353
Short name T712
Test name
Test status
Simulation time 406712199 ps
CPU time 3.57 seconds
Started Jun 30 05:29:53 PM PDT 24
Finished Jun 30 05:29:57 PM PDT 24
Peak memory 225004 kb
Host smart-05309b8a-aa45-49bf-830c-57fd672d1d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688363353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2688363353
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.798198725
Short name T937
Test name
Test status
Simulation time 8032817908 ps
CPU time 23.96 seconds
Started Jun 30 05:29:57 PM PDT 24
Finished Jun 30 05:30:22 PM PDT 24
Peak memory 241180 kb
Host smart-bc6d1755-f915-4659-b7b3-f5d34a7ee8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798198725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.798198725
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3586503144
Short name T975
Test name
Test status
Simulation time 1007107806 ps
CPU time 10.42 seconds
Started Jun 30 05:29:52 PM PDT 24
Finished Jun 30 05:30:04 PM PDT 24
Peak memory 219784 kb
Host smart-4e7763d9-a011-4851-8ae2-9f486c500859
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3586503144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3586503144
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2127437850
Short name T914
Test name
Test status
Simulation time 41042050 ps
CPU time 0.97 seconds
Started Jun 30 05:29:54 PM PDT 24
Finished Jun 30 05:29:56 PM PDT 24
Peak memory 207396 kb
Host smart-427c5194-82ae-4f17-9b0b-504456b5325d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127437850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2127437850
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2865613298
Short name T577
Test name
Test status
Simulation time 661252373 ps
CPU time 7.77 seconds
Started Jun 30 05:29:56 PM PDT 24
Finished Jun 30 05:30:04 PM PDT 24
Peak memory 216984 kb
Host smart-79bd790b-1966-4c6b-97fa-f93163a3cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865613298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2865613298
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.791978442
Short name T974
Test name
Test status
Simulation time 46227460390 ps
CPU time 15.69 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:30:07 PM PDT 24
Peak memory 217056 kb
Host smart-228533ec-1475-4a06-8770-23776c21c692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791978442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.791978442
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4180315851
Short name T442
Test name
Test status
Simulation time 42857443 ps
CPU time 0.99 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:29:53 PM PDT 24
Peak memory 207572 kb
Host smart-844ae1f2-08bc-44e6-8771-3cfd89ced26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180315851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4180315851
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3617120220
Short name T533
Test name
Test status
Simulation time 483688673 ps
CPU time 0.82 seconds
Started Jun 30 05:29:54 PM PDT 24
Finished Jun 30 05:29:55 PM PDT 24
Peak memory 206472 kb
Host smart-0d2dc968-f0f9-47a5-9d38-230497a22dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617120220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3617120220
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3623144217
Short name T798
Test name
Test status
Simulation time 2079776451 ps
CPU time 5.69 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:29:58 PM PDT 24
Peak memory 237380 kb
Host smart-5335eb1b-48be-4bcc-9fdb-cbf05524fdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623144217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3623144217
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2296038209
Short name T799
Test name
Test status
Simulation time 13522694 ps
CPU time 0.71 seconds
Started Jun 30 05:30:00 PM PDT 24
Finished Jun 30 05:30:01 PM PDT 24
Peak memory 205320 kb
Host smart-db663757-2f95-4256-91db-9e36482f79bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296038209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
296038209
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2147763167
Short name T904
Test name
Test status
Simulation time 2188735887 ps
CPU time 7.07 seconds
Started Jun 30 05:30:01 PM PDT 24
Finished Jun 30 05:30:09 PM PDT 24
Peak memory 225112 kb
Host smart-cad08d79-dd0b-461b-8a25-bd034cca56f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147763167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2147763167
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1158606254
Short name T880
Test name
Test status
Simulation time 41148575 ps
CPU time 0.82 seconds
Started Jun 30 05:29:57 PM PDT 24
Finished Jun 30 05:29:58 PM PDT 24
Peak memory 207112 kb
Host smart-17ccf47b-5a01-41c2-9d33-04b1170b9963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158606254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1158606254
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2700109305
Short name T15
Test name
Test status
Simulation time 1001802297 ps
CPU time 13.92 seconds
Started Jun 30 05:29:57 PM PDT 24
Finished Jun 30 05:30:12 PM PDT 24
Peak memory 233168 kb
Host smart-2b356b9b-70c0-427c-a733-acecc4c673b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700109305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2700109305
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1177829450
Short name T334
Test name
Test status
Simulation time 43690774 ps
CPU time 0.84 seconds
Started Jun 30 05:30:00 PM PDT 24
Finished Jun 30 05:30:02 PM PDT 24
Peak memory 217536 kb
Host smart-57baa8e4-cb1e-4a95-9ed2-12e01aa8db95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177829450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1177829450
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.492004699
Short name T816
Test name
Test status
Simulation time 66737647803 ps
CPU time 86.1 seconds
Started Jun 30 05:29:57 PM PDT 24
Finished Jun 30 05:31:24 PM PDT 24
Peak memory 249840 kb
Host smart-1b6c82f1-e8c7-4e3a-bfe6-e4a16cae4d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492004699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
492004699
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4128166689
Short name T977
Test name
Test status
Simulation time 469152010 ps
CPU time 5.71 seconds
Started Jun 30 05:29:57 PM PDT 24
Finished Jun 30 05:30:04 PM PDT 24
Peak memory 233256 kb
Host smart-ebbc71ca-b506-4ebb-a2c2-258ad38ddff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128166689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4128166689
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4271781894
Short name T422
Test name
Test status
Simulation time 386098441 ps
CPU time 2.31 seconds
Started Jun 30 05:29:59 PM PDT 24
Finished Jun 30 05:30:03 PM PDT 24
Peak memory 224088 kb
Host smart-f5aa3f60-e259-4964-ae78-e8571c27e38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271781894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4271781894
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.942253886
Short name T685
Test name
Test status
Simulation time 6425072662 ps
CPU time 81.93 seconds
Started Jun 30 05:29:57 PM PDT 24
Finished Jun 30 05:31:19 PM PDT 24
Peak memory 233288 kb
Host smart-6e3c2090-df32-456a-a031-9aa11011e821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942253886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.942253886
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2560797906
Short name T850
Test name
Test status
Simulation time 8761940260 ps
CPU time 8.39 seconds
Started Jun 30 05:29:59 PM PDT 24
Finished Jun 30 05:30:09 PM PDT 24
Peak memory 241072 kb
Host smart-f0cae1ae-1f1f-4599-9347-cda579fa33b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560797906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2560797906
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3855998269
Short name T267
Test name
Test status
Simulation time 357097955 ps
CPU time 6.88 seconds
Started Jun 30 05:29:54 PM PDT 24
Finished Jun 30 05:30:01 PM PDT 24
Peak memory 240988 kb
Host smart-d649978e-43d0-4972-afc2-90077847d20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855998269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3855998269
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.481993636
Short name T421
Test name
Test status
Simulation time 682044650 ps
CPU time 3.58 seconds
Started Jun 30 05:29:58 PM PDT 24
Finished Jun 30 05:30:03 PM PDT 24
Peak memory 221004 kb
Host smart-f0b8c834-7024-43a4-9b8e-627b1076584d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=481993636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.481993636
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3846153363
Short name T168
Test name
Test status
Simulation time 3908318607 ps
CPU time 11.73 seconds
Started Jun 30 05:29:59 PM PDT 24
Finished Jun 30 05:30:11 PM PDT 24
Peak memory 220512 kb
Host smart-dcadcd7c-a19d-427f-b013-154016e61625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846153363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3846153363
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1716104889
Short name T854
Test name
Test status
Simulation time 11529100015 ps
CPU time 34.59 seconds
Started Jun 30 05:29:54 PM PDT 24
Finished Jun 30 05:30:29 PM PDT 24
Peak memory 216940 kb
Host smart-17051611-99a3-4d5a-a1a9-ec622a3fe42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716104889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1716104889
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.497194326
Short name T629
Test name
Test status
Simulation time 88482479098 ps
CPU time 19.94 seconds
Started Jun 30 05:29:57 PM PDT 24
Finished Jun 30 05:30:18 PM PDT 24
Peak memory 216964 kb
Host smart-f0937422-edf9-4447-935d-8354e841165d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497194326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.497194326
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3026411087
Short name T992
Test name
Test status
Simulation time 51566207 ps
CPU time 0.94 seconds
Started Jun 30 05:29:54 PM PDT 24
Finished Jun 30 05:29:55 PM PDT 24
Peak memory 207196 kb
Host smart-5d69d47f-78ad-41a5-b479-0a709d6fa4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026411087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3026411087
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4117465045
Short name T536
Test name
Test status
Simulation time 130748471 ps
CPU time 1.05 seconds
Started Jun 30 05:29:51 PM PDT 24
Finished Jun 30 05:29:53 PM PDT 24
Peak memory 207480 kb
Host smart-bf47bffd-0bf3-490d-9a61-3becb24d3e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117465045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4117465045
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2896464688
Short name T864
Test name
Test status
Simulation time 6212033628 ps
CPU time 19.52 seconds
Started Jun 30 05:29:59 PM PDT 24
Finished Jun 30 05:30:20 PM PDT 24
Peak memory 233308 kb
Host smart-068e2afd-3c99-4853-8faa-3f47db6da212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896464688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2896464688
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3895937102
Short name T340
Test name
Test status
Simulation time 33240202 ps
CPU time 0.76 seconds
Started Jun 30 05:29:59 PM PDT 24
Finished Jun 30 05:30:01 PM PDT 24
Peak memory 205416 kb
Host smart-0981fc26-ebe8-4b5b-8dd5-db1e8a5eb690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895937102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
895937102
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2225503601
Short name T467
Test name
Test status
Simulation time 37852197 ps
CPU time 2.94 seconds
Started Jun 30 05:29:58 PM PDT 24
Finished Jun 30 05:30:02 PM PDT 24
Peak memory 233168 kb
Host smart-849aee40-2be0-48b6-a79b-074eecabfe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225503601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2225503601
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2462374355
Short name T527
Test name
Test status
Simulation time 23147065 ps
CPU time 0.76 seconds
Started Jun 30 05:30:05 PM PDT 24
Finished Jun 30 05:30:07 PM PDT 24
Peak memory 206412 kb
Host smart-1425b0b2-1cac-4b72-927e-5131b1a5996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462374355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2462374355
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.920735156
Short name T851
Test name
Test status
Simulation time 192219830427 ps
CPU time 324.16 seconds
Started Jun 30 05:29:59 PM PDT 24
Finished Jun 30 05:35:24 PM PDT 24
Peak memory 257156 kb
Host smart-b436b135-cd3b-4e38-b52a-1f732d7cbe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920735156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.920735156
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1372180128
Short name T887
Test name
Test status
Simulation time 4624597564 ps
CPU time 45.17 seconds
Started Jun 30 05:30:06 PM PDT 24
Finished Jun 30 05:30:52 PM PDT 24
Peak memory 241660 kb
Host smart-555add22-bd16-494f-8a0f-47ccc0d0644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372180128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1372180128
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.965423520
Short name T695
Test name
Test status
Simulation time 58049516028 ps
CPU time 120.07 seconds
Started Jun 30 05:30:00 PM PDT 24
Finished Jun 30 05:32:01 PM PDT 24
Peak memory 255836 kb
Host smart-b8b18202-d205-4437-88f9-6f1ff033f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965423520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
965423520
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3335199563
Short name T869
Test name
Test status
Simulation time 4857514539 ps
CPU time 19.58 seconds
Started Jun 30 05:30:01 PM PDT 24
Finished Jun 30 05:30:21 PM PDT 24
Peak memory 225116 kb
Host smart-4cc69155-f3fa-4832-b49d-cdfcb2eb08a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335199563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3335199563
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3900513523
Short name T274
Test name
Test status
Simulation time 184440833 ps
CPU time 3.09 seconds
Started Jun 30 05:29:57 PM PDT 24
Finished Jun 30 05:30:01 PM PDT 24
Peak memory 225000 kb
Host smart-88c6edd6-cd1a-4508-89b1-b1609d0db719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900513523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3900513523
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.74743642
Short name T549
Test name
Test status
Simulation time 562816830 ps
CPU time 4.56 seconds
Started Jun 30 05:29:58 PM PDT 24
Finished Jun 30 05:30:04 PM PDT 24
Peak memory 233184 kb
Host smart-50f68647-4733-4af3-be9c-5839a70825c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74743642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.74743642
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1450321754
Short name T967
Test name
Test status
Simulation time 3092550828 ps
CPU time 6.51 seconds
Started Jun 30 05:30:00 PM PDT 24
Finished Jun 30 05:30:07 PM PDT 24
Peak memory 233356 kb
Host smart-0c792a53-a93f-47eb-ba7b-9315c8898e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450321754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1450321754
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3097571414
Short name T950
Test name
Test status
Simulation time 242862198 ps
CPU time 3.78 seconds
Started Jun 30 05:30:02 PM PDT 24
Finished Jun 30 05:30:06 PM PDT 24
Peak memory 219916 kb
Host smart-65269c2a-cbee-4dfd-9052-cfac13cd0bc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3097571414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3097571414
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2916430885
Short name T540
Test name
Test status
Simulation time 61248326 ps
CPU time 1.07 seconds
Started Jun 30 05:30:01 PM PDT 24
Finished Jun 30 05:30:03 PM PDT 24
Peak memory 207300 kb
Host smart-28f1a52a-d302-43a2-b9ca-d1398a0cd63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916430885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2916430885
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1498864157
Short name T539
Test name
Test status
Simulation time 7376660016 ps
CPU time 25.7 seconds
Started Jun 30 05:29:58 PM PDT 24
Finished Jun 30 05:30:25 PM PDT 24
Peak memory 217132 kb
Host smart-78aac3cc-25cb-4b21-8473-459ff1c4f067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498864157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1498864157
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2609300951
Short name T920
Test name
Test status
Simulation time 3328699045 ps
CPU time 4.15 seconds
Started Jun 30 05:29:59 PM PDT 24
Finished Jun 30 05:30:04 PM PDT 24
Peak memory 216952 kb
Host smart-01707893-0756-4bfb-bbe2-7cf77db6f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609300951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2609300951
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3129823183
Short name T375
Test name
Test status
Simulation time 63415532 ps
CPU time 1 seconds
Started Jun 30 05:30:06 PM PDT 24
Finished Jun 30 05:30:08 PM PDT 24
Peak memory 207504 kb
Host smart-da1510a3-3628-485d-aca2-798e24c109bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129823183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3129823183
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1717669702
Short name T896
Test name
Test status
Simulation time 327452164 ps
CPU time 1.03 seconds
Started Jun 30 05:29:58 PM PDT 24
Finished Jun 30 05:30:00 PM PDT 24
Peak memory 207016 kb
Host smart-d2d81060-9e91-4048-b396-7897f2989151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717669702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1717669702
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1069834361
Short name T238
Test name
Test status
Simulation time 6016383810 ps
CPU time 9.47 seconds
Started Jun 30 05:30:00 PM PDT 24
Finished Jun 30 05:30:10 PM PDT 24
Peak memory 233276 kb
Host smart-17689f2b-10a0-4464-9256-1f6a0715b663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069834361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1069834361
Directory /workspace/9.spi_device_upload/latest
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