Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2908814	1			T1	3383		T3	25		T4	2
all_values[1]	2908814	1			T1	3383		T3	25		T4	2
all_values[2]	2908814	1			T1	3383		T3	25		T4	2
all_values[3]	2908814	1			T1	3383		T3	25		T4	2
all_values[4]	2908814	1			T1	3383		T3	25		T4	2
all_values[5]	2908814	1			T1	3383		T3	25		T4	2
all_values[6]	2908814	1			T1	3383		T3	25		T4	2
all_values[7]	2908814	1			T1	3383		T3	25		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22845530

1

T1

27064

T3

117

T4

16

auto[1]

424982

1

T3

83

T27

55

T29

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23241140

1

T1

27064

T3

143

T4

16

auto[1]

29372

1

T3

57

T17

206

T23

156

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2830737	1			T1	3383		T3	10		T4	2
all_values[0]	auto[0]	auto[1]	13636	1			T3	1		T17	119		T23	66
all_values[0]	auto[1]	auto[0]	63559	1			T3	9		T27	5		T30	3
all_values[0]	auto[1]	auto[1]	882	1			T3	5		T27	4		T29	2
all_values[1]	auto[0]	auto[0]	2830668	1			T1	3383		T3	11		T4	2
all_values[1]	auto[0]	auto[1]	8661	1			T3	6		T17	83		T23	45
all_values[1]	auto[1]	auto[0]	68778	1			T3	5		T27	7		T30	5
all_values[1]	auto[1]	auto[1]	707	1			T3	3		T29	1		T30	3
all_values[2]	auto[0]	auto[0]	2868760	1			T1	3383		T3	13		T4	2
all_values[2]	auto[0]	auto[1]	3329	1			T3	4		T17	4		T23	45
all_values[2]	auto[1]	auto[0]	36405	1			T3	5		T27	4		T29	3
all_values[2]	auto[1]	auto[1]	320	1			T3	3		T27	4		T29	1
all_values[3]	auto[0]	auto[0]	2851640	1			T1	3383		T3	8		T4	2
all_values[3]	auto[0]	auto[1]	184	1			T3	6		T27	1		T30	2
all_values[3]	auto[1]	auto[0]	56806	1			T3	7		T27	7		T30	3
all_values[3]	auto[1]	auto[1]	184	1			T3	4		T30	7		T31	2
all_values[4]	auto[0]	auto[0]	2879329	1			T1	3383		T3	14		T4	2
all_values[4]	auto[0]	auto[1]	188	1			T27	2		T29	1		T30	2
all_values[4]	auto[1]	auto[0]	29106	1			T3	7		T27	1		T30	9
all_values[4]	auto[1]	auto[1]	191	1			T3	4		T27	2		T29	1
all_values[5]	auto[0]	auto[0]	2834515	1			T1	3383		T3	13		T4	2
all_values[5]	auto[0]	auto[1]	162	1			T3	4		T29	1		T30	7
all_values[5]	auto[1]	auto[0]	73964	1			T3	4		T27	5		T30	3
all_values[5]	auto[1]	auto[1]	173	1			T3	4		T27	1		T29	2
all_values[6]	auto[0]	auto[0]	2852058	1			T1	3383		T3	11		T4	2
all_values[6]	auto[0]	auto[1]	177	1			T3	1		T31	4		T32	6
all_values[6]	auto[1]	auto[0]	56387	1			T3	9		T27	5		T29	4
all_values[6]	auto[1]	auto[1]	192	1			T3	4		T27	5		T30	7
all_values[7]	auto[0]	auto[0]	2871283	1			T1	3383		T3	10		T4	2
all_values[7]	auto[0]	auto[1]	203	1			T3	5		T27	2		T29	4
all_values[7]	auto[1]	auto[0]	37145	1			T3	7		T27	5		T30	7
all_values[7]	auto[1]	auto[1]	183	1			T3	3		T30	4		T31	1