Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35076	1			T5	12		T9	4		T17	80
auto[SpiFlashAddrCfg]	7773	1			T5	6		T16	1		T17	23
auto[SpiFlashAddr3b]	9439	1			T5	2		T9	4		T10	4
auto[SpiFlashAddr4b]	7657	1			T17	45		T18	62		T21	24

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34225

1

T10

4

T16

3

T17

100

auto[1]

25720

1

T5

20

T9

8

T17

97

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30849

1

T5

12

T9

6

T10

2

auto[1]

29096

1

T5

8

T9

2

T10

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39974	1			T5	14		T9	8		T16	1
values[1]	1123	1			T17	4		T18	5		T19	2
values[2]	1525	1			T17	9		T18	9		T19	6
values[3]	1449	1			T17	6		T18	7		T20	2
values[4]	1437	1			T17	8		T18	8		T20	6
values[5]	1502	1			T16	2		T17	11		T18	14
values[6]	1432	1			T10	2		T17	6		T18	8
values[7]	1435	1			T17	6		T18	12		T19	2
values[8]	10068	1			T5	6		T10	2		T17	39

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30063

1

T5

20

T9

8

T17

197

auto[1]

29882

1

T10

4

T16

3

T21

265

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56467

1

T5

18

T9

6

T10

4

write

3478

1

T5

2

T9

2

T17

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19698

1

T5

2

T10

4

T16

2

valids[0x1]

40247

1

T5

18

T9

8

T16

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1670	1			T5	2		T17	11		T18	8
internal_process_ops[0x5a]	1620	1			T17	10		T18	7		T19	2
internal_process_ops[0x05]	20966	1			T17	25		T18	248		T21	129
internal_process_ops[0x35]	1579	1			T5	2		T17	6		T18	9
internal_process_ops[0x15]	1521	1			T5	4		T9	2		T17	4
internal_process_ops[0x03]	1003	1			T16	1		T17	11		T18	10
internal_process_ops[0x0b]	1026	1			T17	9		T18	9		T21	3
internal_process_ops[0x3b]	1009	1			T10	2		T16	1		T17	7
internal_process_ops[0x6b]	1071	1			T17	4		T18	4		T21	2
internal_process_ops[0xbb]	1073	1			T10	2		T16	1		T17	7
internal_process_ops[0xeb]	1007	1			T17	1		T18	7		T20	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58296

1

T5

18

T9

6

T10

4

auto[1]

1649

1

T5

2

T9

2

T17

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57410

1

T5

20

T9

8

T10

4

auto[1]

2535

1

T17

13

T18

21

T21

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10428

1

T17

47

T18

221

T39

64

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6357

1

T5

12

T9

2

T17

29

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1815

1

T17

6

T18

14

T20

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1802

1

T5

6

T17

15

T18

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2483

1

T17

20

T18

17

T20

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2058

1

T9

4

T17

27

T18

28

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1889

1

T17

19

T18

30

T39

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1697

1

T17

22

T18

28

T35

12

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

98

1

T17

2

T35

1

T23

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

78

1

T17

2

T18

4

T23

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

101

1

T18

4

T35

1

T27

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

108

1

T9

2

T18

1

T23

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

97

1

T18

2

T28

3

T42

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

82

1

T18

3

T23

3

T28

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

103

1

T17

2

T18

4

T35

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

101

1

T41

1

T43

1

T44

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

132

1

T18

1

T35

1

T46

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T17

2

T35

3

T23

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

84

1

T18

3

T164

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

111

1

T5

2

T18

3

T41

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

105

1

T17

1

T35

2

T27

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

68

1

T17

1

T18

2

T41

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

84

1

T17

2

T18

1

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

87

1

T18

1

T23

1

T42

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10466

1

T21

99

T28

31

T29

116

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6980

1

T21

83

T28

27

T29

22

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1654

1

T16

1

T21

14

T28

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1656

1

T21

17

T28

9

T29

31

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2084

1

T10

4

T16

2

T21

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1891

1

T21

11

T28

17

T29

25

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1641

1

T21

8

T28

10

T29

21

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1566

1

T21

13

T28

7

T29

27

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

118

1

T79

1

T130

3

T167

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

107

1

T21

2

T30

2

T91

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

131

1

T29

1

T84

1

T31

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

104

1

T28

1

T29

2

T79

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

94

1

T28

1

T29

1

T84

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

117

1

T29

1

T30

7

T31

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

141

1

T21

1

T28

3

T29

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

111

1

T29

6

T30

2

T130

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

166

1

T79

1

T30

5

T31

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

150

1

T21

2

T30

3

T33

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

107

1

T21

1

T84

1

T30

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

78

1

T21

2

T84

1

T79

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

135

1

T21

1

T84

1

T30

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

123

1

T21

2

T28

2

T84

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

133

1

T130

4

T33

1

T168

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

129

1

T29

2

T84

1

T30

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3723	1			T17	30		T18	48		T39	6
auto[0]	values[0]	valids[0x1]	15806	1			T5	14		T9	8		T17	78
auto[0]	values[1]	valids[0x1]	555	1			T17	4		T18	5		T19	2
auto[0]	values[2]	valids[0x0]	564	1			T17	2		T18	4		T35	5
auto[0]	values[2]	valids[0x1]	281	1			T17	7		T18	5		T19	6
auto[0]	values[3]	valids[0x0]	527	1			T17	1		T18	5		T40	2
auto[0]	values[3]	valids[0x1]	267	1			T17	5		T18	2		T20	2
auto[0]	values[4]	valids[0x0]	484	1			T17	6		T18	6		T20	6
auto[0]	values[4]	valids[0x1]	258	1			T17	2		T18	2		T35	4
auto[0]	values[5]	valids[0x0]	508	1			T17	7		T18	10		T35	4
auto[0]	values[5]	valids[0x1]	271	1			T17	4		T18	4		T23	1
auto[0]	values[6]	valids[0x0]	474	1			T17	3		T18	5		T35	1
auto[0]	values[6]	valids[0x1]	293	1			T17	3		T18	3		T35	1
auto[0]	values[7]	valids[0x0]	478	1			T17	4		T18	4		T40	2
auto[0]	values[7]	valids[0x1]	288	1			T17	2		T18	8		T19	2
auto[0]	values[8]	valids[0x0]	3382	1			T5	2		T17	22		T18	39
auto[0]	values[8]	valids[0x1]	1904	1			T5	4		T17	17		T18	23
auto[1]	values[0]	valids[0x0]	4271	1			T21	39		T28	28		T29	54
auto[1]	values[0]	valids[0x1]	16174	1			T16	1		T21	162		T28	46
auto[1]	values[1]	valids[0x1]	568	1			T21	5		T28	6		T29	9
auto[1]	values[2]	valids[0x0]	394	1			T21	1		T28	1		T29	7
auto[1]	values[2]	valids[0x1]	286	1			T28	2		T29	2		T79	1
auto[1]	values[3]	valids[0x0]	406	1			T21	2		T29	3		T79	3
auto[1]	values[3]	valids[0x1]	249	1			T29	6		T84	3		T79	2
auto[1]	values[4]	valids[0x0]	446	1			T21	4		T28	5		T29	1
auto[1]	values[4]	valids[0x1]	249	1			T21	1		T29	3		T84	2
auto[1]	values[5]	valids[0x0]	438	1			T16	2		T21	2		T28	1
auto[1]	values[5]	valids[0x1]	285	1			T21	7		T28	2		T29	3
auto[1]	values[6]	valids[0x0]	400	1			T10	2		T21	8		T28	1
auto[1]	values[6]	valids[0x1]	265	1			T21	1		T29	4		T84	1
auto[1]	values[7]	valids[0x0]	415	1			T21	1		T29	2		T84	2
auto[1]	values[7]	valids[0x1]	254	1			T21	2		T29	3		T84	1
auto[1]	values[8]	valids[0x0]	2788	1			T10	2		T21	21		T28	18
auto[1]	values[8]	valids[0x1]	1994	1			T21	9		T28	12		T29	26