Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3333446

1

T4

1

T5

1

T9

1

auto[1]

33665

1

T17

17

T18

235

T21

125

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

964757

1

T4

1

T5

1

T9

1

auto[1]

2402354

1

T17

11479

T18

22630

T21

6831

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	549426	1			T4	1		T5	1		T9	1
auto[524288:1048575]	405956	1			T10	2080		T17	8		T18	2479
auto[1048576:1572863]	440590	1			T17	3		T18	516		T20	2
auto[1572864:2097151]	426273	1			T10	4224		T17	5762		T18	450
auto[2097152:2621439]	366052	1			T10	650		T17	6		T18	8125
auto[2621440:3145727]	405414	1			T10	331		T17	147		T18	322
auto[3145728:3670015]	396007	1			T10	658		T17	4		T18	824
auto[3670016:4194303]	377393	1			T16	636		T17	520		T18	7843

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2435959

1

T4

1

T5

1

T9

1

auto[1]

931152

1

T10

7933

T16

633

T17

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2942154

1

T4

1

T5

1

T9

1

auto[1]

424957

1

T17

275

T18

7263

T21

1950

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	150208	1			T4	1		T5	1		T9	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	334672	1			T17	5080		T18	2149		T21	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	141978	1			T10	2080		T17	4		T18	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	206137	1			T17	2		T18	2442		T21	3031
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	101256	1			T17	1		T18	3		T20	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	275270	1			T17	1		T18	512		T21	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	127141	1			T10	4224		T17	14		T18	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	244779	1			T17	5740		T18	389		T21	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	102825	1			T10	650		T17	1		T18	7
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	207360	1			T17	5		T18	5603		T23	2538
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	123860	1			T10	331		T17	4		T18	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	224371	1			T17	129		T18	265		T21	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	100268	1			T10	658		T17	2		T18	14
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	236812	1			T17	1		T18	785		T21	1820
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	104930	1			T16	636		T17	4		T20	8892
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	231481	1			T17	257		T18	3121		T35	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	1485	1			T17	1		T18	1		T21	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	57975	1			T21	256		T28	517		T41	5
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	585	1			T18	4		T21	8		T28	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	54164	1			T18	2		T21	1602		T28	691
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1097	1			T18	1		T35	1		T23	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	59205	1			T23	644		T29	5		T30	134
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	600	1			T17	2		T18	5		T21	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	50085	1			T17	1		T23	256		T28	1921
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	850	1			T18	8		T35	1		T28	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	51956	1			T18	2466		T23	5		T164	2824
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2000	1			T17	4		T18	1		T35	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47888	1			T17	3		T18	1		T28	1997
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	706	1			T21	1		T28	3		T41	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	54761	1			T28	512		T29	128		T31	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	919	1			T17	2		T18	9		T35	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	35822	1			T17	256		T18	4681		T35	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	502	1			T18	2		T21	1		T39	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	3829	1			T18	11		T21	5		T39	50
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	361	1			T17	2		T21	1		T35	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2106	1			T21	4		T35	16		T23	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	327	1			T17	1		T21	4		T23	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2805	1			T21	23		T41	11		T29	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	382	1			T17	3		T18	2		T21	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2604	1			T17	1		T18	45		T21	7
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	380	1			T18	2		T23	2		T41	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2216	1			T18	29		T41	6		T79	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	520	1			T17	1		T18	3		T28	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	6300	1			T17	1		T18	32		T28	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	436	1			T17	1		T18	3		T23	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2345	1			T18	22		T23	44		T41	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	408	1			T17	1		T35	1		T28	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3285	1			T35	5		T41	7		T30	20
auto[1]	auto[1]	auto[0:524287]	auto[0]	150	1			T28	2		T164	1		T130	11
auto[1]	auto[1]	auto[0:524287]	auto[1]	605	1			T28	9		T164	13		T130	4
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	73	1			T18	2		T21	3		T41	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	552	1			T18	26		T21	76		T41	7
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	99	1			T23	1		T42	5		T30	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	531	1			T23	4		T30	1		T74	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	98	1			T17	1		T29	4		T42	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	584	1			T29	26		T31	12		T164	19
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	74	1			T18	1		T202	1		T203	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	391	1			T18	9		T202	14		T197	23
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	101	1			T17	3		T18	1		T28	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	374	1			T17	2		T18	13		T79	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	63	1			T33	1		T200	3		T202	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	616	1			T202	9		T203	7		T223	15
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	75	1			T18	5		T35	1		T41	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	473	1			T18	27		T41	11		T31	16

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1985542	1			T4	1		T5	1		T9	1
auto[0]	auto[0]	auto[1]	927806	1			T10	7933		T16	633		T18	4
auto[0]	auto[1]	auto[0]	417491	1			T17	269		T18	7173		T21	1869
auto[0]	auto[1]	auto[1]	2607	1			T18	6		T21	2		T35	1
auto[1]	auto[0]	auto[0]	28200	1			T17	10		T18	144		T21	44
auto[1]	auto[0]	auto[1]	606	1			T17	1		T18	7		T21	2
auto[1]	auto[1]	auto[0]	4726	1			T17	6		T18	75		T21	77
auto[1]	auto[1]	auto[1]	133	1			T18	9		T21	2		T23	1