Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2908814	1			T1	3383		T3	25		T4	2
all_pins[1]	2908814	1			T1	3383		T3	25		T4	2
all_pins[2]	2908814	1			T1	3383		T3	25		T4	2
all_pins[3]	2908814	1			T1	3383		T3	25		T4	2
all_pins[4]	2908814	1			T1	3383		T3	25		T4	2
all_pins[5]	2908814	1			T1	3383		T3	25		T4	2
all_pins[6]	2908814	1			T1	3383		T3	25		T4	2
all_pins[7]	2908814	1			T1	3383		T3	25		T4	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23210171	1			T1	27064		T3	170		T4	16
values[0x1]	60341	1			T3	30		T27	16		T29	7
transitions[0x0=>0x1]	59071	1			T3	23		T27	15		T29	5
transitions[0x1=>0x0]	59081	1			T3	23		T27	15		T29	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2907872	1			T1	3383		T3	20		T4	2
all_pins[0]	values[0x1]	942	1			T3	5		T27	4		T29	2
all_pins[0]	transitions[0x0=>0x1]	513	1			T3	5		T27	4		T29	1
all_pins[0]	transitions[0x1=>0x0]	327	1			T3	3		T30	3		T32	3
all_pins[1]	values[0x0]	2908058	1			T1	3383		T3	22		T4	2
all_pins[1]	values[0x1]	756	1			T3	3		T29	1		T30	3
all_pins[1]	transitions[0x0=>0x1]	594	1			T3	2		T29	1		T30	3
all_pins[1]	transitions[0x1=>0x0]	166	1			T3	2		T27	4		T29	1
all_pins[2]	values[0x0]	2908486	1			T1	3383		T3	22		T4	2
all_pins[2]	values[0x1]	328	1			T3	3		T27	4		T29	1
all_pins[2]	transitions[0x0=>0x1]	269	1			T3	1		T27	4		T29	1
all_pins[2]	transitions[0x1=>0x0]	125	1			T3	2		T30	7		T32	5
all_pins[3]	values[0x0]	2908630	1			T1	3383		T3	21		T4	2
all_pins[3]	values[0x1]	184	1			T3	4		T30	7		T31	2
all_pins[3]	transitions[0x0=>0x1]	133	1			T3	2		T30	6		T31	1
all_pins[3]	transitions[0x1=>0x0]	140	1			T3	2		T27	2		T29	1
all_pins[4]	values[0x0]	2908623	1			T1	3383		T3	21		T4	2
all_pins[4]	values[0x1]	191	1			T3	4		T27	2		T29	1
all_pins[4]	transitions[0x0=>0x1]	158	1			T3	4		T27	2		T30	2
all_pins[4]	transitions[0x1=>0x0]	1544	1			T3	4		T27	1		T29	1
all_pins[5]	values[0x0]	2907237	1			T1	3383		T3	21		T4	2
all_pins[5]	values[0x1]	1577	1			T3	4		T27	1		T29	2
all_pins[5]	transitions[0x0=>0x1]	1123	1			T3	4		T29	2		T30	1
all_pins[5]	transitions[0x1=>0x0]	55726	1			T3	4		T27	4		T30	7
all_pins[6]	values[0x0]	2852634	1			T1	3383		T3	21		T4	2
all_pins[6]	values[0x1]	56180	1			T3	4		T27	5		T30	7
all_pins[6]	transitions[0x0=>0x1]	56144	1			T3	3		T27	5		T30	7
all_pins[6]	transitions[0x1=>0x0]	147	1			T3	2		T30	4		T31	1
all_pins[7]	values[0x0]	2908631	1			T1	3383		T3	22		T4	2
all_pins[7]	values[0x1]	183	1			T3	3		T30	4		T31	1
all_pins[7]	transitions[0x0=>0x1]	137	1			T3	2		T30	2		T32	7
all_pins[7]	transitions[0x1=>0x0]	906	1			T3	4		T27	4		T29	2