Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17370

1

T17

100

T18

294

T20

8

auto[1]

12693

1

T5

20

T9

8

T17

97

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3954	1			T39	74		T23	50		T45	21
values[1]	3993	1			T9	8		T17	43		T18	145
values[2]	3970	1			T5	20		T17	48		T18	84
values[3]	4219	1			T17	23		T18	26		T38	2
values[4]	3617	1			T17	22		T18	58		T35	20
values[5]	3410	1			T17	21		T18	83		T20	8
values[6]	3313	1			T17	40		T18	32		T19	14
values[7]	3587	1			T18	67		T27	20		T28	42

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3720	1			T18	151		T39	74		T46	23
values[1]	4187	1			T9	8		T17	21		T18	90
values[2]	4169	1			T17	44		T18	84		T27	20
values[3]	3516	1			T5	20		T17	22		T18	63
values[4]	3973	1			T18	39		T19	14		T38	2
values[5]	3750	1			T17	45		T18	48		T35	41
values[6]	3000	1			T17	22		T18	20		T40	4
values[7]	3748	1			T17	43		T20	8		T23	28

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	492	1			T39	74		T42	10		T223	7
auto[0]	values[0]	values[1]	143	1			T45	12		T72	10		T28	14
auto[0]	values[0]	values[2]	256	1			T41	8		T164	59		T220	4
auto[0]	values[0]	values[3]	154	1			T126	20		T186	17		T214	16
auto[0]	values[0]	values[4]	269	1			T33	19		T186	10		T214	15
auto[0]	values[0]	values[5]	366	1			T41	5		T225	29		T188	8
auto[0]	values[0]	values[6]	187	1			T23	11		T226	10		T32	20
auto[0]	values[0]	values[7]	352	1			T42	11		T200	17		T185	10
auto[0]	values[1]	values[0]	323	1			T18	11		T41	13		T44	117
auto[0]	values[1]	values[1]	275	1			T18	18		T163	4		T205	16
auto[0]	values[1]	values[2]	373	1			T17	11		T42	14		T32	6
auto[0]	values[1]	values[3]	294	1			T17	14		T28	15		T41	7
auto[0]	values[1]	values[4]	292	1			T205	82		T135	13		T186	19
auto[0]	values[1]	values[5]	217	1			T18	11		T35	15		T215	14
auto[0]	values[1]	values[6]	121	1			T227	16		T125	10		T204	17
auto[0]	values[1]	values[7]	456	1			T41	13		T228	16		T43	11
auto[0]	values[2]	values[0]	494	1			T18	43		T42	12		T32	15
auto[0]	values[2]	values[1]	190	1			T44	7		T205	40		T188	16
auto[0]	values[2]	values[2]	308	1			T27	14		T44	4		T200	12
auto[0]	values[2]	values[3]	177	1			T35	13		T23	8		T28	13
auto[0]	values[2]	values[4]	204	1			T45	17		T164	14		T229	29
auto[0]	values[2]	values[5]	505	1			T17	12		T213	6		T230	18
auto[0]	values[2]	values[6]	263	1			T18	15		T28	7		T31	10
auto[0]	values[2]	values[7]	269	1			T17	12		T222	16		T32	9
auto[0]	values[3]	values[0]	171	1			T32	14		T177	12		T58	14
auto[0]	values[3]	values[1]	333	1			T35	9		T23	15		T42	13
auto[0]	values[3]	values[2]	231	1			T17	11		T18	10		T189	11
auto[0]	values[3]	values[3]	264	1			T41	19		T231	12		T205	13
auto[0]	values[3]	values[4]	662	1			T38	2		T43	5		T219	286
auto[0]	values[3]	values[5]	286	1			T43	12		T32	12		T223	7
auto[0]	values[3]	values[6]	209	1			T35	8		T201	4		T32	7
auto[0]	values[3]	values[7]	91	1			T33	7		T205	9		T232	8
auto[0]	values[4]	values[0]	181	1			T28	15		T32	67		T189	20
auto[0]	values[4]	values[1]	333	1			T43	11		T131	8		T32	16
auto[0]	values[4]	values[2]	394	1			T18	48		T33	24		T205	12
auto[0]	values[4]	values[3]	274	1			T42	10		T205	11		T204	11
auto[0]	values[4]	values[4]	151	1			T32	12		T186	11		T58	14
auto[0]	values[4]	values[5]	211	1			T35	12		T32	15		T184	11
auto[0]	values[4]	values[6]	343	1			T17	11		T23	19		T200	13
auto[0]	values[4]	values[7]	220	1			T41	16		T206	15		T193	11
auto[0]	values[5]	values[0]	383	1			T18	9		T33	6		T135	14
auto[0]	values[5]	values[1]	270	1			T17	13		T41	13		T43	12
auto[0]	values[5]	values[2]	208	1			T185	15		T186	10		T197	31
auto[0]	values[5]	values[3]	404	1			T18	59		T23	8		T164	13
auto[0]	values[5]	values[4]	173	1			T185	15		T197	4		T233	6
auto[0]	values[5]	values[5]	183	1			T44	9		T234	8		T204	20
auto[0]	values[5]	values[6]	122	1			T216	8		T176	16		T206	14
auto[0]	values[5]	values[7]	246	1			T20	8		T188	7		T177	22
auto[0]	values[6]	values[0]	241	1			T46	23		T185	25		T53	13
auto[0]	values[6]	values[1]	263	1			T18	20		T28	12		T43	12
auto[0]	values[6]	values[2]	210	1			T31	19		T43	12		T185	14
auto[0]	values[6]	values[3]	183	1			T164	13		T44	15		T235	18
auto[0]	values[6]	values[4]	366	1			T205	9		T188	9		T196	9
auto[0]	values[6]	values[5]	172	1			T17	6		T41	9		T160	4
auto[0]	values[6]	values[6]	350	1			T40	4		T35	12		T42	10
auto[0]	values[6]	values[7]	134	1			T17	10		T23	12		T53	8
auto[0]	values[7]	values[0]	95	1			T236	13		T193	12		T192	9
auto[0]	values[7]	values[1]	472	1			T18	21		T27	13		T44	88
auto[0]	values[7]	values[2]	344	1			T218	20		T188	12		T237	16
auto[0]	values[7]	values[3]	199	1			T44	10		T33	15		T223	47
auto[0]	values[7]	values[4]	289	1			T18	29		T41	15		T165	8
auto[0]	values[7]	values[5]	218	1			T28	30		T180	12		T196	20
auto[0]	values[7]	values[6]	230	1			T164	11		T32	13		T204	52
auto[0]	values[7]	values[7]	281	1			T238	6		T185	11		T58	10
auto[1]	values[0]	values[0]	111	1			T42	10		T223	13		T177	10
auto[1]	values[0]	values[1]	183	1			T45	9		T28	7		T212	82
auto[1]	values[0]	values[2]	250	1			T41	30		T164	4		T195	26
auto[1]	values[0]	values[3]	186	1			T186	48		T214	6		T34	6
auto[1]	values[0]	values[4]	238	1			T33	6		T186	85		T239	12
auto[1]	values[0]	values[5]	224	1			T41	32		T188	13		T176	3
auto[1]	values[0]	values[6]	115	1			T23	39		T32	9		T206	11
auto[1]	values[0]	values[7]	428	1			T42	9		T200	3		T185	16
auto[1]	values[1]	values[0]	198	1			T18	56		T41	24		T44	17
auto[1]	values[1]	values[1]	314	1			T9	8		T18	12		T205	14
auto[1]	values[1]	values[2]	291	1			T17	10		T42	6		T32	14
auto[1]	values[1]	values[3]	126	1			T17	8		T28	6		T41	13
auto[1]	values[1]	values[4]	217	1			T205	8		T135	7		T186	12
auto[1]	values[1]	values[5]	197	1			T18	37		T35	6		T44	11
auto[1]	values[1]	values[6]	64	1			T125	10		T204	3		T240	5
auto[1]	values[1]	values[7]	235	1			T41	11		T43	10		T32	11
auto[1]	values[2]	values[0]	230	1			T18	21		T42	8		T32	5
auto[1]	values[2]	values[1]	230	1			T159	14		T44	13		T205	4
auto[1]	values[2]	values[2]	276	1			T27	6		T44	72		T200	8
auto[1]	values[2]	values[3]	167	1			T5	20		T35	24		T23	15
auto[1]	values[2]	values[4]	112	1			T45	3		T164	20		T241	9
auto[1]	values[2]	values[5]	144	1			T17	13		T43	8		T185	10
auto[1]	values[2]	values[6]	301	1			T18	5		T28	13		T31	17
auto[1]	values[2]	values[7]	100	1			T17	11		T32	12		T135	7
auto[1]	values[3]	values[0]	192	1			T32	6		T177	8		T58	6
auto[1]	values[3]	values[1]	277	1			T35	21		T23	68		T42	7
auto[1]	values[3]	values[2]	267	1			T17	12		T18	16		T189	10
auto[1]	values[3]	values[3]	221	1			T41	11		T205	7		T188	12
auto[1]	values[3]	values[4]	355	1			T43	17		T219	7		T189	12
auto[1]	values[3]	values[5]	279	1			T43	8		T32	18		T223	13
auto[1]	values[3]	values[6]	166	1			T35	12		T32	25		T176	12
auto[1]	values[3]	values[7]	215	1			T33	23		T205	88		T53	44
auto[1]	values[4]	values[0]	90	1			T28	6		T32	19		T189	9
auto[1]	values[4]	values[1]	182	1			T43	9		T32	5		T33	6
auto[1]	values[4]	values[2]	322	1			T18	10		T33	19		T205	30
auto[1]	values[4]	values[3]	241	1			T42	10		T205	9		T204	49
auto[1]	values[4]	values[4]	116	1			T32	12		T186	65		T58	7
auto[1]	values[4]	values[5]	100	1			T35	8		T32	5		T184	14
auto[1]	values[4]	values[6]	166	1			T17	11		T23	6		T200	7
auto[1]	values[4]	values[7]	293	1			T41	21		T242	8		T206	5
auto[1]	values[5]	values[0]	218	1			T18	11		T33	14		T135	6
auto[1]	values[5]	values[1]	116	1			T17	8		T41	20		T43	8
auto[1]	values[5]	values[2]	198	1			T221	20		T185	5		T186	10
auto[1]	values[5]	values[3]	180	1			T18	4		T23	14		T164	7
auto[1]	values[5]	values[4]	175	1			T185	5		T197	26		T53	9
auto[1]	values[5]	values[5]	270	1			T44	46		T243	20		T204	67
auto[1]	values[5]	values[6]	48	1			T176	4		T206	7		T34	6
auto[1]	values[5]	values[7]	216	1			T188	13		T177	18		T204	11
auto[1]	values[6]	values[0]	202	1			T185	21		T53	7		T244	22
auto[1]	values[6]	values[1]	322	1			T18	12		T28	17		T43	13
auto[1]	values[6]	values[2]	103	1			T31	3		T43	8		T185	6
auto[1]	values[6]	values[3]	144	1			T164	35		T44	5		T206	9
auto[1]	values[6]	values[4]	130	1			T19	14		T205	11		T188	14
auto[1]	values[6]	values[5]	169	1			T17	14		T41	11		T197	27
auto[1]	values[6]	values[6]	196	1			T35	8		T42	10		T164	62
auto[1]	values[6]	values[7]	128	1			T17	10		T23	16		T53	18
auto[1]	values[7]	values[0]	99	1			T245	18		T236	7		T193	8
auto[1]	values[7]	values[1]	284	1			T18	7		T27	7		T44	9
auto[1]	values[7]	values[2]	138	1			T188	8		T53	10		T176	4
auto[1]	values[7]	values[3]	302	1			T44	29		T33	9		T223	8
auto[1]	values[7]	values[4]	224	1			T18	10		T41	9		T200	11
auto[1]	values[7]	values[5]	209	1			T28	12		T180	8		T196	4
auto[1]	values[7]	values[6]	119	1			T164	9		T32	7		T204	7
auto[1]	values[7]	values[7]	84	1			T185	9		T58	10		T166	8