Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	370	1			T17	2		T18	2		T20	4
auto[ReadAddrCrossIntoMailbox]	259	1			T17	1		T18	4		T20	2
auto[ReadAddrCrossOutOfMailbox]	329	1			T18	4		T20	2		T35	5
auto[ReadAddrCrossAllMailbox]	196	1			T17	1		T18	1		T27	1
auto[ReadAddrOutsideMailbox]	3359	1			T17	35		T18	37		T39	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2304

1

T17

16

T18

30

T20

4

auto[1]

2209

1

T17

23

T18

18

T20

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	739	1			T17	11		T18	10		T20	2
read_ops[0x0b]	750	1			T17	9		T18	9		T38	2
read_ops[0x3b]	714	1			T17	7		T18	11		T35	5
read_ops[0x6b]	766	1			T17	4		T18	4		T35	6
read_ops[0xbb]	825	1			T17	7		T18	7		T20	4
read_ops[0xeb]	719	1			T17	1		T18	7		T20	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T28	1		T219	1		T196	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T35	1		T212	1		T246	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T23	1		T44	1		T126	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T17	1		T18	1		T126	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T20	1		T41	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T20	1		T35	1		T43	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T28	1		T33	1		T223	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T42	1		T43	1		T164	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	292	1			T17	8		T18	6		T35	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T17	2		T18	3		T35	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T18	1		T38	1		T41	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T38	1		T32	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T18	1		T41	2		T44	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T205	1		T185	1		T186	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T205	1		T185	1		T188	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T27	1		T205	1		T188	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T185	1		T188	1		T186	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T33	1		T216	1		T177	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T17	3		T18	4		T39	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	287	1			T17	6		T18	3		T39	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T17	1		T23	1		T28	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T35	1		T27	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T23	1		T28	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T18	1		T35	2		T43	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T35	1		T42	1		T43	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T18	2		T43	1		T44	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T186	1		T197	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T204	1		T184	1		T247	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T17	3		T18	6		T72	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T17	3		T18	2		T35	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T27	1		T28	1		T238	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T35	1		T238	1		T135	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T205	1		T188	1		T196	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T35	1		T185	1		T58	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T18	1		T28	1		T42	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T35	1		T28	1		T205	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T18	1		T27	1		T197	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T17	1		T32	2		T200	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T35	2		T23	1		T45	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T17	3		T18	2		T35	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T17	1		T20	1		T35	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T20	1		T35	1		T126	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T18	1		T20	1		T23	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T20	1		T35	1		T23	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T35	1		T43	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T18	1		T23	2		T126	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T126	1		T32	2		T186	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T31	1		T126	1		T176	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T18	5		T40	1		T46	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T17	6		T40	1		T35	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T20	1		T33	1		T188	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T18	1		T20	1		T205	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T43	1		T44	1		T185	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T28	1		T205	1		T185	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T35	1		T43	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T28	1		T33	1		T185	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T200	1		T53	1		T248	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T28	2		T32	1		T205	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T18	4		T35	2		T213	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	253	1			T17	1		T18	2		T213	1