Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4095	1			T17	45		T18	130		T39	74
values[1]	4282	1			T17	23		T18	83		T35	20
values[2]	3609	1			T17	20		T18	52		T35	21
values[3]	3953	1			T17	47		T35	40		T23	73
values[4]	3772	1			T5	20		T17	21		T28	22
values[5]	2974	1			T18	84		T19	14		T38	2
values[6]	3609	1			T18	59		T28	21		T41	37
values[7]	3769	1			T9	8		T17	41		T18	87

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3790	1			T17	20		T18	67		T40	4
values[1]	3896	1			T17	44		T18	88		T38	2
values[2]	3216	1			T17	21		T18	112		T41	33
values[3]	3805	1			T5	20		T18	93		T19	14
values[4]	3899	1			T9	8		T17	47		T39	74
values[5]	3836	1			T18	59		T23	50		T27	20
values[6]	3737	1			T17	43		T46	23		T72	10
values[7]	3884	1			T17	22		T18	76		T35	71

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29333

1

T5

18

T9

6

T17

192

auto[1]

730

1

T5

2

T9

2

T17

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	367	1			T18	66		T35	37		T188	44
auto[0]	values[0]	values[1]	466	1			T28	21		T33	25		T198	19
auto[0]	values[0]	values[2]	407	1			T42	20		T188	20		T180	20
auto[0]	values[0]	values[3]	428	1			T18	35		T43	23		T185	20
auto[0]	values[0]	values[4]	698	1			T17	21		T39	74		T231	12
auto[0]	values[0]	values[5]	534	1			T27	20		T41	30		T32	46
auto[0]	values[0]	values[6]	437	1			T17	22		T228	16		T205	69
auto[0]	values[0]	values[7]	660	1			T18	28		T249	20		T219	137
auto[0]	values[1]	values[0]	507	1			T42	35		T31	19		T43	21
auto[0]	values[1]	values[1]	359	1			T17	22		T53	48		T250	8
auto[0]	values[1]	values[2]	501	1			T18	82		T42	20		T43	17
auto[0]	values[1]	values[3]	466	1			T28	21		T41	38		T221	20
auto[0]	values[1]	values[4]	466	1			T200	19		T135	20		T251	6
auto[0]	values[1]	values[5]	481	1			T28	21		T164	48		T215	14
auto[0]	values[1]	values[6]	702	1			T46	23		T44	97		T33	30
auto[0]	values[1]	values[7]	679	1			T35	20		T227	16		T165	8
auto[0]	values[2]	values[0]	412	1			T41	20		T43	20		T177	20
auto[0]	values[2]	values[1]	368	1			T41	37		T252	18		T177	20
auto[0]	values[2]	values[2]	466	1			T43	19		T126	20		T189	29
auto[0]	values[2]	values[3]	704	1			T18	32		T43	17		T253	20
auto[0]	values[2]	values[4]	312	1			T23	26		T45	21		T164	63
auto[0]	values[2]	values[5]	569	1			T18	20		T41	20		T42	20
auto[0]	values[2]	values[6]	390	1			T17	20		T28	20		T226	10
auto[0]	values[2]	values[7]	320	1			T35	20		T27	20		T131	8
auto[0]	values[3]	values[0]	605	1			T28	20		T42	20		T43	17
auto[0]	values[3]	values[1]	620	1			T23	22		T164	20		T195	26
auto[0]	values[3]	values[2]	430	1			T42	20		T32	23		T205	87
auto[0]	values[3]	values[3]	374	1			T35	18		T31	21		T242	6
auto[0]	values[3]	values[4]	361	1			T17	25		T35	20		T41	23
auto[0]	values[3]	values[5]	447	1			T23	48		T204	38		T86	20
auto[0]	values[3]	values[6]	583	1			T230	18		T44	74		T32	21
auto[0]	values[3]	values[7]	425	1			T17	20		T185	20		T198	20
auto[0]	values[4]	values[0]	430	1			T43	21		T200	20		T254	16
auto[0]	values[4]	values[1]	616	1			T17	21		T44	18		T219	293
auto[0]	values[4]	values[2]	284	1			T42	18		T255	18		T197	20
auto[0]	values[4]	values[3]	470	1			T5	18		T44	110		T32	18
auto[0]	values[4]	values[4]	389	1			T201	4		T205	36		T188	42
auto[0]	values[4]	values[5]	486	1			T28	22		T197	30		T198	21
auto[0]	values[4]	values[6]	419	1			T186	91		T189	20		T177	20
auto[0]	values[4]	values[7]	590	1			T205	20		T249	25		T220	4
auto[0]	values[5]	values[0]	478	1			T40	4		T41	24		T159	14
auto[0]	values[5]	values[1]	524	1			T18	54		T38	2		T32	20
auto[0]	values[5]	values[2]	171	1			T41	31		T204	20		T256	22
auto[0]	values[5]	values[3]	337	1			T18	24		T19	14		T213	6
auto[0]	values[5]	values[4]	571	1			T23	80		T41	35		T43	16
auto[0]	values[5]	values[5]	314	1			T32	27		T205	20		T204	45
auto[0]	values[5]	values[6]	243	1			T135	26		T186	44		T223	72
auto[0]	values[5]	values[7]	258	1			T23	22		T33	18		T196	19
auto[0]	values[6]	values[0]	288	1			T44	39		T185	20		T233	6
auto[0]	values[6]	values[1]	549	1			T18	30		T28	21		T164	75
auto[0]	values[6]	values[2]	346	1			T18	27		T33	20		T135	40
auto[0]	values[6]	values[3]	436	1			T197	36		T196	33		T244	25
auto[0]	values[6]	values[4]	585	1			T33	19		T204	58		T53	37
auto[0]	values[6]	values[5]	542	1			T41	36		T44	40		T234	8
auto[0]	values[6]	values[6]	324	1			T160	4		T185	34		T182	8
auto[0]	values[6]	values[7]	466	1			T222	16		T164	34		T166	20
auto[0]	values[7]	values[0]	604	1			T17	20		T45	20		T32	66
auto[0]	values[7]	values[1]	312	1			T257	2		T188	41		T219	20
auto[0]	values[7]	values[2]	531	1			T17	21		T44	54		T186	95
auto[0]	values[7]	values[3]	499	1			T20	8		T23	24		T185	46
auto[0]	values[7]	values[4]	404	1			T9	6		T164	20		T200	19
auto[0]	values[7]	values[5]	375	1			T18	39		T31	25		T258	10
auto[0]	values[7]	values[6]	556	1			T72	10		T127	16		T218	20
auto[0]	values[7]	values[7]	392	1			T18	44		T35	30		T33	24
auto[1]	values[0]	values[0]	3	1			T18	1		T259	2		-	-
auto[1]	values[0]	values[1]	17	1			T198	1		T214	3		T236	4
auto[1]	values[0]	values[2]	8	1			T188	1		T53	1		T260	1
auto[1]	values[0]	values[3]	10	1			T43	2		T206	1		T49	2
auto[1]	values[0]	values[4]	15	1			T17	1		T197	3		T212	3
auto[1]	values[0]	values[5]	10	1			T32	3		T261	3		T262	1
auto[1]	values[0]	values[6]	16	1			T17	1		T205	3		T34	4
auto[1]	values[0]	values[7]	19	1			T249	1		T219	4		T223	1
auto[1]	values[1]	values[0]	25	1			T42	5		T31	1		T43	1
auto[1]	values[1]	values[1]	8	1			T17	1		T53	3		T49	2
auto[1]	values[1]	values[2]	12	1			T18	1		T43	3		T263	1
auto[1]	values[1]	values[3]	13	1			T198	1		T244	1		T49	1
auto[1]	values[1]	values[4]	26	1			T200	1		T240	2		T139	3
auto[1]	values[1]	values[5]	10	1			T135	2		T264	2		T265	2
auto[1]	values[1]	values[6]	9	1			T34	4		T256	2		T136	1
auto[1]	values[1]	values[7]	18	1			T32	5		T33	1		T205	2
auto[1]	values[2]	values[0]	9	1			T266	2		T267	3		T268	1
auto[1]	values[2]	values[1]	7	1			T192	4		T269	2		T270	1
auto[1]	values[2]	values[2]	11	1			T43	1		T58	1		T176	1
auto[1]	values[2]	values[3]	13	1			T43	3		T184	1		T271	4
auto[1]	values[2]	values[4]	8	1			T23	2		T44	1		T239	2
auto[1]	values[2]	values[5]	8	1			T58	3		T206	1		T272	2
auto[1]	values[2]	values[6]	7	1			T219	1		T247	1		T157	2
auto[1]	values[2]	values[7]	5	1			T35	1		T244	2		T240	1
auto[1]	values[3]	values[0]	14	1			T28	1		T43	3		T206	1
auto[1]	values[3]	values[1]	17	1			T23	1		T206	3		T260	2
auto[1]	values[3]	values[2]	8	1			T32	1		T205	3		T136	3
auto[1]	values[3]	values[3]	12	1			T35	2		T31	1		T242	2
auto[1]	values[3]	values[4]	18	1			T41	1		T205	1		T177	3
auto[1]	values[3]	values[5]	17	1			T23	2		T204	2		T192	2
auto[1]	values[3]	values[6]	9	1			T44	2		T186	2		T196	1
auto[1]	values[3]	values[7]	13	1			T17	2		T196	1		T192	2
auto[1]	values[4]	values[0]	15	1			T244	1		T34	2		T273	6
auto[1]	values[4]	values[1]	9	1			T44	2		T212	1		T274	1
auto[1]	values[4]	values[2]	8	1			T42	2		T275	1		T276	4
auto[1]	values[4]	values[3]	11	1			T5	2		T44	4		T32	2
auto[1]	values[4]	values[4]	11	1			T188	2		T176	1		T277	3
auto[1]	values[4]	values[5]	14	1			T193	3		T269	1		T278	2
auto[1]	values[4]	values[6]	13	1			T186	4		T214	3		T193	2
auto[1]	values[4]	values[7]	7	1			T53	1		T244	3		T279	2
auto[1]	values[5]	values[0]	13	1			T200	1		T205	1		T189	1
auto[1]	values[5]	values[1]	16	1			T18	4		T223	3		T214	1
auto[1]	values[5]	values[2]	5	1			T41	2		T280	2		T140	1
auto[1]	values[5]	values[3]	12	1			T18	2		T28	3		T157	2
auto[1]	values[5]	values[4]	13	1			T23	3		T41	2		T43	4
auto[1]	values[5]	values[5]	6	1			T32	3		T206	1		T281	1
auto[1]	values[5]	values[6]	4	1			T186	1		T223	3		-	-
auto[1]	values[5]	values[7]	9	1			T33	2		T196	1		T282	2
auto[1]	values[6]	values[0]	7	1			T206	2		T283	2		T284	1
auto[1]	values[6]	values[1]	5	1			T125	1		T256	1		T136	1
auto[1]	values[6]	values[2]	9	1			T18	2		T53	1		T58	1
auto[1]	values[6]	values[3]	7	1			T196	2		T244	2		T206	1
auto[1]	values[6]	values[4]	17	1			T33	2		T204	2		T176	4
auto[1]	values[6]	values[5]	9	1			T41	1		T189	1		T193	1
auto[1]	values[6]	values[6]	7	1			T185	2		T223	2		T275	1
auto[1]	values[6]	values[7]	12	1			T192	1		T269	3		T137	1
auto[1]	values[7]	values[0]	13	1			T33	1		T267	2		T285	4
auto[1]	values[7]	values[1]	3	1			T188	1		T256	2		-	-
auto[1]	values[7]	values[2]	19	1			T44	1		T186	5		T214	1
auto[1]	values[7]	values[3]	13	1			T23	1		T58	4		T34	2
auto[1]	values[7]	values[4]	5	1			T9	2		T200	1		T286	1
auto[1]	values[7]	values[5]	14	1			T31	2		T258	8		T177	1
auto[1]	values[7]	values[6]	18	1			T127	2		T196	1		T212	1
auto[1]	values[7]	values[7]	11	1			T18	4		T176	1		T206	1