Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	800	1			T3	20		T27	7		T29	4
all_values[1]	800	1			T3	20		T27	7		T29	4
all_values[2]	800	1			T3	20		T27	7		T29	4
all_values[3]	800	1			T3	20		T27	7		T29	4
all_values[4]	800	1			T3	20		T27	7		T29	4
all_values[5]	800	1			T3	20		T27	7		T29	4
all_values[6]	800	1			T3	20		T27	7		T29	4
all_values[7]	800	1			T3	20		T27	7		T29	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3386

1

T3

77

T27

23

T29

20

auto[1]

3014

1

T3

83

T27

33

T29

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2610

1

T3

75

T27

28

T29

15

auto[1]

3790

1

T3

85

T27

28

T29

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3710

1

T3

97

T27

38

T29

19

auto[1]

2690

1

T3

63

T27

18

T29

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	178	1			T3	4		T27	1		T30	3
all_values[0]	auto[0]	auto[0]	auto[1]	71	1			T29	1		T30	2		T31	1
all_values[0]	auto[0]	auto[1]	auto[0]	128	1			T3	7		T27	2		T31	1
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T3	2		T27	3		T30	2
all_values[0]	auto[1]	auto[0]	auto[1]	186	1			T3	3		T29	1		T30	8
all_values[0]	auto[1]	auto[1]	auto[1]	158	1			T3	4		T27	1		T29	2
all_values[1]	auto[0]	auto[0]	auto[0]	187	1			T3	6		T27	3		T29	1
all_values[1]	auto[0]	auto[0]	auto[1]	64	1			T3	2		T29	1		T30	2
all_values[1]	auto[0]	auto[1]	auto[0]	139	1			T3	3		T27	2		T30	2
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T31	1		T155	2		T166	4
all_values[1]	auto[1]	auto[0]	auto[1]	167	1			T3	2		T27	1		T29	1
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T3	7		T27	1		T29	1
all_values[2]	auto[0]	auto[0]	auto[0]	175	1			T3	3		T29	1		T30	5
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T3	3		T27	1		T30	2
all_values[2]	auto[0]	auto[1]	auto[0]	143	1			T3	3		T27	1		T29	2
all_values[2]	auto[0]	auto[1]	auto[1]	89	1			T3	2		T27	2		T31	3
all_values[2]	auto[1]	auto[0]	auto[1]	168	1			T3	7		T27	1		T30	5
all_values[2]	auto[1]	auto[1]	auto[1]	155	1			T3	2		T27	2		T29	1
all_values[3]	auto[0]	auto[0]	auto[0]	163	1			T3	3		T27	2		T29	4
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T3	1		T30	1		T32	2
all_values[3]	auto[0]	auto[1]	auto[0]	149	1			T3	6		T27	3		T30	1
all_values[3]	auto[0]	auto[1]	auto[1]	76	1			T3	2		T30	2		T31	1
all_values[3]	auto[1]	auto[0]	auto[1]	164	1			T3	3		T27	2		T30	1
all_values[3]	auto[1]	auto[1]	auto[1]	165	1			T3	5		T30	7		T31	1
all_values[4]	auto[0]	auto[0]	auto[0]	159	1			T3	6		T27	2		T29	2
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T27	1		T30	1		T31	1
all_values[4]	auto[0]	auto[1]	auto[0]	134	1			T3	6		T27	1		T30	3
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T3	2		T27	1		T30	1
all_values[4]	auto[1]	auto[0]	auto[1]	196	1			T3	2		T27	1		T29	1
all_values[4]	auto[1]	auto[1]	auto[1]	145	1			T3	4		T27	1		T29	1
all_values[5]	auto[0]	auto[0]	auto[0]	257	1			T3	8		T27	4		T29	1
all_values[5]	auto[0]	auto[1]	auto[0]	208	1			T3	4		T27	2		T30	3
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T3	5		T29	1		T30	7
all_values[5]	auto[1]	auto[1]	auto[1]	161	1			T3	3		T27	1		T29	2
all_values[6]	auto[0]	auto[0]	auto[0]	155	1			T3	4		T29	1		T30	4
all_values[6]	auto[0]	auto[0]	auto[1]	63	1			T3	1		T31	1		T32	2
all_values[6]	auto[0]	auto[1]	auto[0]	147	1			T3	6		T27	1		T29	3
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T3	2		T27	1		T30	4
all_values[6]	auto[1]	auto[0]	auto[1]	195	1			T3	3		T27	1		T30	1
all_values[6]	auto[1]	auto[1]	auto[1]	155	1			T3	4		T27	4		T30	5
all_values[7]	auto[0]	auto[0]	auto[0]	153	1			T3	3		T27	1		T30	6
all_values[7]	auto[0]	auto[0]	auto[1]	91	1			T3	3		T27	1		T29	2
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T3	3		T27	3		T30	4
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T3	2		T30	3		T31	1
all_values[7]	auto[1]	auto[0]	auto[1]	181	1			T3	5		T27	1		T29	2
all_values[7]	auto[1]	auto[1]	auto[1]	162	1			T3	4		T27	1		T30	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal