Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1826

1

T1

3

T11

1

T12

14

auto[1]

1816

1

T1

5

T12

26

T14

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2014

1

T1

8

T14

12

T17

23

auto[1]

1628

1

T11

1

T12

40

T14

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2887

1

T1

3

T11

1

T12

40

auto[1]

755

1

T1

5

T14

6

T17

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	696	1			T1	2		T11	1		T12	8
valid[1]	753	1			T1	2		T12	10		T14	2
valid[2]	708	1			T1	2		T12	5		T14	3
valid[3]	718	1			T1	1		T12	8		T14	2
valid[4]	767	1			T1	1		T12	9		T14	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	115	1			T14	3		T17	3		T28	3
auto[0]	auto[0]	valid[0]	auto[1]	162	1			T11	1		T12	4		T26	2
auto[0]	auto[0]	valid[1]	auto[0]	126	1			T1	1		T17	1		T24	2
auto[0]	auto[0]	valid[1]	auto[1]	163	1			T12	1		T14	1		T26	1
auto[0]	auto[0]	valid[2]	auto[0]	129	1			T17	1		T27	1		T28	3
auto[0]	auto[0]	valid[2]	auto[1]	145	1			T12	3		T26	1		T73	2
auto[0]	auto[0]	valid[3]	auto[0]	127	1			T17	2		T23	1		T45	1
auto[0]	auto[0]	valid[3]	auto[1]	173	1			T12	3		T26	1		T73	2
auto[0]	auto[0]	valid[4]	auto[0]	119	1			T17	2		T23	1		T45	1
auto[0]	auto[0]	valid[4]	auto[1]	195	1			T12	3		T26	3		T73	4
auto[0]	auto[1]	valid[0]	auto[0]	125	1			T1	1		T14	1		T17	3
auto[0]	auto[1]	valid[0]	auto[1]	151	1			T12	4		T14	1		T73	6
auto[0]	auto[1]	valid[1]	auto[0]	125	1			T17	2		T28	2		T80	1
auto[0]	auto[1]	valid[1]	auto[1]	187	1			T12	9		T26	4		T73	2
auto[0]	auto[1]	valid[2]	auto[0]	127	1			T14	2		T17	2		T45	3
auto[0]	auto[1]	valid[2]	auto[1]	145	1			T12	2		T26	1		T73	6
auto[0]	auto[1]	valid[3]	auto[0]	122	1			T24	2		T28	2		T80	2
auto[0]	auto[1]	valid[3]	auto[1]	151	1			T12	5		T14	1		T73	2
auto[0]	auto[1]	valid[4]	auto[0]	144	1			T1	1		T17	2		T24	2
auto[0]	auto[1]	valid[4]	auto[1]	156	1			T12	6		T14	1		T26	1
auto[1]	auto[0]	valid[0]	auto[0]	75	1			T14	1		T17	1		T24	1
auto[1]	auto[0]	valid[1]	auto[0]	81	1			T1	1		T14	1		T17	3
auto[1]	auto[0]	valid[2]	auto[0]	74	1			T14	1		T17	1		T23	1
auto[1]	auto[0]	valid[3]	auto[0]	66	1			T1	1		T45	1		T28	1
auto[1]	auto[0]	valid[4]	auto[0]	76	1			T28	2		T80	2		T79	1
auto[1]	auto[1]	valid[0]	auto[0]	68	1			T1	1		T45	1		T28	2
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T28	1		T43	1		T81	2
auto[1]	auto[1]	valid[2]	auto[0]	88	1			T1	2		T24	3		T45	1
auto[1]	auto[1]	valid[3]	auto[0]	79	1			T14	1		T23	1		T27	1
auto[1]	auto[1]	valid[4]	auto[0]	77	1			T14	2		T24	1		T45	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal