Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51128

1

T1

161

T7

10

T8

8

auto[1]

17491

1

T11

1

T12

457

T14

82

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49853

1

T1

104

T7

5

T8

3

auto[1]

18766

1

T1

57

T7

5

T8

5

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35467	1			T1	96		T7	6		T8	5
others[1]	5665	1			T1	8		T7	3		T12	29
others[2]	5791	1			T1	11		T7	1		T8	1
others[3]	6668	1			T1	17		T12	46		T14	39
interest[1]	3739	1			T1	10		T12	23		T14	22
interest[4]	23144	1			T1	65		T7	6		T8	1
interest[64]	11289	1			T1	19		T8	2		T12	76

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16597	1			T1	64		T7	4		T8	2
auto[0]	auto[0]	others[1]	2650	1			T1	5		T7	1		T14	22
auto[0]	auto[0]	others[2]	2763	1			T1	8		T14	28		T17	29
auto[0]	auto[0]	others[3]	3129	1			T1	9		T14	18		T17	46
auto[0]	auto[0]	interest[1]	1850	1			T1	7		T14	11		T17	16
auto[0]	auto[0]	interest[4]	10762	1			T1	43		T7	4		T14	77
auto[0]	auto[0]	interest[64]	5373	1			T1	11		T8	1		T14	43
auto[0]	auto[1]	others[0]	9142	1			T11	1		T12	241		T14	39
auto[0]	auto[1]	others[1]	1462	1			T12	29		T14	11		T73	34
auto[0]	auto[1]	others[2]	1455	1			T12	42		T14	7		T73	43
auto[0]	auto[1]	others[3]	1712	1			T12	46		T14	8		T73	38
auto[0]	auto[1]	interest[1]	905	1			T12	23		T14	4		T73	29
auto[0]	auto[1]	interest[4]	6109	1			T11	1		T12	160		T14	30
auto[0]	auto[1]	interest[64]	2815	1			T12	76		T14	13		T73	74
auto[1]	auto[0]	others[0]	9728	1			T1	32		T7	2		T8	3
auto[1]	auto[0]	others[1]	1553	1			T1	3		T7	2		T14	14
auto[1]	auto[0]	others[2]	1573	1			T1	3		T7	1		T8	1
auto[1]	auto[0]	others[3]	1827	1			T1	8		T14	13		T17	23
auto[1]	auto[0]	interest[1]	984	1			T1	3		T14	7		T17	7
auto[1]	auto[0]	interest[4]	6273	1			T1	22		T7	2		T8	1
auto[1]	auto[0]	interest[64]	3101	1			T1	8		T8	1		T14	20

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal