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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T105 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2302935413 Jul 01 10:32:51 AM PDT 24 Jul 01 10:32:55 AM PDT 24 1374767810 ps
T117 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2365969721 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:37 AM PDT 24 581675619 ps
T118 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1431344 Jul 01 10:32:52 AM PDT 24 Jul 01 10:32:54 AM PDT 24 401952346 ps
T1032 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1886748101 Jul 01 10:32:49 AM PDT 24 Jul 01 10:32:50 AM PDT 24 32211932 ps
T119 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2990293627 Jul 01 10:32:31 AM PDT 24 Jul 01 10:32:34 AM PDT 24 233102709 ps
T96 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2034564896 Jul 01 10:32:32 AM PDT 24 Jul 01 10:32:37 AM PDT 24 375214287 ps
T152 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4044691426 Jul 01 10:32:29 AM PDT 24 Jul 01 10:32:39 AM PDT 24 713832631 ps
T153 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1883767099 Jul 01 10:32:28 AM PDT 24 Jul 01 10:32:37 AM PDT 24 4882203362 ps
T99 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1434148260 Jul 01 10:32:59 AM PDT 24 Jul 01 10:33:02 AM PDT 24 404713427 ps
T1033 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.488750536 Jul 01 10:32:38 AM PDT 24 Jul 01 10:32:41 AM PDT 24 55453187 ps
T170 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.883804406 Jul 01 10:33:03 AM PDT 24 Jul 01 10:33:21 AM PDT 24 1100978711 ps
T154 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3043382932 Jul 01 10:33:09 AM PDT 24 Jul 01 10:33:15 AM PDT 24 211022600 ps
T107 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2711559783 Jul 01 10:32:42 AM PDT 24 Jul 01 10:32:46 AM PDT 24 473705212 ps
T1034 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3987204153 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:39 AM PDT 24 104271458 ps
T1035 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.392641738 Jul 01 10:32:52 AM PDT 24 Jul 01 10:32:55 AM PDT 24 39099732 ps
T1036 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4062638271 Jul 01 10:32:50 AM PDT 24 Jul 01 10:32:51 AM PDT 24 45072749 ps
T1037 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3171720703 Jul 01 10:32:48 AM PDT 24 Jul 01 10:32:49 AM PDT 24 143135703 ps
T1038 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2928556691 Jul 01 10:32:36 AM PDT 24 Jul 01 10:32:40 AM PDT 24 231233729 ps
T1039 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3603465933 Jul 01 10:32:59 AM PDT 24 Jul 01 10:33:00 AM PDT 24 18703054 ps
T98 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1149378598 Jul 01 10:33:02 AM PDT 24 Jul 01 10:33:06 AM PDT 24 207355627 ps
T1040 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2004132295 Jul 01 10:32:51 AM PDT 24 Jul 01 10:32:56 AM PDT 24 58912088 ps
T75 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3975021388 Jul 01 10:32:30 AM PDT 24 Jul 01 10:32:32 AM PDT 24 28426664 ps
T1041 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.700484405 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:37 AM PDT 24 37493225 ps
T76 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3287961723 Jul 01 10:32:31 AM PDT 24 Jul 01 10:32:33 AM PDT 24 58567409 ps
T1042 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2135768456 Jul 01 10:33:06 AM PDT 24 Jul 01 10:33:08 AM PDT 24 14029715 ps
T1043 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.99836849 Jul 01 10:33:06 AM PDT 24 Jul 01 10:33:25 AM PDT 24 1520742955 ps
T1044 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.458648473 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:13 AM PDT 24 31663332 ps
T120 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1539462206 Jul 01 10:32:51 AM PDT 24 Jul 01 10:32:54 AM PDT 24 295819509 ps
T1045 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1072300140 Jul 01 10:32:28 AM PDT 24 Jul 01 10:32:53 AM PDT 24 6258201765 ps
T173 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.515178894 Jul 01 10:32:58 AM PDT 24 Jul 01 10:33:12 AM PDT 24 8569686528 ps
T1046 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2960383619 Jul 01 10:32:43 AM PDT 24 Jul 01 10:32:50 AM PDT 24 31979780 ps
T1047 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.979425038 Jul 01 10:33:00 AM PDT 24 Jul 01 10:33:01 AM PDT 24 18696776 ps
T1048 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1984043390 Jul 01 10:32:47 AM PDT 24 Jul 01 10:32:48 AM PDT 24 56399221 ps
T121 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1689532101 Jul 01 10:32:22 AM PDT 24 Jul 01 10:32:33 AM PDT 24 191128077 ps
T1049 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2358124821 Jul 01 10:32:38 AM PDT 24 Jul 01 10:32:39 AM PDT 24 42172142 ps
T122 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2897159678 Jul 01 10:32:36 AM PDT 24 Jul 01 10:32:39 AM PDT 24 337604157 ps
T1050 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2004328567 Jul 01 10:32:32 AM PDT 24 Jul 01 10:32:35 AM PDT 24 932426626 ps
T1051 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3768869469 Jul 01 10:32:56 AM PDT 24 Jul 01 10:33:00 AM PDT 24 480682583 ps
T1052 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.798668542 Jul 01 10:32:40 AM PDT 24 Jul 01 10:32:41 AM PDT 24 149186928 ps
T1053 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2588359654 Jul 01 10:32:39 AM PDT 24 Jul 01 10:32:42 AM PDT 24 79172585 ps
T102 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1223160730 Jul 01 10:32:57 AM PDT 24 Jul 01 10:32:59 AM PDT 24 42135709 ps
T108 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2974016825 Jul 01 10:32:57 AM PDT 24 Jul 01 10:33:00 AM PDT 24 160593717 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3093159717 Jul 01 10:32:31 AM PDT 24 Jul 01 10:32:46 AM PDT 24 2739624365 ps
T175 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3123812909 Jul 01 10:32:45 AM PDT 24 Jul 01 10:32:51 AM PDT 24 1952313244 ps
T123 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.361058273 Jul 01 10:32:27 AM PDT 24 Jul 01 10:32:30 AM PDT 24 27641642 ps
T1055 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2916378648 Jul 01 10:32:27 AM PDT 24 Jul 01 10:32:31 AM PDT 24 209168597 ps
T1056 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3649696258 Jul 01 10:32:36 AM PDT 24 Jul 01 10:32:39 AM PDT 24 26833313 ps
T1057 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.234194408 Jul 01 10:32:42 AM PDT 24 Jul 01 10:32:43 AM PDT 24 28378688 ps
T124 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3408629374 Jul 01 10:32:27 AM PDT 24 Jul 01 10:32:30 AM PDT 24 49713165 ps
T1058 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3650335078 Jul 01 10:33:06 AM PDT 24 Jul 01 10:33:07 AM PDT 24 46430872 ps
T1059 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2377243381 Jul 01 10:32:55 AM PDT 24 Jul 01 10:32:58 AM PDT 24 239564548 ps
T1060 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3192982484 Jul 01 10:32:49 AM PDT 24 Jul 01 10:32:51 AM PDT 24 15128224 ps
T1061 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3734089779 Jul 01 10:33:08 AM PDT 24 Jul 01 10:33:11 AM PDT 24 98818393 ps
T1062 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4224441079 Jul 01 10:32:37 AM PDT 24 Jul 01 10:32:46 AM PDT 24 2937973033 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3459321499 Jul 01 10:32:33 AM PDT 24 Jul 01 10:33:06 AM PDT 24 527640452 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1051142664 Jul 01 10:32:30 AM PDT 24 Jul 01 10:32:33 AM PDT 24 329480985 ps
T1065 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.456035323 Jul 01 10:32:36 AM PDT 24 Jul 01 10:32:37 AM PDT 24 13988713 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1131826299 Jul 01 10:32:30 AM PDT 24 Jul 01 10:32:47 AM PDT 24 765979033 ps
T1067 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.217523543 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:40 AM PDT 24 186870712 ps
T1068 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2686870062 Jul 01 10:33:01 AM PDT 24 Jul 01 10:33:03 AM PDT 24 36749135 ps
T171 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.276921597 Jul 01 10:33:03 AM PDT 24 Jul 01 10:33:22 AM PDT 24 322821777 ps
T1069 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1011227304 Jul 01 10:32:27 AM PDT 24 Jul 01 10:32:28 AM PDT 24 16256888 ps
T172 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.683859226 Jul 01 10:32:41 AM PDT 24 Jul 01 10:33:03 AM PDT 24 2104142044 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3607913459 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:38 AM PDT 24 255290310 ps
T1071 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.224399174 Jul 01 10:32:58 AM PDT 24 Jul 01 10:32:59 AM PDT 24 12103924 ps
T1072 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.738455747 Jul 01 10:32:56 AM PDT 24 Jul 01 10:33:10 AM PDT 24 2394516925 ps
T1073 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1180809880 Jul 01 10:32:29 AM PDT 24 Jul 01 10:32:30 AM PDT 24 141380788 ps
T1074 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4020706878 Jul 01 10:32:49 AM PDT 24 Jul 01 10:32:51 AM PDT 24 18035926 ps
T97 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2282505417 Jul 01 10:32:39 AM PDT 24 Jul 01 10:32:45 AM PDT 24 181434782 ps
T1075 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4289338709 Jul 01 10:32:29 AM PDT 24 Jul 01 10:32:31 AM PDT 24 22213003 ps
T1076 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.157452136 Jul 01 10:32:32 AM PDT 24 Jul 01 10:32:42 AM PDT 24 440411593 ps
T103 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1849733570 Jul 01 10:32:25 AM PDT 24 Jul 01 10:32:29 AM PDT 24 222608771 ps
T1077 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1266557575 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:39 AM PDT 24 70915350 ps
T1078 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1187336539 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:37 AM PDT 24 35969358 ps
T1079 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.354780008 Jul 01 10:32:42 AM PDT 24 Jul 01 10:32:46 AM PDT 24 153787330 ps
T1080 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4193451510 Jul 01 10:33:06 AM PDT 24 Jul 01 10:33:08 AM PDT 24 13876167 ps
T1081 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1340135029 Jul 01 10:32:38 AM PDT 24 Jul 01 10:32:43 AM PDT 24 903563552 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3561464042 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:48 AM PDT 24 749984444 ps
T1083 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2337849822 Jul 01 10:32:54 AM PDT 24 Jul 01 10:32:56 AM PDT 24 39585207 ps
T1084 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.831869259 Jul 01 10:32:28 AM PDT 24 Jul 01 10:32:29 AM PDT 24 26781925 ps
T1085 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.122864819 Jul 01 10:33:04 AM PDT 24 Jul 01 10:33:05 AM PDT 24 145440844 ps
T174 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.880734779 Jul 01 10:32:32 AM PDT 24 Jul 01 10:32:53 AM PDT 24 821069079 ps
T1086 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.651585057 Jul 01 10:32:54 AM PDT 24 Jul 01 10:32:56 AM PDT 24 895500325 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3079094857 Jul 01 10:32:27 AM PDT 24 Jul 01 10:32:28 AM PDT 24 31793668 ps
T77 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1825569836 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:37 AM PDT 24 60089475 ps
T1088 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1567778287 Jul 01 10:33:10 AM PDT 24 Jul 01 10:33:19 AM PDT 24 5553460756 ps
T1089 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2108326309 Jul 01 10:33:07 AM PDT 24 Jul 01 10:33:09 AM PDT 24 46598140 ps
T1090 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2398896131 Jul 01 10:32:30 AM PDT 24 Jul 01 10:32:33 AM PDT 24 457505390 ps
T1091 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3802285534 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:44 AM PDT 24 1177746576 ps
T1092 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1258586202 Jul 01 10:32:29 AM PDT 24 Jul 01 10:32:33 AM PDT 24 472182819 ps
T106 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3640232789 Jul 01 10:32:31 AM PDT 24 Jul 01 10:32:35 AM PDT 24 54828147 ps
T1093 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3197928387 Jul 01 10:32:54 AM PDT 24 Jul 01 10:32:59 AM PDT 24 898309430 ps
T1094 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.348085488 Jul 01 10:32:58 AM PDT 24 Jul 01 10:33:12 AM PDT 24 868567032 ps
T1095 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1547647952 Jul 01 10:32:56 AM PDT 24 Jul 01 10:33:00 AM PDT 24 3082288566 ps
T1096 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3221965124 Jul 01 10:32:30 AM PDT 24 Jul 01 10:32:33 AM PDT 24 41587832 ps
T1097 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3555445921 Jul 01 10:33:08 AM PDT 24 Jul 01 10:33:10 AM PDT 24 155072022 ps
T1098 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2475369301 Jul 01 10:32:51 AM PDT 24 Jul 01 10:32:52 AM PDT 24 12838655 ps
T1099 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2947551304 Jul 01 10:32:55 AM PDT 24 Jul 01 10:32:59 AM PDT 24 142906541 ps
T1100 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2135161665 Jul 01 10:32:51 AM PDT 24 Jul 01 10:32:52 AM PDT 24 66946645 ps
T1101 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2651925346 Jul 01 10:32:42 AM PDT 24 Jul 01 10:32:49 AM PDT 24 100461501 ps
T1102 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.943789562 Jul 01 10:32:37 AM PDT 24 Jul 01 10:32:42 AM PDT 24 876163732 ps
T78 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.60319865 Jul 01 10:32:28 AM PDT 24 Jul 01 10:32:30 AM PDT 24 23757076 ps
T1103 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.409869677 Jul 01 10:32:59 AM PDT 24 Jul 01 10:33:07 AM PDT 24 534404801 ps
T1104 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.782928261 Jul 01 10:32:52 AM PDT 24 Jul 01 10:32:55 AM PDT 24 117986255 ps
T1105 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.889862908 Jul 01 10:32:59 AM PDT 24 Jul 01 10:33:02 AM PDT 24 85566915 ps
T1106 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1722147837 Jul 01 10:32:55 AM PDT 24 Jul 01 10:32:58 AM PDT 24 83590635 ps
T1107 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1278349877 Jul 01 10:32:51 AM PDT 24 Jul 01 10:32:52 AM PDT 24 14124073 ps
T1108 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3566438250 Jul 01 10:32:58 AM PDT 24 Jul 01 10:32:58 AM PDT 24 22026084 ps
T1109 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.698850949 Jul 01 10:32:56 AM PDT 24 Jul 01 10:33:02 AM PDT 24 28336676 ps
T1110 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2826611334 Jul 01 10:33:04 AM PDT 24 Jul 01 10:33:07 AM PDT 24 839161167 ps
T1111 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3596177592 Jul 01 10:32:26 AM PDT 24 Jul 01 10:32:28 AM PDT 24 57546684 ps
T1112 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1659607952 Jul 01 10:32:54 AM PDT 24 Jul 01 10:32:59 AM PDT 24 476153359 ps
T1113 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2506442203 Jul 01 10:33:06 AM PDT 24 Jul 01 10:33:08 AM PDT 24 11763426 ps
T1114 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2400799664 Jul 01 10:32:48 AM PDT 24 Jul 01 10:32:50 AM PDT 24 30108328 ps
T1115 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2202116020 Jul 01 10:32:55 AM PDT 24 Jul 01 10:32:57 AM PDT 24 59893366 ps
T1116 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1104113690 Jul 01 10:32:24 AM PDT 24 Jul 01 10:32:25 AM PDT 24 20477279 ps
T1117 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1989144917 Jul 01 10:33:06 AM PDT 24 Jul 01 10:33:07 AM PDT 24 35131106 ps
T1118 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1188718813 Jul 01 10:32:52 AM PDT 24 Jul 01 10:32:56 AM PDT 24 162340295 ps
T1119 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3728982961 Jul 01 10:33:02 AM PDT 24 Jul 01 10:33:04 AM PDT 24 21221077 ps
T1120 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4210397783 Jul 01 10:32:32 AM PDT 24 Jul 01 10:32:34 AM PDT 24 74979866 ps
T1121 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1430243554 Jul 01 10:32:27 AM PDT 24 Jul 01 10:32:29 AM PDT 24 39304029 ps
T1122 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1914773751 Jul 01 10:32:31 AM PDT 24 Jul 01 10:32:35 AM PDT 24 76005855 ps
T1123 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2799897657 Jul 01 10:32:43 AM PDT 24 Jul 01 10:32:45 AM PDT 24 259674171 ps
T1124 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2037792464 Jul 01 10:32:35 AM PDT 24 Jul 01 10:32:38 AM PDT 24 135380079 ps
T1125 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1334224925 Jul 01 10:32:54 AM PDT 24 Jul 01 10:32:56 AM PDT 24 32985391 ps
T1126 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.609384006 Jul 01 10:33:04 AM PDT 24 Jul 01 10:33:08 AM PDT 24 230631598 ps
T1127 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.510603183 Jul 01 10:33:01 AM PDT 24 Jul 01 10:33:03 AM PDT 24 96051820 ps
T1128 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1389095818 Jul 01 10:32:43 AM PDT 24 Jul 01 10:32:46 AM PDT 24 118216574 ps
T1129 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1789579368 Jul 01 10:32:57 AM PDT 24 Jul 01 10:33:01 AM PDT 24 132588953 ps
T1130 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3454599903 Jul 01 10:32:48 AM PDT 24 Jul 01 10:32:49 AM PDT 24 25648500 ps
T1131 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.822488854 Jul 01 10:32:37 AM PDT 24 Jul 01 10:32:39 AM PDT 24 87875552 ps

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1279085855
Short name T2
Test name
Test status
Simulation time 1642469608 ps
CPU time 15.05 seconds
Started Jul 01 12:50:27 PM PDT 24
Finished Jul 01 12:50:44 PM PDT 24
Peak memory 222168 kb
Host smart-6f5368b0-55ff-4389-a819-29719cbb20ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1279085855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1279085855
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.368220540
Short name T17
Test name
Test status
Simulation time 53321043691 ps
CPU time 447.77 seconds
Started Jul 01 12:48:05 PM PDT 24
Finished Jul 01 12:55:34 PM PDT 24
Peak memory 249304 kb
Host smart-eafb1488-e5cf-409a-85d7-6966ce76a580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368220540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.368220540
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3641673772
Short name T27
Test name
Test status
Simulation time 44950434193 ps
CPU time 154.27 seconds
Started Jul 01 12:48:50 PM PDT 24
Finished Jul 01 12:51:26 PM PDT 24
Peak memory 257056 kb
Host smart-d7237a0e-686d-4a93-ad37-c50ec0cdfa0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641673772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3641673772
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2199497939
Short name T95
Test name
Test status
Simulation time 1409869275 ps
CPU time 15.63 seconds
Started Jul 01 10:33:05 AM PDT 24
Finished Jul 01 10:33:21 AM PDT 24
Peak memory 215556 kb
Host smart-9b2ff445-2fc9-49d4-ba8c-a6cb321bec98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199497939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2199497939
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2568875022
Short name T30
Test name
Test status
Simulation time 36660163634 ps
CPU time 313.16 seconds
Started Jul 01 12:49:07 PM PDT 24
Finished Jul 01 12:54:23 PM PDT 24
Peak memory 256520 kb
Host smart-b554261f-bc41-446c-aadd-619194390d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568875022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2568875022
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2402588474
Short name T33
Test name
Test status
Simulation time 110744664980 ps
CPU time 585.46 seconds
Started Jul 01 12:50:21 PM PDT 24
Finished Jul 01 01:00:09 PM PDT 24
Peak memory 265804 kb
Host smart-69d72f5a-37f9-46a0-97f5-85e81ad2060a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402588474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2402588474
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.383982030
Short name T28
Test name
Test status
Simulation time 50597548518 ps
CPU time 489.35 seconds
Started Jul 01 12:48:59 PM PDT 24
Finished Jul 01 12:57:10 PM PDT 24
Peak memory 255288 kb
Host smart-dea2229b-0681-4097-b889-abf9c498744b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383982030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.383982030
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2980816791
Short name T66
Test name
Test status
Simulation time 32705010 ps
CPU time 0.75 seconds
Started Jul 01 12:45:55 PM PDT 24
Finished Jul 01 12:45:57 PM PDT 24
Peak memory 216092 kb
Host smart-09a17320-c909-4317-ac5c-1f4957ba73c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980816791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2980816791
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3016850370
Short name T206
Test name
Test status
Simulation time 241928024828 ps
CPU time 681.38 seconds
Started Jul 01 12:50:41 PM PDT 24
Finished Jul 01 01:02:04 PM PDT 24
Peak memory 281420 kb
Host smart-754ff5f2-4089-4b0a-b2ca-f025bcf6ea91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016850370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3016850370
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2782919031
Short name T188
Test name
Test status
Simulation time 49486684271 ps
CPU time 458.13 seconds
Started Jul 01 12:50:41 PM PDT 24
Finished Jul 01 12:58:21 PM PDT 24
Peak memory 255260 kb
Host smart-930fc668-61ce-4422-bed7-a25f75e323f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782919031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2782919031
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2718560582
Short name T12
Test name
Test status
Simulation time 1010773801 ps
CPU time 6.86 seconds
Started Jul 01 12:46:45 PM PDT 24
Finished Jul 01 12:46:53 PM PDT 24
Peak memory 216232 kb
Host smart-a991e8ff-e751-4d52-bbd5-4f45ad9fcf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718560582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2718560582
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3915354718
Short name T18
Test name
Test status
Simulation time 304052955680 ps
CPU time 545.64 seconds
Started Jul 01 12:47:47 PM PDT 24
Finished Jul 01 12:56:53 PM PDT 24
Peak memory 265544 kb
Host smart-ba320455-ef89-48b3-8cc7-50453cc5ed8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915354718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3915354718
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4024479312
Short name T32
Test name
Test status
Simulation time 44237764216 ps
CPU time 448.43 seconds
Started Jul 01 12:48:27 PM PDT 24
Finished Jul 01 12:55:57 PM PDT 24
Peak memory 268660 kb
Host smart-690a2073-55f0-4947-82d6-fa292b0009be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024479312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4024479312
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2682935604
Short name T22
Test name
Test status
Simulation time 118938580 ps
CPU time 1.24 seconds
Started Jul 01 12:46:18 PM PDT 24
Finished Jul 01 12:46:20 PM PDT 24
Peak memory 236112 kb
Host smart-02ad7758-349a-4d6d-8ef9-6d999c9e38db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682935604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2682935604
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1135728423
Short name T185
Test name
Test status
Simulation time 38401124481 ps
CPU time 454.84 seconds
Started Jul 01 12:46:36 PM PDT 24
Finished Jul 01 12:54:12 PM PDT 24
Peak memory 268128 kb
Host smart-ef759d73-992f-491a-8dc6-c2f9f2099ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135728423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1135728423
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1612322919
Short name T93
Test name
Test status
Simulation time 93025522 ps
CPU time 2.9 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:55 AM PDT 24
Peak memory 215952 kb
Host smart-c27af824-e66b-4cc4-a17b-7d5308df7590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612322919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1612322919
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3132232918
Short name T58
Test name
Test status
Simulation time 50228773837 ps
CPU time 400.52 seconds
Started Jul 01 12:50:39 PM PDT 24
Finished Jul 01 12:57:22 PM PDT 24
Peak memory 283620 kb
Host smart-21962b34-e8bb-4502-8a8a-68a89a649eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132232918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3132232918
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2365969721
Short name T117
Test name
Test status
Simulation time 581675619 ps
CPU time 1.88 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:37 AM PDT 24
Peak memory 207368 kb
Host smart-00b00225-0adf-4ed7-829a-e226924b24fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365969721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
365969721
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1746460145
Short name T269
Test name
Test status
Simulation time 70458849561 ps
CPU time 529.45 seconds
Started Jul 01 12:49:43 PM PDT 24
Finished Jul 01 12:58:34 PM PDT 24
Peak memory 264740 kb
Host smart-94013905-3ce5-4f2e-a688-21505fe2e841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746460145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1746460145
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2458157547
Short name T204
Test name
Test status
Simulation time 56181484334 ps
CPU time 250.7 seconds
Started Jul 01 12:47:58 PM PDT 24
Finished Jul 01 12:52:09 PM PDT 24
Peak memory 253552 kb
Host smart-5b337c63-f4de-4eba-a099-5c945e2627ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458157547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2458157547
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3734850653
Short name T135
Test name
Test status
Simulation time 186277332515 ps
CPU time 307.35 seconds
Started Jul 01 12:46:17 PM PDT 24
Finished Jul 01 12:51:25 PM PDT 24
Peak memory 251540 kb
Host smart-c25439d4-1009-4610-ae48-c0d2858cb55d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734850653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3734850653
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3494790866
Short name T177
Test name
Test status
Simulation time 50373692828 ps
CPU time 322.63 seconds
Started Jul 01 12:48:16 PM PDT 24
Finished Jul 01 12:53:39 PM PDT 24
Peak memory 268184 kb
Host smart-54a9a403-f383-492c-bcfd-98ed87b33d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494790866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3494790866
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2399151591
Short name T236
Test name
Test status
Simulation time 58102809328 ps
CPU time 394.09 seconds
Started Jul 01 12:50:31 PM PDT 24
Finished Jul 01 12:57:07 PM PDT 24
Peak memory 263256 kb
Host smart-c8ae3e30-2fc3-411e-9472-5b82d6d2d6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399151591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2399151591
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1469908247
Short name T34
Test name
Test status
Simulation time 146825850912 ps
CPU time 400.44 seconds
Started Jul 01 12:47:48 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 256120 kb
Host smart-340cf91b-0a79-40d4-a03b-cd071dd4c26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469908247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1469908247
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1293775739
Short name T144
Test name
Test status
Simulation time 994658438 ps
CPU time 17.87 seconds
Started Jul 01 12:49:16 PM PDT 24
Finished Jul 01 12:49:35 PM PDT 24
Peak memory 224508 kb
Host smart-cfb2c557-b167-4b4d-9764-91c833fb9390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293775739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1293775739
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1530408572
Short name T49
Test name
Test status
Simulation time 7022764509 ps
CPU time 107.95 seconds
Started Jul 01 12:50:42 PM PDT 24
Finished Jul 01 12:52:31 PM PDT 24
Peak memory 262464 kb
Host smart-82a86b0a-7364-474f-8c5f-eba7d9b40e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530408572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1530408572
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3389481000
Short name T249
Test name
Test status
Simulation time 17960470571 ps
CPU time 191.17 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:51:45 PM PDT 24
Peak memory 252880 kb
Host smart-08ca64b9-9126-4af2-8e9d-f1aa1f7518e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389481000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3389481000
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3788095778
Short name T62
Test name
Test status
Simulation time 45056441 ps
CPU time 0.75 seconds
Started Jul 01 12:48:13 PM PDT 24
Finished Jul 01 12:48:15 PM PDT 24
Peak memory 205560 kb
Host smart-695c0314-3cef-42fa-9d89-90f19321fc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788095778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3788095778
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.559902958
Short name T94
Test name
Test status
Simulation time 2450013638 ps
CPU time 19.48 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:54 AM PDT 24
Peak memory 215704 kb
Host smart-059723e3-2ef1-4475-93d7-84db10bbbe0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559902958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.559902958
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2282505417
Short name T97
Test name
Test status
Simulation time 181434782 ps
CPU time 5.3 seconds
Started Jul 01 10:32:39 AM PDT 24
Finished Jul 01 10:32:45 AM PDT 24
Peak memory 215800 kb
Host smart-4554fbc5-d420-4394-a439-dfe1b4e2100b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282505417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2282505417
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.683859226
Short name T172
Test name
Test status
Simulation time 2104142044 ps
CPU time 21.8 seconds
Started Jul 01 10:32:41 AM PDT 24
Finished Jul 01 10:33:03 AM PDT 24
Peak memory 215596 kb
Host smart-bfa5b877-c55d-464a-ae5f-99f35757a6b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683859226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.683859226
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1417582967
Short name T42
Test name
Test status
Simulation time 2993507988 ps
CPU time 63.22 seconds
Started Jul 01 12:46:08 PM PDT 24
Finished Jul 01 12:47:12 PM PDT 24
Peak memory 252448 kb
Host smart-b26302e4-a1dd-47bc-a6e2-f8aa8a153fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417582967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1417582967
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2174805595
Short name T247
Test name
Test status
Simulation time 9019726419 ps
CPU time 96.08 seconds
Started Jul 01 12:49:30 PM PDT 24
Finished Jul 01 12:51:09 PM PDT 24
Peak memory 265248 kb
Host smart-4f31df63-0998-4a54-b8b4-fd90caaf187e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174805595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2174805595
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1805626524
Short name T53
Test name
Test status
Simulation time 285285230966 ps
CPU time 618.25 seconds
Started Jul 01 12:50:10 PM PDT 24
Finished Jul 01 01:00:29 PM PDT 24
Peak memory 268588 kb
Host smart-ad251b09-c4ea-4ea9-9b1e-dc7a65021b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805626524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1805626524
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.964118625
Short name T186
Test name
Test status
Simulation time 135986734305 ps
CPU time 242.24 seconds
Started Jul 01 12:47:00 PM PDT 24
Finished Jul 01 12:51:04 PM PDT 24
Peak memory 261300 kb
Host smart-b75b5773-51c5-4764-9ebb-2059b8795c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964118625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.964118625
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.761663501
Short name T41
Test name
Test status
Simulation time 213259064069 ps
CPU time 383.76 seconds
Started Jul 01 12:47:17 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 256292 kb
Host smart-3f291b01-0e92-4ffe-a1a6-3308e3975d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761663501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.761663501
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1116258130
Short name T1003
Test name
Test status
Simulation time 104811883650 ps
CPU time 834.56 seconds
Started Jul 01 12:47:46 PM PDT 24
Finished Jul 01 01:01:41 PM PDT 24
Peak memory 283904 kb
Host smart-4003276f-65a6-456b-ad0d-12e6f1649233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116258130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1116258130
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4103331738
Short name T984
Test name
Test status
Simulation time 246828592568 ps
CPU time 441.54 seconds
Started Jul 01 12:49:22 PM PDT 24
Finished Jul 01 12:56:49 PM PDT 24
Peak memory 257368 kb
Host smart-10f87857-bd36-499e-8f24-fa7227764ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103331738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4103331738
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3150963372
Short name T291
Test name
Test status
Simulation time 469331407 ps
CPU time 11.83 seconds
Started Jul 01 12:49:40 PM PDT 24
Finished Jul 01 12:49:53 PM PDT 24
Peak memory 224460 kb
Host smart-c89e2ceb-e405-4287-a595-050aad740bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150963372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3150963372
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3746840310
Short name T274
Test name
Test status
Simulation time 10284922610 ps
CPU time 132.7 seconds
Started Jul 01 12:48:53 PM PDT 24
Finished Jul 01 12:51:06 PM PDT 24
Peak memory 257376 kb
Host smart-3c57e55a-7c62-4757-8ea6-b7eba1a20bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746840310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3746840310
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.815590055
Short name T261
Test name
Test status
Simulation time 3194593647 ps
CPU time 36.15 seconds
Started Jul 01 12:47:38 PM PDT 24
Finished Jul 01 12:48:16 PM PDT 24
Peak memory 236920 kb
Host smart-e0f1b2c5-c970-4162-994a-a2cd8fb4a45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815590055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.815590055
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2802631310
Short name T584
Test name
Test status
Simulation time 18354995912 ps
CPU time 136.41 seconds
Started Jul 01 12:47:56 PM PDT 24
Finished Jul 01 12:50:13 PM PDT 24
Peak memory 253956 kb
Host smart-ccd11dc8-ef49-459b-8dac-af0838ebe4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802631310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2802631310
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.555875114
Short name T244
Test name
Test status
Simulation time 28908149712 ps
CPU time 344.95 seconds
Started Jul 01 12:50:13 PM PDT 24
Finished Jul 01 12:55:59 PM PDT 24
Peak memory 266532 kb
Host smart-e11512d3-3961-43dc-8326-194fa003e8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555875114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.555875114
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1649445235
Short name T88
Test name
Test status
Simulation time 11237035070 ps
CPU time 52.5 seconds
Started Jul 01 12:48:03 PM PDT 24
Finished Jul 01 12:48:57 PM PDT 24
Peak memory 232816 kb
Host smart-f152f4a6-0789-48a8-ab5f-fff1a950706b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649445235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1649445235
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_intercept.558921139
Short name T190
Test name
Test status
Simulation time 278789846 ps
CPU time 5.82 seconds
Started Jul 01 12:47:59 PM PDT 24
Finished Jul 01 12:48:05 PM PDT 24
Peak memory 232656 kb
Host smart-2b03dab9-e731-4df7-b736-29bfc68da28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558921139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.558921139
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.60319865
Short name T78
Test name
Test status
Simulation time 23757076 ps
CPU time 1.37 seconds
Started Jul 01 10:32:28 AM PDT 24
Finished Jul 01 10:32:30 AM PDT 24
Peak memory 216532 kb
Host smart-7eb5e081-6678-434f-9b90-6734b53b61d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60319865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
hw_reset.60319865
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.609384006
Short name T1126
Test name
Test status
Simulation time 230631598 ps
CPU time 3.6 seconds
Started Jul 01 10:33:04 AM PDT 24
Finished Jul 01 10:33:08 AM PDT 24
Peak memory 215900 kb
Host smart-990a4fb5-dd3d-4542-bf38-dbe78478c80e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609384006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.609384006
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2192742092
Short name T20
Test name
Test status
Simulation time 20812832764 ps
CPU time 74.68 seconds
Started Jul 01 12:47:40 PM PDT 24
Finished Jul 01 12:48:56 PM PDT 24
Peak memory 233868 kb
Host smart-f0f04a88-5b6d-44d9-b8fd-ada62a7c4498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192742092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2192742092
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3802285534
Short name T1091
Test name
Test status
Simulation time 1177746576 ps
CPU time 8.53 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:44 AM PDT 24
Peak memory 207252 kb
Host smart-d9e570f8-132d-4eb8-a68e-6c693bc1ec1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802285534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3802285534
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1689532101
Short name T121
Test name
Test status
Simulation time 191128077 ps
CPU time 10.63 seconds
Started Jul 01 10:32:22 AM PDT 24
Finished Jul 01 10:32:33 AM PDT 24
Peak memory 207216 kb
Host smart-4e964c85-a0de-4cdd-bb76-db9b8aec3398
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689532101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1689532101
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3987204153
Short name T1034
Test name
Test status
Simulation time 104271458 ps
CPU time 3.77 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:39 AM PDT 24
Peak memory 217352 kb
Host smart-f98ec1bc-0e02-4606-b81f-2569cea8b394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987204153 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3987204153
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1104113690
Short name T1116
Test name
Test status
Simulation time 20477279 ps
CPU time 0.7 seconds
Started Jul 01 10:32:24 AM PDT 24
Finished Jul 01 10:32:25 AM PDT 24
Peak memory 204040 kb
Host smart-a0d1de78-b2bd-432a-b573-b32829ce27e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104113690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
104113690
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3408629374
Short name T124
Test name
Test status
Simulation time 49713165 ps
CPU time 1.75 seconds
Started Jul 01 10:32:27 AM PDT 24
Finished Jul 01 10:32:30 AM PDT 24
Peak memory 215556 kb
Host smart-aa29b1f3-4a0a-4648-849f-dcd44ba85934
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408629374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3408629374
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1187336539
Short name T1078
Test name
Test status
Simulation time 35969358 ps
CPU time 0.66 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:37 AM PDT 24
Peak memory 203776 kb
Host smart-5aacfd95-f239-47d3-a484-f6b518db31fc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187336539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1187336539
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.217523543
Short name T1067
Test name
Test status
Simulation time 186870712 ps
CPU time 3.86 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:40 AM PDT 24
Peak memory 215592 kb
Host smart-f973fcb5-31e5-4b09-9b4f-0fe098afb2db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217523543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.217523543
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1153989182
Short name T65
Test name
Test status
Simulation time 108536902 ps
CPU time 2.68 seconds
Started Jul 01 10:32:28 AM PDT 24
Finished Jul 01 10:32:31 AM PDT 24
Peak memory 215732 kb
Host smart-2e6310aa-79b6-45b7-b473-5ed831f4172a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153989182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
153989182
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3093159717
Short name T1054
Test name
Test status
Simulation time 2739624365 ps
CPU time 15.06 seconds
Started Jul 01 10:32:31 AM PDT 24
Finished Jul 01 10:32:46 AM PDT 24
Peak memory 217060 kb
Host smart-c9461061-287e-4560-937b-744f8cbdba9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093159717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3093159717
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.157452136
Short name T1076
Test name
Test status
Simulation time 440411593 ps
CPU time 8.99 seconds
Started Jul 01 10:32:32 AM PDT 24
Finished Jul 01 10:32:42 AM PDT 24
Peak memory 207272 kb
Host smart-a34443fd-bc41-4853-8a7c-108103e06a99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157452136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.157452136
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3459321499
Short name T1063
Test name
Test status
Simulation time 527640452 ps
CPU time 32.17 seconds
Started Jul 01 10:32:33 AM PDT 24
Finished Jul 01 10:33:06 AM PDT 24
Peak memory 207352 kb
Host smart-1bf29d96-57c4-4ece-8140-ad6e192c911e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459321499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3459321499
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1430243554
Short name T1121
Test name
Test status
Simulation time 39304029 ps
CPU time 1.25 seconds
Started Jul 01 10:32:27 AM PDT 24
Finished Jul 01 10:32:29 AM PDT 24
Peak memory 207232 kb
Host smart-b5c68991-05dd-4285-b087-ae7a4dbbe461
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430243554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1430243554
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2916378648
Short name T1055
Test name
Test status
Simulation time 209168597 ps
CPU time 3.36 seconds
Started Jul 01 10:32:27 AM PDT 24
Finished Jul 01 10:32:31 AM PDT 24
Peak memory 218100 kb
Host smart-a788d7a1-f09b-4e85-a96c-ae79fbd58b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916378648 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2916378648
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3749807220
Short name T110
Test name
Test status
Simulation time 366812948 ps
CPU time 2.78 seconds
Started Jul 01 10:32:29 AM PDT 24
Finished Jul 01 10:32:33 AM PDT 24
Peak memory 215408 kb
Host smart-eacd2520-e964-4410-875f-816d7df24932
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749807220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
749807220
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1180809880
Short name T1073
Test name
Test status
Simulation time 141380788 ps
CPU time 0.73 seconds
Started Jul 01 10:32:29 AM PDT 24
Finished Jul 01 10:32:30 AM PDT 24
Peak memory 204428 kb
Host smart-6aed28af-ffd4-492f-b470-4a788b11b6d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180809880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
180809880
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2061723268
Short name T115
Test name
Test status
Simulation time 59537263 ps
CPU time 1.65 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:37 AM PDT 24
Peak memory 215604 kb
Host smart-9b662bea-196b-457e-90ee-952d65203a5e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061723268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2061723268
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4219714225
Short name T1012
Test name
Test status
Simulation time 41303785 ps
CPU time 0.65 seconds
Started Jul 01 10:32:32 AM PDT 24
Finished Jul 01 10:32:33 AM PDT 24
Peak memory 203824 kb
Host smart-4d2dbcc8-643b-4845-bab5-9b6a1040b238
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219714225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4219714225
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3596177592
Short name T1111
Test name
Test status
Simulation time 57546684 ps
CPU time 1.88 seconds
Started Jul 01 10:32:26 AM PDT 24
Finished Jul 01 10:32:28 AM PDT 24
Peak memory 215500 kb
Host smart-6576d6d2-f640-48d9-9e2d-f67868b62c54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596177592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3596177592
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1849733570
Short name T103
Test name
Test status
Simulation time 222608771 ps
CPU time 3.18 seconds
Started Jul 01 10:32:25 AM PDT 24
Finished Jul 01 10:32:29 AM PDT 24
Peak memory 215732 kb
Host smart-e852ab2b-4894-4dcd-812c-075449228865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849733570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
849733570
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2108326309
Short name T1089
Test name
Test status
Simulation time 46598140 ps
CPU time 1.56 seconds
Started Jul 01 10:33:07 AM PDT 24
Finished Jul 01 10:33:09 AM PDT 24
Peak memory 215588 kb
Host smart-a3b43dfc-0f3f-46ee-945c-6bc26e75a1eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108326309 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2108326309
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1553705716
Short name T114
Test name
Test status
Simulation time 157229790 ps
CPU time 1.49 seconds
Started Jul 01 10:32:49 AM PDT 24
Finished Jul 01 10:32:51 AM PDT 24
Peak memory 207272 kb
Host smart-e59ea7cb-5727-4d56-b232-26c41ee25be1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553705716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1553705716
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2358124821
Short name T1049
Test name
Test status
Simulation time 42172142 ps
CPU time 0.74 seconds
Started Jul 01 10:32:38 AM PDT 24
Finished Jul 01 10:32:39 AM PDT 24
Peak memory 204420 kb
Host smart-6e7445f5-d010-41d9-b426-590a0a32be9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358124821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2358124821
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1694720112
Short name T1028
Test name
Test status
Simulation time 104697560 ps
CPU time 2.88 seconds
Started Jul 01 10:32:40 AM PDT 24
Finished Jul 01 10:32:44 AM PDT 24
Peak memory 215576 kb
Host smart-50615ad2-0f1d-42e2-afe1-6a4e9b1aab2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694720112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1694720112
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1149378598
Short name T98
Test name
Test status
Simulation time 207355627 ps
CPU time 3.84 seconds
Started Jul 01 10:33:02 AM PDT 24
Finished Jul 01 10:33:06 AM PDT 24
Peak memory 215980 kb
Host smart-c9b6c2d4-a907-482a-a130-724c55326469
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149378598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1149378598
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.738455747
Short name T1072
Test name
Test status
Simulation time 2394516925 ps
CPU time 13.25 seconds
Started Jul 01 10:32:56 AM PDT 24
Finished Jul 01 10:33:10 AM PDT 24
Peak memory 215552 kb
Host smart-2c742849-95e3-4da4-960f-cf007b89f569
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738455747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.738455747
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3465052498
Short name T104
Test name
Test status
Simulation time 659181611 ps
CPU time 2.71 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:33:13 AM PDT 24
Peak memory 217296 kb
Host smart-47a877a7-0829-4681-b819-2033afb2584e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465052498 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3465052498
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2686870062
Short name T1068
Test name
Test status
Simulation time 36749135 ps
CPU time 1.26 seconds
Started Jul 01 10:33:01 AM PDT 24
Finished Jul 01 10:33:03 AM PDT 24
Peak memory 207260 kb
Host smart-d75db115-1a6d-48ca-b6fe-5a355381b24b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686870062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2686870062
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2400799664
Short name T1114
Test name
Test status
Simulation time 30108328 ps
CPU time 0.67 seconds
Started Jul 01 10:32:48 AM PDT 24
Finished Jul 01 10:32:50 AM PDT 24
Peak memory 204408 kb
Host smart-bb57ea51-ecbf-4119-8bb7-ca242d7cd6df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400799664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2400799664
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.651585057
Short name T1086
Test name
Test status
Simulation time 895500325 ps
CPU time 1.72 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:32:56 AM PDT 24
Peak memory 215748 kb
Host smart-6c6182cb-226c-4fa5-be78-2acb201242d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651585057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.651585057
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.276921597
Short name T171
Test name
Test status
Simulation time 322821777 ps
CPU time 19.12 seconds
Started Jul 01 10:33:03 AM PDT 24
Finished Jul 01 10:33:22 AM PDT 24
Peak memory 215680 kb
Host smart-61d55e4f-61c4-4dc9-98af-26c90aeb6547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276921597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.276921597
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2947551304
Short name T1099
Test name
Test status
Simulation time 142906541 ps
CPU time 3.37 seconds
Started Jul 01 10:32:55 AM PDT 24
Finished Jul 01 10:32:59 AM PDT 24
Peak memory 217264 kb
Host smart-af5d81bc-3771-475e-bab6-06f72f7feb73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947551304 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2947551304
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1722147837
Short name T1106
Test name
Test status
Simulation time 83590635 ps
CPU time 2.34 seconds
Started Jul 01 10:32:55 AM PDT 24
Finished Jul 01 10:32:58 AM PDT 24
Peak memory 215436 kb
Host smart-b56f1b1c-eb9f-4c2f-ab0d-53a250b7979c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722147837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1722147837
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.234194408
Short name T1057
Test name
Test status
Simulation time 28378688 ps
CPU time 0.76 seconds
Started Jul 01 10:32:42 AM PDT 24
Finished Jul 01 10:32:43 AM PDT 24
Peak memory 204132 kb
Host smart-47f58199-b2d5-47f9-a190-80598ebabb52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234194408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.234194408
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1573698307
Short name T1026
Test name
Test status
Simulation time 61725307 ps
CPU time 3.96 seconds
Started Jul 01 10:32:58 AM PDT 24
Finished Jul 01 10:33:03 AM PDT 24
Peak memory 215596 kb
Host smart-421c70ee-ab99-4426-b4bd-16d5f37eff52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573698307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1573698307
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1174426835
Short name T92
Test name
Test status
Simulation time 434355202 ps
CPU time 2.74 seconds
Started Jul 01 10:32:39 AM PDT 24
Finished Jul 01 10:32:42 AM PDT 24
Peak memory 215688 kb
Host smart-dbd76e80-b073-4734-92fc-21f0e9d4fcfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174426835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1174426835
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.883804406
Short name T170
Test name
Test status
Simulation time 1100978711 ps
CPU time 17.57 seconds
Started Jul 01 10:33:03 AM PDT 24
Finished Jul 01 10:33:21 AM PDT 24
Peak memory 215648 kb
Host smart-93e3e75b-8253-4923-b53c-83c13d23992f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883804406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.883804406
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.392641738
Short name T1035
Test name
Test status
Simulation time 39099732 ps
CPU time 2.57 seconds
Started Jul 01 10:32:52 AM PDT 24
Finished Jul 01 10:32:55 AM PDT 24
Peak memory 216716 kb
Host smart-72f04e12-a6fc-4576-a1ac-580f3c17f3dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392641738 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.392641738
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3728982961
Short name T1119
Test name
Test status
Simulation time 21221077 ps
CPU time 1.24 seconds
Started Jul 01 10:33:02 AM PDT 24
Finished Jul 01 10:33:04 AM PDT 24
Peak memory 207336 kb
Host smart-899b3d8e-2223-40e6-9f3a-3376d56110b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728982961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3728982961
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2475369301
Short name T1098
Test name
Test status
Simulation time 12838655 ps
CPU time 0.75 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:52 AM PDT 24
Peak memory 204064 kb
Host smart-4bb2294e-dd42-45f7-bcce-9a9c80dd1dc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475369301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2475369301
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.488750536
Short name T1033
Test name
Test status
Simulation time 55453187 ps
CPU time 1.93 seconds
Started Jul 01 10:32:38 AM PDT 24
Finished Jul 01 10:32:41 AM PDT 24
Peak memory 215528 kb
Host smart-3497c660-1484-40e1-b33e-d98f92511e8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488750536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.488750536
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1223160730
Short name T102
Test name
Test status
Simulation time 42135709 ps
CPU time 1.61 seconds
Started Jul 01 10:32:57 AM PDT 24
Finished Jul 01 10:32:59 AM PDT 24
Peak memory 215836 kb
Host smart-c91f8740-a724-4039-b931-4ee396ff20eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223160730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1223160730
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.348085488
Short name T1094
Test name
Test status
Simulation time 868567032 ps
CPU time 12.79 seconds
Started Jul 01 10:32:58 AM PDT 24
Finished Jul 01 10:33:12 AM PDT 24
Peak memory 216052 kb
Host smart-3eb00326-f584-4ebf-a119-2855e03eba01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348085488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.348085488
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2302935413
Short name T105
Test name
Test status
Simulation time 1374767810 ps
CPU time 3.44 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:55 AM PDT 24
Peak memory 218736 kb
Host smart-58fe0252-8c88-4342-98d0-c5ec713bac71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302935413 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2302935413
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1431344
Short name T118
Test name
Test status
Simulation time 401952346 ps
CPU time 1.36 seconds
Started Jul 01 10:32:52 AM PDT 24
Finished Jul 01 10:32:54 AM PDT 24
Peak memory 207272 kb
Host smart-8b341071-56c9-4346-971d-17607ac86b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.1431344
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2960383619
Short name T1046
Test name
Test status
Simulation time 31979780 ps
CPU time 0.7 seconds
Started Jul 01 10:32:43 AM PDT 24
Finished Jul 01 10:32:50 AM PDT 24
Peak memory 204428 kb
Host smart-906ad5dd-eb3e-4f3d-84bd-9acfeb852ef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960383619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2960383619
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3197928387
Short name T1093
Test name
Test status
Simulation time 898309430 ps
CPU time 3.54 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:32:59 AM PDT 24
Peak memory 215612 kb
Host smart-c6f03949-bdb5-4da1-b678-7784ed2eb580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197928387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3197928387
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.515178894
Short name T173
Test name
Test status
Simulation time 8569686528 ps
CPU time 13.25 seconds
Started Jul 01 10:32:58 AM PDT 24
Finished Jul 01 10:33:12 AM PDT 24
Peak memory 215708 kb
Host smart-0bb9796d-5a89-49ae-8c1b-c23a9939d378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515178894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.515178894
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1547647952
Short name T1095
Test name
Test status
Simulation time 3082288566 ps
CPU time 3.63 seconds
Started Jul 01 10:32:56 AM PDT 24
Finished Jul 01 10:33:00 AM PDT 24
Peak memory 218096 kb
Host smart-d41b8eb1-f9cd-4919-ab51-4361d1c7f280
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547647952 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1547647952
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.889862908
Short name T1105
Test name
Test status
Simulation time 85566915 ps
CPU time 2.7 seconds
Started Jul 01 10:32:59 AM PDT 24
Finished Jul 01 10:33:02 AM PDT 24
Peak memory 207612 kb
Host smart-e574fecb-d9f1-46d0-8814-77e561fc6fce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889862908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.889862908
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3785562835
Short name T1020
Test name
Test status
Simulation time 16756704 ps
CPU time 0.72 seconds
Started Jul 01 10:32:52 AM PDT 24
Finished Jul 01 10:32:54 AM PDT 24
Peak memory 204152 kb
Host smart-7ece8f97-8aa3-458d-83c9-60b9bf801db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785562835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3785562835
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.354780008
Short name T1079
Test name
Test status
Simulation time 153787330 ps
CPU time 3.8 seconds
Started Jul 01 10:32:42 AM PDT 24
Finished Jul 01 10:32:46 AM PDT 24
Peak memory 215888 kb
Host smart-5ebed9ee-ef53-4f92-9a7d-afb2f4437195
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354780008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.354780008
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1434148260
Short name T99
Test name
Test status
Simulation time 404713427 ps
CPU time 2.07 seconds
Started Jul 01 10:32:59 AM PDT 24
Finished Jul 01 10:33:02 AM PDT 24
Peak memory 215720 kb
Host smart-289b343f-3950-4691-8f65-17f6c0528b81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434148260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1434148260
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1567778287
Short name T1088
Test name
Test status
Simulation time 5553460756 ps
CPU time 7.13 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:33:19 AM PDT 24
Peak memory 216004 kb
Host smart-d0996587-1291-478a-ad1d-ed0d3edd80a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567778287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1567778287
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3768869469
Short name T1051
Test name
Test status
Simulation time 480682583 ps
CPU time 3.46 seconds
Started Jul 01 10:32:56 AM PDT 24
Finished Jul 01 10:33:00 AM PDT 24
Peak memory 218116 kb
Host smart-37e3b0aa-a4ce-4826-8478-efc0227cb935
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768869469 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3768869469
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2396908339
Short name T112
Test name
Test status
Simulation time 21512599 ps
CPU time 1.17 seconds
Started Jul 01 10:32:48 AM PDT 24
Finished Jul 01 10:32:50 AM PDT 24
Peak memory 207320 kb
Host smart-6a9330da-56dc-4b62-ba18-c1c42ac3d5b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396908339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2396908339
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.979425038
Short name T1047
Test name
Test status
Simulation time 18696776 ps
CPU time 0.79 seconds
Started Jul 01 10:33:00 AM PDT 24
Finished Jul 01 10:33:01 AM PDT 24
Peak memory 204428 kb
Host smart-29ca2493-36a8-405e-92bd-50f26f36b632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979425038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.979425038
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1432869633
Short name T143
Test name
Test status
Simulation time 47421640 ps
CPU time 1.89 seconds
Started Jul 01 10:32:59 AM PDT 24
Finished Jul 01 10:33:01 AM PDT 24
Peak memory 207356 kb
Host smart-e6506c5a-6808-4fbd-952f-f676e7c08b0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432869633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1432869633
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.510603183
Short name T1127
Test name
Test status
Simulation time 96051820 ps
CPU time 1.64 seconds
Started Jul 01 10:33:01 AM PDT 24
Finished Jul 01 10:33:03 AM PDT 24
Peak memory 215780 kb
Host smart-1e0edcc9-2ea7-4906-b268-6fae5c3e0ef4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510603183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.510603183
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.409869677
Short name T1103
Test name
Test status
Simulation time 534404801 ps
CPU time 7.39 seconds
Started Jul 01 10:32:59 AM PDT 24
Finished Jul 01 10:33:07 AM PDT 24
Peak memory 215684 kb
Host smart-b8321089-a645-4fda-a6f6-342794ca6b27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409869677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.409869677
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.782928261
Short name T1104
Test name
Test status
Simulation time 117986255 ps
CPU time 1.74 seconds
Started Jul 01 10:32:52 AM PDT 24
Finished Jul 01 10:32:55 AM PDT 24
Peak memory 216212 kb
Host smart-5253bec0-90d9-4456-a1c9-26ef993380ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782928261 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.782928261
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2202116020
Short name T1115
Test name
Test status
Simulation time 59893366 ps
CPU time 1.18 seconds
Started Jul 01 10:32:55 AM PDT 24
Finished Jul 01 10:32:57 AM PDT 24
Peak memory 207396 kb
Host smart-935a6766-696b-43ff-9cac-8f1a1069d562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202116020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2202116020
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3555445921
Short name T1097
Test name
Test status
Simulation time 155072022 ps
CPU time 0.69 seconds
Started Jul 01 10:33:08 AM PDT 24
Finished Jul 01 10:33:10 AM PDT 24
Peak memory 204132 kb
Host smart-c136b4f5-0601-4a4c-8f1f-f2f03cee9439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555445921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3555445921
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2820147882
Short name T1027
Test name
Test status
Simulation time 58169199 ps
CPU time 3.73 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:55 AM PDT 24
Peak memory 215456 kb
Host smart-47e00ef2-da2d-496d-8cb1-45e1195f7bd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820147882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2820147882
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2974016825
Short name T108
Test name
Test status
Simulation time 160593717 ps
CPU time 2.66 seconds
Started Jul 01 10:32:57 AM PDT 24
Finished Jul 01 10:33:00 AM PDT 24
Peak memory 215800 kb
Host smart-ec68987e-0ea3-45d2-8d74-f6dd6c6cfa62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974016825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2974016825
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1099320161
Short name T169
Test name
Test status
Simulation time 1671322361 ps
CPU time 16.14 seconds
Started Jul 01 10:33:03 AM PDT 24
Finished Jul 01 10:33:20 AM PDT 24
Peak memory 215520 kb
Host smart-ab0fd30e-e266-4aa6-82d6-6adc9aa1b048
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099320161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1099320161
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1659607952
Short name T1112
Test name
Test status
Simulation time 476153359 ps
CPU time 3.83 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:32:59 AM PDT 24
Peak memory 218036 kb
Host smart-dc467773-3cbb-45ce-9608-68f727b819f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659607952 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1659607952
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1976934681
Short name T113
Test name
Test status
Simulation time 130616610 ps
CPU time 2.03 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:53 AM PDT 24
Peak memory 215508 kb
Host smart-191e85a6-d036-428f-aea4-8c53658aaf3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976934681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1976934681
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3566438250
Short name T1108
Test name
Test status
Simulation time 22026084 ps
CPU time 0.68 seconds
Started Jul 01 10:32:58 AM PDT 24
Finished Jul 01 10:32:58 AM PDT 24
Peak memory 204164 kb
Host smart-91adfbb1-3145-4f2e-a97f-6cb007ec5c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566438250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3566438250
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1188718813
Short name T1118
Test name
Test status
Simulation time 162340295 ps
CPU time 2.53 seconds
Started Jul 01 10:32:52 AM PDT 24
Finished Jul 01 10:32:56 AM PDT 24
Peak memory 215512 kb
Host smart-b4c1ab81-6891-4dd7-b9b4-28dc811dc015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188718813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1188718813
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2826611334
Short name T1110
Test name
Test status
Simulation time 839161167 ps
CPU time 1.72 seconds
Started Jul 01 10:33:04 AM PDT 24
Finished Jul 01 10:33:07 AM PDT 24
Peak memory 215656 kb
Host smart-62c3b966-a1d4-4859-887b-e76b257491cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826611334 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2826611334
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2377243381
Short name T1059
Test name
Test status
Simulation time 239564548 ps
CPU time 2.2 seconds
Started Jul 01 10:32:55 AM PDT 24
Finished Jul 01 10:32:58 AM PDT 24
Peak memory 207404 kb
Host smart-20a8491b-d9c3-47a4-8303-e3b3711e41b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377243381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2377243381
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1061260265
Short name T1013
Test name
Test status
Simulation time 13474041 ps
CPU time 0.72 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:57 AM PDT 24
Peak memory 204192 kb
Host smart-be2ece55-2474-424f-9511-76fd25c9babf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061260265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1061260265
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3043382932
Short name T154
Test name
Test status
Simulation time 211022600 ps
CPU time 4.05 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:33:15 AM PDT 24
Peak memory 216748 kb
Host smart-88751238-ce64-4429-92bd-f817a5e69d0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043382932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3043382932
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1789579368
Short name T1129
Test name
Test status
Simulation time 132588953 ps
CPU time 3.45 seconds
Started Jul 01 10:32:57 AM PDT 24
Finished Jul 01 10:33:01 AM PDT 24
Peak memory 215828 kb
Host smart-b3fd8614-0c4f-4e5c-a418-b93b948a376e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789579368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1789579368
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.99836849
Short name T1043
Test name
Test status
Simulation time 1520742955 ps
CPU time 17.49 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:33:25 AM PDT 24
Peak memory 215592 kb
Host smart-44c974a8-bd1d-4aa3-b2b3-ffc14b403bc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99836849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_
tl_intg_err.99836849
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1131826299
Short name T1066
Test name
Test status
Simulation time 765979033 ps
CPU time 16.1 seconds
Started Jul 01 10:32:30 AM PDT 24
Finished Jul 01 10:32:47 AM PDT 24
Peak memory 215464 kb
Host smart-facf034e-cdc0-4cda-9867-93389fe29096
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131826299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1131826299
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1072300140
Short name T1045
Test name
Test status
Simulation time 6258201765 ps
CPU time 24.12 seconds
Started Jul 01 10:32:28 AM PDT 24
Finished Jul 01 10:32:53 AM PDT 24
Peak memory 207448 kb
Host smart-d208d8c6-a2c5-405e-b80a-02c642c02cf1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072300140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1072300140
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3975021388
Short name T75
Test name
Test status
Simulation time 28426664 ps
CPU time 0.91 seconds
Started Jul 01 10:32:30 AM PDT 24
Finished Jul 01 10:32:32 AM PDT 24
Peak memory 207048 kb
Host smart-bd9a0f29-de5e-4fd4-aaea-f03a07ff67b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975021388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3975021388
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2398896131
Short name T1090
Test name
Test status
Simulation time 457505390 ps
CPU time 2.36 seconds
Started Jul 01 10:32:30 AM PDT 24
Finished Jul 01 10:32:33 AM PDT 24
Peak memory 215872 kb
Host smart-6c7b9c12-bfc8-47a5-86f3-090f5f873bd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398896131 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2398896131
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3061600137
Short name T111
Test name
Test status
Simulation time 101244356 ps
CPU time 1.75 seconds
Started Jul 01 10:32:34 AM PDT 24
Finished Jul 01 10:32:36 AM PDT 24
Peak memory 207236 kb
Host smart-422983fb-3e8b-4ce7-88ee-20a007e2d43a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061600137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
061600137
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.700484405
Short name T1041
Test name
Test status
Simulation time 37493225 ps
CPU time 0.77 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:37 AM PDT 24
Peak memory 204456 kb
Host smart-6f0a0013-351a-43c7-906a-7d3ec60fe673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700484405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.700484405
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.361058273
Short name T123
Test name
Test status
Simulation time 27641642 ps
CPU time 2 seconds
Started Jul 01 10:32:27 AM PDT 24
Finished Jul 01 10:32:30 AM PDT 24
Peak memory 215588 kb
Host smart-0575e025-8e46-4c18-8679-ed35d74c32ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361058273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.361058273
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3079094857
Short name T1087
Test name
Test status
Simulation time 31793668 ps
CPU time 0.64 seconds
Started Jul 01 10:32:27 AM PDT 24
Finished Jul 01 10:32:28 AM PDT 24
Peak memory 203852 kb
Host smart-84faecd4-5280-470f-b90c-fe8f879bfbd1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079094857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3079094857
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2928556691
Short name T1038
Test name
Test status
Simulation time 231233729 ps
CPU time 3.55 seconds
Started Jul 01 10:32:36 AM PDT 24
Finished Jul 01 10:32:40 AM PDT 24
Peak memory 215592 kb
Host smart-9f2a038f-f4af-4a8c-8ee2-6f89c800e930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928556691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2928556691
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1517271339
Short name T100
Test name
Test status
Simulation time 40273438 ps
CPU time 1.47 seconds
Started Jul 01 10:32:36 AM PDT 24
Finished Jul 01 10:32:38 AM PDT 24
Peak memory 215832 kb
Host smart-f170f1f0-4704-4b0d-9689-6337a5b3e039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517271339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
517271339
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2695247399
Short name T64
Test name
Test status
Simulation time 982208909 ps
CPU time 21.13 seconds
Started Jul 01 10:32:27 AM PDT 24
Finished Jul 01 10:32:48 AM PDT 24
Peak memory 215576 kb
Host smart-f865fd6d-1f70-45ee-bf19-b9d973c445d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695247399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2695247399
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1989144917
Short name T1117
Test name
Test status
Simulation time 35131106 ps
CPU time 0.73 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:33:07 AM PDT 24
Peak memory 204420 kb
Host smart-6f2adee8-4695-40cf-abb9-1dc75d68146f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989144917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1989144917
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3650335078
Short name T1058
Test name
Test status
Simulation time 46430872 ps
CPU time 0.74 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:33:07 AM PDT 24
Peak memory 204160 kb
Host smart-d3a2a220-bccb-4e75-8b0f-4799d15e2b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650335078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3650335078
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3171720703
Short name T1037
Test name
Test status
Simulation time 143135703 ps
CPU time 0.69 seconds
Started Jul 01 10:32:48 AM PDT 24
Finished Jul 01 10:32:49 AM PDT 24
Peak memory 204116 kb
Host smart-ca846240-7771-4d93-b94c-ffb80b7c0ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171720703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3171720703
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2135161665
Short name T1100
Test name
Test status
Simulation time 66946645 ps
CPU time 0.74 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:52 AM PDT 24
Peak memory 204096 kb
Host smart-cbefa687-42de-4c6c-9a07-c777d88805b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135161665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2135161665
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2988708651
Short name T1030
Test name
Test status
Simulation time 11771197 ps
CPU time 0.69 seconds
Started Jul 01 10:32:49 AM PDT 24
Finished Jul 01 10:32:50 AM PDT 24
Peak memory 204416 kb
Host smart-049957f5-6581-431a-8a1e-77d5256babf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988708651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2988708651
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4044187469
Short name T1031
Test name
Test status
Simulation time 22634735 ps
CPU time 0.7 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:33:11 AM PDT 24
Peak memory 204148 kb
Host smart-c861e1f0-266d-4cad-b0e2-203435b25e7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044187469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4044187469
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1984043390
Short name T1048
Test name
Test status
Simulation time 56399221 ps
CPU time 0.69 seconds
Started Jul 01 10:32:47 AM PDT 24
Finished Jul 01 10:32:48 AM PDT 24
Peak memory 204104 kb
Host smart-1ab0f757-e637-4207-b015-51a70f7ac77d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984043390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1984043390
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2974037678
Short name T1022
Test name
Test status
Simulation time 127791571 ps
CPU time 0.66 seconds
Started Jul 01 10:32:50 AM PDT 24
Finished Jul 01 10:32:51 AM PDT 24
Peak memory 204348 kb
Host smart-5de463c9-ec01-4c13-bfb2-2358908ee507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974037678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2974037678
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3407649409
Short name T1019
Test name
Test status
Simulation time 39185283 ps
CPU time 0.71 seconds
Started Jul 01 10:33:04 AM PDT 24
Finished Jul 01 10:33:06 AM PDT 24
Peak memory 204112 kb
Host smart-5f55cf1f-408f-4fdc-95df-8793d64e625c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407649409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3407649409
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2780745057
Short name T1021
Test name
Test status
Simulation time 16523534 ps
CPU time 0.84 seconds
Started Jul 01 10:33:04 AM PDT 24
Finished Jul 01 10:33:05 AM PDT 24
Peak memory 204080 kb
Host smart-37775830-7886-4b3a-bfa9-e3cd1b918cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780745057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2780745057
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2848416753
Short name T116
Test name
Test status
Simulation time 432520017 ps
CPU time 7.25 seconds
Started Jul 01 10:32:29 AM PDT 24
Finished Jul 01 10:32:36 AM PDT 24
Peak memory 215500 kb
Host smart-a0b2e5f3-ba2a-4a8d-bbd2-147b67174896
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848416753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2848416753
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4189884351
Short name T1011
Test name
Test status
Simulation time 2475882460 ps
CPU time 25.17 seconds
Started Jul 01 10:32:30 AM PDT 24
Finished Jul 01 10:32:56 AM PDT 24
Peak memory 207320 kb
Host smart-b0069721-1dba-4d4c-87da-66b8d5f2d194
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189884351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4189884351
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3287961723
Short name T76
Test name
Test status
Simulation time 58567409 ps
CPU time 1.17 seconds
Started Jul 01 10:32:31 AM PDT 24
Finished Jul 01 10:32:33 AM PDT 24
Peak memory 207308 kb
Host smart-3f8580ae-393e-46cd-a00f-c6570fcac463
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287961723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3287961723
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3221965124
Short name T1096
Test name
Test status
Simulation time 41587832 ps
CPU time 2.63 seconds
Started Jul 01 10:32:30 AM PDT 24
Finished Jul 01 10:32:33 AM PDT 24
Peak memory 216936 kb
Host smart-2f3062be-1605-4d4f-841f-6cb88297ba85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221965124 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3221965124
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2897159678
Short name T122
Test name
Test status
Simulation time 337604157 ps
CPU time 2.52 seconds
Started Jul 01 10:32:36 AM PDT 24
Finished Jul 01 10:32:39 AM PDT 24
Peak memory 215552 kb
Host smart-b3b6436b-98e1-401b-8550-db6aead4fc8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897159678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
897159678
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4289338709
Short name T1075
Test name
Test status
Simulation time 22213003 ps
CPU time 0.68 seconds
Started Jul 01 10:32:29 AM PDT 24
Finished Jul 01 10:32:31 AM PDT 24
Peak memory 204092 kb
Host smart-80f67e62-eeb7-4b5a-a589-d05534a9f3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289338709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
289338709
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3607913459
Short name T1070
Test name
Test status
Simulation time 255290310 ps
CPU time 1.84 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:38 AM PDT 24
Peak memory 215504 kb
Host smart-b7d60777-b22e-447d-b39b-37ec8e1c4619
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607913459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3607913459
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.831869259
Short name T1084
Test name
Test status
Simulation time 26781925 ps
CPU time 0.65 seconds
Started Jul 01 10:32:28 AM PDT 24
Finished Jul 01 10:32:29 AM PDT 24
Peak memory 203828 kb
Host smart-77b7a4ef-b3f9-42c1-b0b1-66330c960a29
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831869259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.831869259
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1258586202
Short name T1092
Test name
Test status
Simulation time 472182819 ps
CPU time 2.95 seconds
Started Jul 01 10:32:29 AM PDT 24
Finished Jul 01 10:32:33 AM PDT 24
Peak memory 215480 kb
Host smart-b6e7fd40-77eb-4c80-bd56-68f3d36ebe78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258586202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1258586202
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.943789562
Short name T1102
Test name
Test status
Simulation time 876163732 ps
CPU time 3.64 seconds
Started Jul 01 10:32:37 AM PDT 24
Finished Jul 01 10:32:42 AM PDT 24
Peak memory 215792 kb
Host smart-0bb89c8a-2999-4322-8a96-382ecab46c53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943789562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.943789562
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4044691426
Short name T152
Test name
Test status
Simulation time 713832631 ps
CPU time 8.46 seconds
Started Jul 01 10:32:29 AM PDT 24
Finished Jul 01 10:32:39 AM PDT 24
Peak memory 215476 kb
Host smart-8a2dcbe3-389f-4962-b5b3-8d3990120b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044691426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4044691426
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2422983997
Short name T1023
Test name
Test status
Simulation time 25007531 ps
CPU time 0.67 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:52 AM PDT 24
Peak memory 204020 kb
Host smart-b5cff03a-d8c0-4a70-ab9e-eb3d3573cf20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422983997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2422983997
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.122864819
Short name T1085
Test name
Test status
Simulation time 145440844 ps
CPU time 0.82 seconds
Started Jul 01 10:33:04 AM PDT 24
Finished Jul 01 10:33:05 AM PDT 24
Peak memory 204032 kb
Host smart-f2729087-3b2e-4b9b-9be3-4e6542908c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122864819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.122864819
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.698850949
Short name T1109
Test name
Test status
Simulation time 28336676 ps
CPU time 0.73 seconds
Started Jul 01 10:32:56 AM PDT 24
Finished Jul 01 10:33:02 AM PDT 24
Peak memory 204488 kb
Host smart-5c0905b9-e5db-4291-b6b4-0151eb100a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698850949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.698850949
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.464154349
Short name T1014
Test name
Test status
Simulation time 23790277 ps
CPU time 0.75 seconds
Started Jul 01 10:33:03 AM PDT 24
Finished Jul 01 10:33:05 AM PDT 24
Peak memory 204092 kb
Host smart-a3632099-31a6-4cb5-aa23-961588bbf65c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464154349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.464154349
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1278349877
Short name T1107
Test name
Test status
Simulation time 14124073 ps
CPU time 0.75 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:52 AM PDT 24
Peak memory 204096 kb
Host smart-775f73bf-1286-41f4-ac11-7e92a731261e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278349877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1278349877
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.458648473
Short name T1044
Test name
Test status
Simulation time 31663332 ps
CPU time 0.71 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:13 AM PDT 24
Peak memory 204164 kb
Host smart-d618571b-406e-4048-8b87-65bcfa0c9800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458648473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.458648473
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1886748101
Short name T1032
Test name
Test status
Simulation time 32211932 ps
CPU time 0.74 seconds
Started Jul 01 10:32:49 AM PDT 24
Finished Jul 01 10:32:50 AM PDT 24
Peak memory 204408 kb
Host smart-205b74a4-fb54-483b-8262-4ec3be127788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886748101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1886748101
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4193451510
Short name T1080
Test name
Test status
Simulation time 13876167 ps
CPU time 0.72 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:33:08 AM PDT 24
Peak memory 204092 kb
Host smart-c82998d0-b734-4720-ad5f-739718fbffa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193451510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4193451510
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2488728448
Short name T1018
Test name
Test status
Simulation time 59155120 ps
CPU time 0.78 seconds
Started Jul 01 10:33:05 AM PDT 24
Finished Jul 01 10:33:06 AM PDT 24
Peak memory 204416 kb
Host smart-1a47fd51-45e6-406f-a34e-8b1199942216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488728448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2488728448
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1334224925
Short name T1125
Test name
Test status
Simulation time 32985391 ps
CPU time 0.73 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:32:56 AM PDT 24
Peak memory 204464 kb
Host smart-7a2453b6-a210-4ff5-8e22-e90b0f6eda07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334224925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1334224925
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1883767099
Short name T153
Test name
Test status
Simulation time 4882203362 ps
CPU time 8.53 seconds
Started Jul 01 10:32:28 AM PDT 24
Finished Jul 01 10:32:37 AM PDT 24
Peak memory 207416 kb
Host smart-ccf32d32-68e4-46d3-adcc-b679cca91871
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883767099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1883767099
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3561464042
Short name T1082
Test name
Test status
Simulation time 749984444 ps
CPU time 11.65 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:48 AM PDT 24
Peak memory 207324 kb
Host smart-b2910ed2-29be-41bc-8746-67322db2ad74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561464042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3561464042
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1825569836
Short name T77
Test name
Test status
Simulation time 60089475 ps
CPU time 1.11 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:37 AM PDT 24
Peak memory 216440 kb
Host smart-53466cb1-7bd4-488e-816d-21e7e82ce852
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825569836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1825569836
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2588359654
Short name T1053
Test name
Test status
Simulation time 79172585 ps
CPU time 2.68 seconds
Started Jul 01 10:32:39 AM PDT 24
Finished Jul 01 10:32:42 AM PDT 24
Peak memory 216548 kb
Host smart-f684ea93-fddc-46e7-ab48-557f4b617fa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588359654 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2588359654
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1389095818
Short name T1128
Test name
Test status
Simulation time 118216574 ps
CPU time 2.77 seconds
Started Jul 01 10:32:43 AM PDT 24
Finished Jul 01 10:32:46 AM PDT 24
Peak memory 215460 kb
Host smart-5baab23a-c3bc-476f-b60d-ec305ecaf889
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389095818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
389095818
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1011227304
Short name T1069
Test name
Test status
Simulation time 16256888 ps
CPU time 0.72 seconds
Started Jul 01 10:32:27 AM PDT 24
Finished Jul 01 10:32:28 AM PDT 24
Peak memory 204056 kb
Host smart-a5634814-8613-45ec-9c2f-7d3681748580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011227304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
011227304
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1051142664
Short name T1064
Test name
Test status
Simulation time 329480985 ps
CPU time 1.58 seconds
Started Jul 01 10:32:30 AM PDT 24
Finished Jul 01 10:32:33 AM PDT 24
Peak memory 215584 kb
Host smart-76eb2ebe-a268-4939-91ae-94dfee1bb915
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051142664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1051142664
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1174737943
Short name T1015
Test name
Test status
Simulation time 56030487 ps
CPU time 0.67 seconds
Started Jul 01 10:32:49 AM PDT 24
Finished Jul 01 10:32:56 AM PDT 24
Peak memory 203896 kb
Host smart-18dc62c1-b1ba-4553-a22d-30c17e49e3c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174737943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1174737943
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3649696258
Short name T1056
Test name
Test status
Simulation time 26833313 ps
CPU time 1.79 seconds
Started Jul 01 10:32:36 AM PDT 24
Finished Jul 01 10:32:39 AM PDT 24
Peak memory 215512 kb
Host smart-26351e53-8e23-4d96-8ba8-2dd647a26d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649696258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3649696258
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3640232789
Short name T106
Test name
Test status
Simulation time 54828147 ps
CPU time 3.51 seconds
Started Jul 01 10:32:31 AM PDT 24
Finished Jul 01 10:32:35 AM PDT 24
Peak memory 215720 kb
Host smart-b67ad359-57ec-4fb3-9bea-5ae440764276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640232789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
640232789
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.880734779
Short name T174
Test name
Test status
Simulation time 821069079 ps
CPU time 20.89 seconds
Started Jul 01 10:32:32 AM PDT 24
Finished Jul 01 10:32:53 AM PDT 24
Peak memory 215600 kb
Host smart-d26cfba7-0eda-4582-a04b-4c9311081a87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880734779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.880734779
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.224399174
Short name T1071
Test name
Test status
Simulation time 12103924 ps
CPU time 0.7 seconds
Started Jul 01 10:32:58 AM PDT 24
Finished Jul 01 10:32:59 AM PDT 24
Peak memory 204020 kb
Host smart-455b20ee-17fb-4789-9d9f-f13df229b920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224399174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.224399174
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3454599903
Short name T1130
Test name
Test status
Simulation time 25648500 ps
CPU time 0.73 seconds
Started Jul 01 10:32:48 AM PDT 24
Finished Jul 01 10:32:49 AM PDT 24
Peak memory 204176 kb
Host smart-ab1ef9cf-7b0a-49e2-9e83-b6c9cd7fdeb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454599903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3454599903
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4020706878
Short name T1074
Test name
Test status
Simulation time 18035926 ps
CPU time 0.69 seconds
Started Jul 01 10:32:49 AM PDT 24
Finished Jul 01 10:32:51 AM PDT 24
Peak memory 204472 kb
Host smart-367e02e7-caac-48a1-9166-24739ecf3414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020706878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4020706878
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2135768456
Short name T1042
Test name
Test status
Simulation time 14029715 ps
CPU time 0.72 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:33:08 AM PDT 24
Peak memory 204416 kb
Host smart-5baa344b-3bf4-4b05-a2c4-47896d1c19ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135768456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2135768456
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4062638271
Short name T1036
Test name
Test status
Simulation time 45072749 ps
CPU time 0.7 seconds
Started Jul 01 10:32:50 AM PDT 24
Finished Jul 01 10:32:51 AM PDT 24
Peak memory 204104 kb
Host smart-085aba4c-4183-48bf-a168-150788502360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062638271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
4062638271
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2506442203
Short name T1113
Test name
Test status
Simulation time 11763426 ps
CPU time 0.79 seconds
Started Jul 01 10:33:06 AM PDT 24
Finished Jul 01 10:33:08 AM PDT 24
Peak memory 204420 kb
Host smart-74b16d0a-f3a6-4993-bdd5-d6ea1b957f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506442203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2506442203
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1499423523
Short name T1025
Test name
Test status
Simulation time 92563524 ps
CPU time 0.74 seconds
Started Jul 01 10:32:46 AM PDT 24
Finished Jul 01 10:32:47 AM PDT 24
Peak memory 204032 kb
Host smart-5fc6bd8d-19a8-4af2-a24c-8e2649dda8f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499423523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1499423523
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2348145758
Short name T1029
Test name
Test status
Simulation time 111974310 ps
CPU time 0.75 seconds
Started Jul 01 10:33:01 AM PDT 24
Finished Jul 01 10:33:02 AM PDT 24
Peak memory 204048 kb
Host smart-c1625365-9fd0-4b60-b409-fc22b840abc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348145758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2348145758
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2337849822
Short name T1083
Test name
Test status
Simulation time 39585207 ps
CPU time 0.72 seconds
Started Jul 01 10:32:54 AM PDT 24
Finished Jul 01 10:32:56 AM PDT 24
Peak memory 204468 kb
Host smart-676c08f2-b364-4fea-b9c6-0c689d602950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337849822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2337849822
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3192982484
Short name T1060
Test name
Test status
Simulation time 15128224 ps
CPU time 0.7 seconds
Started Jul 01 10:32:49 AM PDT 24
Finished Jul 01 10:32:51 AM PDT 24
Peak memory 204380 kb
Host smart-062aa656-fe7f-456a-b193-884d6c68bf7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192982484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3192982484
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2004328567
Short name T1050
Test name
Test status
Simulation time 932426626 ps
CPU time 2.66 seconds
Started Jul 01 10:32:32 AM PDT 24
Finished Jul 01 10:32:35 AM PDT 24
Peak memory 218428 kb
Host smart-8e23d610-d67a-43c8-a1e7-0f44df06ead0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004328567 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2004328567
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2799897657
Short name T1123
Test name
Test status
Simulation time 259674171 ps
CPU time 1.74 seconds
Started Jul 01 10:32:43 AM PDT 24
Finished Jul 01 10:32:45 AM PDT 24
Peak memory 207332 kb
Host smart-c0dbc220-1012-4b05-95ce-aafdc4831dcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799897657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
799897657
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3699371734
Short name T1017
Test name
Test status
Simulation time 17417769 ps
CPU time 0.75 seconds
Started Jul 01 10:32:37 AM PDT 24
Finished Jul 01 10:32:38 AM PDT 24
Peak memory 204420 kb
Host smart-d0c4df23-bfb9-4d31-a4c0-b872d3c8cb69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699371734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
699371734
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.632902284
Short name T150
Test name
Test status
Simulation time 134969853 ps
CPU time 1.78 seconds
Started Jul 01 10:32:32 AM PDT 24
Finished Jul 01 10:32:34 AM PDT 24
Peak memory 215468 kb
Host smart-f2037e4c-cf14-4c6a-9e31-a684394e3e63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632902284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.632902284
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2486788532
Short name T63
Test name
Test status
Simulation time 93392056 ps
CPU time 2.29 seconds
Started Jul 01 10:32:30 AM PDT 24
Finished Jul 01 10:32:38 AM PDT 24
Peak memory 215744 kb
Host smart-678af837-04df-4355-a12f-25f8fa3af3ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486788532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
486788532
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1266557575
Short name T1077
Test name
Test status
Simulation time 70915350 ps
CPU time 2.49 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:39 AM PDT 24
Peak memory 216728 kb
Host smart-9ff1d197-2906-4f2f-bde0-90d0afe99ae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266557575 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1266557575
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2990293627
Short name T119
Test name
Test status
Simulation time 233102709 ps
CPU time 2.62 seconds
Started Jul 01 10:32:31 AM PDT 24
Finished Jul 01 10:32:34 AM PDT 24
Peak memory 207324 kb
Host smart-9440b552-5ed1-4866-8562-7d7e98df5c47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990293627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
990293627
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3603465933
Short name T1039
Test name
Test status
Simulation time 18703054 ps
CPU time 0.66 seconds
Started Jul 01 10:32:59 AM PDT 24
Finished Jul 01 10:33:00 AM PDT 24
Peak memory 204164 kb
Host smart-798adeb4-3a7d-4c76-b680-d84d2b7a48d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603465933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
603465933
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3562906774
Short name T1016
Test name
Test status
Simulation time 285079877 ps
CPU time 1.72 seconds
Started Jul 01 10:32:39 AM PDT 24
Finished Jul 01 10:32:41 AM PDT 24
Peak memory 215516 kb
Host smart-1c5fc9c4-69e5-4189-a6bb-8eb23e9552db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562906774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3562906774
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2037792464
Short name T1124
Test name
Test status
Simulation time 135380079 ps
CPU time 1.94 seconds
Started Jul 01 10:32:35 AM PDT 24
Finished Jul 01 10:32:38 AM PDT 24
Peak memory 215832 kb
Host smart-7fd91dc9-b488-4283-acaa-2e4deaa87156
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037792464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
037792464
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3123812909
Short name T175
Test name
Test status
Simulation time 1952313244 ps
CPU time 6.6 seconds
Started Jul 01 10:32:45 AM PDT 24
Finished Jul 01 10:32:51 AM PDT 24
Peak memory 215620 kb
Host smart-2be04a16-a7bc-421c-844a-b2a550515281
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123812909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3123812909
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.822488854
Short name T1131
Test name
Test status
Simulation time 87875552 ps
CPU time 1.72 seconds
Started Jul 01 10:32:37 AM PDT 24
Finished Jul 01 10:32:39 AM PDT 24
Peak memory 215572 kb
Host smart-5dfcc597-694c-4c14-b990-7bc156eebeee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822488854 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.822488854
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1899660328
Short name T1010
Test name
Test status
Simulation time 390044573 ps
CPU time 2.73 seconds
Started Jul 01 10:32:37 AM PDT 24
Finished Jul 01 10:32:40 AM PDT 24
Peak memory 207288 kb
Host smart-eef219f2-e9df-4c4b-b2b4-06766c5216a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899660328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
899660328
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4110160575
Short name T1024
Test name
Test status
Simulation time 37844349 ps
CPU time 0.73 seconds
Started Jul 01 10:32:33 AM PDT 24
Finished Jul 01 10:32:34 AM PDT 24
Peak memory 204100 kb
Host smart-21e3e83f-322e-4975-8e82-16f566581196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110160575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
110160575
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1340135029
Short name T1081
Test name
Test status
Simulation time 903563552 ps
CPU time 4.2 seconds
Started Jul 01 10:32:38 AM PDT 24
Finished Jul 01 10:32:43 AM PDT 24
Peak memory 215476 kb
Host smart-54cab498-8e9b-42ea-8825-52ea88ec5bf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340135029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1340135029
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2034564896
Short name T96
Test name
Test status
Simulation time 375214287 ps
CPU time 4.48 seconds
Started Jul 01 10:32:32 AM PDT 24
Finished Jul 01 10:32:37 AM PDT 24
Peak memory 215780 kb
Host smart-7583754e-54a1-4756-ab85-3d6259640ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034564896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
034564896
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.277643146
Short name T151
Test name
Test status
Simulation time 349390655 ps
CPU time 8.29 seconds
Started Jul 01 10:32:36 AM PDT 24
Finished Jul 01 10:32:45 AM PDT 24
Peak memory 215944 kb
Host smart-aadaf034-92f1-4601-986e-f25f1694ccc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277643146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.277643146
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.145802024
Short name T109
Test name
Test status
Simulation time 81810517 ps
CPU time 1.81 seconds
Started Jul 01 10:33:02 AM PDT 24
Finished Jul 01 10:33:04 AM PDT 24
Peak memory 216688 kb
Host smart-36923c48-5c94-4723-ada9-ea30b0496b0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145802024 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.145802024
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4210397783
Short name T1120
Test name
Test status
Simulation time 74979866 ps
CPU time 1.32 seconds
Started Jul 01 10:32:32 AM PDT 24
Finished Jul 01 10:32:34 AM PDT 24
Peak memory 215480 kb
Host smart-c92d0858-2bc8-41c6-9831-a9ba352df2c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210397783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
210397783
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.456035323
Short name T1065
Test name
Test status
Simulation time 13988713 ps
CPU time 0.72 seconds
Started Jul 01 10:32:36 AM PDT 24
Finished Jul 01 10:32:37 AM PDT 24
Peak memory 204112 kb
Host smart-772267a3-039a-45cb-89d2-2ad729aa76ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456035323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.456035323
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2004132295
Short name T1040
Test name
Test status
Simulation time 58912088 ps
CPU time 3.49 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:56 AM PDT 24
Peak memory 215628 kb
Host smart-36c7f731-e2d7-4aa6-b095-f864c27d4f00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004132295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2004132295
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1914773751
Short name T1122
Test name
Test status
Simulation time 76005855 ps
CPU time 4.26 seconds
Started Jul 01 10:32:31 AM PDT 24
Finished Jul 01 10:32:35 AM PDT 24
Peak memory 215872 kb
Host smart-f97036af-1e36-4221-be64-fec74500ea6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914773751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
914773751
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4224441079
Short name T1062
Test name
Test status
Simulation time 2937973033 ps
CPU time 8.15 seconds
Started Jul 01 10:32:37 AM PDT 24
Finished Jul 01 10:32:46 AM PDT 24
Peak memory 216528 kb
Host smart-58b12784-418d-4aa8-93f9-be6f2dcc6ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224441079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4224441079
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2711559783
Short name T107
Test name
Test status
Simulation time 473705212 ps
CPU time 3.44 seconds
Started Jul 01 10:32:42 AM PDT 24
Finished Jul 01 10:32:46 AM PDT 24
Peak memory 218648 kb
Host smart-61d1146e-c75f-4514-be13-b2a1c873a553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711559783 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2711559783
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1539462206
Short name T120
Test name
Test status
Simulation time 295819509 ps
CPU time 1.74 seconds
Started Jul 01 10:32:51 AM PDT 24
Finished Jul 01 10:32:54 AM PDT 24
Peak memory 215552 kb
Host smart-b0dcbd3a-5ebd-4c14-b238-21ee18e12e7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539462206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
539462206
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.798668542
Short name T1052
Test name
Test status
Simulation time 149186928 ps
CPU time 0.66 seconds
Started Jul 01 10:32:40 AM PDT 24
Finished Jul 01 10:32:41 AM PDT 24
Peak memory 204428 kb
Host smart-4833ad9c-472e-474b-a752-8970b1dfcbd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798668542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.798668542
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3734089779
Short name T1061
Test name
Test status
Simulation time 98818393 ps
CPU time 1.7 seconds
Started Jul 01 10:33:08 AM PDT 24
Finished Jul 01 10:33:11 AM PDT 24
Peak memory 215580 kb
Host smart-ec2defd1-c96f-4287-be94-471c2a3bc509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734089779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3734089779
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2200967500
Short name T101
Test name
Test status
Simulation time 73224536 ps
CPU time 1.1 seconds
Started Jul 01 10:32:50 AM PDT 24
Finished Jul 01 10:32:51 AM PDT 24
Peak memory 215728 kb
Host smart-71353341-3961-4439-925d-9ea0a3220152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200967500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
200967500
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2651925346
Short name T1101
Test name
Test status
Simulation time 100461501 ps
CPU time 6.49 seconds
Started Jul 01 10:32:42 AM PDT 24
Finished Jul 01 10:32:49 AM PDT 24
Peak memory 215824 kb
Host smart-e6f5342e-bfcb-48dd-99ed-2c6d87199d58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651925346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2651925346
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2490240053
Short name T509
Test name
Test status
Simulation time 19926460 ps
CPU time 0.7 seconds
Started Jul 01 12:46:11 PM PDT 24
Finished Jul 01 12:46:14 PM PDT 24
Peak memory 205488 kb
Host smart-324d20b1-0352-4c07-8484-ec3168864ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490240053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
490240053
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.568585314
Short name T610
Test name
Test status
Simulation time 195966773 ps
CPU time 2.89 seconds
Started Jul 01 12:46:06 PM PDT 24
Finished Jul 01 12:46:11 PM PDT 24
Peak memory 232580 kb
Host smart-e4e5781a-e6a8-4ef2-a983-036010fec164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568585314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.568585314
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1101099127
Short name T917
Test name
Test status
Simulation time 15273331 ps
CPU time 0.76 seconds
Started Jul 01 12:45:56 PM PDT 24
Finished Jul 01 12:45:58 PM PDT 24
Peak memory 206592 kb
Host smart-0a349ad2-0e84-45e6-b5ea-23c1c0b0c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101099127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1101099127
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2087727151
Short name T265
Test name
Test status
Simulation time 23701926386 ps
CPU time 103.69 seconds
Started Jul 01 12:46:06 PM PDT 24
Finished Jul 01 12:47:51 PM PDT 24
Peak memory 249448 kb
Host smart-4d254c19-1c81-4a4f-902f-072a70047b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087727151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2087727151
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3665559328
Short name T209
Test name
Test status
Simulation time 29838174946 ps
CPU time 145.07 seconds
Started Jul 01 12:46:08 PM PDT 24
Finished Jul 01 12:48:34 PM PDT 24
Peak memory 248652 kb
Host smart-30bffd43-0991-4115-8ac4-762462ddfcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665559328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3665559328
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4070835600
Short name T361
Test name
Test status
Simulation time 4614938823 ps
CPU time 4.6 seconds
Started Jul 01 12:46:11 PM PDT 24
Finished Jul 01 12:46:18 PM PDT 24
Peak memory 217452 kb
Host smart-e6659f80-a4f4-4f90-b448-8730e760cc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070835600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4070835600
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2273879115
Short name T728
Test name
Test status
Simulation time 865237669 ps
CPU time 11.36 seconds
Started Jul 01 12:46:05 PM PDT 24
Finished Jul 01 12:46:18 PM PDT 24
Peak memory 233440 kb
Host smart-85bbad5f-143b-4e9d-b65b-0379686a245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273879115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2273879115
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2823170282
Short name T777
Test name
Test status
Simulation time 1272445792 ps
CPU time 4.37 seconds
Started Jul 01 12:46:06 PM PDT 24
Finished Jul 01 12:46:12 PM PDT 24
Peak memory 224456 kb
Host smart-abc7885b-7916-40d1-ad03-f57bca50773f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823170282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2823170282
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1002562133
Short name T536
Test name
Test status
Simulation time 2117037494 ps
CPU time 16.75 seconds
Started Jul 01 12:46:07 PM PDT 24
Finished Jul 01 12:46:25 PM PDT 24
Peak memory 232728 kb
Host smart-bed5bb0f-33ee-40ac-9426-c44bc768b3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002562133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1002562133
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1486194956
Short name T217
Test name
Test status
Simulation time 3629971970 ps
CPU time 11.38 seconds
Started Jul 01 12:46:06 PM PDT 24
Finished Jul 01 12:46:19 PM PDT 24
Peak memory 233036 kb
Host smart-b86eeb5c-26c6-4796-8297-4857e687732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486194956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1486194956
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2183785764
Short name T758
Test name
Test status
Simulation time 2155779462 ps
CPU time 9.22 seconds
Started Jul 01 12:46:06 PM PDT 24
Finished Jul 01 12:46:17 PM PDT 24
Peak memory 224480 kb
Host smart-580d860a-4a50-4515-ab0d-713f98693844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183785764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2183785764
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1712980848
Short name T970
Test name
Test status
Simulation time 889367144 ps
CPU time 10.73 seconds
Started Jul 01 12:46:08 PM PDT 24
Finished Jul 01 12:46:19 PM PDT 24
Peak memory 222616 kb
Host smart-369898ec-e6bc-4062-bad4-82b5da86e949
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1712980848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1712980848
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1521312013
Short name T69
Test name
Test status
Simulation time 60672825 ps
CPU time 0.95 seconds
Started Jul 01 12:46:12 PM PDT 24
Finished Jul 01 12:46:14 PM PDT 24
Peak memory 236628 kb
Host smart-10d84caf-f15f-4f6b-9213-76a71c7b1c8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521312013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1521312013
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.767918931
Short name T830
Test name
Test status
Simulation time 56693372 ps
CPU time 1.06 seconds
Started Jul 01 12:46:13 PM PDT 24
Finished Jul 01 12:46:15 PM PDT 24
Peak memory 207924 kb
Host smart-84279e97-a51c-4336-8dc5-15391af82add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767918931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.767918931
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3490508624
Short name T448
Test name
Test status
Simulation time 1387294373 ps
CPU time 5.11 seconds
Started Jul 01 12:46:05 PM PDT 24
Finished Jul 01 12:46:11 PM PDT 24
Peak memory 216284 kb
Host smart-0732483c-db89-4207-b0d4-b57aada6e444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490508624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3490508624
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3428988707
Short name T403
Test name
Test status
Simulation time 955386158 ps
CPU time 3.82 seconds
Started Jul 01 12:45:56 PM PDT 24
Finished Jul 01 12:46:01 PM PDT 24
Peak memory 216140 kb
Host smart-190ec84f-c4e8-421d-a35f-586a67a18414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428988707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3428988707
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2426147085
Short name T414
Test name
Test status
Simulation time 317125343 ps
CPU time 1.26 seconds
Started Jul 01 12:46:05 PM PDT 24
Finished Jul 01 12:46:08 PM PDT 24
Peak memory 216332 kb
Host smart-7ef8f8d2-6d9e-4530-8e88-05885c5ee46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426147085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2426147085
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2321529040
Short name T605
Test name
Test status
Simulation time 233153690 ps
CPU time 0.9 seconds
Started Jul 01 12:46:05 PM PDT 24
Finished Jul 01 12:46:08 PM PDT 24
Peak memory 205936 kb
Host smart-4d6dba5a-2eb5-4830-90c8-fc8a64ad5301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321529040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2321529040
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1159296125
Short name T671
Test name
Test status
Simulation time 6003069831 ps
CPU time 22.35 seconds
Started Jul 01 12:46:07 PM PDT 24
Finished Jul 01 12:46:31 PM PDT 24
Peak memory 249052 kb
Host smart-64f3f817-983b-41d4-923b-0e3deec11ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159296125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1159296125
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.362074198
Short name T697
Test name
Test status
Simulation time 108919623 ps
CPU time 0.72 seconds
Started Jul 01 12:46:20 PM PDT 24
Finished Jul 01 12:46:21 PM PDT 24
Peak memory 205456 kb
Host smart-3ac9c605-bee2-411b-a645-993dac51db88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362074198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.362074198
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1817907919
Short name T250
Test name
Test status
Simulation time 173924669 ps
CPU time 3.4 seconds
Started Jul 01 12:46:15 PM PDT 24
Finished Jul 01 12:46:20 PM PDT 24
Peak memory 224436 kb
Host smart-41f7e151-0433-46df-8b18-037f42a64b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817907919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1817907919
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.607259025
Short name T785
Test name
Test status
Simulation time 17808899 ps
CPU time 0.77 seconds
Started Jul 01 12:46:12 PM PDT 24
Finished Jul 01 12:46:14 PM PDT 24
Peak memory 205896 kb
Host smart-0ccf16e0-93e4-4c3e-8999-e994c89cfeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607259025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.607259025
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.951154593
Short name T739
Test name
Test status
Simulation time 5216675459 ps
CPU time 52.84 seconds
Started Jul 01 12:46:15 PM PDT 24
Finished Jul 01 12:47:09 PM PDT 24
Peak memory 251868 kb
Host smart-0841377b-50ad-4d65-a8d1-5e2215036406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951154593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.951154593
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.102911213
Short name T304
Test name
Test status
Simulation time 5231603138 ps
CPU time 83.24 seconds
Started Jul 01 12:46:16 PM PDT 24
Finished Jul 01 12:47:41 PM PDT 24
Peak memory 249256 kb
Host smart-85ecd5a6-b52e-4f2c-816a-b5ac9158330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102911213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.102911213
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.437479184
Short name T278
Test name
Test status
Simulation time 9393836970 ps
CPU time 69.62 seconds
Started Jul 01 12:46:18 PM PDT 24
Finished Jul 01 12:47:29 PM PDT 24
Peak memory 256068 kb
Host smart-4d23145a-b95e-4f03-b4a3-7ff1486cd14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437479184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
437479184
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2770798864
Short name T459
Test name
Test status
Simulation time 152320746 ps
CPU time 2.48 seconds
Started Jul 01 12:46:17 PM PDT 24
Finished Jul 01 12:46:20 PM PDT 24
Peak memory 224492 kb
Host smart-07d3a3e5-f1d6-445c-b547-cf071631e681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770798864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2770798864
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2924095772
Short name T262
Test name
Test status
Simulation time 9097092136 ps
CPU time 120.82 seconds
Started Jul 01 12:46:16 PM PDT 24
Finished Jul 01 12:48:18 PM PDT 24
Peak memory 254640 kb
Host smart-ca915dc5-e112-4ac7-aea1-2760f1b07071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924095772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2924095772
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.293444414
Short name T645
Test name
Test status
Simulation time 279988567 ps
CPU time 3.06 seconds
Started Jul 01 12:46:16 PM PDT 24
Finished Jul 01 12:46:20 PM PDT 24
Peak memory 232648 kb
Host smart-7f5ed291-3fd3-4e44-aeb2-11834f15ec3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293444414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.293444414
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.360467337
Short name T619
Test name
Test status
Simulation time 9563673299 ps
CPU time 61.31 seconds
Started Jul 01 12:46:16 PM PDT 24
Finished Jul 01 12:47:18 PM PDT 24
Peak memory 224640 kb
Host smart-beb62509-dc15-405a-92a0-f635993f645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360467337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.360467337
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3782695454
Short name T479
Test name
Test status
Simulation time 511008273 ps
CPU time 6.79 seconds
Started Jul 01 12:46:15 PM PDT 24
Finished Jul 01 12:46:22 PM PDT 24
Peak memory 224624 kb
Host smart-4177d178-a73e-40ed-910d-b53f5db8f64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782695454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3782695454
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3723511963
Short name T947
Test name
Test status
Simulation time 373464007 ps
CPU time 3.5 seconds
Started Jul 01 12:46:12 PM PDT 24
Finished Jul 01 12:46:17 PM PDT 24
Peak memory 224456 kb
Host smart-4612a4ef-b0ce-4fbb-9ba1-4eae2535ce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723511963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3723511963
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1987129524
Short name T530
Test name
Test status
Simulation time 332363628 ps
CPU time 4.71 seconds
Started Jul 01 12:46:18 PM PDT 24
Finished Jul 01 12:46:23 PM PDT 24
Peak memory 223024 kb
Host smart-f2c61453-fc36-48f7-b5d1-80feaba30b3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1987129524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1987129524
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2762532139
Short name T294
Test name
Test status
Simulation time 34386215763 ps
CPU time 42.23 seconds
Started Jul 01 12:46:13 PM PDT 24
Finished Jul 01 12:46:57 PM PDT 24
Peak memory 216272 kb
Host smart-c191c825-c93d-4f5f-b4ce-0b41d8d93361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762532139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2762532139
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3297287025
Short name T474
Test name
Test status
Simulation time 15842323694 ps
CPU time 26.65 seconds
Started Jul 01 12:46:12 PM PDT 24
Finished Jul 01 12:46:40 PM PDT 24
Peak memory 216260 kb
Host smart-90edf394-f98a-4fa9-b2d9-aa5f2af2fd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297287025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3297287025
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2054864605
Short name T599
Test name
Test status
Simulation time 28907674 ps
CPU time 1.02 seconds
Started Jul 01 12:46:12 PM PDT 24
Finished Jul 01 12:46:15 PM PDT 24
Peak memory 207428 kb
Host smart-b4caaca3-13d2-499d-8bdf-faa1bfca60ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054864605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2054864605
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1273919165
Short name T82
Test name
Test status
Simulation time 361383648 ps
CPU time 1 seconds
Started Jul 01 12:46:10 PM PDT 24
Finished Jul 01 12:46:13 PM PDT 24
Peak memory 205976 kb
Host smart-b30f052d-a36e-4eeb-9a49-c0c16c40eaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273919165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1273919165
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3988681457
Short name T56
Test name
Test status
Simulation time 292703439 ps
CPU time 4.21 seconds
Started Jul 01 12:46:15 PM PDT 24
Finished Jul 01 12:46:20 PM PDT 24
Peak memory 232668 kb
Host smart-9b84d4fe-b778-445a-b577-59bb84e4fc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988681457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3988681457
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3574651449
Short name T919
Test name
Test status
Simulation time 14745290 ps
CPU time 0.76 seconds
Started Jul 01 12:47:31 PM PDT 24
Finished Jul 01 12:47:32 PM PDT 24
Peak memory 204972 kb
Host smart-cfab7c12-2cf3-40d5-9e3b-d52efeba3912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574651449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3574651449
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.44267586
Short name T922
Test name
Test status
Simulation time 294349407 ps
CPU time 3.01 seconds
Started Jul 01 12:47:22 PM PDT 24
Finished Jul 01 12:47:29 PM PDT 24
Peak memory 232612 kb
Host smart-470a47d4-6333-42f4-ab76-7dae9e8b512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44267586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.44267586
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1204224749
Short name T502
Test name
Test status
Simulation time 70101339 ps
CPU time 0.89 seconds
Started Jul 01 12:47:17 PM PDT 24
Finished Jul 01 12:47:19 PM PDT 24
Peak memory 206600 kb
Host smart-9c8d615a-3a8b-4bc3-a946-9f34d3b3d985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204224749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1204224749
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.989292633
Short name T463
Test name
Test status
Simulation time 27244148956 ps
CPU time 200.99 seconds
Started Jul 01 12:47:25 PM PDT 24
Finished Jul 01 12:50:49 PM PDT 24
Peak memory 257324 kb
Host smart-fb31dacc-bc7c-40eb-ad76-6836cd8e1932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989292633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.989292633
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3974120897
Short name T802
Test name
Test status
Simulation time 6418504999 ps
CPU time 62.37 seconds
Started Jul 01 12:47:23 PM PDT 24
Finished Jul 01 12:48:29 PM PDT 24
Peak memory 249684 kb
Host smart-50ad4172-bad4-4869-a2ae-a087e27bac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974120897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3974120897
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1908004753
Short name T561
Test name
Test status
Simulation time 22601616797 ps
CPU time 213.61 seconds
Started Jul 01 12:47:23 PM PDT 24
Finished Jul 01 12:51:01 PM PDT 24
Peak memory 250708 kb
Host smart-563c2199-75e0-4ff8-9031-4e90da142e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908004753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1908004753
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1889899017
Short name T309
Test name
Test status
Simulation time 125814369 ps
CPU time 3.3 seconds
Started Jul 01 12:47:23 PM PDT 24
Finished Jul 01 12:47:30 PM PDT 24
Peak memory 232672 kb
Host smart-d5b22206-4016-4d94-855d-ffd50778a91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889899017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1889899017
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3678808578
Short name T901
Test name
Test status
Simulation time 167629650960 ps
CPU time 229.94 seconds
Started Jul 01 12:47:23 PM PDT 24
Finished Jul 01 12:51:17 PM PDT 24
Peak memory 249220 kb
Host smart-d4ffaa77-e3d2-4b78-b53d-359b725eba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678808578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3678808578
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2142047113
Short name T705
Test name
Test status
Simulation time 3202031085 ps
CPU time 19.79 seconds
Started Jul 01 12:47:24 PM PDT 24
Finished Jul 01 12:47:47 PM PDT 24
Peak memory 224632 kb
Host smart-e12d72ce-cec9-4ea6-a31c-a7b6ffc53984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142047113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2142047113
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2113857366
Short name T60
Test name
Test status
Simulation time 109567670 ps
CPU time 2.31 seconds
Started Jul 01 12:47:31 PM PDT 24
Finished Jul 01 12:47:34 PM PDT 24
Peak memory 222988 kb
Host smart-108c5a59-4f92-4608-a5c3-d602c2c88543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113857366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2113857366
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3476324539
Short name T499
Test name
Test status
Simulation time 2732792210 ps
CPU time 2.97 seconds
Started Jul 01 12:47:23 PM PDT 24
Finished Jul 01 12:47:30 PM PDT 24
Peak memory 224468 kb
Host smart-8ebebc66-8e60-48b8-8ea5-c633447baef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476324539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3476324539
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.683598523
Short name T408
Test name
Test status
Simulation time 1659008341 ps
CPU time 3.37 seconds
Started Jul 01 12:47:23 PM PDT 24
Finished Jul 01 12:47:30 PM PDT 24
Peak memory 224460 kb
Host smart-d014cb85-5375-484e-b48b-b77239a48557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683598523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.683598523
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4118783639
Short name T643
Test name
Test status
Simulation time 6433670930 ps
CPU time 12.64 seconds
Started Jul 01 12:47:30 PM PDT 24
Finished Jul 01 12:47:44 PM PDT 24
Peak memory 222192 kb
Host smart-b5761441-0ea4-49a3-94c3-e7df88d6fdf5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4118783639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4118783639
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.118283247
Short name T303
Test name
Test status
Simulation time 2950441199 ps
CPU time 63.6 seconds
Started Jul 01 12:47:23 PM PDT 24
Finished Jul 01 12:48:30 PM PDT 24
Peak memory 249296 kb
Host smart-7ebd585d-dc39-4b4b-a7d8-3905d3b7b3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118283247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.118283247
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.54482417
Short name T297
Test name
Test status
Simulation time 610764002 ps
CPU time 6.73 seconds
Started Jul 01 12:47:19 PM PDT 24
Finished Jul 01 12:47:27 PM PDT 24
Peak memory 216428 kb
Host smart-b2c330ef-9785-480a-a1d6-0a385ebf1c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54482417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.54482417
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2599110109
Short name T537
Test name
Test status
Simulation time 18579025579 ps
CPU time 15.08 seconds
Started Jul 01 12:47:18 PM PDT 24
Finished Jul 01 12:47:34 PM PDT 24
Peak memory 217628 kb
Host smart-5c1f7bf1-08e9-4d9f-9058-4576f1551bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599110109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2599110109
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1857669563
Short name T811
Test name
Test status
Simulation time 4045057104 ps
CPU time 11.31 seconds
Started Jul 01 12:47:23 PM PDT 24
Finished Jul 01 12:47:38 PM PDT 24
Peak memory 216280 kb
Host smart-3d9517fd-86f6-42a1-b897-84c920189f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857669563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1857669563
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.70458869
Short name T575
Test name
Test status
Simulation time 70221735 ps
CPU time 0.96 seconds
Started Jul 01 12:47:19 PM PDT 24
Finished Jul 01 12:47:21 PM PDT 24
Peak memory 206980 kb
Host smart-07c538b8-9051-4aa5-9d43-5af4145712e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70458869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.70458869
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1080838172
Short name T694
Test name
Test status
Simulation time 4867081561 ps
CPU time 14.2 seconds
Started Jul 01 12:47:25 PM PDT 24
Finished Jul 01 12:47:42 PM PDT 24
Peak memory 232824 kb
Host smart-867ab06c-9c0e-4eb8-80a5-219fb61bca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080838172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1080838172
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2421087293
Short name T533
Test name
Test status
Simulation time 14768098 ps
CPU time 0.7 seconds
Started Jul 01 12:47:34 PM PDT 24
Finished Jul 01 12:47:35 PM PDT 24
Peak memory 204972 kb
Host smart-5730239d-bade-4fb9-83fc-95726a169fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421087293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2421087293
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2386641669
Short name T806
Test name
Test status
Simulation time 285128619 ps
CPU time 5.54 seconds
Started Jul 01 12:47:28 PM PDT 24
Finished Jul 01 12:47:35 PM PDT 24
Peak memory 232636 kb
Host smart-936fea41-259c-44e6-baf2-1548cf9dbe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386641669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2386641669
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2414557531
Short name T431
Test name
Test status
Simulation time 59068371 ps
CPU time 0.75 seconds
Started Jul 01 12:47:31 PM PDT 24
Finished Jul 01 12:47:32 PM PDT 24
Peak memory 206612 kb
Host smart-cdfd5657-b643-41c4-a025-f5212834f5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414557531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2414557531
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1823946896
Short name T881
Test name
Test status
Simulation time 2860643803 ps
CPU time 47.81 seconds
Started Jul 01 12:47:28 PM PDT 24
Finished Jul 01 12:48:17 PM PDT 24
Peak memory 249000 kb
Host smart-7853d8a9-8673-440e-b871-37a038bc3a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823946896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1823946896
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1244498419
Short name T256
Test name
Test status
Simulation time 16709579854 ps
CPU time 180.27 seconds
Started Jul 01 12:47:32 PM PDT 24
Finished Jul 01 12:50:33 PM PDT 24
Peak memory 255572 kb
Host smart-e25c10e6-70ee-436e-9150-31566bf2580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244498419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1244498419
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3853590039
Short name T457
Test name
Test status
Simulation time 31287416555 ps
CPU time 283.33 seconds
Started Jul 01 12:47:32 PM PDT 24
Finished Jul 01 12:52:16 PM PDT 24
Peak memory 255672 kb
Host smart-e00b60a1-ab3b-4d01-b4a0-7a6bec9066ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853590039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3853590039
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4271093432
Short name T849
Test name
Test status
Simulation time 256174941 ps
CPU time 4.35 seconds
Started Jul 01 12:47:28 PM PDT 24
Finished Jul 01 12:47:34 PM PDT 24
Peak memory 236264 kb
Host smart-114b26ba-824c-462e-bc78-12262bca88a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271093432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4271093432
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.4029288870
Short name T317
Test name
Test status
Simulation time 37499920 ps
CPU time 0.8 seconds
Started Jul 01 12:47:32 PM PDT 24
Finished Jul 01 12:47:33 PM PDT 24
Peak memory 215840 kb
Host smart-e17b6188-8685-4ffe-aafa-b676bf204a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029288870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.4029288870
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3617941355
Short name T87
Test name
Test status
Simulation time 6683097961 ps
CPU time 15.69 seconds
Started Jul 01 12:47:28 PM PDT 24
Finished Jul 01 12:47:45 PM PDT 24
Peak memory 224632 kb
Host smart-70b49309-1183-484b-94ee-4466ebdc0c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617941355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3617941355
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1140560715
Short name T655
Test name
Test status
Simulation time 52005476 ps
CPU time 2.65 seconds
Started Jul 01 12:47:27 PM PDT 24
Finished Jul 01 12:47:31 PM PDT 24
Peak memory 232624 kb
Host smart-0f736cc1-0c63-4ec0-a0de-018c3c060b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140560715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1140560715
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3036820881
Short name T903
Test name
Test status
Simulation time 36773549 ps
CPU time 2.68 seconds
Started Jul 01 12:47:28 PM PDT 24
Finished Jul 01 12:47:32 PM PDT 24
Peak memory 232672 kb
Host smart-4ce90d02-1d9d-4c7d-8c1d-6a70ef1530d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036820881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3036820881
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3569770361
Short name T787
Test name
Test status
Simulation time 474113897 ps
CPU time 4.74 seconds
Started Jul 01 12:47:27 PM PDT 24
Finished Jul 01 12:47:33 PM PDT 24
Peak memory 227796 kb
Host smart-db322c18-b7bb-47e1-8590-199ccbea5e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569770361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3569770361
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3604894479
Short name T604
Test name
Test status
Simulation time 456314070 ps
CPU time 4.54 seconds
Started Jul 01 12:47:28 PM PDT 24
Finished Jul 01 12:47:34 PM PDT 24
Peak memory 219364 kb
Host smart-ed4bc635-d8a8-4e03-95e6-a4874952d975
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3604894479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3604894479
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2307594220
Short name T286
Test name
Test status
Simulation time 9248688948 ps
CPU time 115.59 seconds
Started Jul 01 12:47:31 PM PDT 24
Finished Jul 01 12:49:28 PM PDT 24
Peak memory 265748 kb
Host smart-3e6acfb7-747b-4986-8b12-e91c2ae27231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307594220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2307594220
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.446418122
Short name T14
Test name
Test status
Simulation time 4713444249 ps
CPU time 22.8 seconds
Started Jul 01 12:47:23 PM PDT 24
Finished Jul 01 12:47:49 PM PDT 24
Peak memory 216276 kb
Host smart-3989251d-3db2-45ab-8dfd-95c5d8a12101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446418122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.446418122
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2601520876
Short name T405
Test name
Test status
Simulation time 324145506 ps
CPU time 2.11 seconds
Started Jul 01 12:47:23 PM PDT 24
Finished Jul 01 12:47:29 PM PDT 24
Peak memory 216100 kb
Host smart-6b354ebb-e4b3-43e0-ba39-b73ff49fe7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601520876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2601520876
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1331772660
Short name T734
Test name
Test status
Simulation time 105258098 ps
CPU time 1.51 seconds
Started Jul 01 12:47:28 PM PDT 24
Finished Jul 01 12:47:31 PM PDT 24
Peak memory 217060 kb
Host smart-697c30e5-1bed-42b9-9fba-aeedbc91f15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331772660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1331772660
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2193579817
Short name T795
Test name
Test status
Simulation time 84934436 ps
CPU time 0.8 seconds
Started Jul 01 12:47:29 PM PDT 24
Finished Jul 01 12:47:31 PM PDT 24
Peak memory 205944 kb
Host smart-95891adc-03bd-4486-ad36-5c65a46f109f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193579817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2193579817
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3348571536
Short name T349
Test name
Test status
Simulation time 540666565 ps
CPU time 5.08 seconds
Started Jul 01 12:47:28 PM PDT 24
Finished Jul 01 12:47:34 PM PDT 24
Peak memory 224428 kb
Host smart-fc6fba5c-869e-48aa-b6fc-faf0090e4672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348571536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3348571536
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3202224050
Short name T571
Test name
Test status
Simulation time 72307577 ps
CPU time 0.69 seconds
Started Jul 01 12:47:38 PM PDT 24
Finished Jul 01 12:47:40 PM PDT 24
Peak memory 205524 kb
Host smart-c8f1ee5c-2825-4872-9e7a-1e6a5f8d5e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202224050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3202224050
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.587007318
Short name T430
Test name
Test status
Simulation time 35673586 ps
CPU time 2.48 seconds
Started Jul 01 12:47:38 PM PDT 24
Finished Jul 01 12:47:42 PM PDT 24
Peak memory 232692 kb
Host smart-9fbca1a2-6ee4-43e2-a485-1661e72233dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587007318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.587007318
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3333197010
Short name T495
Test name
Test status
Simulation time 52625753 ps
CPU time 0.75 seconds
Started Jul 01 12:47:37 PM PDT 24
Finished Jul 01 12:47:38 PM PDT 24
Peak memory 206656 kb
Host smart-dea59a2f-8c24-4e8a-afe9-90f3a7a63279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333197010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3333197010
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.161372167
Short name T865
Test name
Test status
Simulation time 10772572876 ps
CPU time 105.58 seconds
Started Jul 01 12:47:38 PM PDT 24
Finished Jul 01 12:49:25 PM PDT 24
Peak memory 234308 kb
Host smart-93ce4775-c31d-4c8f-a52e-df11925b2b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161372167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.161372167
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2319174539
Short name T50
Test name
Test status
Simulation time 18155488815 ps
CPU time 60.98 seconds
Started Jul 01 12:47:37 PM PDT 24
Finished Jul 01 12:48:39 PM PDT 24
Peak memory 249280 kb
Host smart-db767086-5c71-42ab-af3e-20e275541b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319174539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2319174539
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4191327488
Short name T829
Test name
Test status
Simulation time 5244813904 ps
CPU time 22.15 seconds
Started Jul 01 12:47:40 PM PDT 24
Finished Jul 01 12:48:03 PM PDT 24
Peak memory 238924 kb
Host smart-a21ee100-a454-4e43-814c-889067e6789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191327488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4191327488
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2966799631
Short name T928
Test name
Test status
Simulation time 5413796439 ps
CPU time 30.5 seconds
Started Jul 01 12:47:39 PM PDT 24
Finished Jul 01 12:48:11 PM PDT 24
Peak memory 251944 kb
Host smart-b692fd3d-6ba3-4e08-867c-582ef027d5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966799631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2966799631
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2891037942
Short name T466
Test name
Test status
Simulation time 3086827142 ps
CPU time 23.14 seconds
Started Jul 01 12:47:33 PM PDT 24
Finished Jul 01 12:47:57 PM PDT 24
Peak memory 232784 kb
Host smart-2b7989e7-4a07-4e7d-a134-fcd2cf3e39ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891037942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2891037942
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.920557810
Short name T340
Test name
Test status
Simulation time 32052442226 ps
CPU time 52.82 seconds
Started Jul 01 12:47:39 PM PDT 24
Finished Jul 01 12:48:33 PM PDT 24
Peak memory 232896 kb
Host smart-32740f32-48a3-4021-916c-266a533804d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920557810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.920557810
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1038162061
Short name T868
Test name
Test status
Simulation time 13280166619 ps
CPU time 9.1 seconds
Started Jul 01 12:47:31 PM PDT 24
Finished Jul 01 12:47:41 PM PDT 24
Peak memory 224472 kb
Host smart-9ae0b088-fb80-442e-9f52-6b304ad2ef3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038162061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1038162061
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.80742696
Short name T700
Test name
Test status
Simulation time 342518370 ps
CPU time 3.76 seconds
Started Jul 01 12:47:39 PM PDT 24
Finished Jul 01 12:47:44 PM PDT 24
Peak memory 232676 kb
Host smart-0a3ffbb3-8705-4e4a-a3af-40420ee33b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80742696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.80742696
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1312585334
Short name T145
Test name
Test status
Simulation time 807564431 ps
CPU time 7.29 seconds
Started Jul 01 12:47:40 PM PDT 24
Finished Jul 01 12:47:48 PM PDT 24
Peak memory 221948 kb
Host smart-1d988193-c8b8-4120-896b-bfb36febaffe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1312585334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1312585334
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3346094229
Short name T212
Test name
Test status
Simulation time 5853142369 ps
CPU time 80.86 seconds
Started Jul 01 12:47:37 PM PDT 24
Finished Jul 01 12:48:59 PM PDT 24
Peak memory 257108 kb
Host smart-f36cc631-3c79-4c2b-8df2-f3e4f9db109c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346094229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3346094229
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1979098549
Short name T891
Test name
Test status
Simulation time 13862121544 ps
CPU time 20.95 seconds
Started Jul 01 12:47:33 PM PDT 24
Finished Jul 01 12:47:54 PM PDT 24
Peak memory 220680 kb
Host smart-3ac44441-eb4c-429c-aefa-37786f487d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979098549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1979098549
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1061179254
Short name T344
Test name
Test status
Simulation time 20430361391 ps
CPU time 16.22 seconds
Started Jul 01 12:47:33 PM PDT 24
Finished Jul 01 12:47:50 PM PDT 24
Peak memory 216384 kb
Host smart-c8a9923e-bad2-4da2-921a-b3a25a839503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061179254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1061179254
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3118764679
Short name T935
Test name
Test status
Simulation time 33755264 ps
CPU time 0.7 seconds
Started Jul 01 12:47:32 PM PDT 24
Finished Jul 01 12:47:33 PM PDT 24
Peak memory 205684 kb
Host smart-86a770fb-01bd-4fdc-a050-ba33458cc747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118764679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3118764679
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.603625718
Short name T371
Test name
Test status
Simulation time 11338523 ps
CPU time 0.69 seconds
Started Jul 01 12:47:39 PM PDT 24
Finished Jul 01 12:47:41 PM PDT 24
Peak memory 205688 kb
Host smart-bdc3ec86-a5eb-4e34-91e6-55a29a04f3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603625718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.603625718
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2537610337
Short name T674
Test name
Test status
Simulation time 629362091 ps
CPU time 4.34 seconds
Started Jul 01 12:47:34 PM PDT 24
Finished Jul 01 12:47:39 PM PDT 24
Peak memory 232636 kb
Host smart-47bfc02d-edca-4d7f-b7f4-cba8462c58ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537610337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2537610337
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1114843943
Short name T588
Test name
Test status
Simulation time 14372917 ps
CPU time 0.72 seconds
Started Jul 01 12:47:43 PM PDT 24
Finished Jul 01 12:47:44 PM PDT 24
Peak memory 205888 kb
Host smart-4555aff9-608b-4c8a-a27d-62f7528add46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114843943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1114843943
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2192765641
Short name T930
Test name
Test status
Simulation time 1306108885 ps
CPU time 5.36 seconds
Started Jul 01 12:47:41 PM PDT 24
Finished Jul 01 12:47:47 PM PDT 24
Peak memory 232652 kb
Host smart-a9c1c936-9edb-434a-b4c6-bbc3a3a61402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192765641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2192765641
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2390742396
Short name T906
Test name
Test status
Simulation time 47426229 ps
CPU time 0.8 seconds
Started Jul 01 12:47:37 PM PDT 24
Finished Jul 01 12:47:38 PM PDT 24
Peak memory 206912 kb
Host smart-897eebbf-3557-4b20-9675-68ffbdeaa66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390742396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2390742396
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3177160744
Short name T276
Test name
Test status
Simulation time 123006180404 ps
CPU time 97.7 seconds
Started Jul 01 12:47:41 PM PDT 24
Finished Jul 01 12:49:20 PM PDT 24
Peak memory 249204 kb
Host smart-87cce133-7aa6-41fd-a08f-c0dfb98c598a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177160744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3177160744
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2869752734
Short name T300
Test name
Test status
Simulation time 5680803211 ps
CPU time 28.08 seconds
Started Jul 01 12:47:44 PM PDT 24
Finished Jul 01 12:48:13 PM PDT 24
Peak memory 239504 kb
Host smart-03a395fa-af92-407b-8b25-23fc26aa5872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869752734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2869752734
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.400008173
Short name T812
Test name
Test status
Simulation time 436430672 ps
CPU time 2.86 seconds
Started Jul 01 12:47:42 PM PDT 24
Finished Jul 01 12:47:46 PM PDT 24
Peak memory 217476 kb
Host smart-3d48bf11-a1b6-41dc-8f20-95ff78b04097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400008173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.400008173
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2489784081
Short name T320
Test name
Test status
Simulation time 329044428 ps
CPU time 2.72 seconds
Started Jul 01 12:47:41 PM PDT 24
Finished Jul 01 12:47:44 PM PDT 24
Peak memory 224508 kb
Host smart-55c00046-42a8-4214-bebf-cfd2a2695ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489784081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2489784081
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3923278175
Short name T199
Test name
Test status
Simulation time 9256628216 ps
CPU time 15.77 seconds
Started Jul 01 12:47:45 PM PDT 24
Finished Jul 01 12:48:01 PM PDT 24
Peak memory 236160 kb
Host smart-89843d35-58eb-42d1-b5fe-49ed7e8e5ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923278175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3923278175
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3536828401
Short name T191
Test name
Test status
Simulation time 301496843 ps
CPU time 5.76 seconds
Started Jul 01 12:47:39 PM PDT 24
Finished Jul 01 12:47:46 PM PDT 24
Peak memory 232636 kb
Host smart-f3fbd1e3-50d5-44f9-81ee-6ab2007c7bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536828401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3536828401
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.720685967
Short name T931
Test name
Test status
Simulation time 2498889460 ps
CPU time 11.71 seconds
Started Jul 01 12:47:37 PM PDT 24
Finished Jul 01 12:47:50 PM PDT 24
Peak memory 232760 kb
Host smart-037531c9-9c72-4449-ab50-7010659a22e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720685967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.720685967
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.499945156
Short name T989
Test name
Test status
Simulation time 40650360 ps
CPU time 2.48 seconds
Started Jul 01 12:47:37 PM PDT 24
Finished Jul 01 12:47:40 PM PDT 24
Peak memory 232624 kb
Host smart-14a71070-104c-4a08-b3fd-1617ee956cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499945156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.499945156
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3777841243
Short name T752
Test name
Test status
Simulation time 30430727 ps
CPU time 2.62 seconds
Started Jul 01 12:47:37 PM PDT 24
Finished Jul 01 12:47:41 PM PDT 24
Peak memory 232264 kb
Host smart-796d5b47-f0d2-48c8-b030-c64d05467b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777841243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3777841243
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.214749156
Short name T525
Test name
Test status
Simulation time 1762007633 ps
CPU time 9.24 seconds
Started Jul 01 12:47:46 PM PDT 24
Finished Jul 01 12:47:56 PM PDT 24
Peak memory 222176 kb
Host smart-130584cf-ce0f-41f0-bda8-ed2af03548e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=214749156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.214749156
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2977356752
Short name T867
Test name
Test status
Simulation time 1538981363 ps
CPU time 23.45 seconds
Started Jul 01 12:47:38 PM PDT 24
Finished Jul 01 12:48:03 PM PDT 24
Peak memory 216392 kb
Host smart-18a9fb66-2e5d-4d6c-85b7-f579300d528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977356752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2977356752
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2022941064
Short name T302
Test name
Test status
Simulation time 4830506033 ps
CPU time 5.38 seconds
Started Jul 01 12:47:38 PM PDT 24
Finished Jul 01 12:47:45 PM PDT 24
Peak memory 216308 kb
Host smart-b789d3aa-850c-4257-8d01-c1616bc2dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022941064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2022941064
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.360178817
Short name T446
Test name
Test status
Simulation time 60142273 ps
CPU time 1.44 seconds
Started Jul 01 12:47:38 PM PDT 24
Finished Jul 01 12:47:40 PM PDT 24
Peak memory 208012 kb
Host smart-3029857b-1e2d-4654-8710-945b8df9b415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360178817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.360178817
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1576000963
Short name T401
Test name
Test status
Simulation time 151952934 ps
CPU time 0.8 seconds
Started Jul 01 12:47:38 PM PDT 24
Finished Jul 01 12:47:40 PM PDT 24
Peak memory 205948 kb
Host smart-e743749b-1025-401f-9fd8-31269c942376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576000963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1576000963
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2452703461
Short name T743
Test name
Test status
Simulation time 320772489 ps
CPU time 2.19 seconds
Started Jul 01 12:47:41 PM PDT 24
Finished Jul 01 12:47:45 PM PDT 24
Peak memory 224184 kb
Host smart-500a52fa-f3ea-41d2-bd51-112d12315b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452703461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2452703461
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1524784132
Short name T676
Test name
Test status
Simulation time 48761978 ps
CPU time 0.76 seconds
Started Jul 01 12:47:48 PM PDT 24
Finished Jul 01 12:47:49 PM PDT 24
Peak memory 205772 kb
Host smart-020af5f5-bb41-492d-82ae-9c086f206b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524784132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1524784132
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3185656661
Short name T183
Test name
Test status
Simulation time 116484769 ps
CPU time 2.32 seconds
Started Jul 01 12:47:47 PM PDT 24
Finished Jul 01 12:47:50 PM PDT 24
Peak memory 224632 kb
Host smart-fdb5d80c-7d17-4272-8442-331b6753b51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185656661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3185656661
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.66914942
Short name T761
Test name
Test status
Simulation time 17955742 ps
CPU time 0.76 seconds
Started Jul 01 12:47:42 PM PDT 24
Finished Jul 01 12:47:43 PM PDT 24
Peak memory 206904 kb
Host smart-b072ba5a-b329-4c50-b424-90cf1f26d486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66914942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.66914942
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2165520206
Short name T434
Test name
Test status
Simulation time 26653103211 ps
CPU time 232.85 seconds
Started Jul 01 12:47:48 PM PDT 24
Finished Jul 01 12:51:42 PM PDT 24
Peak memory 249244 kb
Host smart-1641e366-f1eb-4079-ad0f-55cfdde088bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165520206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2165520206
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3925935534
Short name T288
Test name
Test status
Simulation time 5860237692 ps
CPU time 24.01 seconds
Started Jul 01 12:47:42 PM PDT 24
Finished Jul 01 12:48:07 PM PDT 24
Peak memory 232764 kb
Host smart-c601370d-9b71-4d3f-b997-281001772eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925935534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3925935534
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3531793779
Short name T1008
Test name
Test status
Simulation time 2889975811 ps
CPU time 21.46 seconds
Started Jul 01 12:47:47 PM PDT 24
Finished Jul 01 12:48:09 PM PDT 24
Peak memory 249336 kb
Host smart-fc80de38-f769-48c8-a33a-c8cfbeb59baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531793779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3531793779
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2395516236
Short name T460
Test name
Test status
Simulation time 3339446538 ps
CPU time 17.34 seconds
Started Jul 01 12:47:46 PM PDT 24
Finished Jul 01 12:48:03 PM PDT 24
Peak memory 232744 kb
Host smart-83319a1a-5987-4ab6-81d6-34c75179b5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395516236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2395516236
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2166695618
Short name T659
Test name
Test status
Simulation time 6093324943 ps
CPU time 13.41 seconds
Started Jul 01 12:47:42 PM PDT 24
Finished Jul 01 12:47:56 PM PDT 24
Peak memory 224740 kb
Host smart-ac737c3b-0ed0-42a7-9818-27d8a1bd41b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166695618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2166695618
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.347706718
Short name T252
Test name
Test status
Simulation time 3145829004 ps
CPU time 7.36 seconds
Started Jul 01 12:47:47 PM PDT 24
Finished Jul 01 12:47:55 PM PDT 24
Peak memory 232904 kb
Host smart-aa7c2f9e-b734-47e8-9f10-0a701dad61c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347706718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.347706718
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2237332629
Short name T692
Test name
Test status
Simulation time 825476232 ps
CPU time 11.85 seconds
Started Jul 01 12:47:41 PM PDT 24
Finished Jul 01 12:47:54 PM PDT 24
Peak memory 220212 kb
Host smart-9000aa13-518a-430a-b139-e2fdb3299ee2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2237332629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2237332629
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1384240783
Short name T29
Test name
Test status
Simulation time 26676855837 ps
CPU time 254.8 seconds
Started Jul 01 12:47:51 PM PDT 24
Finished Jul 01 12:52:06 PM PDT 24
Peak memory 249300 kb
Host smart-e0785f12-c2fc-47c8-bc50-a45d87d76163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384240783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1384240783
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1664899011
Short name T435
Test name
Test status
Simulation time 634700006 ps
CPU time 6.56 seconds
Started Jul 01 12:47:42 PM PDT 24
Finished Jul 01 12:47:50 PM PDT 24
Peak memory 218820 kb
Host smart-3153a402-af53-4316-b35b-9b089530b924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664899011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1664899011
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1876925158
Short name T450
Test name
Test status
Simulation time 2605515657 ps
CPU time 6.98 seconds
Started Jul 01 12:47:41 PM PDT 24
Finished Jul 01 12:47:49 PM PDT 24
Peak memory 216300 kb
Host smart-cf118498-75a5-4e88-96eb-a7ea020fe1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876925158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1876925158
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4261188275
Short name T548
Test name
Test status
Simulation time 759790109 ps
CPU time 2.29 seconds
Started Jul 01 12:47:44 PM PDT 24
Finished Jul 01 12:47:47 PM PDT 24
Peak memory 216212 kb
Host smart-0b06c766-8b98-4e4a-a6a9-bab1eea1c27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261188275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4261188275
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2493020769
Short name T557
Test name
Test status
Simulation time 80707069 ps
CPU time 0.72 seconds
Started Jul 01 12:47:42 PM PDT 24
Finished Jul 01 12:47:44 PM PDT 24
Peak memory 205896 kb
Host smart-fc1c1ac0-ec77-4b69-aab3-17490c3765c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493020769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2493020769
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3586276704
Short name T229
Test name
Test status
Simulation time 215437051 ps
CPU time 2.65 seconds
Started Jul 01 12:47:43 PM PDT 24
Finished Jul 01 12:47:46 PM PDT 24
Peak memory 224344 kb
Host smart-9ae8ce33-02bc-42d6-b0b0-86f541f2b1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586276704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3586276704
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.610256293
Short name T973
Test name
Test status
Simulation time 11350171 ps
CPU time 0.72 seconds
Started Jul 01 12:47:53 PM PDT 24
Finished Jul 01 12:47:54 PM PDT 24
Peak memory 205532 kb
Host smart-fce30617-dd8f-4be4-a91b-0cf6ae144077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610256293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.610256293
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1005660107
Short name T893
Test name
Test status
Simulation time 1506496172 ps
CPU time 9.17 seconds
Started Jul 01 12:47:52 PM PDT 24
Finished Jul 01 12:48:01 PM PDT 24
Peak memory 224440 kb
Host smart-3f6fe518-f222-41ab-9f72-ddcf6d58f462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005660107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1005660107
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3028488809
Short name T630
Test name
Test status
Simulation time 41345210 ps
CPU time 0.72 seconds
Started Jul 01 12:47:47 PM PDT 24
Finished Jul 01 12:47:48 PM PDT 24
Peak memory 205592 kb
Host smart-5c836f18-96fe-4608-a973-7a654d6672c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028488809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3028488809
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1162026013
Short name T71
Test name
Test status
Simulation time 53382966 ps
CPU time 0.77 seconds
Started Jul 01 12:47:55 PM PDT 24
Finished Jul 01 12:47:56 PM PDT 24
Peak memory 215700 kb
Host smart-3f31cea6-c999-4f02-97bc-3016c97b1afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162026013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1162026013
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3395670262
Short name T45
Test name
Test status
Simulation time 44390545451 ps
CPU time 89.11 seconds
Started Jul 01 12:47:52 PM PDT 24
Finished Jul 01 12:49:22 PM PDT 24
Peak memory 224612 kb
Host smart-b6adaf26-3ed1-4a3a-a5b5-f19b92431451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395670262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3395670262
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3052556984
Short name T559
Test name
Test status
Simulation time 19994055203 ps
CPU time 112.83 seconds
Started Jul 01 12:47:52 PM PDT 24
Finished Jul 01 12:49:46 PM PDT 24
Peak memory 237176 kb
Host smart-3a8200b9-83f9-4bfe-a411-6d4c1c1a47a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052556984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3052556984
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2868223320
Short name T10
Test name
Test status
Simulation time 8260627198 ps
CPU time 30.54 seconds
Started Jul 01 12:47:53 PM PDT 24
Finished Jul 01 12:48:24 PM PDT 24
Peak memory 232820 kb
Host smart-3ce3bef6-ce56-4196-8fd7-0d5f6bbd2f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868223320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2868223320
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1394334332
Short name T954
Test name
Test status
Simulation time 3492292832 ps
CPU time 13.48 seconds
Started Jul 01 12:47:53 PM PDT 24
Finished Jul 01 12:48:08 PM PDT 24
Peak memory 240052 kb
Host smart-206b1b62-7995-4425-bf8c-cb759e4e5eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394334332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1394334332
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.56789077
Short name T215
Test name
Test status
Simulation time 3608088825 ps
CPU time 13.62 seconds
Started Jul 01 12:47:48 PM PDT 24
Finished Jul 01 12:48:02 PM PDT 24
Peak memory 224476 kb
Host smart-51710625-588d-4951-861c-8c0e8c7c9327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56789077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.56789077
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3906029700
Short name T988
Test name
Test status
Simulation time 9842836088 ps
CPU time 83.85 seconds
Started Jul 01 12:47:47 PM PDT 24
Finished Jul 01 12:49:12 PM PDT 24
Peak memory 233944 kb
Host smart-b05b4723-e1fc-4a6e-bc16-1a460ad065e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906029700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3906029700
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4095766811
Short name T979
Test name
Test status
Simulation time 3977127622 ps
CPU time 11.92 seconds
Started Jul 01 12:47:49 PM PDT 24
Finished Jul 01 12:48:01 PM PDT 24
Peak memory 224560 kb
Host smart-ec234af6-e32a-4389-b11b-14e6abcdfac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095766811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4095766811
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2410611292
Short name T505
Test name
Test status
Simulation time 5390751760 ps
CPU time 5.91 seconds
Started Jul 01 12:47:47 PM PDT 24
Finished Jul 01 12:47:54 PM PDT 24
Peak memory 224616 kb
Host smart-5d166fed-649f-4f26-91d4-c7ba2b1cb763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410611292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2410611292
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2907942062
Short name T134
Test name
Test status
Simulation time 141473262 ps
CPU time 3.47 seconds
Started Jul 01 12:47:53 PM PDT 24
Finished Jul 01 12:47:58 PM PDT 24
Peak memory 223152 kb
Host smart-9d69f0c5-3fcb-48f5-8636-48e7fcf54042
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2907942062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2907942062
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3430977814
Short name T658
Test name
Test status
Simulation time 122202329665 ps
CPU time 547.02 seconds
Started Jul 01 12:47:53 PM PDT 24
Finished Jul 01 12:57:02 PM PDT 24
Peak memory 265676 kb
Host smart-f0610913-c843-400d-9c06-b9f498a09da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430977814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3430977814
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1399996504
Short name T1
Test name
Test status
Simulation time 3431131925 ps
CPU time 18.3 seconds
Started Jul 01 12:47:48 PM PDT 24
Finished Jul 01 12:48:07 PM PDT 24
Peak memory 216336 kb
Host smart-67882e7b-ba98-4d53-a878-44abc70475d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399996504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1399996504
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3496183605
Short name T603
Test name
Test status
Simulation time 909389228 ps
CPU time 4.74 seconds
Started Jul 01 12:47:47 PM PDT 24
Finished Jul 01 12:47:53 PM PDT 24
Peak memory 216236 kb
Host smart-c32c3fed-6014-4a0e-9456-81df61d16b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496183605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3496183605
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.462770028
Short name T690
Test name
Test status
Simulation time 82704081 ps
CPU time 1.71 seconds
Started Jul 01 12:47:48 PM PDT 24
Finished Jul 01 12:47:50 PM PDT 24
Peak memory 216168 kb
Host smart-0fd9cbaf-b4ca-4bf0-9f47-791b82a58d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462770028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.462770028
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.640762106
Short name T359
Test name
Test status
Simulation time 16270361 ps
CPU time 0.7 seconds
Started Jul 01 12:47:46 PM PDT 24
Finished Jul 01 12:47:48 PM PDT 24
Peak memory 206004 kb
Host smart-735196ac-fb07-4c3c-acda-85981d22a646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640762106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.640762106
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.389230424
Short name T555
Test name
Test status
Simulation time 3772053309 ps
CPU time 11.6 seconds
Started Jul 01 12:47:52 PM PDT 24
Finished Jul 01 12:48:05 PM PDT 24
Peak memory 224588 kb
Host smart-24afff8f-6bc9-46cb-892b-dd038112ae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389230424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.389230424
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.273482141
Short name T607
Test name
Test status
Simulation time 20591978 ps
CPU time 0.73 seconds
Started Jul 01 12:48:04 PM PDT 24
Finished Jul 01 12:48:06 PM PDT 24
Peak memory 205560 kb
Host smart-51249312-a94c-43c3-88d5-9ca6174bdcb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273482141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.273482141
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2704718009
Short name T230
Test name
Test status
Simulation time 417040146 ps
CPU time 4.13 seconds
Started Jul 01 12:47:58 PM PDT 24
Finished Jul 01 12:48:03 PM PDT 24
Peak memory 232684 kb
Host smart-ad5c6654-29b4-4c9e-90f3-1be949659bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704718009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2704718009
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1003436917
Short name T497
Test name
Test status
Simulation time 28323022 ps
CPU time 0.77 seconds
Started Jul 01 12:47:52 PM PDT 24
Finished Jul 01 12:47:53 PM PDT 24
Peak memory 205580 kb
Host smart-00f7a7c3-4810-4d75-a2b6-bd9bde7851b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003436917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1003436917
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3423860393
Short name T168
Test name
Test status
Simulation time 116014616678 ps
CPU time 235.78 seconds
Started Jul 01 12:47:57 PM PDT 24
Finished Jul 01 12:51:53 PM PDT 24
Peak memory 256944 kb
Host smart-7ed36d27-004c-4a97-b65d-bf970af326e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423860393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3423860393
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3814451843
Short name T189
Test name
Test status
Simulation time 8196939572 ps
CPU time 85.01 seconds
Started Jul 01 12:48:03 PM PDT 24
Finished Jul 01 12:49:29 PM PDT 24
Peak memory 249032 kb
Host smart-533acb9e-ed48-4ae8-86be-38793f07f02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814451843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3814451843
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3167714216
Short name T661
Test name
Test status
Simulation time 248616207 ps
CPU time 5.24 seconds
Started Jul 01 12:48:00 PM PDT 24
Finished Jul 01 12:48:05 PM PDT 24
Peak memory 224400 kb
Host smart-35bb0ac1-ff61-4b71-80a3-db3b63eef077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167714216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3167714216
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1226181276
Short name T813
Test name
Test status
Simulation time 4002575132 ps
CPU time 9.85 seconds
Started Jul 01 12:47:58 PM PDT 24
Finished Jul 01 12:48:08 PM PDT 24
Peak memory 232796 kb
Host smart-9340b539-7b29-4b8e-b52b-c4a5256df8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226181276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1226181276
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1645232732
Short name T273
Test name
Test status
Simulation time 2031560495 ps
CPU time 10.75 seconds
Started Jul 01 12:47:58 PM PDT 24
Finished Jul 01 12:48:09 PM PDT 24
Peak memory 248692 kb
Host smart-b2333734-631f-4cd4-9666-78aae8273eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645232732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1645232732
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2769658729
Short name T933
Test name
Test status
Simulation time 701021298 ps
CPU time 3.59 seconds
Started Jul 01 12:47:54 PM PDT 24
Finished Jul 01 12:47:58 PM PDT 24
Peak memory 232720 kb
Host smart-eb582b93-9499-4fdb-9f72-b874defbf532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769658729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2769658729
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.838648590
Short name T976
Test name
Test status
Simulation time 467345705 ps
CPU time 8.57 seconds
Started Jul 01 12:47:57 PM PDT 24
Finished Jul 01 12:48:07 PM PDT 24
Peak memory 219784 kb
Host smart-41f8614f-6a2a-488a-8ddb-bd40afa1f1c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=838648590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.838648590
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1794904964
Short name T141
Test name
Test status
Simulation time 79381575060 ps
CPU time 394.45 seconds
Started Jul 01 12:48:04 PM PDT 24
Finished Jul 01 12:54:40 PM PDT 24
Peak memory 265668 kb
Host smart-0c682105-038c-441a-b220-31a937b7fb36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794904964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1794904964
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.202907390
Short name T725
Test name
Test status
Simulation time 21646008 ps
CPU time 0.75 seconds
Started Jul 01 12:47:53 PM PDT 24
Finished Jul 01 12:47:55 PM PDT 24
Peak memory 205728 kb
Host smart-c61aaa36-7053-4ddf-b7c6-142f0f3eb8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202907390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.202907390
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.335336255
Short name T513
Test name
Test status
Simulation time 1173503263 ps
CPU time 3.16 seconds
Started Jul 01 12:47:55 PM PDT 24
Finished Jul 01 12:47:59 PM PDT 24
Peak memory 216176 kb
Host smart-4438a208-91fe-4c25-b9c7-89407cfaeae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335336255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.335336255
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3057339135
Short name T161
Test name
Test status
Simulation time 277104312 ps
CPU time 1.48 seconds
Started Jul 01 12:47:53 PM PDT 24
Finished Jul 01 12:47:55 PM PDT 24
Peak memory 216180 kb
Host smart-6bf14128-bfe9-4ea3-acd3-4cffc0b64f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057339135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3057339135
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3934695336
Short name T923
Test name
Test status
Simulation time 40069334 ps
CPU time 0.85 seconds
Started Jul 01 12:47:52 PM PDT 24
Finished Jul 01 12:47:53 PM PDT 24
Peak memory 206000 kb
Host smart-84f54bde-829c-471f-8ac6-8e7b62e6b804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934695336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3934695336
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.951102608
Short name T957
Test name
Test status
Simulation time 51595513849 ps
CPU time 13.66 seconds
Started Jul 01 12:47:58 PM PDT 24
Finished Jul 01 12:48:12 PM PDT 24
Peak memory 240912 kb
Host smart-81dd807e-4bb0-41fe-a801-eee5279a15e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951102608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.951102608
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2836529880
Short name T875
Test name
Test status
Simulation time 21119484 ps
CPU time 0.71 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:48:14 PM PDT 24
Peak memory 205556 kb
Host smart-4dda79d7-9aca-4436-919c-3c2cdd2426b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836529880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2836529880
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.923197227
Short name T339
Test name
Test status
Simulation time 831364876 ps
CPU time 5.05 seconds
Started Jul 01 12:48:05 PM PDT 24
Finished Jul 01 12:48:11 PM PDT 24
Peak memory 232708 kb
Host smart-12793d44-2409-4ca7-a125-8ce6646fed96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923197227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.923197227
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.869353953
Short name T501
Test name
Test status
Simulation time 69835008 ps
CPU time 0.84 seconds
Started Jul 01 12:48:04 PM PDT 24
Finished Jul 01 12:48:06 PM PDT 24
Peak memory 205608 kb
Host smart-3bf982d4-aec9-406d-aad2-32ac2a749a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869353953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.869353953
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3312110814
Short name T949
Test name
Test status
Simulation time 2098252272 ps
CPU time 15.91 seconds
Started Jul 01 12:48:05 PM PDT 24
Finished Jul 01 12:48:22 PM PDT 24
Peak memory 240904 kb
Host smart-267f693b-b9b0-4258-960d-7449dfe9dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312110814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3312110814
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.4236478610
Short name T691
Test name
Test status
Simulation time 136873919764 ps
CPU time 269.42 seconds
Started Jul 01 12:48:05 PM PDT 24
Finished Jul 01 12:52:36 PM PDT 24
Peak memory 265652 kb
Host smart-c238a98e-f9b4-4329-9842-7e4cee2653dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236478610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4236478610
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3552903279
Short name T461
Test name
Test status
Simulation time 8681874146 ps
CPU time 38.76 seconds
Started Jul 01 12:48:05 PM PDT 24
Finished Jul 01 12:48:45 PM PDT 24
Peak memory 240464 kb
Host smart-efcb39da-2cc5-461b-bcce-38bcc32ec2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552903279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3552903279
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2838772122
Short name T373
Test name
Test status
Simulation time 2628517652 ps
CPU time 22.42 seconds
Started Jul 01 12:48:06 PM PDT 24
Finished Jul 01 12:48:30 PM PDT 24
Peak memory 249212 kb
Host smart-e665d0c4-cef1-4494-a7c0-4de70b5386ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838772122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2838772122
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1936569686
Short name T586
Test name
Test status
Simulation time 166133287 ps
CPU time 2.54 seconds
Started Jul 01 12:48:03 PM PDT 24
Finished Jul 01 12:48:06 PM PDT 24
Peak memory 232316 kb
Host smart-887dc781-f9e4-4c38-be54-2141ad21c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936569686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1936569686
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3056662508
Short name T545
Test name
Test status
Simulation time 1185161831 ps
CPU time 2.81 seconds
Started Jul 01 12:48:04 PM PDT 24
Finished Jul 01 12:48:08 PM PDT 24
Peak memory 224428 kb
Host smart-03bbba57-e071-4c32-a0ba-aecea40604b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056662508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3056662508
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1785532360
Short name T892
Test name
Test status
Simulation time 1697675790 ps
CPU time 6.15 seconds
Started Jul 01 12:48:03 PM PDT 24
Finished Jul 01 12:48:10 PM PDT 24
Peak memory 232720 kb
Host smart-02c5ddf8-f265-410b-92c4-ee18f3b53ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785532360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1785532360
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.938312402
Short name T693
Test name
Test status
Simulation time 746846632 ps
CPU time 5.24 seconds
Started Jul 01 12:48:04 PM PDT 24
Finished Jul 01 12:48:10 PM PDT 24
Peak memory 218852 kb
Host smart-555f6f9f-03cf-4b6b-90b4-7a238950a6ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=938312402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.938312402
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1377766755
Short name T3
Test name
Test status
Simulation time 103466931 ps
CPU time 1.12 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:48:14 PM PDT 24
Peak memory 207172 kb
Host smart-1ad14a36-15a1-4103-9327-d31c58071158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377766755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1377766755
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.941402715
Short name T718
Test name
Test status
Simulation time 4268317066 ps
CPU time 18.73 seconds
Started Jul 01 12:48:04 PM PDT 24
Finished Jul 01 12:48:24 PM PDT 24
Peak memory 216640 kb
Host smart-59e06a94-1bc2-4b67-a8c1-b8933811eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941402715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.941402715
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3183475840
Short name T653
Test name
Test status
Simulation time 18522868090 ps
CPU time 9.94 seconds
Started Jul 01 12:48:04 PM PDT 24
Finished Jul 01 12:48:15 PM PDT 24
Peak memory 216352 kb
Host smart-c97d88ef-677c-452f-b63c-30f2db0ff2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183475840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3183475840
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1565580544
Short name T532
Test name
Test status
Simulation time 55644898 ps
CPU time 0.87 seconds
Started Jul 01 12:48:05 PM PDT 24
Finished Jul 01 12:48:07 PM PDT 24
Peak memory 206012 kb
Host smart-227d92f3-1e6f-4483-9e52-d3ca4a62b44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565580544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1565580544
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2857387328
Short name T613
Test name
Test status
Simulation time 191735261 ps
CPU time 0.91 seconds
Started Jul 01 12:48:02 PM PDT 24
Finished Jul 01 12:48:04 PM PDT 24
Peak memory 206492 kb
Host smart-53c06461-2230-46ee-a115-886f286e5ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857387328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2857387328
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.393687480
Short name T782
Test name
Test status
Simulation time 7742429028 ps
CPU time 26.51 seconds
Started Jul 01 12:48:04 PM PDT 24
Finished Jul 01 12:48:31 PM PDT 24
Peak memory 233716 kb
Host smart-a0e7be58-ab05-47f0-b49f-b2a50d82aa3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393687480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.393687480
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1528825675
Short name T741
Test name
Test status
Simulation time 402295977 ps
CPU time 2.77 seconds
Started Jul 01 12:48:11 PM PDT 24
Finished Jul 01 12:48:14 PM PDT 24
Peak memory 232636 kb
Host smart-08d4f5e3-dc99-41ee-86c2-e5c2cd22d274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528825675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1528825675
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.211154561
Short name T800
Test name
Test status
Simulation time 100226964 ps
CPU time 0.75 seconds
Started Jul 01 12:48:11 PM PDT 24
Finished Jul 01 12:48:13 PM PDT 24
Peak memory 206628 kb
Host smart-e7257b18-5170-4520-8e5f-d7e484c976fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211154561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.211154561
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.166729882
Short name T272
Test name
Test status
Simulation time 11154537433 ps
CPU time 63.66 seconds
Started Jul 01 12:48:13 PM PDT 24
Finished Jul 01 12:49:18 PM PDT 24
Peak memory 256608 kb
Host smart-617ba314-9dd5-4324-a916-4ffbaeaf2175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166729882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.166729882
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1540644534
Short name T202
Test name
Test status
Simulation time 18211959997 ps
CPU time 83.96 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:49:37 PM PDT 24
Peak memory 256080 kb
Host smart-8216371e-d845-4b2d-8761-b1e74e4a7f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540644534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1540644534
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2326845817
Short name T284
Test name
Test status
Simulation time 8081584978 ps
CPU time 119.33 seconds
Started Jul 01 12:48:13 PM PDT 24
Finished Jul 01 12:50:14 PM PDT 24
Peak memory 265620 kb
Host smart-1f1b5d19-4f4d-4e9c-906e-20f27f3486b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326845817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2326845817
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1867257973
Short name T290
Test name
Test status
Simulation time 43021129599 ps
CPU time 79.22 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:49:32 PM PDT 24
Peak memory 249196 kb
Host smart-083e96aa-d1d7-4b12-bca3-b808216020b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867257973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1867257973
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1701882036
Short name T498
Test name
Test status
Simulation time 12722426952 ps
CPU time 94.89 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:49:48 PM PDT 24
Peak memory 251472 kb
Host smart-2daffebd-c9e1-4698-8b0d-53197943dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701882036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1701882036
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2627561606
Short name T308
Test name
Test status
Simulation time 1990093292 ps
CPU time 7.99 seconds
Started Jul 01 12:48:14 PM PDT 24
Finished Jul 01 12:48:23 PM PDT 24
Peak memory 224400 kb
Host smart-b1b15878-8bb3-48fa-8a73-ee07927a3efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627561606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2627561606
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.181487981
Short name T220
Test name
Test status
Simulation time 4981364190 ps
CPU time 16.75 seconds
Started Jul 01 12:48:10 PM PDT 24
Finished Jul 01 12:48:28 PM PDT 24
Peak memory 224648 kb
Host smart-ea6005b0-72ee-4408-954c-52addff92432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181487981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.181487981
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3765237394
Short name T818
Test name
Test status
Simulation time 39808464217 ps
CPU time 17.26 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:48:30 PM PDT 24
Peak memory 248960 kb
Host smart-9c1e32b4-2895-4aff-83c1-fbefff894f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765237394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3765237394
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1880788393
Short name T1005
Test name
Test status
Simulation time 266719619 ps
CPU time 4.54 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:48:18 PM PDT 24
Peak memory 232732 kb
Host smart-2eb2dd2b-fccd-488b-9d77-83908ee27c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880788393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1880788393
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1520640605
Short name T991
Test name
Test status
Simulation time 168772128 ps
CPU time 3.76 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:48:16 PM PDT 24
Peak memory 219320 kb
Host smart-97e03ef0-0612-4149-af70-8ef4ab00dd65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1520640605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1520640605
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.272715822
Short name T155
Test name
Test status
Simulation time 7165623998 ps
CPU time 108.82 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:50:02 PM PDT 24
Peak memory 254656 kb
Host smart-2b5d5f9f-8526-46d4-83df-a5f6253d89b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272715822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.272715822
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3668828702
Short name T771
Test name
Test status
Simulation time 9175290062 ps
CPU time 32.46 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:48:46 PM PDT 24
Peak memory 216352 kb
Host smart-0b0e5627-602b-46aa-97ee-0a3638ad7cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668828702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3668828702
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1772733049
Short name T132
Test name
Test status
Simulation time 573612013 ps
CPU time 4.92 seconds
Started Jul 01 12:48:11 PM PDT 24
Finished Jul 01 12:48:17 PM PDT 24
Peak memory 216128 kb
Host smart-04aa4223-710b-4f52-a2ef-dbc1aa267608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772733049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1772733049
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1570189659
Short name T685
Test name
Test status
Simulation time 195957761 ps
CPU time 0.95 seconds
Started Jul 01 12:48:12 PM PDT 24
Finished Jul 01 12:48:14 PM PDT 24
Peak memory 206968 kb
Host smart-0b68e3c9-555f-402e-b4c6-70fd044347ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570189659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1570189659
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1120205514
Short name T702
Test name
Test status
Simulation time 97625509 ps
CPU time 0.9 seconds
Started Jul 01 12:48:11 PM PDT 24
Finished Jul 01 12:48:13 PM PDT 24
Peak memory 206008 kb
Host smart-3c9bfc80-7a7c-4e93-a913-932bfcafc7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120205514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1120205514
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2902476184
Short name T399
Test name
Test status
Simulation time 2342683306 ps
CPU time 5.64 seconds
Started Jul 01 12:48:13 PM PDT 24
Finished Jul 01 12:48:20 PM PDT 24
Peak memory 224464 kb
Host smart-f4f8bf79-2225-4918-97df-e02ab7895b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902476184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2902476184
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3104389669
Short name T565
Test name
Test status
Simulation time 155466553 ps
CPU time 0.73 seconds
Started Jul 01 12:48:19 PM PDT 24
Finished Jul 01 12:48:21 PM PDT 24
Peak memory 205292 kb
Host smart-b9c8c500-6a1c-448c-9e15-b0b5d5f80d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104389669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3104389669
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2732518398
Short name T398
Test name
Test status
Simulation time 216602405 ps
CPU time 5.19 seconds
Started Jul 01 12:48:15 PM PDT 24
Finished Jul 01 12:48:21 PM PDT 24
Peak memory 232644 kb
Host smart-14b40187-13ce-4ef0-8636-9e8f47426826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732518398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2732518398
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.380097833
Short name T13
Test name
Test status
Simulation time 19590393 ps
CPU time 0.78 seconds
Started Jul 01 12:48:13 PM PDT 24
Finished Jul 01 12:48:15 PM PDT 24
Peak memory 206612 kb
Host smart-4cde2438-c000-4eab-9772-d66e89eb9821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380097833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.380097833
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.281725469
Short name T184
Test name
Test status
Simulation time 14389284411 ps
CPU time 51.88 seconds
Started Jul 01 12:48:15 PM PDT 24
Finished Jul 01 12:49:08 PM PDT 24
Peak memory 241040 kb
Host smart-7620735d-a9df-42b0-956c-99e2ae21f003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281725469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.281725469
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1309918621
Short name T960
Test name
Test status
Simulation time 7001046730 ps
CPU time 112.64 seconds
Started Jul 01 12:48:14 PM PDT 24
Finished Jul 01 12:50:08 PM PDT 24
Peak memory 249532 kb
Host smart-e3251bc6-64f9-4148-8fd5-5660c562fb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309918621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1309918621
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3409950034
Short name T634
Test name
Test status
Simulation time 83148125999 ps
CPU time 374.85 seconds
Started Jul 01 12:48:17 PM PDT 24
Finished Jul 01 12:54:33 PM PDT 24
Peak memory 255344 kb
Host smart-86bad89d-3e4e-4b74-aaf6-df38f5744f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409950034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3409950034
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1194913879
Short name T287
Test name
Test status
Simulation time 1252050418 ps
CPU time 22.08 seconds
Started Jul 01 12:48:24 PM PDT 24
Finished Jul 01 12:48:47 PM PDT 24
Peak memory 249096 kb
Host smart-69993f6f-572a-4d37-9972-2321396f103d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194913879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1194913879
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3515392826
Short name T72
Test name
Test status
Simulation time 232638936 ps
CPU time 5.35 seconds
Started Jul 01 12:48:17 PM PDT 24
Finished Jul 01 12:48:24 PM PDT 24
Peak memory 232640 kb
Host smart-400f87a2-9404-4874-b2db-69844027ae83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515392826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3515392826
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.189430213
Short name T400
Test name
Test status
Simulation time 13992129331 ps
CPU time 96.9 seconds
Started Jul 01 12:48:17 PM PDT 24
Finished Jul 01 12:49:54 PM PDT 24
Peak memory 232852 kb
Host smart-8dd68f46-b5bb-4e85-a531-08d727077820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189430213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.189430213
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.868519789
Short name T9
Test name
Test status
Simulation time 2749502694 ps
CPU time 7.91 seconds
Started Jul 01 12:48:18 PM PDT 24
Finished Jul 01 12:48:27 PM PDT 24
Peak memory 232828 kb
Host smart-dbe8e24a-c060-4b55-afa2-8363d535644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868519789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.868519789
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2440113012
Short name T886
Test name
Test status
Simulation time 25022587130 ps
CPU time 17.04 seconds
Started Jul 01 12:48:25 PM PDT 24
Finished Jul 01 12:48:42 PM PDT 24
Peak memory 232816 kb
Host smart-69290784-c2c0-4440-9617-138cd0008ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440113012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2440113012
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2514185478
Short name T821
Test name
Test status
Simulation time 3734323402 ps
CPU time 10.03 seconds
Started Jul 01 12:48:23 PM PDT 24
Finished Jul 01 12:48:34 PM PDT 24
Peak memory 222040 kb
Host smart-5000e72e-c395-4909-a0b4-b0425ee836c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2514185478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2514185478
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3875115217
Short name T606
Test name
Test status
Simulation time 40973734106 ps
CPU time 168.58 seconds
Started Jul 01 12:48:18 PM PDT 24
Finished Jul 01 12:51:07 PM PDT 24
Peak memory 273752 kb
Host smart-5d58991e-271a-44d8-b82b-09a7dbf5eb43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875115217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3875115217
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1874861084
Short name T737
Test name
Test status
Simulation time 7608522016 ps
CPU time 20.27 seconds
Started Jul 01 12:48:14 PM PDT 24
Finished Jul 01 12:48:35 PM PDT 24
Peak memory 216372 kb
Host smart-42f5f3f5-8bf4-4396-adbe-43e606609731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874861084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1874861084
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4143877595
Short name T772
Test name
Test status
Simulation time 5984088127 ps
CPU time 6.4 seconds
Started Jul 01 12:48:13 PM PDT 24
Finished Jul 01 12:48:21 PM PDT 24
Peak memory 216264 kb
Host smart-252eed03-c996-4820-a467-5942dfcc256b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143877595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4143877595
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3302816877
Short name T996
Test name
Test status
Simulation time 134093312 ps
CPU time 2.27 seconds
Started Jul 01 12:48:14 PM PDT 24
Finished Jul 01 12:48:18 PM PDT 24
Peak memory 216196 kb
Host smart-8fbbcd40-564a-4a2b-88ca-85ec9199be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302816877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3302816877
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.886409
Short name T402
Test name
Test status
Simulation time 68186732 ps
CPU time 0.87 seconds
Started Jul 01 12:48:15 PM PDT 24
Finished Jul 01 12:48:17 PM PDT 24
Peak memory 205944 kb
Host smart-816f6b64-db13-4621-8458-570584e2b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.886409
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1873782057
Short name T226
Test name
Test status
Simulation time 2901368497 ps
CPU time 4.18 seconds
Started Jul 01 12:48:17 PM PDT 24
Finished Jul 01 12:48:22 PM PDT 24
Peak memory 224588 kb
Host smart-fded1583-705e-4588-b2d3-1d5e3839bfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873782057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1873782057
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1664190802
Short name T391
Test name
Test status
Simulation time 23832114 ps
CPU time 0.71 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:46:48 PM PDT 24
Peak memory 204948 kb
Host smart-87c77690-7500-4646-a311-2e3f0328603a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664190802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
664190802
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1141014599
Short name T809
Test name
Test status
Simulation time 64983563 ps
CPU time 2.86 seconds
Started Jul 01 12:46:27 PM PDT 24
Finished Jul 01 12:46:31 PM PDT 24
Peak memory 232696 kb
Host smart-82e1f541-5931-43c3-ab0b-95a157ebc48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141014599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1141014599
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3766876687
Short name T760
Test name
Test status
Simulation time 15360005 ps
CPU time 0.73 seconds
Started Jul 01 12:46:21 PM PDT 24
Finished Jul 01 12:46:23 PM PDT 24
Peak memory 205520 kb
Host smart-6b2638e7-7cd7-4058-8872-619e4703dd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766876687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3766876687
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.663393712
Short name T962
Test name
Test status
Simulation time 8839234824 ps
CPU time 66.66 seconds
Started Jul 01 12:46:33 PM PDT 24
Finished Jul 01 12:47:40 PM PDT 24
Peak memory 263616 kb
Host smart-72bb2ed6-5069-4f2c-8a28-68f27c1987b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663393712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.663393712
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3160455221
Short name T528
Test name
Test status
Simulation time 4325669785 ps
CPU time 97.82 seconds
Started Jul 01 12:46:34 PM PDT 24
Finished Jul 01 12:48:12 PM PDT 24
Peak memory 265496 kb
Host smart-942c1eea-4f73-4969-8e05-cd016c927e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160455221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3160455221
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3579681566
Short name T794
Test name
Test status
Simulation time 39990050978 ps
CPU time 347.22 seconds
Started Jul 01 12:46:31 PM PDT 24
Finished Jul 01 12:52:19 PM PDT 24
Peak memory 254832 kb
Host smart-94627b25-3e23-40a3-b6fb-d74ff1b90cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579681566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3579681566
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2243273471
Short name T89
Test name
Test status
Simulation time 794471572 ps
CPU time 10.2 seconds
Started Jul 01 12:46:27 PM PDT 24
Finished Jul 01 12:46:38 PM PDT 24
Peak memory 250856 kb
Host smart-5754047f-2250-48d0-b080-3a0419d2e455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243273471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2243273471
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.687281377
Short name T305
Test name
Test status
Simulation time 652694873 ps
CPU time 0.92 seconds
Started Jul 01 12:46:29 PM PDT 24
Finished Jul 01 12:46:30 PM PDT 24
Peak memory 215820 kb
Host smart-daa2b68d-8a93-4411-b094-66796bfccc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687281377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
687281377
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.517553760
Short name T856
Test name
Test status
Simulation time 56214741 ps
CPU time 2.71 seconds
Started Jul 01 12:46:27 PM PDT 24
Finished Jul 01 12:46:30 PM PDT 24
Peak memory 224444 kb
Host smart-a1471466-4d71-4dd1-a46e-ff0b8fb1dfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517553760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.517553760
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1088931857
Short name T673
Test name
Test status
Simulation time 2155793790 ps
CPU time 11.81 seconds
Started Jul 01 12:46:27 PM PDT 24
Finished Jul 01 12:46:39 PM PDT 24
Peak memory 249112 kb
Host smart-66e9af76-197e-4244-8d0d-a8d359c17efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088931857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1088931857
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3372275339
Short name T972
Test name
Test status
Simulation time 139794091 ps
CPU time 3.63 seconds
Started Jul 01 12:46:27 PM PDT 24
Finished Jul 01 12:46:32 PM PDT 24
Peak memory 232600 kb
Host smart-9300e9fb-c2cc-47f3-9345-97284fa1f7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372275339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3372275339
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1039885937
Short name T57
Test name
Test status
Simulation time 58177270 ps
CPU time 2.43 seconds
Started Jul 01 12:46:21 PM PDT 24
Finished Jul 01 12:46:24 PM PDT 24
Peak memory 224528 kb
Host smart-53b65728-407f-40ad-80e7-43867acb6dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039885937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1039885937
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3582403558
Short name T876
Test name
Test status
Simulation time 182298110 ps
CPU time 4.25 seconds
Started Jul 01 12:46:27 PM PDT 24
Finished Jul 01 12:46:31 PM PDT 24
Peak memory 219116 kb
Host smart-5c3ff46f-c8b3-4d5f-9922-a8dc7177423e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3582403558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3582403558
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.611063385
Short name T67
Test name
Test status
Simulation time 271180903 ps
CPU time 1.51 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:46:49 PM PDT 24
Peak memory 236576 kb
Host smart-5e8b930d-010f-4a77-9702-3ec5da438208
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611063385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.611063385
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3152671329
Short name T140
Test name
Test status
Simulation time 15608840501 ps
CPU time 193.89 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:50:02 PM PDT 24
Peak memory 265532 kb
Host smart-51dccab5-0a1d-47df-af0e-c082df25ab77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152671329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3152671329
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3944956781
Short name T623
Test name
Test status
Simulation time 3612195644 ps
CPU time 35.64 seconds
Started Jul 01 12:46:21 PM PDT 24
Finished Jul 01 12:46:57 PM PDT 24
Peak memory 216392 kb
Host smart-90153e47-e8f0-4ae3-9729-a13adb8cc569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944956781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3944956781
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3067958994
Short name T504
Test name
Test status
Simulation time 11580432611 ps
CPU time 11.18 seconds
Started Jul 01 12:46:21 PM PDT 24
Finished Jul 01 12:46:33 PM PDT 24
Peak memory 216332 kb
Host smart-842bf981-ba6b-4efd-8473-3cfa31ea3352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067958994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3067958994
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1429604396
Short name T566
Test name
Test status
Simulation time 66686059 ps
CPU time 1.99 seconds
Started Jul 01 12:46:22 PM PDT 24
Finished Jul 01 12:46:26 PM PDT 24
Peak memory 208052 kb
Host smart-c0fd9940-2c89-4929-90d4-d09b83c15cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429604396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1429604396
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3419795180
Short name T748
Test name
Test status
Simulation time 14593100 ps
CPU time 0.7 seconds
Started Jul 01 12:46:22 PM PDT 24
Finished Jul 01 12:46:23 PM PDT 24
Peak memory 205976 kb
Host smart-85bd269b-86f4-461b-b30a-0f7d2e193d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419795180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3419795180
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2830274115
Short name T731
Test name
Test status
Simulation time 20503152314 ps
CPU time 17.38 seconds
Started Jul 01 12:46:25 PM PDT 24
Finished Jul 01 12:46:43 PM PDT 24
Peak memory 224616 kb
Host smart-5fcd996e-dd6a-4bea-b707-62ec6e2ede87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830274115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2830274115
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1855811471
Short name T133
Test name
Test status
Simulation time 22507064 ps
CPU time 0.7 seconds
Started Jul 01 12:48:29 PM PDT 24
Finished Jul 01 12:48:30 PM PDT 24
Peak memory 205556 kb
Host smart-7320a495-f672-4664-8a4c-5083e41bbab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855811471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1855811471
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2758710325
Short name T85
Test name
Test status
Simulation time 152020409 ps
CPU time 2.33 seconds
Started Jul 01 12:48:29 PM PDT 24
Finished Jul 01 12:48:33 PM PDT 24
Peak memory 224444 kb
Host smart-5fdd51b0-95fb-46d4-81e5-fcabb9050f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758710325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2758710325
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.795392405
Short name T708
Test name
Test status
Simulation time 63642234 ps
CPU time 0.8 seconds
Started Jul 01 12:48:24 PM PDT 24
Finished Jul 01 12:48:25 PM PDT 24
Peak memory 206920 kb
Host smart-4adcd6cf-7e69-4ed3-91d7-6763490568cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795392405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.795392405
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2065423795
Short name T680
Test name
Test status
Simulation time 34926318780 ps
CPU time 69.83 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:49:43 PM PDT 24
Peak memory 249228 kb
Host smart-0596f920-da7f-4f47-b597-1dfdbfa6ea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065423795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2065423795
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3803357062
Short name T263
Test name
Test status
Simulation time 6545547412 ps
CPU time 17.63 seconds
Started Jul 01 12:48:29 PM PDT 24
Finished Jul 01 12:48:47 PM PDT 24
Peak memory 238688 kb
Host smart-348596dc-b718-4a26-8c03-006493250828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803357062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3803357062
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4149936793
Short name T55
Test name
Test status
Simulation time 405639304 ps
CPU time 4 seconds
Started Jul 01 12:48:29 PM PDT 24
Finished Jul 01 12:48:34 PM PDT 24
Peak memory 217724 kb
Host smart-8cd61d99-b85b-408b-a189-631f29391582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149936793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4149936793
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2689282836
Short name T864
Test name
Test status
Simulation time 3338318435 ps
CPU time 14.26 seconds
Started Jul 01 12:48:30 PM PDT 24
Finished Jul 01 12:48:45 PM PDT 24
Peak memory 232816 kb
Host smart-da6752e9-68b8-4ad9-9260-82983c828e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689282836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2689282836
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.304883801
Short name T853
Test name
Test status
Simulation time 10556678196 ps
CPU time 102.57 seconds
Started Jul 01 12:48:30 PM PDT 24
Finished Jul 01 12:50:14 PM PDT 24
Peak memory 257416 kb
Host smart-c5d5a9a8-5e79-4980-8671-3b01ca3204ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304883801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.304883801
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.162760778
Short name T1006
Test name
Test status
Simulation time 5692121352 ps
CPU time 14.15 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:48:47 PM PDT 24
Peak memory 224572 kb
Host smart-d7d493ce-e29a-4f24-8a00-585e64a5f3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162760778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.162760778
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.495011781
Short name T632
Test name
Test status
Simulation time 7477357677 ps
CPU time 18.48 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:48:52 PM PDT 24
Peak memory 241052 kb
Host smart-3d3d6709-d9b9-45b6-a952-e963b0ea6515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495011781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.495011781
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2500397307
Short name T329
Test name
Test status
Simulation time 14917803353 ps
CPU time 22.98 seconds
Started Jul 01 12:48:17 PM PDT 24
Finished Jul 01 12:48:41 PM PDT 24
Peak memory 237800 kb
Host smart-94962195-9563-45ce-8b15-768cd178b931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500397307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2500397307
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1360526268
Short name T360
Test name
Test status
Simulation time 1660604338 ps
CPU time 4.45 seconds
Started Jul 01 12:48:24 PM PDT 24
Finished Jul 01 12:48:30 PM PDT 24
Peak memory 224504 kb
Host smart-185eff5a-47a1-425f-9222-2452929beb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360526268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1360526268
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.771826554
Short name T955
Test name
Test status
Simulation time 1868799637 ps
CPU time 12.85 seconds
Started Jul 01 12:48:28 PM PDT 24
Finished Jul 01 12:48:42 PM PDT 24
Peak memory 219880 kb
Host smart-27642f85-14f3-414c-b5fe-5f0333e27432
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=771826554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.771826554
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3830144136
Short name T816
Test name
Test status
Simulation time 26913040612 ps
CPU time 282.34 seconds
Started Jul 01 12:48:30 PM PDT 24
Finished Jul 01 12:53:14 PM PDT 24
Peak memory 268296 kb
Host smart-887d1b02-f618-406c-8007-23d4ce95897a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830144136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3830144136
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2377274862
Short name T539
Test name
Test status
Simulation time 14822500996 ps
CPU time 25.09 seconds
Started Jul 01 12:48:19 PM PDT 24
Finished Jul 01 12:48:45 PM PDT 24
Peak memory 216288 kb
Host smart-56b955a3-ebb5-4d4e-8e40-8eb76afb987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377274862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2377274862
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.161095795
Short name T334
Test name
Test status
Simulation time 11703300142 ps
CPU time 9.24 seconds
Started Jul 01 12:48:17 PM PDT 24
Finished Jul 01 12:48:27 PM PDT 24
Peak memory 217320 kb
Host smart-7c0cecf0-6713-4fb4-b288-b264a0e5bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161095795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.161095795
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1544432660
Short name T715
Test name
Test status
Simulation time 14353137 ps
CPU time 0.74 seconds
Started Jul 01 12:48:16 PM PDT 24
Finished Jul 01 12:48:18 PM PDT 24
Peak memory 205968 kb
Host smart-7482e42d-1306-4b7c-af8d-7725a4aed474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544432660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1544432660
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1827899816
Short name T926
Test name
Test status
Simulation time 409306298 ps
CPU time 0.88 seconds
Started Jul 01 12:48:15 PM PDT 24
Finished Jul 01 12:48:17 PM PDT 24
Peak memory 206968 kb
Host smart-35a750d3-68a8-4d4e-8128-3478eb89a752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827899816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1827899816
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.879044771
Short name T327
Test name
Test status
Simulation time 123004898 ps
CPU time 2.63 seconds
Started Jul 01 12:48:28 PM PDT 24
Finished Jul 01 12:48:31 PM PDT 24
Peak memory 224216 kb
Host smart-533d7303-ca98-4ba8-beed-600d3d3c440e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879044771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.879044771
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.383626294
Short name T826
Test name
Test status
Simulation time 25847670 ps
CPU time 0.72 seconds
Started Jul 01 12:48:26 PM PDT 24
Finished Jul 01 12:48:28 PM PDT 24
Peak memory 205888 kb
Host smart-14ebb6ea-0612-4b3c-abcd-e602eaccb5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383626294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.383626294
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2936436424
Short name T426
Test name
Test status
Simulation time 294931432 ps
CPU time 5.8 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:48:39 PM PDT 24
Peak memory 224448 kb
Host smart-2a7dc64d-b480-41e6-82a5-64900099dd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936436424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2936436424
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4213300128
Short name T819
Test name
Test status
Simulation time 58197088 ps
CPU time 0.8 seconds
Started Jul 01 12:48:30 PM PDT 24
Finished Jul 01 12:48:32 PM PDT 24
Peak memory 206804 kb
Host smart-041d38f5-d899-4951-a4c7-174b913a1e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213300128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4213300128
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4045743278
Short name T192
Test name
Test status
Simulation time 111228068224 ps
CPU time 394.26 seconds
Started Jul 01 12:48:26 PM PDT 24
Finished Jul 01 12:55:01 PM PDT 24
Peak memory 265488 kb
Host smart-5b32457f-c8e3-4f5f-a18d-b1103e036577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045743278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4045743278
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1432013731
Short name T138
Test name
Test status
Simulation time 6690847727 ps
CPU time 84.47 seconds
Started Jul 01 12:48:26 PM PDT 24
Finished Jul 01 12:49:52 PM PDT 24
Peak memory 251604 kb
Host smart-c8f61f68-2952-4107-a264-a813b31a9e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432013731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1432013731
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2695745628
Short name T633
Test name
Test status
Simulation time 1631034065 ps
CPU time 30.87 seconds
Started Jul 01 12:48:25 PM PDT 24
Finished Jul 01 12:48:57 PM PDT 24
Peak memory 233688 kb
Host smart-35f43b0c-2e1c-4b6b-9caa-b1ddb145c09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695745628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2695745628
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2231846533
Short name T918
Test name
Test status
Simulation time 126581268 ps
CPU time 6.72 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:48:40 PM PDT 24
Peak memory 224508 kb
Host smart-308eb94d-9f92-42ed-828b-a6d5fdad959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231846533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2231846533
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3789581299
Short name T267
Test name
Test status
Simulation time 2002951025 ps
CPU time 49.94 seconds
Started Jul 01 12:48:24 PM PDT 24
Finished Jul 01 12:49:15 PM PDT 24
Peak memory 253436 kb
Host smart-ec4e06a5-62ca-4714-a50e-be23c10e78e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789581299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3789581299
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.847448657
Short name T817
Test name
Test status
Simulation time 67410910 ps
CPU time 2.45 seconds
Started Jul 01 12:48:33 PM PDT 24
Finished Jul 01 12:48:36 PM PDT 24
Peak memory 224436 kb
Host smart-fd47b6bb-dd8e-4a02-a8ba-a0385c49cbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847448657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.847448657
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3956297665
Short name T394
Test name
Test status
Simulation time 119399130 ps
CPU time 3.37 seconds
Started Jul 01 12:48:33 PM PDT 24
Finished Jul 01 12:48:37 PM PDT 24
Peak memory 232648 kb
Host smart-18e02bf4-fde7-4364-a2df-68227f5275d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956297665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3956297665
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2477845594
Short name T159
Test name
Test status
Simulation time 885717422 ps
CPU time 7.79 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:48:41 PM PDT 24
Peak memory 232720 kb
Host smart-46b8f241-f7b4-4c31-ad42-7e0c729de9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477845594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2477845594
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1506710676
Short name T529
Test name
Test status
Simulation time 667662903 ps
CPU time 8.88 seconds
Started Jul 01 12:48:31 PM PDT 24
Finished Jul 01 12:48:41 PM PDT 24
Peak memory 232692 kb
Host smart-2d9baa3d-5a19-4787-b241-ddcc6bd75244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506710676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1506710676
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3978136482
Short name T364
Test name
Test status
Simulation time 800710440 ps
CPU time 6.19 seconds
Started Jul 01 12:48:28 PM PDT 24
Finished Jul 01 12:48:35 PM PDT 24
Peak memory 222468 kb
Host smart-03f911b9-8cb4-4c4a-8b43-47b2e8d0ceb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3978136482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3978136482
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1106452873
Short name T80
Test name
Test status
Simulation time 2903438845 ps
CPU time 30.92 seconds
Started Jul 01 12:48:30 PM PDT 24
Finished Jul 01 12:49:02 PM PDT 24
Peak memory 216316 kb
Host smart-21f2506d-de59-4539-8188-435164fd624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106452873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1106452873
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2885919720
Short name T519
Test name
Test status
Simulation time 4020018878 ps
CPU time 5.64 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:48:39 PM PDT 24
Peak memory 216312 kb
Host smart-22f15a75-b27d-4c64-9a48-1b7a69d0951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885919720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2885919720
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1370738652
Short name T572
Test name
Test status
Simulation time 81479667 ps
CPU time 1.08 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:48:35 PM PDT 24
Peak memory 207884 kb
Host smart-2977dda4-3368-4b4b-945f-a66ce560e8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370738652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1370738652
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.719508975
Short name T969
Test name
Test status
Simulation time 174306806 ps
CPU time 0.87 seconds
Started Jul 01 12:48:30 PM PDT 24
Finished Jul 01 12:48:32 PM PDT 24
Peak memory 206988 kb
Host smart-2cee66d0-6cee-4f8a-bd77-9443d5d82ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719508975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.719508975
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2974909909
Short name T436
Test name
Test status
Simulation time 9458495663 ps
CPU time 9.64 seconds
Started Jul 01 12:48:33 PM PDT 24
Finished Jul 01 12:48:44 PM PDT 24
Peak memory 232740 kb
Host smart-e6d3de8a-beda-4dd1-9d47-3d07eefd1154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974909909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2974909909
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2604353032
Short name T703
Test name
Test status
Simulation time 41431132 ps
CPU time 0.73 seconds
Started Jul 01 12:48:34 PM PDT 24
Finished Jul 01 12:48:35 PM PDT 24
Peak memory 204968 kb
Host smart-99c3e418-ef20-4ac8-8762-2d02e034d6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604353032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2604353032
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2609051731
Short name T227
Test name
Test status
Simulation time 390173067 ps
CPU time 6.59 seconds
Started Jul 01 12:48:37 PM PDT 24
Finished Jul 01 12:48:45 PM PDT 24
Peak memory 224304 kb
Host smart-869e310c-42c9-4028-a5a4-719f641b0fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609051731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2609051731
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2730001381
Short name T552
Test name
Test status
Simulation time 41429479 ps
CPU time 0.76 seconds
Started Jul 01 12:48:26 PM PDT 24
Finished Jul 01 12:48:27 PM PDT 24
Peak memory 206948 kb
Host smart-8106c867-6d1a-476d-abc0-4cad3af7cdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730001381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2730001381
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.803302725
Short name T934
Test name
Test status
Simulation time 1626825232 ps
CPU time 24.77 seconds
Started Jul 01 12:48:31 PM PDT 24
Finished Jul 01 12:48:57 PM PDT 24
Peak memory 236196 kb
Host smart-cfbf9673-d927-46de-a24d-7e623d62c3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803302725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.803302725
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1334578678
Short name T223
Test name
Test status
Simulation time 24428427834 ps
CPU time 228.42 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:52:21 PM PDT 24
Peak memory 265568 kb
Host smart-61ae2b6e-be6b-489b-8d64-3591cbb76541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334578678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1334578678
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3036139684
Short name T268
Test name
Test status
Simulation time 2533153866 ps
CPU time 62.23 seconds
Started Jul 01 12:48:37 PM PDT 24
Finished Jul 01 12:49:41 PM PDT 24
Peak memory 268288 kb
Host smart-93552569-5bb2-404d-8fb0-ea9a9dfcf0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036139684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3036139684
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3675944086
Short name T146
Test name
Test status
Simulation time 1510997768 ps
CPU time 13.58 seconds
Started Jul 01 12:48:31 PM PDT 24
Finished Jul 01 12:48:45 PM PDT 24
Peak memory 224420 kb
Host smart-57eb0cca-6791-4015-92a2-d1fa1d6e64df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675944086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3675944086
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3855725509
Short name T84
Test name
Test status
Simulation time 1616661570 ps
CPU time 22.18 seconds
Started Jul 01 12:48:35 PM PDT 24
Finished Jul 01 12:48:59 PM PDT 24
Peak memory 240872 kb
Host smart-da09b48a-c228-45ec-9653-8c274f26226d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855725509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3855725509
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3923314162
Short name T358
Test name
Test status
Simulation time 231845574 ps
CPU time 3.49 seconds
Started Jul 01 12:48:33 PM PDT 24
Finished Jul 01 12:48:37 PM PDT 24
Peak memory 228204 kb
Host smart-d6a57765-1a0a-4c07-9b51-e20241289534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923314162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3923314162
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1138358952
Short name T163
Test name
Test status
Simulation time 10895605352 ps
CPU time 71.49 seconds
Started Jul 01 12:48:35 PM PDT 24
Finished Jul 01 12:49:48 PM PDT 24
Peak memory 249224 kb
Host smart-ec17593f-ac95-4f9d-bcc7-afa2eb5d22bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138358952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1138358952
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2834412672
Short name T258
Test name
Test status
Simulation time 20772357852 ps
CPU time 16.51 seconds
Started Jul 01 12:48:25 PM PDT 24
Finished Jul 01 12:48:42 PM PDT 24
Peak memory 232816 kb
Host smart-466c8400-11eb-4249-9e2a-9739dd9335e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834412672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2834412672
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.261818691
Short name T218
Test name
Test status
Simulation time 214114506 ps
CPU time 3.48 seconds
Started Jul 01 12:48:24 PM PDT 24
Finished Jul 01 12:48:29 PM PDT 24
Peak memory 232628 kb
Host smart-27c0044a-d5da-4d0e-a073-aa2ed5b9b8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261818691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.261818691
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3145901279
Short name T376
Test name
Test status
Simulation time 2439184867 ps
CPU time 14.45 seconds
Started Jul 01 12:48:32 PM PDT 24
Finished Jul 01 12:48:48 PM PDT 24
Peak memory 222144 kb
Host smart-88c9c9a4-3664-47f7-9719-cf7e729a4203
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3145901279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3145901279
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4202347727
Short name T797
Test name
Test status
Simulation time 3754725290 ps
CPU time 21.45 seconds
Started Jul 01 12:48:27 PM PDT 24
Finished Jul 01 12:48:49 PM PDT 24
Peak memory 216236 kb
Host smart-21105997-4cbc-4c34-ad17-a245b5660cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202347727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4202347727
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2474895674
Short name T888
Test name
Test status
Simulation time 8255379371 ps
CPU time 16.8 seconds
Started Jul 01 12:48:28 PM PDT 24
Finished Jul 01 12:48:45 PM PDT 24
Peak memory 216304 kb
Host smart-c313cd62-f102-4b22-8442-fd605aa1f887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474895674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2474895674
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1835521037
Short name T413
Test name
Test status
Simulation time 279671492 ps
CPU time 1.51 seconds
Started Jul 01 12:48:27 PM PDT 24
Finished Jul 01 12:48:29 PM PDT 24
Peak memory 216160 kb
Host smart-4e648b65-5929-49d0-b24a-4001d2b91e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835521037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1835521037
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2374067487
Short name T803
Test name
Test status
Simulation time 239944809 ps
CPU time 0.96 seconds
Started Jul 01 12:48:25 PM PDT 24
Finished Jul 01 12:48:27 PM PDT 24
Peak memory 207000 kb
Host smart-8cd43cdb-fe57-4f6c-8487-14b2838bfaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374067487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2374067487
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3547533650
Short name T456
Test name
Test status
Simulation time 348097322 ps
CPU time 2.64 seconds
Started Jul 01 12:48:36 PM PDT 24
Finished Jul 01 12:48:39 PM PDT 24
Peak memory 227932 kb
Host smart-025f7214-c951-4a75-a292-1e3ca3e51cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547533650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3547533650
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1340086821
Short name T396
Test name
Test status
Simulation time 24112218 ps
CPU time 0.75 seconds
Started Jul 01 12:48:37 PM PDT 24
Finished Jul 01 12:48:40 PM PDT 24
Peak memory 204960 kb
Host smart-bb5116f0-f132-4f8c-a696-1462b93a1005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340086821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1340086821
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.886159065
Short name T465
Test name
Test status
Simulation time 100807186 ps
CPU time 2.71 seconds
Started Jul 01 12:48:40 PM PDT 24
Finished Jul 01 12:48:43 PM PDT 24
Peak memory 224424 kb
Host smart-f2a9475f-9a45-4cd3-a548-13eb1478171c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886159065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.886159065
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.233824791
Short name T428
Test name
Test status
Simulation time 20682333 ps
CPU time 0.8 seconds
Started Jul 01 12:48:30 PM PDT 24
Finished Jul 01 12:48:32 PM PDT 24
Peak memory 206520 kb
Host smart-b4d06002-1987-4050-ab64-81337c9eb21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233824791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.233824791
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.514937691
Short name T397
Test name
Test status
Simulation time 2621262258 ps
CPU time 22.14 seconds
Started Jul 01 12:48:36 PM PDT 24
Finished Jul 01 12:49:00 PM PDT 24
Peak memory 238116 kb
Host smart-ebe28389-d77b-4bd0-9158-0c9b1de4b10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514937691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.514937691
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.397985518
Short name T1000
Test name
Test status
Simulation time 32353589748 ps
CPU time 361.61 seconds
Started Jul 01 12:48:38 PM PDT 24
Finished Jul 01 12:54:41 PM PDT 24
Peak memory 266916 kb
Host smart-a30dc610-8fb9-4f8b-977d-f998ec6fdecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397985518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.397985518
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2757722152
Short name T723
Test name
Test status
Simulation time 26122032984 ps
CPU time 88.45 seconds
Started Jul 01 12:48:37 PM PDT 24
Finished Jul 01 12:50:07 PM PDT 24
Peak memory 253448 kb
Host smart-a373894c-668f-49bb-914d-64e5b4f65843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757722152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2757722152
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1946548886
Short name T52
Test name
Test status
Simulation time 21508283579 ps
CPU time 18.7 seconds
Started Jul 01 12:48:36 PM PDT 24
Finished Jul 01 12:48:57 PM PDT 24
Peak memory 249224 kb
Host smart-16cb79e2-59ea-42d5-bf88-03978adecc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946548886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1946548886
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.437988735
Short name T880
Test name
Test status
Simulation time 2616486446 ps
CPU time 46.8 seconds
Started Jul 01 12:48:36 PM PDT 24
Finished Jul 01 12:49:24 PM PDT 24
Peak memory 249772 kb
Host smart-7e8b9ab9-05f8-486b-884f-4f6442641e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437988735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.437988735
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1664065972
Short name T238
Test name
Test status
Simulation time 530246370 ps
CPU time 4.25 seconds
Started Jul 01 12:48:37 PM PDT 24
Finished Jul 01 12:48:43 PM PDT 24
Peak memory 232560 kb
Host smart-6f235565-29e5-4ebb-a194-465cf4852817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664065972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1664065972
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2559357145
Short name T208
Test name
Test status
Simulation time 26007474244 ps
CPU time 109.05 seconds
Started Jul 01 12:48:31 PM PDT 24
Finished Jul 01 12:50:21 PM PDT 24
Peak memory 240952 kb
Host smart-1733f8a1-38e5-485f-8289-d4cd351c2355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559357145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2559357145
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3766954033
Short name T253
Test name
Test status
Simulation time 579874631 ps
CPU time 9.73 seconds
Started Jul 01 12:48:31 PM PDT 24
Finished Jul 01 12:48:42 PM PDT 24
Peak memory 232636 kb
Host smart-b49fa905-364a-4a7c-b60f-03dcc834d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766954033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3766954033
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3063918550
Short name T307
Test name
Test status
Simulation time 385692082 ps
CPU time 2.41 seconds
Started Jul 01 12:48:37 PM PDT 24
Finished Jul 01 12:48:41 PM PDT 24
Peak memory 232244 kb
Host smart-f51d4aa9-70f9-4521-9a1f-060e2eae2894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063918550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3063918550
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1394309134
Short name T944
Test name
Test status
Simulation time 592840867 ps
CPU time 7.3 seconds
Started Jul 01 12:48:38 PM PDT 24
Finished Jul 01 12:48:47 PM PDT 24
Peak memory 219476 kb
Host smart-08aa62b1-3f0e-4d40-87e4-e2d8deb14f0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1394309134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1394309134
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1628118114
Short name T598
Test name
Test status
Simulation time 163708980 ps
CPU time 1.07 seconds
Started Jul 01 12:48:37 PM PDT 24
Finished Jul 01 12:48:40 PM PDT 24
Peak memory 206940 kb
Host smart-d9311c36-1e77-4e33-b88f-6e3892f690f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628118114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1628118114
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4245159253
Short name T844
Test name
Test status
Simulation time 9639749656 ps
CPU time 25.55 seconds
Started Jul 01 12:48:33 PM PDT 24
Finished Jul 01 12:49:00 PM PDT 24
Peak memory 216272 kb
Host smart-a610903c-c1e2-4cc8-8d32-d9f70dbd7a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245159253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4245159253
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.646452800
Short name T585
Test name
Test status
Simulation time 7964982726 ps
CPU time 7.8 seconds
Started Jul 01 12:48:36 PM PDT 24
Finished Jul 01 12:48:44 PM PDT 24
Peak memory 216312 kb
Host smart-7b6ea545-3b5f-49ad-830b-124a71b6debd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646452800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.646452800
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1029474629
Short name T808
Test name
Test status
Simulation time 15922572 ps
CPU time 0.92 seconds
Started Jul 01 12:48:31 PM PDT 24
Finished Jul 01 12:48:33 PM PDT 24
Peak memory 206956 kb
Host smart-11ec55f4-b6eb-4234-8b57-aa3d0de5c080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029474629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1029474629
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2803700693
Short name T324
Test name
Test status
Simulation time 47225890 ps
CPU time 0.73 seconds
Started Jul 01 12:48:33 PM PDT 24
Finished Jul 01 12:48:35 PM PDT 24
Peak memory 205968 kb
Host smart-100741a4-3f1a-4e9b-a1e7-33d87f4be3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803700693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2803700693
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.532118401
Short name T234
Test name
Test status
Simulation time 6197834660 ps
CPU time 19.23 seconds
Started Jul 01 12:48:38 PM PDT 24
Finished Jul 01 12:48:58 PM PDT 24
Peak memory 239044 kb
Host smart-8040c096-b577-4ffe-9c2b-60889da2aa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532118401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.532118401
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.237999551
Short name T609
Test name
Test status
Simulation time 47390193 ps
CPU time 0.7 seconds
Started Jul 01 12:48:43 PM PDT 24
Finished Jul 01 12:48:46 PM PDT 24
Peak memory 205888 kb
Host smart-fc6b7d66-e509-448d-93eb-b82ab97a95b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237999551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.237999551
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.4285763871
Short name T347
Test name
Test status
Simulation time 763707466 ps
CPU time 3.13 seconds
Started Jul 01 12:48:42 PM PDT 24
Finished Jul 01 12:48:47 PM PDT 24
Peak memory 232604 kb
Host smart-d2c3672c-ac19-484d-a977-0f366dacadec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285763871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.4285763871
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3663127655
Short name T587
Test name
Test status
Simulation time 43709298 ps
CPU time 0.8 seconds
Started Jul 01 12:48:38 PM PDT 24
Finished Jul 01 12:48:40 PM PDT 24
Peak memory 206876 kb
Host smart-36a46b0f-7979-43fb-8555-fc138b2ecf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663127655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3663127655
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1900896763
Short name T667
Test name
Test status
Simulation time 55564263102 ps
CPU time 181.29 seconds
Started Jul 01 12:48:41 PM PDT 24
Finished Jul 01 12:51:44 PM PDT 24
Peak memory 253344 kb
Host smart-29d69c60-9221-4fb7-b887-5b2b89143a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900896763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1900896763
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1811671518
Short name T845
Test name
Test status
Simulation time 90135735272 ps
CPU time 480.78 seconds
Started Jul 01 12:48:44 PM PDT 24
Finished Jul 01 12:56:47 PM PDT 24
Peak memory 255800 kb
Host smart-fcecf39c-ddaa-435a-aa02-a2e6e96a06f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811671518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1811671518
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.414579791
Short name T440
Test name
Test status
Simulation time 3524961989 ps
CPU time 85.81 seconds
Started Jul 01 12:48:43 PM PDT 24
Finished Jul 01 12:50:11 PM PDT 24
Peak memory 256104 kb
Host smart-efc12a43-8641-4b12-af0c-31da072b26bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414579791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.414579791
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2545343141
Short name T756
Test name
Test status
Simulation time 678381928 ps
CPU time 6.93 seconds
Started Jul 01 12:48:42 PM PDT 24
Finished Jul 01 12:48:51 PM PDT 24
Peak memory 233648 kb
Host smart-34f8c547-39b7-4025-957b-4aa985439760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545343141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2545343141
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3338307549
Short name T524
Test name
Test status
Simulation time 63233699284 ps
CPU time 145.75 seconds
Started Jul 01 12:48:45 PM PDT 24
Finished Jul 01 12:51:13 PM PDT 24
Peak memory 258192 kb
Host smart-844ea68e-866f-4ba9-8998-abaf752f07f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338307549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3338307549
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1122911429
Short name T514
Test name
Test status
Simulation time 5896346659 ps
CPU time 7.96 seconds
Started Jul 01 12:48:44 PM PDT 24
Finished Jul 01 12:48:55 PM PDT 24
Peak memory 232784 kb
Host smart-13d6a7ad-ecf7-45fc-883c-5544f58b0d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122911429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1122911429
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2694226173
Short name T626
Test name
Test status
Simulation time 3736346867 ps
CPU time 11.83 seconds
Started Jul 01 12:48:42 PM PDT 24
Finished Jul 01 12:48:55 PM PDT 24
Peak memory 232760 kb
Host smart-30bd803e-0d3c-43ca-be6b-13a1ebb3e415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694226173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2694226173
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1809293116
Short name T902
Test name
Test status
Simulation time 620220539 ps
CPU time 3.27 seconds
Started Jul 01 12:48:44 PM PDT 24
Finished Jul 01 12:48:50 PM PDT 24
Peak memory 232636 kb
Host smart-4170c30a-1c84-4fa5-a270-f4789287c7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809293116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1809293116
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1646148067
Short name T927
Test name
Test status
Simulation time 2735758222 ps
CPU time 4.07 seconds
Started Jul 01 12:48:41 PM PDT 24
Finished Jul 01 12:48:47 PM PDT 24
Peak memory 232736 kb
Host smart-c8f89ccb-8fd9-4be6-a766-b97d3cc12059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646148067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1646148067
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2970935906
Short name T484
Test name
Test status
Simulation time 1038747783 ps
CPU time 4.31 seconds
Started Jul 01 12:48:42 PM PDT 24
Finished Jul 01 12:48:48 PM PDT 24
Peak memory 223020 kb
Host smart-455b5501-5596-44b6-baa2-5131ea064752
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2970935906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2970935906
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.543545992
Short name T137
Test name
Test status
Simulation time 25598015167 ps
CPU time 234.87 seconds
Started Jul 01 12:48:42 PM PDT 24
Finished Jul 01 12:52:39 PM PDT 24
Peak memory 257456 kb
Host smart-2cceb273-22a7-434a-bd93-2e2f4d2e8a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543545992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.543545992
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.218534072
Short name T129
Test name
Test status
Simulation time 21838814779 ps
CPU time 26.8 seconds
Started Jul 01 12:48:41 PM PDT 24
Finished Jul 01 12:49:09 PM PDT 24
Peak memory 216336 kb
Host smart-3ca014a3-d342-4ba9-8454-bcf4b58bfb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218534072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.218534072
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1574489790
Short name T368
Test name
Test status
Simulation time 1178385831 ps
CPU time 2.4 seconds
Started Jul 01 12:48:39 PM PDT 24
Finished Jul 01 12:48:43 PM PDT 24
Peak memory 207192 kb
Host smart-b2ae698a-4244-4431-9993-8e37e9d23d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574489790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1574489790
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.251071083
Short name T855
Test name
Test status
Simulation time 141310967 ps
CPU time 1.51 seconds
Started Jul 01 12:48:40 PM PDT 24
Finished Jul 01 12:48:42 PM PDT 24
Peak memory 216196 kb
Host smart-0a4cf269-5af3-44a2-8c9b-27afd36520d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251071083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.251071083
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2042780470
Short name T444
Test name
Test status
Simulation time 12952686 ps
CPU time 0.69 seconds
Started Jul 01 12:48:42 PM PDT 24
Finished Jul 01 12:48:45 PM PDT 24
Peak memory 205536 kb
Host smart-fc15da28-c8e4-46a0-a021-8ee4f85019e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042780470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2042780470
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2728200628
Short name T165
Test name
Test status
Simulation time 114206186 ps
CPU time 3.09 seconds
Started Jul 01 12:48:43 PM PDT 24
Finished Jul 01 12:48:48 PM PDT 24
Peak memory 232692 kb
Host smart-497531e8-1161-44af-a15a-a16af1631b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728200628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2728200628
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.981005408
Short name T337
Test name
Test status
Simulation time 22711449 ps
CPU time 0.69 seconds
Started Jul 01 12:48:49 PM PDT 24
Finished Jul 01 12:48:51 PM PDT 24
Peak memory 204988 kb
Host smart-3a648d38-7981-47e0-adce-e9948090d8ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981005408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.981005408
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2962389399
Short name T228
Test name
Test status
Simulation time 2875741243 ps
CPU time 16.75 seconds
Started Jul 01 12:48:50 PM PDT 24
Finished Jul 01 12:49:07 PM PDT 24
Peak memory 232768 kb
Host smart-8893fd2f-6271-492b-b997-f619198c8e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962389399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2962389399
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3754509299
Short name T342
Test name
Test status
Simulation time 132473367 ps
CPU time 0.78 seconds
Started Jul 01 12:48:42 PM PDT 24
Finished Jul 01 12:48:45 PM PDT 24
Peak memory 205608 kb
Host smart-5d14e5c9-a488-49ce-8256-993dea167364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754509299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3754509299
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3609212652
Short name T546
Test name
Test status
Simulation time 1280668809 ps
CPU time 5.41 seconds
Started Jul 01 12:48:51 PM PDT 24
Finished Jul 01 12:48:57 PM PDT 24
Peak memory 224528 kb
Host smart-a159f6d0-4de7-45f1-9f79-e7a89da95820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609212652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3609212652
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.89506651
Short name T420
Test name
Test status
Simulation time 18359522938 ps
CPU time 45.98 seconds
Started Jul 01 12:48:50 PM PDT 24
Finished Jul 01 12:49:37 PM PDT 24
Peak memory 241028 kb
Host smart-5857631a-2833-4005-8145-f434cc433b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89506651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.89506651
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2423571129
Short name T54
Test name
Test status
Simulation time 34809327406 ps
CPU time 264.24 seconds
Started Jul 01 12:48:47 PM PDT 24
Finished Jul 01 12:53:13 PM PDT 24
Peak memory 254284 kb
Host smart-ad86da79-d269-4ecf-ac65-9933df4829ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423571129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2423571129
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.913241074
Short name T654
Test name
Test status
Simulation time 3400986795 ps
CPU time 8.13 seconds
Started Jul 01 12:48:48 PM PDT 24
Finished Jul 01 12:48:58 PM PDT 24
Peak memory 232756 kb
Host smart-c0b21503-2aec-4474-a80d-e22daefaf3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913241074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.913241074
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2142331030
Short name T595
Test name
Test status
Simulation time 29928285653 ps
CPU time 179.95 seconds
Started Jul 01 12:48:48 PM PDT 24
Finished Jul 01 12:51:50 PM PDT 24
Peak memory 250996 kb
Host smart-e3b2f497-5468-4136-8e58-320f6702af7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142331030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2142331030
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1426006004
Short name T432
Test name
Test status
Simulation time 5794743928 ps
CPU time 9.1 seconds
Started Jul 01 12:48:48 PM PDT 24
Finished Jul 01 12:48:58 PM PDT 24
Peak memory 232804 kb
Host smart-96319171-e6bb-415d-af14-26badcba51d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426006004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1426006004
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1486647986
Short name T712
Test name
Test status
Simulation time 2666224802 ps
CPU time 12.23 seconds
Started Jul 01 12:48:52 PM PDT 24
Finished Jul 01 12:49:05 PM PDT 24
Peak memory 239304 kb
Host smart-6f465d7c-063f-4593-b1ac-f3862bfb566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486647986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1486647986
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1211757806
Short name T656
Test name
Test status
Simulation time 142088711 ps
CPU time 2.24 seconds
Started Jul 01 12:48:47 PM PDT 24
Finished Jul 01 12:48:51 PM PDT 24
Peak memory 218488 kb
Host smart-bceb5529-9310-43c8-9d85-f6eb2416b7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211757806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1211757806
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2590456225
Short name T639
Test name
Test status
Simulation time 2493697985 ps
CPU time 10.22 seconds
Started Jul 01 12:48:44 PM PDT 24
Finished Jul 01 12:48:56 PM PDT 24
Peak memory 224640 kb
Host smart-0f365adb-4bab-48de-8d0a-89b93bc944d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590456225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2590456225
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2089289130
Short name T843
Test name
Test status
Simulation time 564012494 ps
CPU time 8.86 seconds
Started Jul 01 12:48:47 PM PDT 24
Finished Jul 01 12:48:57 PM PDT 24
Peak memory 220516 kb
Host smart-67d79e69-fd4c-4cd8-bc9e-eaf16017d377
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2089289130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2089289130
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2813648520
Short name T706
Test name
Test status
Simulation time 1156313695 ps
CPU time 15.08 seconds
Started Jul 01 12:48:43 PM PDT 24
Finished Jul 01 12:49:00 PM PDT 24
Peak memory 216280 kb
Host smart-f0dc809b-6160-4943-9bfe-8912fbc75c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813648520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2813648520
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1061493823
Short name T321
Test name
Test status
Simulation time 556620721 ps
CPU time 2.56 seconds
Started Jul 01 12:48:44 PM PDT 24
Finished Jul 01 12:48:50 PM PDT 24
Peak memory 216120 kb
Host smart-dc2cee6e-4066-440e-948d-5ac652fe265e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061493823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1061493823
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.4182969737
Short name T600
Test name
Test status
Simulation time 53044762 ps
CPU time 1.27 seconds
Started Jul 01 12:48:41 PM PDT 24
Finished Jul 01 12:48:43 PM PDT 24
Peak memory 216216 kb
Host smart-24877687-bfaa-4685-ac36-db831bd1e562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182969737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4182969737
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3933437713
Short name T769
Test name
Test status
Simulation time 58419569 ps
CPU time 0.9 seconds
Started Jul 01 12:48:45 PM PDT 24
Finished Jul 01 12:48:49 PM PDT 24
Peak memory 205996 kb
Host smart-d4e9329f-5270-411c-8315-334030a3fa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933437713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3933437713
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.12999030
Short name T835
Test name
Test status
Simulation time 72547226 ps
CPU time 2.56 seconds
Started Jul 01 12:48:49 PM PDT 24
Finished Jul 01 12:48:53 PM PDT 24
Peak memory 232704 kb
Host smart-58af2703-53a5-45d8-a97c-0bc19499eaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12999030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.12999030
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.162214937
Short name T568
Test name
Test status
Simulation time 43543467 ps
CPU time 0.71 seconds
Started Jul 01 12:48:53 PM PDT 24
Finished Jul 01 12:48:55 PM PDT 24
Peak memory 205488 kb
Host smart-7f85bc83-a8cc-4fd0-bbd6-05b721b82d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162214937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.162214937
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2321166871
Short name T562
Test name
Test status
Simulation time 684970839 ps
CPU time 4.74 seconds
Started Jul 01 12:48:55 PM PDT 24
Finished Jul 01 12:49:01 PM PDT 24
Peak memory 232604 kb
Host smart-a32dd94f-03bc-4899-a028-224ea21132b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321166871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2321166871
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1204620062
Short name T549
Test name
Test status
Simulation time 27360400 ps
CPU time 0.76 seconds
Started Jul 01 12:48:49 PM PDT 24
Finished Jul 01 12:48:51 PM PDT 24
Peak memory 206552 kb
Host smart-a431cdaa-c0b8-42a6-a603-e60b2289863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204620062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1204620062
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1547113142
Short name T352
Test name
Test status
Simulation time 17621717025 ps
CPU time 71.71 seconds
Started Jul 01 12:48:51 PM PDT 24
Finished Jul 01 12:50:04 PM PDT 24
Peak memory 249376 kb
Host smart-4c6e0306-b67a-4893-bea9-0030646e166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547113142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1547113142
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2566911483
Short name T79
Test name
Test status
Simulation time 12812898094 ps
CPU time 137.53 seconds
Started Jul 01 12:48:55 PM PDT 24
Finished Jul 01 12:51:14 PM PDT 24
Peak memory 253276 kb
Host smart-c67ed9ca-8591-4362-ad4d-47a78f7728df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566911483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2566911483
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2535921634
Short name T203
Test name
Test status
Simulation time 13854249547 ps
CPU time 193.44 seconds
Started Jul 01 12:48:53 PM PDT 24
Finished Jul 01 12:52:08 PM PDT 24
Peak memory 253624 kb
Host smart-8dde07aa-7cab-421e-bd7a-dfd52ee2e252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535921634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2535921634
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.839695829
Short name T993
Test name
Test status
Simulation time 73236951 ps
CPU time 3.48 seconds
Started Jul 01 12:48:59 PM PDT 24
Finished Jul 01 12:49:04 PM PDT 24
Peak memory 232660 kb
Host smart-47156dea-59b0-4290-88c6-888892c551d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839695829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.839695829
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2891575901
Short name T828
Test name
Test status
Simulation time 430872153 ps
CPU time 3.78 seconds
Started Jul 01 12:48:51 PM PDT 24
Finished Jul 01 12:48:56 PM PDT 24
Peak memory 224384 kb
Host smart-8508d905-78ed-4645-bd07-eedefe32b52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891575901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2891575901
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2689172677
Short name T825
Test name
Test status
Simulation time 1602883621 ps
CPU time 20.12 seconds
Started Jul 01 12:48:52 PM PDT 24
Finished Jul 01 12:49:13 PM PDT 24
Peak memory 232668 kb
Host smart-34bf7131-50f1-4b06-8302-51be93ac859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689172677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2689172677
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2179001014
Short name T805
Test name
Test status
Simulation time 6950701734 ps
CPU time 13.76 seconds
Started Jul 01 12:48:52 PM PDT 24
Finished Jul 01 12:49:07 PM PDT 24
Peak memory 234632 kb
Host smart-8ef71d41-957f-4f68-a890-1dd7d96d2d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179001014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2179001014
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3246454079
Short name T235
Test name
Test status
Simulation time 13479236834 ps
CPU time 22.93 seconds
Started Jul 01 12:48:55 PM PDT 24
Finished Jul 01 12:49:19 PM PDT 24
Peak memory 232836 kb
Host smart-71168803-a7bf-44aa-a73b-3b098bf1b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246454079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3246454079
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1354711267
Short name T968
Test name
Test status
Simulation time 897246617 ps
CPU time 9.17 seconds
Started Jul 01 12:48:53 PM PDT 24
Finished Jul 01 12:49:03 PM PDT 24
Peak memory 222080 kb
Host smart-d50a7d24-7ccd-4bd7-aed8-d4e8d7cd2928
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1354711267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1354711267
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1607395686
Short name T492
Test name
Test status
Simulation time 143426180 ps
CPU time 0.94 seconds
Started Jul 01 12:48:53 PM PDT 24
Finished Jul 01 12:48:55 PM PDT 24
Peak memory 207592 kb
Host smart-07dd626e-5290-4d96-a764-760562706e0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607395686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1607395686
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1168217335
Short name T162
Test name
Test status
Simulation time 447936732 ps
CPU time 6.87 seconds
Started Jul 01 12:48:47 PM PDT 24
Finished Jul 01 12:48:56 PM PDT 24
Peak memory 216248 kb
Host smart-c0075b4a-65ac-4cb1-8466-b6d9d4c5ad0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168217335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1168217335
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.268605343
Short name T73
Test name
Test status
Simulation time 14803385694 ps
CPU time 13.86 seconds
Started Jul 01 12:48:47 PM PDT 24
Finished Jul 01 12:49:03 PM PDT 24
Peak memory 216376 kb
Host smart-16422ee2-697e-4c5b-b31b-e31caf19a493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268605343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.268605343
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2911514411
Short name T447
Test name
Test status
Simulation time 21211002 ps
CPU time 1.08 seconds
Started Jul 01 12:48:54 PM PDT 24
Finished Jul 01 12:48:56 PM PDT 24
Peak memory 207496 kb
Host smart-f63bd8c5-b6c2-43f4-ae50-0b932db600e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911514411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2911514411
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1127038878
Short name T418
Test name
Test status
Simulation time 15311597 ps
CPU time 0.75 seconds
Started Jul 01 12:48:50 PM PDT 24
Finished Jul 01 12:48:51 PM PDT 24
Peak memory 205964 kb
Host smart-8f63d200-1af6-464c-a052-a85becc9cf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127038878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1127038878
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3665029318
Short name T624
Test name
Test status
Simulation time 163642415 ps
CPU time 2.27 seconds
Started Jul 01 12:48:59 PM PDT 24
Finished Jul 01 12:49:02 PM PDT 24
Peak memory 223716 kb
Host smart-5c2abea9-bd25-4480-9e4a-bd3077c49e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665029318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3665029318
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2902587517
Short name T749
Test name
Test status
Simulation time 16016222 ps
CPU time 0.95 seconds
Started Jul 01 12:49:01 PM PDT 24
Finished Jul 01 12:49:04 PM PDT 24
Peak memory 205580 kb
Host smart-16ab0525-4fdd-4e13-8e54-ec3a3383bac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902587517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2902587517
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1603405882
Short name T611
Test name
Test status
Simulation time 1282794554 ps
CPU time 4.89 seconds
Started Jul 01 12:48:58 PM PDT 24
Finished Jul 01 12:49:05 PM PDT 24
Peak memory 232660 kb
Host smart-6c8a3f98-6281-4f74-95e2-6aba46190cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603405882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1603405882
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2055005151
Short name T616
Test name
Test status
Simulation time 31864103 ps
CPU time 0.84 seconds
Started Jul 01 12:48:59 PM PDT 24
Finished Jul 01 12:49:02 PM PDT 24
Peak memory 206572 kb
Host smart-c7043bec-1357-4f02-835f-7bac1f4987ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055005151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2055005151
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1688529980
Short name T416
Test name
Test status
Simulation time 96615021090 ps
CPU time 154.51 seconds
Started Jul 01 12:48:59 PM PDT 24
Finished Jul 01 12:51:36 PM PDT 24
Peak memory 257428 kb
Host smart-3bee6e99-b2ef-4d80-8f99-fd1fd25f4dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688529980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1688529980
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.73074662
Short name T717
Test name
Test status
Simulation time 4759720395 ps
CPU time 84.14 seconds
Started Jul 01 12:49:00 PM PDT 24
Finished Jul 01 12:50:27 PM PDT 24
Peak memory 261084 kb
Host smart-f23c71d7-68d1-4a35-9e7d-1f28ba9d7a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73074662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.73074662
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2313631434
Short name T471
Test name
Test status
Simulation time 2067876948 ps
CPU time 43.09 seconds
Started Jul 01 12:48:59 PM PDT 24
Finished Jul 01 12:49:43 PM PDT 24
Peak memory 249140 kb
Host smart-a0abc739-08d5-4d8a-b612-369ecb1f20c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313631434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2313631434
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1692097328
Short name T793
Test name
Test status
Simulation time 239801750 ps
CPU time 9.41 seconds
Started Jul 01 12:49:00 PM PDT 24
Finished Jul 01 12:49:12 PM PDT 24
Peak memory 234944 kb
Host smart-29642332-deb6-416e-bd9e-9b1106124e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692097328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1692097328
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.357468466
Short name T503
Test name
Test status
Simulation time 27172034700 ps
CPU time 95.94 seconds
Started Jul 01 12:48:58 PM PDT 24
Finished Jul 01 12:50:35 PM PDT 24
Peak memory 249176 kb
Host smart-c6e011f1-01ee-4ab9-a604-403972f94fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357468466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.357468466
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3193718178
Short name T642
Test name
Test status
Simulation time 161349484 ps
CPU time 3.58 seconds
Started Jul 01 12:48:57 PM PDT 24
Finished Jul 01 12:49:02 PM PDT 24
Peak memory 224464 kb
Host smart-a835e62a-6ebb-4980-be93-46137539c9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193718178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3193718178
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3711963165
Short name T483
Test name
Test status
Simulation time 2179835605 ps
CPU time 38.83 seconds
Started Jul 01 12:48:57 PM PDT 24
Finished Jul 01 12:49:37 PM PDT 24
Peak memory 249736 kb
Host smart-c8444279-b908-43fd-a1e7-50cbcc5ca5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711963165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3711963165
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2554850020
Short name T780
Test name
Test status
Simulation time 3785346883 ps
CPU time 14.26 seconds
Started Jul 01 12:49:00 PM PDT 24
Finished Jul 01 12:49:16 PM PDT 24
Peak memory 232700 kb
Host smart-f4770fb4-eac5-45c7-af64-a9ca208eb5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554850020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2554850020
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3898719864
Short name T786
Test name
Test status
Simulation time 6251517669 ps
CPU time 8.62 seconds
Started Jul 01 12:49:02 PM PDT 24
Finished Jul 01 12:49:13 PM PDT 24
Peak memory 232768 kb
Host smart-887ba0a7-a7ee-46e2-8a99-94e3f48d9114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898719864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3898719864
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1923498574
Short name T675
Test name
Test status
Simulation time 3019112101 ps
CPU time 6.64 seconds
Started Jul 01 12:48:57 PM PDT 24
Finished Jul 01 12:49:05 PM PDT 24
Peak memory 222636 kb
Host smart-34d84e45-5482-4d72-8629-a015cf76455a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1923498574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1923498574
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1515226422
Short name T745
Test name
Test status
Simulation time 52577815295 ps
CPU time 23.84 seconds
Started Jul 01 12:48:52 PM PDT 24
Finished Jul 01 12:49:17 PM PDT 24
Peak memory 216408 kb
Host smart-0425d9bf-88ae-4656-af8f-5d5e05f925ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515226422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1515226422
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1938185775
Short name T374
Test name
Test status
Simulation time 6496325376 ps
CPU time 19.88 seconds
Started Jul 01 12:48:53 PM PDT 24
Finished Jul 01 12:49:14 PM PDT 24
Peak memory 216316 kb
Host smart-b1a4dbf1-c551-4bf1-85a7-9bd13bff4bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938185775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1938185775
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2778586008
Short name T714
Test name
Test status
Simulation time 746060054 ps
CPU time 1.53 seconds
Started Jul 01 12:48:59 PM PDT 24
Finished Jul 01 12:49:02 PM PDT 24
Peak memory 208012 kb
Host smart-536e0b77-7742-4e52-ae39-e3ab073bb008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778586008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2778586008
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3374874265
Short name T910
Test name
Test status
Simulation time 60963784 ps
CPU time 0.88 seconds
Started Jul 01 12:48:59 PM PDT 24
Finished Jul 01 12:49:02 PM PDT 24
Peak memory 205880 kb
Host smart-7b138dab-2837-4c53-8d4e-040a81e6743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374874265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3374874265
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3703190133
Short name T381
Test name
Test status
Simulation time 22621307652 ps
CPU time 20.29 seconds
Started Jul 01 12:48:59 PM PDT 24
Finished Jul 01 12:49:21 PM PDT 24
Peak memory 240908 kb
Host smart-a3e0e827-5244-47e8-9318-345651106e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703190133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3703190133
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.23316154
Short name T377
Test name
Test status
Simulation time 12252716 ps
CPU time 0.72 seconds
Started Jul 01 12:49:08 PM PDT 24
Finished Jul 01 12:49:12 PM PDT 24
Peak memory 205516 kb
Host smart-a86831ba-05e5-4daf-b764-039732bb4e38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23316154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.23316154
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.583403194
Short name T998
Test name
Test status
Simulation time 55572289 ps
CPU time 2.76 seconds
Started Jul 01 12:49:04 PM PDT 24
Finished Jul 01 12:49:10 PM PDT 24
Peak memory 232680 kb
Host smart-fb8a135d-a68d-4630-8d1f-5aea550c0fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583403194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.583403194
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2628173073
Short name T322
Test name
Test status
Simulation time 20608709 ps
CPU time 0.8 seconds
Started Jul 01 12:48:57 PM PDT 24
Finished Jul 01 12:48:59 PM PDT 24
Peak memory 206608 kb
Host smart-08607d5d-94fa-4eec-bcc7-85387a5a441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628173073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2628173073
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2228519271
Short name T507
Test name
Test status
Simulation time 40932894643 ps
CPU time 122.97 seconds
Started Jul 01 12:49:08 PM PDT 24
Finished Jul 01 12:51:14 PM PDT 24
Peak memory 238724 kb
Host smart-694e3164-1e24-4b25-b672-b52d32856c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228519271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2228519271
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2713558723
Short name T824
Test name
Test status
Simulation time 2233072659 ps
CPU time 14.83 seconds
Started Jul 01 12:49:05 PM PDT 24
Finished Jul 01 12:49:22 PM PDT 24
Peak memory 217712 kb
Host smart-8a2b1c8f-77bf-494d-a7b1-e21d3cfee5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713558723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2713558723
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3923672260
Short name T593
Test name
Test status
Simulation time 22359319994 ps
CPU time 119.37 seconds
Started Jul 01 12:49:04 PM PDT 24
Finished Jul 01 12:51:07 PM PDT 24
Peak memory 254120 kb
Host smart-e790d33a-5fe1-4645-89df-acdcae8ada00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923672260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3923672260
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1871747362
Short name T707
Test name
Test status
Simulation time 161422630 ps
CPU time 6.32 seconds
Started Jul 01 12:49:04 PM PDT 24
Finished Jul 01 12:49:13 PM PDT 24
Peak memory 224348 kb
Host smart-7f738f73-b9cc-4e2b-b46b-cf1fbf4235cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871747362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1871747362
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.20274563
Short name T130
Test name
Test status
Simulation time 10235101425 ps
CPU time 53.78 seconds
Started Jul 01 12:49:00 PM PDT 24
Finished Jul 01 12:49:57 PM PDT 24
Peak memory 257112 kb
Host smart-e6985fee-ef6f-42f4-98f0-b7a66dbd8706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20274563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.20274563
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3846802362
Short name T510
Test name
Test status
Simulation time 2179010159 ps
CPU time 12.62 seconds
Started Jul 01 12:49:03 PM PDT 24
Finished Jul 01 12:49:18 PM PDT 24
Peak memory 232768 kb
Host smart-b314b089-7dca-4695-8064-73ca3c6a1513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846802362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3846802362
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2869894843
Short name T216
Test name
Test status
Simulation time 62233607974 ps
CPU time 88.12 seconds
Started Jul 01 12:49:02 PM PDT 24
Finished Jul 01 12:50:33 PM PDT 24
Peak memory 224672 kb
Host smart-764d763e-b530-49e9-b388-16116bcfd725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869894843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2869894843
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.75905659
Short name T924
Test name
Test status
Simulation time 756264699 ps
CPU time 3.34 seconds
Started Jul 01 12:49:05 PM PDT 24
Finished Jul 01 12:49:11 PM PDT 24
Peak memory 224424 kb
Host smart-46f3b7e8-3a3b-4623-89b4-1ae6fb5a9ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75905659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.75905659
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4105789475
Short name T427
Test name
Test status
Simulation time 5788939336 ps
CPU time 6.28 seconds
Started Jul 01 12:49:01 PM PDT 24
Finished Jul 01 12:49:10 PM PDT 24
Peak memory 232784 kb
Host smart-55fa7a39-a544-4d3e-8389-8c8b496f457c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105789475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4105789475
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1160049257
Short name T36
Test name
Test status
Simulation time 117013295 ps
CPU time 3.82 seconds
Started Jul 01 12:49:02 PM PDT 24
Finished Jul 01 12:49:09 PM PDT 24
Peak memory 223064 kb
Host smart-d44d43a7-7252-43f7-8b28-1af42297d3fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1160049257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1160049257
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.397360286
Short name T704
Test name
Test status
Simulation time 1743394690 ps
CPU time 15.12 seconds
Started Jul 01 12:49:01 PM PDT 24
Finished Jul 01 12:49:18 PM PDT 24
Peak memory 216344 kb
Host smart-0ab8a5f2-d53d-484a-aeca-2053585ca0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397360286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.397360286
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1558779106
Short name T884
Test name
Test status
Simulation time 859447994 ps
CPU time 5.83 seconds
Started Jul 01 12:48:57 PM PDT 24
Finished Jul 01 12:49:04 PM PDT 24
Peak memory 216140 kb
Host smart-47318377-e5e0-4e31-bcb3-c8bd8b7e9593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558779106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1558779106
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1419912813
Short name T827
Test name
Test status
Simulation time 53551396 ps
CPU time 0.8 seconds
Started Jul 01 12:49:05 PM PDT 24
Finished Jul 01 12:49:08 PM PDT 24
Peak memory 206532 kb
Host smart-5509f39a-6e0f-416d-8ec2-312b6a5ddb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419912813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1419912813
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3245943269
Short name T83
Test name
Test status
Simulation time 503815956 ps
CPU time 0.86 seconds
Started Jul 01 12:49:03 PM PDT 24
Finished Jul 01 12:49:06 PM PDT 24
Peak memory 205932 kb
Host smart-63fb4778-fdb0-4e8a-a5d3-6b1e81ab4cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245943269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3245943269
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2028374932
Short name T573
Test name
Test status
Simulation time 486112441 ps
CPU time 3.3 seconds
Started Jul 01 12:49:07 PM PDT 24
Finished Jul 01 12:49:13 PM PDT 24
Peak memory 232640 kb
Host smart-5984d341-7f01-408b-b430-ec314854a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028374932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2028374932
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.809770964
Short name T61
Test name
Test status
Simulation time 12125779 ps
CPU time 0.74 seconds
Started Jul 01 12:49:11 PM PDT 24
Finished Jul 01 12:49:14 PM PDT 24
Peak memory 205888 kb
Host smart-f3fcfa83-2fdc-4b93-baf4-d8fcf92e077d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809770964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.809770964
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2995614124
Short name T911
Test name
Test status
Simulation time 209569046 ps
CPU time 3.64 seconds
Started Jul 01 12:49:08 PM PDT 24
Finished Jul 01 12:49:15 PM PDT 24
Peak memory 224456 kb
Host smart-5d060d78-1f41-4424-a4bc-8b98ab3cb12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995614124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2995614124
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3698263560
Short name T417
Test name
Test status
Simulation time 11883367 ps
CPU time 0.76 seconds
Started Jul 01 12:49:07 PM PDT 24
Finished Jul 01 12:49:11 PM PDT 24
Peak memory 205576 kb
Host smart-65d4c12c-4d9b-470e-a5df-f58a16c3ef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698263560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3698263560
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2625262311
Short name T270
Test name
Test status
Simulation time 269375563437 ps
CPU time 442.35 seconds
Started Jul 01 12:49:07 PM PDT 24
Finished Jul 01 12:56:33 PM PDT 24
Peak memory 250476 kb
Host smart-591822eb-c7e6-4fcf-85b3-07d63d118e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625262311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2625262311
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1239505011
Short name T907
Test name
Test status
Simulation time 20323368088 ps
CPU time 185.67 seconds
Started Jul 01 12:49:05 PM PDT 24
Finished Jul 01 12:52:14 PM PDT 24
Peak memory 249188 kb
Host smart-e01ab24a-36ac-445b-9951-45611d11f869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239505011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1239505011
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.185025909
Short name T369
Test name
Test status
Simulation time 6853885656 ps
CPU time 11.97 seconds
Started Jul 01 12:49:11 PM PDT 24
Finished Jul 01 12:49:25 PM PDT 24
Peak memory 219316 kb
Host smart-efe390f1-7250-4eda-9d46-d32b75eb7713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185025909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.185025909
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2094586992
Short name T589
Test name
Test status
Simulation time 41224013 ps
CPU time 2.77 seconds
Started Jul 01 12:49:07 PM PDT 24
Finished Jul 01 12:49:13 PM PDT 24
Peak memory 232692 kb
Host smart-c712949a-7e0c-4afa-9f41-9dbae5d5bdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094586992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2094586992
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2738189369
Short name T710
Test name
Test status
Simulation time 13125673 ps
CPU time 0.78 seconds
Started Jul 01 12:49:07 PM PDT 24
Finished Jul 01 12:49:11 PM PDT 24
Peak memory 215784 kb
Host smart-f36e2ff6-f4b5-4fe5-8c88-60db4d78737f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738189369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2738189369
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2869359926
Short name T735
Test name
Test status
Simulation time 7673158183 ps
CPU time 17.81 seconds
Started Jul 01 12:49:07 PM PDT 24
Finished Jul 01 12:49:28 PM PDT 24
Peak memory 232804 kb
Host smart-4e25ecf1-74d7-4218-966a-61aa2d2ce33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869359926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2869359926
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3836380490
Short name T131
Test name
Test status
Simulation time 9918481047 ps
CPU time 52.6 seconds
Started Jul 01 12:49:08 PM PDT 24
Finished Jul 01 12:50:04 PM PDT 24
Peak memory 239880 kb
Host smart-b5a3c923-d019-43f2-8ced-8b95015650b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836380490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3836380490
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3213842567
Short name T221
Test name
Test status
Simulation time 10720974241 ps
CPU time 21.11 seconds
Started Jul 01 12:49:07 PM PDT 24
Finished Jul 01 12:49:31 PM PDT 24
Peak memory 235880 kb
Host smart-60204842-daa4-4a10-a3c4-99b0ce12a0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213842567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3213842567
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1020300979
Short name T409
Test name
Test status
Simulation time 8243038995 ps
CPU time 9.39 seconds
Started Jul 01 12:49:07 PM PDT 24
Finished Jul 01 12:49:20 PM PDT 24
Peak memory 224664 kb
Host smart-b6d2c8b0-c926-4442-8d13-17bd86257537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020300979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1020300979
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.414718351
Short name T678
Test name
Test status
Simulation time 225389205 ps
CPU time 4.87 seconds
Started Jul 01 12:49:09 PM PDT 24
Finished Jul 01 12:49:17 PM PDT 24
Peak memory 223632 kb
Host smart-b68aa5c1-9c91-4958-a724-b19830a400e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=414718351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.414718351
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2550260618
Short name T783
Test name
Test status
Simulation time 245832504227 ps
CPU time 277.98 seconds
Started Jul 01 12:49:09 PM PDT 24
Finished Jul 01 12:53:50 PM PDT 24
Peak memory 265708 kb
Host smart-8e99f8e1-3c85-4140-9cf4-9b4a7cd366d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550260618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2550260618
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1441130570
Short name T740
Test name
Test status
Simulation time 4988365157 ps
CPU time 28.59 seconds
Started Jul 01 12:49:02 PM PDT 24
Finished Jul 01 12:49:34 PM PDT 24
Peak memory 216324 kb
Host smart-43b7783d-d840-4cce-be44-a0705e36a786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441130570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1441130570
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.285380360
Short name T620
Test name
Test status
Simulation time 642671896 ps
CPU time 1.49 seconds
Started Jul 01 12:49:04 PM PDT 24
Finished Jul 01 12:49:07 PM PDT 24
Peak memory 207904 kb
Host smart-8e0bd4a0-527c-4b6d-85ad-760507aad81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285380360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.285380360
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3651817085
Short name T454
Test name
Test status
Simulation time 94762104 ps
CPU time 1.87 seconds
Started Jul 01 12:49:11 PM PDT 24
Finished Jul 01 12:49:15 PM PDT 24
Peak memory 216268 kb
Host smart-fb71fc10-7dcf-4e0f-adea-09470f6b7df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651817085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3651817085
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3190532195
Short name T866
Test name
Test status
Simulation time 133725222 ps
CPU time 0.83 seconds
Started Jul 01 12:49:07 PM PDT 24
Finished Jul 01 12:49:11 PM PDT 24
Peak memory 205936 kb
Host smart-4da6b0f0-d4e9-477a-84c1-7f7f109a663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190532195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3190532195
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3331192313
Short name T569
Test name
Test status
Simulation time 1108087622 ps
CPU time 6.79 seconds
Started Jul 01 12:49:06 PM PDT 24
Finished Jul 01 12:49:16 PM PDT 24
Peak memory 224512 kb
Host smart-9c8333d5-146d-4898-b5fe-13ad741115b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331192313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3331192313
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1398095113
Short name T967
Test name
Test status
Simulation time 11551500 ps
CPU time 0.7 seconds
Started Jul 01 12:46:38 PM PDT 24
Finished Jul 01 12:46:39 PM PDT 24
Peak memory 205484 kb
Host smart-0c3bf112-bea1-4ace-997d-69477bbc550a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398095113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
398095113
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2224239062
Short name T971
Test name
Test status
Simulation time 1455159586 ps
CPU time 12.89 seconds
Started Jul 01 12:46:32 PM PDT 24
Finished Jul 01 12:46:45 PM PDT 24
Peak memory 224432 kb
Host smart-0720eb70-403c-4dbc-9510-a7f4aadbb309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224239062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2224239062
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3237179448
Short name T878
Test name
Test status
Simulation time 39575472 ps
CPU time 0.79 seconds
Started Jul 01 12:46:33 PM PDT 24
Finished Jul 01 12:46:35 PM PDT 24
Peak memory 206588 kb
Host smart-7329d530-957e-405c-8ad3-1aadd708d9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237179448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3237179448
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.398854272
Short name T711
Test name
Test status
Simulation time 33973606015 ps
CPU time 250.19 seconds
Started Jul 01 12:46:38 PM PDT 24
Finished Jul 01 12:50:49 PM PDT 24
Peak memory 265588 kb
Host smart-24064032-d578-4baf-b3e0-1116dd8d2347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398854272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.398854272
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3399259401
Short name T264
Test name
Test status
Simulation time 18119774067 ps
CPU time 69.42 seconds
Started Jul 01 12:46:37 PM PDT 24
Finished Jul 01 12:47:47 PM PDT 24
Peak memory 249260 kb
Host smart-7e841317-1f75-4ddc-8951-82f059f0ec5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399259401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3399259401
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.296189349
Short name T139
Test name
Test status
Simulation time 4933449165 ps
CPU time 124.49 seconds
Started Jul 01 12:46:36 PM PDT 24
Finished Jul 01 12:48:42 PM PDT 24
Peak memory 264748 kb
Host smart-8a24f027-71b8-4f00-8c70-65daf901c1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296189349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
296189349
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1655215157
Short name T128
Test name
Test status
Simulation time 264120040 ps
CPU time 6.06 seconds
Started Jul 01 12:46:38 PM PDT 24
Finished Jul 01 12:46:45 PM PDT 24
Peak memory 232664 kb
Host smart-c3c1d674-1558-4280-8ccd-7f59422ab661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655215157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1655215157
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.827719188
Short name T948
Test name
Test status
Simulation time 2194426173 ps
CPU time 9.21 seconds
Started Jul 01 12:46:35 PM PDT 24
Finished Jul 01 12:46:46 PM PDT 24
Peak memory 237120 kb
Host smart-62a4fb74-96a8-48b0-9f2c-799b3d43a6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827719188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
827719188
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1781890349
Short name T246
Test name
Test status
Simulation time 10001896020 ps
CPU time 32.61 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:47:20 PM PDT 24
Peak memory 232804 kb
Host smart-ac4f9142-6c20-41a8-a8bc-30b4c36161f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781890349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1781890349
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2617939327
Short name T736
Test name
Test status
Simulation time 76160772 ps
CPU time 2.29 seconds
Started Jul 01 12:46:34 PM PDT 24
Finished Jul 01 12:46:38 PM PDT 24
Peak memory 224432 kb
Host smart-ef3f6604-ed2d-4710-b31a-6ffc1a469f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617939327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2617939327
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3278842253
Short name T834
Test name
Test status
Simulation time 92986565 ps
CPU time 2.18 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:46:49 PM PDT 24
Peak memory 223700 kb
Host smart-2031ca94-e61b-49af-9da8-1b1053e711e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278842253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3278842253
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.356101814
Short name T622
Test name
Test status
Simulation time 31739954 ps
CPU time 2.16 seconds
Started Jul 01 12:46:30 PM PDT 24
Finished Jul 01 12:46:33 PM PDT 24
Peak memory 223808 kb
Host smart-96e04f01-c6b9-4f0d-9d0d-d6099484a002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356101814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.356101814
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2692469926
Short name T384
Test name
Test status
Simulation time 250403085 ps
CPU time 4.72 seconds
Started Jul 01 12:46:36 PM PDT 24
Finished Jul 01 12:46:41 PM PDT 24
Peak memory 220608 kb
Host smart-d61d4ea8-3d49-4f98-8bc8-52eb47213deb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2692469926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2692469926
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.608521847
Short name T68
Test name
Test status
Simulation time 235192572 ps
CPU time 1.06 seconds
Started Jul 01 12:46:35 PM PDT 24
Finished Jul 01 12:46:37 PM PDT 24
Peak memory 236544 kb
Host smart-50bf407b-2a46-4e60-bf4e-5feda85bc565
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608521847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.608521847
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.191807585
Short name T765
Test name
Test status
Simulation time 29570186102 ps
CPU time 28.69 seconds
Started Jul 01 12:46:34 PM PDT 24
Finished Jul 01 12:47:04 PM PDT 24
Peak memory 216576 kb
Host smart-1d3366a0-7609-4475-832e-3bb0f5ef848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191807585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.191807585
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2600130134
Short name T534
Test name
Test status
Simulation time 163499808 ps
CPU time 1.59 seconds
Started Jul 01 12:46:33 PM PDT 24
Finished Jul 01 12:46:35 PM PDT 24
Peak memory 207876 kb
Host smart-044bf303-cf29-42d4-82a4-854757433f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600130134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2600130134
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1665787312
Short name T390
Test name
Test status
Simulation time 13142139 ps
CPU time 0.72 seconds
Started Jul 01 12:46:32 PM PDT 24
Finished Jul 01 12:46:33 PM PDT 24
Peak memory 205628 kb
Host smart-23f19bfe-fe2f-404c-a16f-c349fa28aff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665787312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1665787312
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1550851445
Short name T594
Test name
Test status
Simulation time 336739687 ps
CPU time 1 seconds
Started Jul 01 12:46:32 PM PDT 24
Finished Jul 01 12:46:34 PM PDT 24
Peak memory 206916 kb
Host smart-3ec1e257-cc34-45d2-aade-79b0599adfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550851445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1550851445
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2429696266
Short name T522
Test name
Test status
Simulation time 32606055 ps
CPU time 2.45 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:46:50 PM PDT 24
Peak memory 224156 kb
Host smart-13104d51-756a-43fe-aff7-a055f7f62299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429696266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2429696266
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4189398722
Short name T311
Test name
Test status
Simulation time 42082440 ps
CPU time 0.73 seconds
Started Jul 01 12:49:16 PM PDT 24
Finished Jul 01 12:49:18 PM PDT 24
Peak memory 205860 kb
Host smart-444860c9-bf48-4224-9f53-ca56d3b65ab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189398722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4189398722
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2877343048
Short name T721
Test name
Test status
Simulation time 193665638 ps
CPU time 2.43 seconds
Started Jul 01 12:49:12 PM PDT 24
Finished Jul 01 12:49:16 PM PDT 24
Peak memory 224448 kb
Host smart-8a038bbe-02f7-4588-af49-955d07ebd9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877343048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2877343048
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2841038606
Short name T345
Test name
Test status
Simulation time 68735392 ps
CPU time 0.81 seconds
Started Jul 01 12:49:11 PM PDT 24
Finished Jul 01 12:49:14 PM PDT 24
Peak memory 206608 kb
Host smart-5ee8c10c-89c3-4f33-9347-dce9497a83be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841038606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2841038606
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3646932764
Short name T744
Test name
Test status
Simulation time 138188438 ps
CPU time 0.78 seconds
Started Jul 01 12:49:12 PM PDT 24
Finished Jul 01 12:49:15 PM PDT 24
Peak memory 215788 kb
Host smart-b00db7ed-7515-4a2d-97b2-1da1d645654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646932764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3646932764
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1067499996
Short name T125
Test name
Test status
Simulation time 15562926607 ps
CPU time 108.07 seconds
Started Jul 01 12:49:11 PM PDT 24
Finished Jul 01 12:51:02 PM PDT 24
Peak memory 241036 kb
Host smart-6df6a468-f7bb-4155-9380-3ad4dca1ee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067499996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1067499996
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1790860317
Short name T990
Test name
Test status
Simulation time 14342039779 ps
CPU time 13.85 seconds
Started Jul 01 12:49:13 PM PDT 24
Finished Jul 01 12:49:28 PM PDT 24
Peak memory 217792 kb
Host smart-dc6d6e31-696a-4606-9f22-c3c2538b3efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790860317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1790860317
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2401017443
Short name T838
Test name
Test status
Simulation time 23158819066 ps
CPU time 124.32 seconds
Started Jul 01 12:49:12 PM PDT 24
Finished Jul 01 12:51:19 PM PDT 24
Peak memory 256468 kb
Host smart-db84d896-547b-43d3-9519-23e4af2e21e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401017443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2401017443
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1557306857
Short name T319
Test name
Test status
Simulation time 27136327559 ps
CPU time 17.74 seconds
Started Jul 01 12:49:18 PM PDT 24
Finished Jul 01 12:49:41 PM PDT 24
Peak memory 232776 kb
Host smart-5a1fe21f-8ac9-4db1-8b12-1c91ddf7fbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557306857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1557306857
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.769219035
Short name T194
Test name
Test status
Simulation time 40417828360 ps
CPU time 62.21 seconds
Started Jul 01 12:49:19 PM PDT 24
Finished Jul 01 12:50:26 PM PDT 24
Peak memory 232800 kb
Host smart-d7e9a885-d4d1-48ae-bcbb-f0c00efc6266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769219035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.769219035
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.489727551
Short name T952
Test name
Test status
Simulation time 2340649813 ps
CPU time 14.16 seconds
Started Jul 01 12:49:12 PM PDT 24
Finished Jul 01 12:49:28 PM PDT 24
Peak memory 232784 kb
Host smart-22c08259-028c-495b-b1e4-03bb97ac5244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489727551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.489727551
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2904131742
Short name T570
Test name
Test status
Simulation time 8892602992 ps
CPU time 10.35 seconds
Started Jul 01 12:49:12 PM PDT 24
Finished Jul 01 12:49:25 PM PDT 24
Peak memory 240608 kb
Host smart-a2675091-bb96-4fca-9cbb-8dc1808b99b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904131742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2904131742
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3489879779
Short name T346
Test name
Test status
Simulation time 1506987936 ps
CPU time 6.11 seconds
Started Jul 01 12:49:14 PM PDT 24
Finished Jul 01 12:49:22 PM PDT 24
Peak memory 220076 kb
Host smart-0446a8d9-4894-4b87-83f2-523b947113ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3489879779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3489879779
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2191074117
Short name T157
Test name
Test status
Simulation time 112461200525 ps
CPU time 437.55 seconds
Started Jul 01 12:49:16 PM PDT 24
Finished Jul 01 12:56:35 PM PDT 24
Peak memory 269848 kb
Host smart-760dfcdb-a054-469f-bc6d-d8e7a55443e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191074117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2191074117
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1544657026
Short name T24
Test name
Test status
Simulation time 5024444866 ps
CPU time 26.28 seconds
Started Jul 01 12:49:08 PM PDT 24
Finished Jul 01 12:49:38 PM PDT 24
Peak memory 216204 kb
Host smart-13f3dc28-8c11-4f42-9856-bf4cdf51a05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544657026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1544657026
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3374400388
Short name T862
Test name
Test status
Simulation time 201845854 ps
CPU time 1.93 seconds
Started Jul 01 12:49:06 PM PDT 24
Finished Jul 01 12:49:10 PM PDT 24
Peak memory 216124 kb
Host smart-38fc2568-bf86-4ed8-ae7e-04db1176db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374400388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3374400388
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2771483558
Short name T701
Test name
Test status
Simulation time 311219630 ps
CPU time 1.16 seconds
Started Jul 01 12:49:14 PM PDT 24
Finished Jul 01 12:49:16 PM PDT 24
Peak memory 207944 kb
Host smart-224391d0-6e30-4c3e-8bbf-bb6ce4bd68e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771483558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2771483558
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4089630809
Short name T341
Test name
Test status
Simulation time 27966799 ps
CPU time 0.68 seconds
Started Jul 01 12:49:14 PM PDT 24
Finished Jul 01 12:49:17 PM PDT 24
Peak memory 205624 kb
Host smart-7be1ec4b-b202-4715-9ea2-615bad9f9c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089630809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4089630809
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1487001789
Short name T46
Test name
Test status
Simulation time 73115668701 ps
CPU time 37.36 seconds
Started Jul 01 12:49:13 PM PDT 24
Finished Jul 01 12:49:52 PM PDT 24
Peak memory 240924 kb
Host smart-509fd692-c238-49f5-8280-66abe34a0a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487001789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1487001789
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1871079858
Short name T820
Test name
Test status
Simulation time 78827942 ps
CPU time 0.7 seconds
Started Jul 01 12:49:18 PM PDT 24
Finished Jul 01 12:49:20 PM PDT 24
Peak memory 204912 kb
Host smart-85c8058b-b14e-4ce5-be08-40063f7ae169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871079858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1871079858
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.87167814
Short name T733
Test name
Test status
Simulation time 1131903649 ps
CPU time 5.55 seconds
Started Jul 01 12:49:18 PM PDT 24
Finished Jul 01 12:49:25 PM PDT 24
Peak memory 232656 kb
Host smart-83e6eb2b-0898-40b6-8b4e-e17e07e1be9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87167814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.87167814
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3338503548
Short name T467
Test name
Test status
Simulation time 15329207 ps
CPU time 0.74 seconds
Started Jul 01 12:49:16 PM PDT 24
Finished Jul 01 12:49:18 PM PDT 24
Peak memory 205564 kb
Host smart-1b46afe4-24f7-4c23-95e6-917522e41bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338503548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3338503548
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.689684936
Short name T578
Test name
Test status
Simulation time 8648828130 ps
CPU time 50.38 seconds
Started Jul 01 12:49:18 PM PDT 24
Finished Jul 01 12:50:11 PM PDT 24
Peak memory 257308 kb
Host smart-bfb36ab3-ca50-47d2-b3fb-a6de56d86c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689684936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.689684936
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2332599881
Short name T831
Test name
Test status
Simulation time 3876762184 ps
CPU time 32.78 seconds
Started Jul 01 12:49:19 PM PDT 24
Finished Jul 01 12:49:59 PM PDT 24
Peak memory 241036 kb
Host smart-dab5dcee-3c30-4e74-9017-44183c099231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332599881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2332599881
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4026149139
Short name T74
Test name
Test status
Simulation time 29733450116 ps
CPU time 160.06 seconds
Started Jul 01 12:49:18 PM PDT 24
Finished Jul 01 12:52:00 PM PDT 24
Peak memory 250296 kb
Host smart-f8a63243-6d29-4477-8e34-7178add71378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026149139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4026149139
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2781844212
Short name T757
Test name
Test status
Simulation time 49277760 ps
CPU time 3.2 seconds
Started Jul 01 12:49:18 PM PDT 24
Finished Jul 01 12:49:26 PM PDT 24
Peak memory 232708 kb
Host smart-72293beb-78f2-46d9-9b45-f15d507f4fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781844212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2781844212
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3256626289
Short name T602
Test name
Test status
Simulation time 14910556302 ps
CPU time 49.54 seconds
Started Jul 01 12:49:18 PM PDT 24
Finished Jul 01 12:50:09 PM PDT 24
Peak memory 249468 kb
Host smart-6dc7a954-e493-44a4-88a2-240a9708e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256626289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3256626289
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2226556551
Short name T899
Test name
Test status
Simulation time 2230631364 ps
CPU time 9.23 seconds
Started Jul 01 12:49:17 PM PDT 24
Finished Jul 01 12:49:28 PM PDT 24
Peak memory 232752 kb
Host smart-dded8d89-b7b1-46b9-a51a-eea13f9fa216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226556551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2226556551
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2110839742
Short name T232
Test name
Test status
Simulation time 118639713242 ps
CPU time 66.52 seconds
Started Jul 01 12:49:20 PM PDT 24
Finished Jul 01 12:50:33 PM PDT 24
Peak memory 233696 kb
Host smart-2976cfbf-bfa8-43ac-ae19-e20752bbcf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110839742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2110839742
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.775953837
Short name T542
Test name
Test status
Simulation time 1298546338 ps
CPU time 9.38 seconds
Started Jul 01 12:49:18 PM PDT 24
Finished Jul 01 12:49:32 PM PDT 24
Peak memory 232656 kb
Host smart-0512fc74-5ea2-49f5-b600-441d3d04765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775953837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.775953837
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.722540598
Short name T650
Test name
Test status
Simulation time 391211113 ps
CPU time 4.55 seconds
Started Jul 01 12:49:19 PM PDT 24
Finished Jul 01 12:49:29 PM PDT 24
Peak memory 232632 kb
Host smart-5fc4c2ba-011c-4026-9657-6532ea0967f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722540598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.722540598
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3787544721
Short name T392
Test name
Test status
Simulation time 142430329 ps
CPU time 4.29 seconds
Started Jul 01 12:49:19 PM PDT 24
Finished Jul 01 12:49:30 PM PDT 24
Peak memory 220320 kb
Host smart-992e97b1-234b-4e44-ab18-4ba8225e74ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3787544721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3787544721
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1088495350
Short name T887
Test name
Test status
Simulation time 3088861610 ps
CPU time 24.76 seconds
Started Jul 01 12:49:19 PM PDT 24
Finished Jul 01 12:49:49 PM PDT 24
Peak memory 224704 kb
Host smart-3f089faf-4a62-43d2-9f4a-a76a804d698a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088495350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1088495350
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.388021825
Short name T335
Test name
Test status
Simulation time 2326715655 ps
CPU time 5.88 seconds
Started Jul 01 12:49:18 PM PDT 24
Finished Jul 01 12:49:25 PM PDT 24
Peak memory 216372 kb
Host smart-303ae387-03e0-4cee-ba5b-ce192ced28af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388021825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.388021825
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.793207941
Short name T614
Test name
Test status
Simulation time 3051470772 ps
CPU time 4.55 seconds
Started Jul 01 12:49:19 PM PDT 24
Finished Jul 01 12:49:29 PM PDT 24
Peak memory 216360 kb
Host smart-853900f7-3b2c-4d3f-a63f-063aa99edfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793207941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.793207941
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1659344836
Short name T438
Test name
Test status
Simulation time 451717066 ps
CPU time 3.13 seconds
Started Jul 01 12:49:17 PM PDT 24
Finished Jul 01 12:49:21 PM PDT 24
Peak memory 216400 kb
Host smart-b9648b65-9e0d-4bb3-a91f-ada68b597a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659344836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1659344836
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.656138567
Short name T958
Test name
Test status
Simulation time 17240884 ps
CPU time 0.71 seconds
Started Jul 01 12:49:20 PM PDT 24
Finished Jul 01 12:49:27 PM PDT 24
Peak memory 205552 kb
Host smart-6ca9543a-a08a-4d06-aa1d-7c33a4773905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656138567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.656138567
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.469978813
Short name T833
Test name
Test status
Simulation time 3709500286 ps
CPU time 16.77 seconds
Started Jul 01 12:49:19 PM PDT 24
Finished Jul 01 12:49:43 PM PDT 24
Peak memory 239852 kb
Host smart-d6991194-f060-46d1-825b-d782d268e0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469978813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.469978813
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2451882557
Short name T389
Test name
Test status
Simulation time 17502041 ps
CPU time 0.69 seconds
Started Jul 01 12:49:26 PM PDT 24
Finished Jul 01 12:49:31 PM PDT 24
Peak memory 204968 kb
Host smart-e6cab596-4407-461a-8998-3b61d9021ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451882557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2451882557
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.995819780
Short name T332
Test name
Test status
Simulation time 35341193 ps
CPU time 2.19 seconds
Started Jul 01 12:49:26 PM PDT 24
Finished Jul 01 12:49:32 PM PDT 24
Peak memory 224436 kb
Host smart-e19e9139-8a6f-42ac-8284-ae63e1327c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995819780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.995819780
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.217692964
Short name T453
Test name
Test status
Simulation time 33938900 ps
CPU time 0.77 seconds
Started Jul 01 12:49:18 PM PDT 24
Finished Jul 01 12:49:23 PM PDT 24
Peak memory 206608 kb
Host smart-1ec97218-85c3-4e90-9482-77b723b4ccce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217692964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.217692964
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2570990399
Short name T939
Test name
Test status
Simulation time 6916405259 ps
CPU time 37.79 seconds
Started Jul 01 12:49:24 PM PDT 24
Finished Jul 01 12:50:07 PM PDT 24
Peak memory 251588 kb
Host smart-4ad27830-0de3-4b6a-930c-32dbda05443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570990399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2570990399
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.431586838
Short name T496
Test name
Test status
Simulation time 6961708680 ps
CPU time 52.93 seconds
Started Jul 01 12:49:22 PM PDT 24
Finished Jul 01 12:50:20 PM PDT 24
Peak memory 252804 kb
Host smart-3ef04766-81f5-451e-94d1-b3699587f423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431586838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.431586838
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3789056792
Short name T142
Test name
Test status
Simulation time 12467933283 ps
CPU time 170.92 seconds
Started Jul 01 12:49:22 PM PDT 24
Finished Jul 01 12:52:19 PM PDT 24
Peak memory 249256 kb
Host smart-094a6c5f-d8fa-40da-9fc7-6b48234c9641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789056792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3789056792
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4119946212
Short name T333
Test name
Test status
Simulation time 263280213 ps
CPU time 2.82 seconds
Started Jul 01 12:49:21 PM PDT 24
Finished Jul 01 12:49:30 PM PDT 24
Peak memory 232548 kb
Host smart-5bacb920-8f9e-449c-a6ae-f5fdbf083313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119946212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4119946212
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3794393571
Short name T383
Test name
Test status
Simulation time 33204987 ps
CPU time 0.75 seconds
Started Jul 01 12:49:22 PM PDT 24
Finished Jul 01 12:49:28 PM PDT 24
Peak memory 215812 kb
Host smart-476592a8-46b2-41b7-a019-61fd0c346219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794393571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3794393571
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1062252760
Short name T608
Test name
Test status
Simulation time 122639233 ps
CPU time 3.18 seconds
Started Jul 01 12:49:23 PM PDT 24
Finished Jul 01 12:49:31 PM PDT 24
Peak memory 232560 kb
Host smart-a800ced2-51cf-4e03-b9b0-177fdc3cff4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062252760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1062252760
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1744275639
Short name T233
Test name
Test status
Simulation time 337412074 ps
CPU time 8.46 seconds
Started Jul 01 12:49:25 PM PDT 24
Finished Jul 01 12:49:38 PM PDT 24
Peak memory 239944 kb
Host smart-30d87cf8-0c9e-4a5d-96c3-c205e406c77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744275639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1744275639
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2746625598
Short name T19
Test name
Test status
Simulation time 401460212 ps
CPU time 4.77 seconds
Started Jul 01 12:49:24 PM PDT 24
Finished Jul 01 12:49:34 PM PDT 24
Peak memory 224452 kb
Host smart-7a3c102c-1f48-4478-b3e1-40f1021cb12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746625598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2746625598
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.911239181
Short name T912
Test name
Test status
Simulation time 30701367 ps
CPU time 2.54 seconds
Started Jul 01 12:49:22 PM PDT 24
Finished Jul 01 12:49:30 PM PDT 24
Peak memory 232408 kb
Host smart-fea10545-0111-47b8-a9d6-9986488b8f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911239181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.911239181
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3692167772
Short name T147
Test name
Test status
Simulation time 1916477153 ps
CPU time 4.02 seconds
Started Jul 01 12:49:25 PM PDT 24
Finished Jul 01 12:49:34 PM PDT 24
Peak memory 219928 kb
Host smart-a4502e20-2871-4b04-bada-2b2e0d541a33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3692167772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3692167772
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.403974074
Short name T687
Test name
Test status
Simulation time 12581788 ps
CPU time 0.74 seconds
Started Jul 01 12:49:19 PM PDT 24
Finished Jul 01 12:49:27 PM PDT 24
Peak memory 205564 kb
Host smart-657c6f71-c6b9-4405-a843-e6f066196397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403974074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.403974074
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1353751752
Short name T516
Test name
Test status
Simulation time 2577421911 ps
CPU time 4.98 seconds
Started Jul 01 12:49:16 PM PDT 24
Finished Jul 01 12:49:23 PM PDT 24
Peak memory 216308 kb
Host smart-41e196e4-f804-4228-9bf7-b48e5298134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353751752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1353751752
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1710384493
Short name T419
Test name
Test status
Simulation time 105125371 ps
CPU time 1.27 seconds
Started Jul 01 12:49:25 PM PDT 24
Finished Jul 01 12:49:30 PM PDT 24
Peak memory 216220 kb
Host smart-1f4e0bcc-c0c5-4aad-8c18-cf00d83678d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710384493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1710384493
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.847078671
Short name T915
Test name
Test status
Simulation time 202086760 ps
CPU time 0.92 seconds
Started Jul 01 12:49:22 PM PDT 24
Finished Jul 01 12:49:29 PM PDT 24
Peak memory 206996 kb
Host smart-0f86526a-97ea-48c8-9b1d-f13e40230fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847078671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.847078671
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.521267642
Short name T668
Test name
Test status
Simulation time 5741980770 ps
CPU time 5.19 seconds
Started Jul 01 12:49:21 PM PDT 24
Finished Jul 01 12:49:32 PM PDT 24
Peak memory 224500 kb
Host smart-cae2a34b-aca1-4e9a-b1d9-6d668bb37251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521267642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.521267642
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1750112466
Short name T348
Test name
Test status
Simulation time 14972633 ps
CPU time 0.73 seconds
Started Jul 01 12:49:30 PM PDT 24
Finished Jul 01 12:49:34 PM PDT 24
Peak memory 206020 kb
Host smart-95d89ecc-49e3-4d2d-9c1d-59e12987826a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750112466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1750112466
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3152565028
Short name T160
Test name
Test status
Simulation time 165907125 ps
CPU time 4.04 seconds
Started Jul 01 12:49:28 PM PDT 24
Finished Jul 01 12:49:36 PM PDT 24
Peak memory 232716 kb
Host smart-65ad30f2-fe8d-4183-82c4-064459bece77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152565028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3152565028
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3807727522
Short name T651
Test name
Test status
Simulation time 100247746 ps
CPU time 0.83 seconds
Started Jul 01 12:49:23 PM PDT 24
Finished Jul 01 12:49:29 PM PDT 24
Peak memory 206592 kb
Host smart-4fdfe659-ea2d-4199-bd20-3e0480a5d054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807727522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3807727522
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.29153691
Short name T554
Test name
Test status
Simulation time 4805737586 ps
CPU time 81.96 seconds
Started Jul 01 12:49:28 PM PDT 24
Finished Jul 01 12:50:54 PM PDT 24
Peak memory 249220 kb
Host smart-f019565a-517c-4466-b636-ed34d081eb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29153691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.29153691
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.522953588
Short name T473
Test name
Test status
Simulation time 40627812747 ps
CPU time 72.67 seconds
Started Jul 01 12:49:30 PM PDT 24
Finished Jul 01 12:50:46 PM PDT 24
Peak memory 232776 kb
Host smart-e2217941-e67a-4927-acb9-97d7f1e6cde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522953588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.522953588
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3790823849
Short name T406
Test name
Test status
Simulation time 494072936 ps
CPU time 10.6 seconds
Started Jul 01 12:49:30 PM PDT 24
Finished Jul 01 12:49:44 PM PDT 24
Peak memory 224460 kb
Host smart-7a1986fb-cf6a-497b-9945-4af7ca1d2c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790823849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3790823849
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1047233589
Short name T640
Test name
Test status
Simulation time 1917662823 ps
CPU time 23.57 seconds
Started Jul 01 12:49:29 PM PDT 24
Finished Jul 01 12:49:56 PM PDT 24
Peak memory 249116 kb
Host smart-6c7e4ba1-2b62-4033-8b29-8b7e023ef5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047233589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1047233589
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3359957100
Short name T582
Test name
Test status
Simulation time 347615209 ps
CPU time 4.28 seconds
Started Jul 01 12:49:25 PM PDT 24
Finished Jul 01 12:49:34 PM PDT 24
Peak memory 232724 kb
Host smart-11177abd-94e0-4978-bece-93473e5fcf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359957100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3359957100
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3551370302
Short name T672
Test name
Test status
Simulation time 553563910 ps
CPU time 15.25 seconds
Started Jul 01 12:49:27 PM PDT 24
Finished Jul 01 12:49:47 PM PDT 24
Peak memory 232700 kb
Host smart-842c9618-cab9-452a-ac99-6b9532e007ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551370302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3551370302
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2574642970
Short name T271
Test name
Test status
Simulation time 5230153073 ps
CPU time 20.29 seconds
Started Jul 01 12:49:23 PM PDT 24
Finished Jul 01 12:49:48 PM PDT 24
Peak memory 240668 kb
Host smart-2a64899e-09a9-4366-8232-c148e45d33d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574642970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2574642970
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.485065997
Short name T790
Test name
Test status
Simulation time 382600942 ps
CPU time 5.1 seconds
Started Jul 01 12:49:25 PM PDT 24
Finished Jul 01 12:49:34 PM PDT 24
Peak memory 224508 kb
Host smart-fbe65114-b4ea-4c53-ab99-99e6036d3e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485065997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.485065997
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1004577017
Short name T695
Test name
Test status
Simulation time 4247144570 ps
CPU time 12.97 seconds
Started Jul 01 12:49:28 PM PDT 24
Finished Jul 01 12:49:45 PM PDT 24
Peak memory 220472 kb
Host smart-01992b9c-96c5-4bf4-9d23-5a9ab478e3e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1004577017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1004577017
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.227810561
Short name T23
Test name
Test status
Simulation time 24317416708 ps
CPU time 179.96 seconds
Started Jul 01 12:49:28 PM PDT 24
Finished Jul 01 12:52:32 PM PDT 24
Peak memory 255952 kb
Host smart-1011a77e-2f3c-416a-bd75-2f921d2aa9cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227810561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.227810561
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3077135924
Short name T563
Test name
Test status
Simulation time 85110516034 ps
CPU time 44.44 seconds
Started Jul 01 12:49:22 PM PDT 24
Finished Jul 01 12:50:12 PM PDT 24
Peak memory 216324 kb
Host smart-a9970abf-40b0-4406-846f-36c457ccb5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077135924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3077135924
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2169095987
Short name T722
Test name
Test status
Simulation time 24353024006 ps
CPU time 17.97 seconds
Started Jul 01 12:49:22 PM PDT 24
Finished Jul 01 12:49:46 PM PDT 24
Peak memory 216376 kb
Host smart-fbc78173-a44f-4f2c-a446-bca4176d83e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169095987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2169095987
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3816277640
Short name T961
Test name
Test status
Simulation time 64330186 ps
CPU time 0.9 seconds
Started Jul 01 12:49:23 PM PDT 24
Finished Jul 01 12:49:29 PM PDT 24
Peak memory 206996 kb
Host smart-c1c85c2c-16dc-42f2-9afb-ff1b762a55a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816277640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3816277640
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3570264212
Short name T443
Test name
Test status
Simulation time 102645476 ps
CPU time 1 seconds
Started Jul 01 12:49:22 PM PDT 24
Finished Jul 01 12:49:29 PM PDT 24
Peak memory 206000 kb
Host smart-36f30a06-8a01-489f-8f08-a9f1e54b6390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570264212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3570264212
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2874523037
Short name T187
Test name
Test status
Simulation time 1235396230 ps
CPU time 9.04 seconds
Started Jul 01 12:49:30 PM PDT 24
Finished Jul 01 12:49:42 PM PDT 24
Peak memory 224520 kb
Host smart-e1bc9532-9516-481c-be05-543a7ef880ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874523037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2874523037
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2079899444
Short name T560
Test name
Test status
Simulation time 54396436 ps
CPU time 0.72 seconds
Started Jul 01 12:49:36 PM PDT 24
Finished Jul 01 12:49:40 PM PDT 24
Peak memory 205000 kb
Host smart-b0868ec3-e8c7-44ba-96d6-19f6ff4d3833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079899444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2079899444
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.951088617
Short name T326
Test name
Test status
Simulation time 927773105 ps
CPU time 4.26 seconds
Started Jul 01 12:49:31 PM PDT 24
Finished Jul 01 12:49:38 PM PDT 24
Peak memory 224468 kb
Host smart-fd461808-54df-4658-8af7-67af73491dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951088617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.951088617
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.627588617
Short name T904
Test name
Test status
Simulation time 12489037 ps
CPU time 0.74 seconds
Started Jul 01 12:49:29 PM PDT 24
Finished Jul 01 12:49:33 PM PDT 24
Peak memory 205916 kb
Host smart-0a0f2bbd-20f7-413d-a094-9a3c7238c086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627588617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.627588617
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.931374890
Short name T219
Test name
Test status
Simulation time 6666489797 ps
CPU time 39.29 seconds
Started Jul 01 12:49:34 PM PDT 24
Finished Jul 01 12:50:16 PM PDT 24
Peak memory 253784 kb
Host smart-419af113-c7c5-4178-9bd8-0dedf7fd9100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931374890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.931374890
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.224540124
Short name T301
Test name
Test status
Simulation time 31568140258 ps
CPU time 76.9 seconds
Started Jul 01 12:49:38 PM PDT 24
Finished Jul 01 12:50:57 PM PDT 24
Peak memory 232812 kb
Host smart-fd23f1e2-e16f-469f-abaa-f47e98fa2a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224540124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.224540124
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1846650770
Short name T48
Test name
Test status
Simulation time 77071205290 ps
CPU time 36.26 seconds
Started Jul 01 12:49:38 PM PDT 24
Finished Jul 01 12:50:17 PM PDT 24
Peak memory 232888 kb
Host smart-46704aec-0a9e-41c0-8e77-075b2b5d0bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846650770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1846650770
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1123117802
Short name T660
Test name
Test status
Simulation time 508943888 ps
CPU time 7.96 seconds
Started Jul 01 12:49:36 PM PDT 24
Finished Jul 01 12:49:47 PM PDT 24
Peak memory 224500 kb
Host smart-2d346c0f-1be4-4c66-9572-7293408e92c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123117802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1123117802
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1060581520
Short name T179
Test name
Test status
Simulation time 60853954881 ps
CPU time 135.65 seconds
Started Jul 01 12:49:33 PM PDT 24
Finished Jul 01 12:51:52 PM PDT 24
Peak memory 251076 kb
Host smart-67218a51-914d-4ab9-9fee-f813dd6bc0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060581520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1060581520
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1258112770
Short name T729
Test name
Test status
Simulation time 467306616 ps
CPU time 5.41 seconds
Started Jul 01 12:49:34 PM PDT 24
Finished Jul 01 12:49:43 PM PDT 24
Peak memory 232548 kb
Host smart-de992bc1-1aea-401c-a786-3ba8253a8de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258112770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1258112770
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1749120486
Short name T719
Test name
Test status
Simulation time 34825176068 ps
CPU time 65.58 seconds
Started Jul 01 12:49:33 PM PDT 24
Finished Jul 01 12:50:42 PM PDT 24
Peak memory 232748 kb
Host smart-7346253b-20a8-4fca-9e44-d805bbe3d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749120486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1749120486
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1296506048
Short name T1001
Test name
Test status
Simulation time 451792220 ps
CPU time 2.71 seconds
Started Jul 01 12:49:34 PM PDT 24
Finished Jul 01 12:49:39 PM PDT 24
Peak memory 232688 kb
Host smart-a8b16c8a-5cd6-4cc3-8d3f-8b30149b1f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296506048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1296506048
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3360784044
Short name T488
Test name
Test status
Simulation time 3503343868 ps
CPU time 7.16 seconds
Started Jul 01 12:49:35 PM PDT 24
Finished Jul 01 12:49:45 PM PDT 24
Peak memory 240412 kb
Host smart-20561535-4ba0-4b4b-ac38-d25106bcb41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360784044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3360784044
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3401899711
Short name T804
Test name
Test status
Simulation time 244348524 ps
CPU time 4.11 seconds
Started Jul 01 12:49:33 PM PDT 24
Finished Jul 01 12:49:40 PM PDT 24
Peak memory 222992 kb
Host smart-d395798d-4963-4b58-90a6-62c994b333ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3401899711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3401899711
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2186657305
Short name T945
Test name
Test status
Simulation time 2919838444 ps
CPU time 27.03 seconds
Started Jul 01 12:49:35 PM PDT 24
Finished Jul 01 12:50:05 PM PDT 24
Peak memory 233148 kb
Host smart-397ca705-9230-4c81-87f2-8e132a2dc3ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186657305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2186657305
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1291146662
Short name T296
Test name
Test status
Simulation time 2969184906 ps
CPU time 22.53 seconds
Started Jul 01 12:49:33 PM PDT 24
Finished Jul 01 12:49:59 PM PDT 24
Peak memory 216728 kb
Host smart-1ed86311-bd6a-4cfb-ac80-257257f18acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291146662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1291146662
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3704493622
Short name T850
Test name
Test status
Simulation time 21715071939 ps
CPU time 14.95 seconds
Started Jul 01 12:49:27 PM PDT 24
Finished Jul 01 12:49:46 PM PDT 24
Peak memory 217532 kb
Host smart-c4c2b1bb-6e25-4194-9ffe-e25575c672bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704493622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3704493622
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2273032024
Short name T310
Test name
Test status
Simulation time 131437692 ps
CPU time 3.97 seconds
Started Jul 01 12:49:35 PM PDT 24
Finished Jul 01 12:49:42 PM PDT 24
Peak memory 216224 kb
Host smart-4d3220f7-368a-42d1-855d-c6a928f5a34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273032024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2273032024
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.307499085
Short name T512
Test name
Test status
Simulation time 19659595 ps
CPU time 0.78 seconds
Started Jul 01 12:49:33 PM PDT 24
Finished Jul 01 12:49:37 PM PDT 24
Peak memory 205928 kb
Host smart-90e46056-e26e-422a-9768-be4bc7f547b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307499085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.307499085
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2112932906
Short name T637
Test name
Test status
Simulation time 66637436 ps
CPU time 2.45 seconds
Started Jul 01 12:49:35 PM PDT 24
Finished Jul 01 12:49:41 PM PDT 24
Peak memory 232416 kb
Host smart-e6921d9e-1e98-4144-813c-3546616be9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112932906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2112932906
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3624088896
Short name T940
Test name
Test status
Simulation time 11828299 ps
CPU time 0.7 seconds
Started Jul 01 12:49:40 PM PDT 24
Finished Jul 01 12:49:42 PM PDT 24
Peak memory 205852 kb
Host smart-11d7971b-48ba-4d6e-b068-d6f299587c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624088896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3624088896
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4190743369
Short name T412
Test name
Test status
Simulation time 232504888 ps
CPU time 3.36 seconds
Started Jul 01 12:49:37 PM PDT 24
Finished Jul 01 12:49:43 PM PDT 24
Peak memory 232676 kb
Host smart-2a5c230e-e02c-4d58-af82-79ab547d324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190743369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4190743369
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.768601070
Short name T540
Test name
Test status
Simulation time 19456352 ps
CPU time 0.81 seconds
Started Jul 01 12:49:33 PM PDT 24
Finished Jul 01 12:49:37 PM PDT 24
Peak memory 206908 kb
Host smart-c169750f-b616-4a37-ad21-d2b0d4df26e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768601070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.768601070
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1337896859
Short name T44
Test name
Test status
Simulation time 11923273900 ps
CPU time 69.05 seconds
Started Jul 01 12:49:41 PM PDT 24
Finished Jul 01 12:50:51 PM PDT 24
Peak memory 265108 kb
Host smart-6dd0efd7-4de3-4f7d-9688-55a8b1bfd5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337896859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1337896859
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.400898009
Short name T751
Test name
Test status
Simulation time 72798668164 ps
CPU time 370.92 seconds
Started Jul 01 12:49:38 PM PDT 24
Finished Jul 01 12:55:52 PM PDT 24
Peak memory 254736 kb
Host smart-e50f07db-6935-4adf-8d62-fe1f76e1e90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400898009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.400898009
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1802214447
Short name T909
Test name
Test status
Simulation time 2427292575 ps
CPU time 47.64 seconds
Started Jul 01 12:49:39 PM PDT 24
Finished Jul 01 12:50:29 PM PDT 24
Peak memory 248468 kb
Host smart-ac16fb59-7941-4a52-a706-d7e97b5c9fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802214447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1802214447
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3122285968
Short name T839
Test name
Test status
Simulation time 5449777110 ps
CPU time 31.4 seconds
Started Jul 01 12:49:37 PM PDT 24
Finished Jul 01 12:50:11 PM PDT 24
Peak memory 241024 kb
Host smart-fe6876de-fe77-4277-816d-f99f5d724af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122285968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3122285968
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2037160237
Short name T491
Test name
Test status
Simulation time 233178220 ps
CPU time 4.04 seconds
Started Jul 01 12:49:38 PM PDT 24
Finished Jul 01 12:49:44 PM PDT 24
Peak memory 232632 kb
Host smart-5c43e3bb-2940-4f40-b041-6f40be49d811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037160237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2037160237
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2452720212
Short name T355
Test name
Test status
Simulation time 2797631499 ps
CPU time 10.34 seconds
Started Jul 01 12:49:38 PM PDT 24
Finished Jul 01 12:49:51 PM PDT 24
Peak memory 224768 kb
Host smart-7a9e2f9f-18a8-4039-9809-7713418f764d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452720212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2452720212
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.720103598
Short name T5
Test name
Test status
Simulation time 2594245128 ps
CPU time 13.16 seconds
Started Jul 01 12:49:35 PM PDT 24
Finished Jul 01 12:49:51 PM PDT 24
Peak memory 249236 kb
Host smart-3644a22c-382c-4cea-8000-178c10c7cf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720103598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.720103598
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1312209708
Short name T863
Test name
Test status
Simulation time 2796177574 ps
CPU time 6.73 seconds
Started Jul 01 12:49:33 PM PDT 24
Finished Jul 01 12:49:43 PM PDT 24
Peak memory 232756 kb
Host smart-929246d4-c3bc-44ad-bbd4-c5a31184a5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312209708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1312209708
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2030246400
Short name T441
Test name
Test status
Simulation time 301894038 ps
CPU time 4.04 seconds
Started Jul 01 12:49:39 PM PDT 24
Finished Jul 01 12:49:45 PM PDT 24
Peak memory 222104 kb
Host smart-ed970e56-3297-43d1-8709-d17a04e30803
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2030246400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2030246400
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2503518626
Short name T437
Test name
Test status
Simulation time 430668158 ps
CPU time 1.02 seconds
Started Jul 01 12:49:38 PM PDT 24
Finished Jul 01 12:49:42 PM PDT 24
Peak memory 206716 kb
Host smart-661b2e00-d27d-424b-9982-2d0efd019740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503518626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2503518626
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.197641229
Short name T986
Test name
Test status
Simulation time 15195883607 ps
CPU time 21.46 seconds
Started Jul 01 12:49:36 PM PDT 24
Finished Jul 01 12:50:00 PM PDT 24
Peak memory 216440 kb
Host smart-c3cab532-a91f-4068-8f47-9107f6a616f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197641229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.197641229
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4043361928
Short name T848
Test name
Test status
Simulation time 3804193063 ps
CPU time 9.21 seconds
Started Jul 01 12:49:33 PM PDT 24
Finished Jul 01 12:49:45 PM PDT 24
Peak memory 216380 kb
Host smart-3fd4175e-80b4-4792-8d80-7d1bf47c67a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043361928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4043361928
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3217191414
Short name T468
Test name
Test status
Simulation time 717258617 ps
CPU time 6.34 seconds
Started Jul 01 12:49:34 PM PDT 24
Finished Jul 01 12:49:43 PM PDT 24
Peak memory 216124 kb
Host smart-0c70eff4-6bd8-41d2-847e-1d987cb72c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217191414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3217191414
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.790716859
Short name T558
Test name
Test status
Simulation time 52103110 ps
CPU time 0.83 seconds
Started Jul 01 12:49:35 PM PDT 24
Finished Jul 01 12:49:38 PM PDT 24
Peak memory 205892 kb
Host smart-920c87e4-46da-4ed5-a4fa-163a155f03fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790716859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.790716859
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4045821845
Short name T987
Test name
Test status
Simulation time 33766930732 ps
CPU time 8.51 seconds
Started Jul 01 12:49:36 PM PDT 24
Finished Jul 01 12:49:47 PM PDT 24
Peak memory 232836 kb
Host smart-39749c6c-e763-4761-ad6b-71ff41d23422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045821845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4045821845
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3924397504
Short name T647
Test name
Test status
Simulation time 14803810 ps
CPU time 0.71 seconds
Started Jul 01 12:49:49 PM PDT 24
Finished Jul 01 12:49:52 PM PDT 24
Peak memory 205860 kb
Host smart-fff2244a-d3ec-4df9-a8b7-fbb31db789e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924397504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3924397504
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2113371992
Short name T713
Test name
Test status
Simulation time 982335989 ps
CPU time 5.07 seconds
Started Jul 01 12:49:43 PM PDT 24
Finished Jul 01 12:49:49 PM PDT 24
Peak memory 224504 kb
Host smart-c489c544-ce2d-43f5-a9a5-97d565d41e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113371992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2113371992
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3887654708
Short name T709
Test name
Test status
Simulation time 22704305 ps
CPU time 0.77 seconds
Started Jul 01 12:49:38 PM PDT 24
Finished Jul 01 12:49:41 PM PDT 24
Peak memory 206944 kb
Host smart-bc282720-825c-4f47-9c8c-1d4091841d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887654708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3887654708
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2304303004
Short name T618
Test name
Test status
Simulation time 12328597403 ps
CPU time 116.37 seconds
Started Jul 01 12:49:44 PM PDT 24
Finished Jul 01 12:51:41 PM PDT 24
Peak memory 249320 kb
Host smart-16fd750a-8b82-4010-bbce-36761ecdeb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304303004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2304303004
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.236024683
Short name T385
Test name
Test status
Simulation time 17606394769 ps
CPU time 162.66 seconds
Started Jul 01 12:49:45 PM PDT 24
Finished Jul 01 12:52:28 PM PDT 24
Peak memory 239360 kb
Host smart-37a19797-145b-4466-8359-5255ebb52d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236024683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.236024683
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1258306413
Short name T330
Test name
Test status
Simulation time 2776737861 ps
CPU time 13.11 seconds
Started Jul 01 12:49:44 PM PDT 24
Finished Jul 01 12:49:58 PM PDT 24
Peak memory 224556 kb
Host smart-b5c16db0-8bc5-47f5-966f-05868ec4bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258306413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1258306413
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2766433234
Short name T897
Test name
Test status
Simulation time 1913133095 ps
CPU time 27.02 seconds
Started Jul 01 12:49:43 PM PDT 24
Finished Jul 01 12:50:11 PM PDT 24
Peak memory 240916 kb
Host smart-220f5909-1a69-4814-bd0c-6ed90040b52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766433234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2766433234
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1183088951
Short name T251
Test name
Test status
Simulation time 13596840917 ps
CPU time 27.34 seconds
Started Jul 01 12:49:42 PM PDT 24
Finished Jul 01 12:50:11 PM PDT 24
Peak memory 232780 kb
Host smart-def5afe6-6949-4dc0-b58a-17a28518bcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183088951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1183088951
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1402669678
Short name T462
Test name
Test status
Simulation time 392201042 ps
CPU time 8.76 seconds
Started Jul 01 12:49:43 PM PDT 24
Finished Jul 01 12:49:53 PM PDT 24
Peak memory 224516 kb
Host smart-68aac518-a91b-429d-ac4c-15169d1f68e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402669678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1402669678
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1672387876
Short name T956
Test name
Test status
Simulation time 5531318319 ps
CPU time 7.7 seconds
Started Jul 01 12:49:44 PM PDT 24
Finished Jul 01 12:49:53 PM PDT 24
Peak memory 232816 kb
Host smart-42966cd0-8ff3-4c6b-ac56-c70467af3345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672387876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1672387876
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1132723803
Short name T580
Test name
Test status
Simulation time 1300733794 ps
CPU time 9.66 seconds
Started Jul 01 12:49:43 PM PDT 24
Finished Jul 01 12:49:54 PM PDT 24
Peak memory 232556 kb
Host smart-5391f334-0e0e-44a8-81ee-e6b6dd3ba4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132723803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1132723803
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2394962463
Short name T149
Test name
Test status
Simulation time 2135373932 ps
CPU time 8.64 seconds
Started Jul 01 12:49:43 PM PDT 24
Finished Jul 01 12:49:53 PM PDT 24
Peak memory 222108 kb
Host smart-701fb1f5-c7fd-47de-8044-68483fb707de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2394962463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2394962463
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3804922878
Short name T861
Test name
Test status
Simulation time 349623775 ps
CPU time 3.47 seconds
Started Jul 01 12:49:43 PM PDT 24
Finished Jul 01 12:49:48 PM PDT 24
Peak memory 217592 kb
Host smart-62571946-34a7-4995-b835-d790956421c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804922878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3804922878
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3477583785
Short name T754
Test name
Test status
Simulation time 17589427 ps
CPU time 0.74 seconds
Started Jul 01 12:49:36 PM PDT 24
Finished Jul 01 12:49:40 PM PDT 24
Peak memory 205748 kb
Host smart-869da00b-8516-455d-82a8-ee556c68dc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477583785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3477583785
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3653732492
Short name T445
Test name
Test status
Simulation time 2512198313 ps
CPU time 3.76 seconds
Started Jul 01 12:49:37 PM PDT 24
Finished Jul 01 12:49:43 PM PDT 24
Peak memory 216320 kb
Host smart-2186e57a-c8b3-4b7f-9923-261211c3052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653732492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3653732492
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2430064112
Short name T433
Test name
Test status
Simulation time 159608842 ps
CPU time 1.26 seconds
Started Jul 01 12:49:40 PM PDT 24
Finished Jul 01 12:49:43 PM PDT 24
Peak memory 208028 kb
Host smart-121f602c-03d6-406c-a44b-96164956eac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430064112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2430064112
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.594940495
Short name T475
Test name
Test status
Simulation time 109514902 ps
CPU time 0.79 seconds
Started Jul 01 12:49:38 PM PDT 24
Finished Jul 01 12:49:41 PM PDT 24
Peak memory 205884 kb
Host smart-01738ffa-8abf-4c55-b2c4-f70591bba235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594940495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.594940495
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3022632406
Short name T730
Test name
Test status
Simulation time 465065187 ps
CPU time 3.08 seconds
Started Jul 01 12:49:42 PM PDT 24
Finished Jul 01 12:49:47 PM PDT 24
Peak memory 232620 kb
Host smart-79c6be13-8559-4a73-8cca-c0746fd70bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022632406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3022632406
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3556347356
Short name T472
Test name
Test status
Simulation time 125651442 ps
CPU time 0.72 seconds
Started Jul 01 12:49:53 PM PDT 24
Finished Jul 01 12:49:55 PM PDT 24
Peak memory 205548 kb
Host smart-5c8930dd-280f-4aeb-a5de-d36d1302ac4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556347356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3556347356
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2060830086
Short name T648
Test name
Test status
Simulation time 65753455 ps
CPU time 2.63 seconds
Started Jul 01 12:49:48 PM PDT 24
Finished Jul 01 12:49:52 PM PDT 24
Peak memory 232256 kb
Host smart-ab43e2a2-ec11-48c2-a332-d284636c4efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060830086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2060830086
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2666951801
Short name T908
Test name
Test status
Simulation time 21043229 ps
CPU time 0.81 seconds
Started Jul 01 12:49:48 PM PDT 24
Finished Jul 01 12:49:50 PM PDT 24
Peak memory 206936 kb
Host smart-7c40ed23-3cf3-4e68-99b9-c6009b77d455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666951801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2666951801
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1833746306
Short name T21
Test name
Test status
Simulation time 10374182105 ps
CPU time 68.62 seconds
Started Jul 01 12:49:49 PM PDT 24
Finished Jul 01 12:50:59 PM PDT 24
Peak memory 252196 kb
Host smart-63a470f3-8813-4b1f-9419-9beea35a043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833746306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1833746306
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4249995066
Short name T677
Test name
Test status
Simulation time 125678269548 ps
CPU time 291.04 seconds
Started Jul 01 12:49:47 PM PDT 24
Finished Jul 01 12:54:40 PM PDT 24
Peak memory 260700 kb
Host smart-4e12facc-6542-4dcd-aac8-f9504916ba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249995066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4249995066
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2373297956
Short name T837
Test name
Test status
Simulation time 160839452613 ps
CPU time 421.39 seconds
Started Jul 01 12:49:51 PM PDT 24
Finished Jul 01 12:56:53 PM PDT 24
Peak memory 257444 kb
Host smart-fb8c6518-40b1-4e56-a9b1-24ee6e69179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373297956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2373297956
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3786291909
Short name T455
Test name
Test status
Simulation time 695997819 ps
CPU time 3.48 seconds
Started Jul 01 12:49:50 PM PDT 24
Finished Jul 01 12:49:55 PM PDT 24
Peak memory 232684 kb
Host smart-4cdaf299-476b-42e8-862c-05f668da6ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786291909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3786291909
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1118170073
Short name T178
Test name
Test status
Simulation time 4276108327 ps
CPU time 15.49 seconds
Started Jul 01 12:49:53 PM PDT 24
Finished Jul 01 12:50:10 PM PDT 24
Peak memory 240448 kb
Host smart-ac64fb95-38bf-411a-bdd3-bb2aa451bdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118170073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1118170073
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2302878494
Short name T213
Test name
Test status
Simulation time 11284556382 ps
CPU time 21.53 seconds
Started Jul 01 12:49:51 PM PDT 24
Finished Jul 01 12:50:14 PM PDT 24
Peak memory 224484 kb
Host smart-d94ada06-86f7-423c-9eda-8fb880e84532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302878494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2302878494
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1943643284
Short name T312
Test name
Test status
Simulation time 28322516 ps
CPU time 2.12 seconds
Started Jul 01 12:49:51 PM PDT 24
Finished Jul 01 12:49:55 PM PDT 24
Peak memory 222964 kb
Host smart-59b49f2c-fea7-42ba-97d1-433cfec0b9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943643284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1943643284
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.866271437
Short name T242
Test name
Test status
Simulation time 1053154955 ps
CPU time 5.26 seconds
Started Jul 01 12:49:50 PM PDT 24
Finished Jul 01 12:49:57 PM PDT 24
Peak memory 224504 kb
Host smart-aff44b78-4902-4efb-ad14-3c4857abdc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866271437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.866271437
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2673530535
Short name T1007
Test name
Test status
Simulation time 3119634966 ps
CPU time 6.74 seconds
Started Jul 01 12:49:50 PM PDT 24
Finished Jul 01 12:49:58 PM PDT 24
Peak memory 232684 kb
Host smart-d86cc859-6d2b-4654-91b7-807ae19f80e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673530535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2673530535
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3244575936
Short name T576
Test name
Test status
Simulation time 1001387322 ps
CPU time 3.31 seconds
Started Jul 01 12:49:48 PM PDT 24
Finished Jul 01 12:49:53 PM PDT 24
Peak memory 219268 kb
Host smart-9568d5fd-d2ff-47a9-91a5-c633205c3829
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3244575936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3244575936
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1153281994
Short name T846
Test name
Test status
Simulation time 54685830 ps
CPU time 1.06 seconds
Started Jul 01 12:49:48 PM PDT 24
Finished Jul 01 12:49:51 PM PDT 24
Peak memory 206940 kb
Host smart-eaf589c1-95f6-4dbd-bccb-dd7078a8f95a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153281994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1153281994
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1046501463
Short name T81
Test name
Test status
Simulation time 4169563640 ps
CPU time 35.88 seconds
Started Jul 01 12:49:49 PM PDT 24
Finished Jul 01 12:50:26 PM PDT 24
Peak memory 216588 kb
Host smart-da6f916f-cf8d-44b0-bfd8-9f322852be9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046501463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1046501463
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2692612621
Short name T621
Test name
Test status
Simulation time 14394353937 ps
CPU time 21.19 seconds
Started Jul 01 12:49:50 PM PDT 24
Finished Jul 01 12:50:13 PM PDT 24
Peak memory 216312 kb
Host smart-9c2e6a1f-2ed5-4e33-8e3f-7729a14a6613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692612621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2692612621
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1633762278
Short name T567
Test name
Test status
Simulation time 14466317 ps
CPU time 0.78 seconds
Started Jul 01 12:49:50 PM PDT 24
Finished Jul 01 12:49:53 PM PDT 24
Peak memory 206008 kb
Host smart-81eaa46d-ffa1-4004-be7c-6ae4d2b32071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633762278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1633762278
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2677184759
Short name T951
Test name
Test status
Simulation time 172877604 ps
CPU time 0.8 seconds
Started Jul 01 12:49:53 PM PDT 24
Finished Jul 01 12:49:55 PM PDT 24
Peak memory 205928 kb
Host smart-8a7d9782-f71a-4f41-9c87-9b9e1230b418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677184759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2677184759
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2361562952
Short name T231
Test name
Test status
Simulation time 97203229936 ps
CPU time 21.18 seconds
Started Jul 01 12:49:49 PM PDT 24
Finished Jul 01 12:50:12 PM PDT 24
Peak memory 232768 kb
Host smart-21d0618c-8ddf-4c42-b821-5b7f7739bf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361562952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2361562952
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.184025715
Short name T423
Test name
Test status
Simulation time 76467334 ps
CPU time 0.73 seconds
Started Jul 01 12:49:59 PM PDT 24
Finished Jul 01 12:50:01 PM PDT 24
Peak memory 204932 kb
Host smart-e3daf61a-3132-4f9b-ac12-0eaeff6adc80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184025715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.184025715
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2634939851
Short name T847
Test name
Test status
Simulation time 40574914 ps
CPU time 2.45 seconds
Started Jul 01 12:49:53 PM PDT 24
Finished Jul 01 12:49:56 PM PDT 24
Peak memory 232708 kb
Host smart-150dbfc7-0266-40c2-b0ed-4b81f59c6fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634939851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2634939851
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.904676725
Short name T807
Test name
Test status
Simulation time 52365504 ps
CPU time 0.77 seconds
Started Jul 01 12:49:54 PM PDT 24
Finished Jul 01 12:49:56 PM PDT 24
Peak memory 206916 kb
Host smart-dfcd4ad5-d3fe-4e4d-a083-0f6b69e386de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904676725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.904676725
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2914959399
Short name T164
Test name
Test status
Simulation time 127212475146 ps
CPU time 115.82 seconds
Started Jul 01 12:49:55 PM PDT 24
Finished Jul 01 12:51:52 PM PDT 24
Peak memory 249212 kb
Host smart-3841ee07-6e38-437e-8b84-d24af2426f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914959399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2914959399
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3631017347
Short name T925
Test name
Test status
Simulation time 102274674246 ps
CPU time 231.99 seconds
Started Jul 01 12:49:54 PM PDT 24
Finished Jul 01 12:53:47 PM PDT 24
Peak memory 257372 kb
Host smart-470e048a-bb12-4963-953d-262db711f87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631017347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3631017347
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1337310310
Short name T282
Test name
Test status
Simulation time 85288641619 ps
CPU time 434.1 seconds
Started Jul 01 12:50:02 PM PDT 24
Finished Jul 01 12:57:17 PM PDT 24
Peak memory 256536 kb
Host smart-4999b25f-a44e-461c-b3cf-38a4b6508d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337310310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1337310310
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3126743565
Short name T726
Test name
Test status
Simulation time 840075669 ps
CPU time 10.68 seconds
Started Jul 01 12:49:53 PM PDT 24
Finished Jul 01 12:50:05 PM PDT 24
Peak memory 232708 kb
Host smart-c0bd8466-38dd-4ac3-bfdd-1d3f651959fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126743565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3126743565
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4040901877
Short name T896
Test name
Test status
Simulation time 11401283336 ps
CPU time 55.18 seconds
Started Jul 01 12:49:54 PM PDT 24
Finished Jul 01 12:50:50 PM PDT 24
Peak memory 249312 kb
Host smart-4ef847da-b0a2-4550-86bc-bb2e8b7823df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040901877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4040901877
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.903249091
Short name T913
Test name
Test status
Simulation time 521680456 ps
CPU time 6.75 seconds
Started Jul 01 12:49:55 PM PDT 24
Finished Jul 01 12:50:03 PM PDT 24
Peak memory 232596 kb
Host smart-cc1ce929-b346-4232-a940-3615c2fb2e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903249091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.903249091
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4094343834
Short name T508
Test name
Test status
Simulation time 180309953 ps
CPU time 3.99 seconds
Started Jul 01 12:49:56 PM PDT 24
Finished Jul 01 12:50:01 PM PDT 24
Peak memory 224440 kb
Host smart-b5627de5-bf5e-4580-a43c-6447f3a73122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094343834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4094343834
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4100237108
Short name T720
Test name
Test status
Simulation time 1094016438 ps
CPU time 6.87 seconds
Started Jul 01 12:49:53 PM PDT 24
Finished Jul 01 12:50:01 PM PDT 24
Peak memory 232676 kb
Host smart-1720071a-f0a9-428e-9a5a-8ab3dd5837ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100237108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4100237108
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3000853542
Short name T617
Test name
Test status
Simulation time 772087261 ps
CPU time 3.86 seconds
Started Jul 01 12:49:54 PM PDT 24
Finished Jul 01 12:49:59 PM PDT 24
Peak memory 224524 kb
Host smart-2ed3b8c9-5253-47c5-a25c-23cfa985320a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000853542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3000853542
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3495326311
Short name T766
Test name
Test status
Simulation time 570529507 ps
CPU time 3.36 seconds
Started Jul 01 12:49:53 PM PDT 24
Finished Jul 01 12:49:58 PM PDT 24
Peak memory 218924 kb
Host smart-f1b8eb27-a6b9-4ca2-8ce6-ca782dd857fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3495326311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3495326311
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1344933700
Short name T51
Test name
Test status
Simulation time 48272245587 ps
CPU time 326.49 seconds
Started Jul 01 12:50:00 PM PDT 24
Finished Jul 01 12:55:27 PM PDT 24
Peak memory 265660 kb
Host smart-5df0215d-a621-4623-af7f-92d00ef59ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344933700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1344933700
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.723741422
Short name T485
Test name
Test status
Simulation time 7037855023 ps
CPU time 38.81 seconds
Started Jul 01 12:49:56 PM PDT 24
Finished Jul 01 12:50:36 PM PDT 24
Peak memory 216348 kb
Host smart-5ae141ac-27b9-4953-8e93-e44cba254f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723741422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.723741422
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2022556669
Short name T487
Test name
Test status
Simulation time 398170039 ps
CPU time 2.19 seconds
Started Jul 01 12:49:55 PM PDT 24
Finished Jul 01 12:49:59 PM PDT 24
Peak memory 215996 kb
Host smart-d576b9fb-83ce-43f2-8923-b809f4d1df17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022556669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2022556669
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3797171624
Short name T784
Test name
Test status
Simulation time 262943042 ps
CPU time 2.5 seconds
Started Jul 01 12:49:55 PM PDT 24
Finished Jul 01 12:49:59 PM PDT 24
Peak memory 216212 kb
Host smart-9bf78a03-cd10-4f64-ac10-8205caecb4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797171624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3797171624
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2954652282
Short name T747
Test name
Test status
Simulation time 48078741 ps
CPU time 0.79 seconds
Started Jul 01 12:49:54 PM PDT 24
Finished Jul 01 12:49:56 PM PDT 24
Peak memory 205960 kb
Host smart-3e00714d-8f4d-452d-ba19-6beed9578806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954652282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2954652282
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1102122712
Short name T823
Test name
Test status
Simulation time 14722300305 ps
CPU time 7.77 seconds
Started Jul 01 12:49:53 PM PDT 24
Finished Jul 01 12:50:02 PM PDT 24
Peak memory 232744 kb
Host smart-b68546f8-0bb0-4e96-9976-6846bb9372a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102122712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1102122712
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3051860588
Short name T750
Test name
Test status
Simulation time 21365736 ps
CPU time 0.76 seconds
Started Jul 01 12:50:09 PM PDT 24
Finished Jul 01 12:50:11 PM PDT 24
Peak memory 205512 kb
Host smart-e88c2cb2-a12e-4d69-bf3f-9377a53c4f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051860588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3051860588
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1355055329
Short name T852
Test name
Test status
Simulation time 3066523901 ps
CPU time 6.1 seconds
Started Jul 01 12:50:02 PM PDT 24
Finished Jul 01 12:50:09 PM PDT 24
Peak memory 224572 kb
Host smart-dd399d0f-b73e-4b24-a6e0-2dc4eda84f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355055329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1355055329
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.89660897
Short name T15
Test name
Test status
Simulation time 28514347 ps
CPU time 0.79 seconds
Started Jul 01 12:50:00 PM PDT 24
Finished Jul 01 12:50:02 PM PDT 24
Peak memory 206584 kb
Host smart-d36168fe-6080-4cd8-896f-038f1e0ded79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89660897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.89660897
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3338436467
Short name T275
Test name
Test status
Simulation time 202937280350 ps
CPU time 250.19 seconds
Started Jul 01 12:50:05 PM PDT 24
Finished Jul 01 12:54:16 PM PDT 24
Peak memory 254704 kb
Host smart-c03a7680-ada4-4857-bc9c-b71b034e9f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338436467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3338436467
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.259700201
Short name T914
Test name
Test status
Simulation time 34627548435 ps
CPU time 167.64 seconds
Started Jul 01 12:50:04 PM PDT 24
Finished Jul 01 12:52:53 PM PDT 24
Peak memory 252652 kb
Host smart-66c8d1ca-16bd-44c1-973a-5ac47344c079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259700201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.259700201
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.881117793
Short name T938
Test name
Test status
Simulation time 21288553665 ps
CPU time 82.7 seconds
Started Jul 01 12:50:07 PM PDT 24
Finished Jul 01 12:51:30 PM PDT 24
Peak memory 249288 kb
Host smart-7baea151-f280-46e5-a878-5a9679a2947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881117793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.881117793
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1079687752
Short name T293
Test name
Test status
Simulation time 300008349 ps
CPU time 7.82 seconds
Started Jul 01 12:50:01 PM PDT 24
Finished Jul 01 12:50:09 PM PDT 24
Peak memory 240912 kb
Host smart-4b921327-c62b-436d-ac2e-bde9ea7ac94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079687752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1079687752
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.437506439
Short name T4
Test name
Test status
Simulation time 53038260 ps
CPU time 0.84 seconds
Started Jul 01 12:49:59 PM PDT 24
Finished Jul 01 12:50:01 PM PDT 24
Peak memory 215808 kb
Host smart-8db014a5-7266-42f0-8888-b65fda65ce36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437506439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.437506439
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4018366639
Short name T684
Test name
Test status
Simulation time 322634085 ps
CPU time 3.84 seconds
Started Jul 01 12:49:59 PM PDT 24
Finished Jul 01 12:50:04 PM PDT 24
Peak memory 224456 kb
Host smart-4c6098cf-a889-4dff-b6c9-f62f54e18cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018366639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4018366639
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3584732560
Short name T224
Test name
Test status
Simulation time 7796566073 ps
CPU time 24.58 seconds
Started Jul 01 12:49:59 PM PDT 24
Finished Jul 01 12:50:25 PM PDT 24
Peak memory 232760 kb
Host smart-945705d9-25df-451b-845a-77a98f7c0f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584732560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3584732560
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3132448835
Short name T245
Test name
Test status
Simulation time 1196712849 ps
CPU time 8.07 seconds
Started Jul 01 12:50:00 PM PDT 24
Finished Jul 01 12:50:09 PM PDT 24
Peak memory 232616 kb
Host smart-824d181f-6adc-4af0-9c5f-ce3043336b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132448835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3132448835
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1626986244
Short name T822
Test name
Test status
Simulation time 859436147 ps
CPU time 4.5 seconds
Started Jul 01 12:50:00 PM PDT 24
Finished Jul 01 12:50:05 PM PDT 24
Peak memory 224516 kb
Host smart-95c016f0-2adb-4acb-9fe9-5dc0247e7094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626986244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1626986244
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1540633212
Short name T336
Test name
Test status
Simulation time 134806321 ps
CPU time 4.09 seconds
Started Jul 01 12:49:59 PM PDT 24
Finished Jul 01 12:50:03 PM PDT 24
Peak memory 223020 kb
Host smart-1a2cd083-9638-4b8f-a324-fbc7a3be857e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1540633212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1540633212
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3842651958
Short name T363
Test name
Test status
Simulation time 3416549695 ps
CPU time 18.39 seconds
Started Jul 01 12:49:59 PM PDT 24
Finished Jul 01 12:50:18 PM PDT 24
Peak memory 216356 kb
Host smart-e6790697-0f4a-4b76-872f-bfdc7f44089c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842651958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3842651958
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2348192523
Short name T489
Test name
Test status
Simulation time 754335789 ps
CPU time 4.9 seconds
Started Jul 01 12:50:01 PM PDT 24
Finished Jul 01 12:50:07 PM PDT 24
Peak memory 216228 kb
Host smart-94ed561a-3ff1-4af9-9400-4c42456c008f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348192523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2348192523
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1631007132
Short name T799
Test name
Test status
Simulation time 324730076 ps
CPU time 3.06 seconds
Started Jul 01 12:50:00 PM PDT 24
Finished Jul 01 12:50:03 PM PDT 24
Peak memory 216180 kb
Host smart-ab9c8aca-4760-44d1-b9ba-b71fe497a5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631007132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1631007132
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.919279141
Short name T395
Test name
Test status
Simulation time 219957155 ps
CPU time 0.98 seconds
Started Jul 01 12:49:59 PM PDT 24
Finished Jul 01 12:50:00 PM PDT 24
Peak memory 207256 kb
Host smart-2651f517-89e7-48bd-8563-b6633c80741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919279141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.919279141
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1237138327
Short name T789
Test name
Test status
Simulation time 355922589 ps
CPU time 6.32 seconds
Started Jul 01 12:50:00 PM PDT 24
Finished Jul 01 12:50:08 PM PDT 24
Peak memory 232732 kb
Host smart-c27ebbd1-21f0-482c-953b-f1b5e0b4b899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237138327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1237138327
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2155379228
Short name T425
Test name
Test status
Simulation time 43666678 ps
CPU time 0.72 seconds
Started Jul 01 12:46:45 PM PDT 24
Finished Jul 01 12:46:47 PM PDT 24
Peak memory 205520 kb
Host smart-d324fe8c-bc25-4ba4-b7c8-c2c1c57f871e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155379228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
155379228
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1568121719
Short name T727
Test name
Test status
Simulation time 1869878586 ps
CPU time 8.32 seconds
Started Jul 01 12:46:40 PM PDT 24
Finished Jul 01 12:46:49 PM PDT 24
Peak memory 224460 kb
Host smart-bd19ce50-1524-4435-834d-aed56df66214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568121719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1568121719
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2693041674
Short name T679
Test name
Test status
Simulation time 59819502 ps
CPU time 0.78 seconds
Started Jul 01 12:46:35 PM PDT 24
Finished Jul 01 12:46:37 PM PDT 24
Peak memory 206608 kb
Host smart-54249aff-c3b2-4a9c-bff9-3047ca672776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693041674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2693041674
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1478982865
Short name T937
Test name
Test status
Simulation time 101174416193 ps
CPU time 191.7 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:49:59 PM PDT 24
Peak memory 260920 kb
Host smart-7fe71869-4f82-4291-a0ee-c9c52295fdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478982865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1478982865
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1305913360
Short name T999
Test name
Test status
Simulation time 4848704157 ps
CPU time 34.06 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:47:21 PM PDT 24
Peak memory 249280 kb
Host smart-6167b577-30bd-4f1d-abea-209d328be4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305913360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1305913360
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.812954792
Short name T683
Test name
Test status
Simulation time 29708743412 ps
CPU time 292.53 seconds
Started Jul 01 12:46:48 PM PDT 24
Finished Jul 01 12:51:42 PM PDT 24
Peak memory 249824 kb
Host smart-3f204b97-2af4-4317-a6e0-379810ee347c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812954792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
812954792
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4276566217
Short name T480
Test name
Test status
Simulation time 137745730 ps
CPU time 3.33 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:46:51 PM PDT 24
Peak memory 232476 kb
Host smart-e3d825c1-e849-4283-841b-1515c4a0eb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276566217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4276566217
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.42677713
Short name T662
Test name
Test status
Simulation time 1993188541 ps
CPU time 47.09 seconds
Started Jul 01 12:46:41 PM PDT 24
Finished Jul 01 12:47:29 PM PDT 24
Peak memory 250948 kb
Host smart-f3a71929-4ed2-4fb3-89b0-e50b139ddca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42677713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.42677713
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.905621417
Short name T649
Test name
Test status
Simulation time 335052051 ps
CPU time 4.55 seconds
Started Jul 01 12:46:41 PM PDT 24
Finished Jul 01 12:46:46 PM PDT 24
Peak memory 224428 kb
Host smart-35fd88c0-4093-451d-9f39-0ecd39612027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905621417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.905621417
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.147782919
Short name T842
Test name
Test status
Simulation time 1082612577 ps
CPU time 9.66 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:46:58 PM PDT 24
Peak memory 232632 kb
Host smart-4f9068fc-512e-43ab-8c91-ee94f688f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147782919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.147782919
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1354101811
Short name T243
Test name
Test status
Simulation time 7881161231 ps
CPU time 17.06 seconds
Started Jul 01 12:46:39 PM PDT 24
Finished Jul 01 12:46:57 PM PDT 24
Peak memory 249180 kb
Host smart-e45630a5-64be-440e-b47e-f7a15e1c19c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354101811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1354101811
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.452867820
Short name T686
Test name
Test status
Simulation time 5066936560 ps
CPU time 11.17 seconds
Started Jul 01 12:46:42 PM PDT 24
Finished Jul 01 12:46:54 PM PDT 24
Peak memory 224604 kb
Host smart-849d1492-405a-4ddb-a801-bac95c88f817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452867820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.452867820
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.363976448
Short name T921
Test name
Test status
Simulation time 3648366094 ps
CPU time 10.08 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:46:58 PM PDT 24
Peak memory 223340 kb
Host smart-6fc39e59-33f9-4f20-b97c-e1c1fa6f0355
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=363976448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.363976448
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3325366517
Short name T70
Test name
Test status
Simulation time 366435521 ps
CPU time 1.13 seconds
Started Jul 01 12:46:47 PM PDT 24
Finished Jul 01 12:46:49 PM PDT 24
Peak memory 236584 kb
Host smart-4ceee269-217d-4e82-8cc6-318786ab9711
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325366517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3325366517
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3752045236
Short name T411
Test name
Test status
Simulation time 98530485 ps
CPU time 1.16 seconds
Started Jul 01 12:46:48 PM PDT 24
Finished Jul 01 12:46:50 PM PDT 24
Peak memory 206920 kb
Host smart-0a5046d1-3e9e-471d-8d99-46a2572b26c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752045236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3752045236
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3339210990
Short name T551
Test name
Test status
Simulation time 7076735237 ps
CPU time 37.91 seconds
Started Jul 01 12:46:40 PM PDT 24
Finished Jul 01 12:47:18 PM PDT 24
Peak memory 216656 kb
Host smart-4a3790c4-4e96-4643-bffc-90d92cce7e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339210990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3339210990
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3463947465
Short name T351
Test name
Test status
Simulation time 4660332077 ps
CPU time 4.35 seconds
Started Jul 01 12:46:42 PM PDT 24
Finished Jul 01 12:46:47 PM PDT 24
Peak memory 216248 kb
Host smart-96b3b4b6-7ff0-468e-b5be-aa1a09e10719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463947465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3463947465
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.61607984
Short name T314
Test name
Test status
Simulation time 75920073 ps
CPU time 1.52 seconds
Started Jul 01 12:46:42 PM PDT 24
Finished Jul 01 12:46:45 PM PDT 24
Peak memory 216268 kb
Host smart-d6b4fade-7ae7-49cd-953b-eb42e43a0f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61607984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.61607984
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2501420724
Short name T625
Test name
Test status
Simulation time 14997815 ps
CPU time 0.74 seconds
Started Jul 01 12:46:40 PM PDT 24
Finished Jul 01 12:46:42 PM PDT 24
Peak memory 205944 kb
Host smart-36c0d1c9-8e2c-4b48-abdc-81a0de216f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501420724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2501420724
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4137883467
Short name T40
Test name
Test status
Simulation time 14895281838 ps
CPU time 10.63 seconds
Started Jul 01 12:46:40 PM PDT 24
Finished Jul 01 12:46:52 PM PDT 24
Peak memory 224544 kb
Host smart-c43fa4f5-718f-463e-b2dc-54a02dd406b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137883467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4137883467
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3720598760
Short name T59
Test name
Test status
Simulation time 38707598 ps
CPU time 0.75 seconds
Started Jul 01 12:50:11 PM PDT 24
Finished Jul 01 12:50:13 PM PDT 24
Peak memory 205860 kb
Host smart-dc1a39b0-09b7-4494-af0f-a5610c243d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720598760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3720598760
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2454283099
Short name T442
Test name
Test status
Simulation time 142819354 ps
CPU time 2.96 seconds
Started Jul 01 12:50:08 PM PDT 24
Finished Jul 01 12:50:12 PM PDT 24
Peak memory 224460 kb
Host smart-fe058a4c-ef46-464a-8960-93edd0c956e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454283099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2454283099
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.503369675
Short name T415
Test name
Test status
Simulation time 26459064 ps
CPU time 0.76 seconds
Started Jul 01 12:50:05 PM PDT 24
Finished Jul 01 12:50:07 PM PDT 24
Peak memory 205568 kb
Host smart-1e681dce-862b-4102-b332-9015a003f220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503369675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.503369675
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1970702375
Short name T773
Test name
Test status
Simulation time 2961078208 ps
CPU time 67.31 seconds
Started Jul 01 12:50:04 PM PDT 24
Finished Jul 01 12:51:13 PM PDT 24
Peak memory 255456 kb
Host smart-7ff28914-5efe-40ce-815d-4873dcab28a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970702375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1970702375
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.495273796
Short name T198
Test name
Test status
Simulation time 8709245690 ps
CPU time 70.93 seconds
Started Jul 01 12:50:06 PM PDT 24
Finished Jul 01 12:51:17 PM PDT 24
Peak memory 249264 kb
Host smart-08bdf309-e857-4932-a081-76e42d8158e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495273796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.495273796
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1271040692
Short name T689
Test name
Test status
Simulation time 38131377014 ps
CPU time 79.93 seconds
Started Jul 01 12:50:05 PM PDT 24
Finished Jul 01 12:51:25 PM PDT 24
Peak memory 249168 kb
Host smart-8a77c68c-27e2-47d6-a2d3-f6772bf42ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271040692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1271040692
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2441753313
Short name T292
Test name
Test status
Simulation time 103933704 ps
CPU time 4.71 seconds
Started Jul 01 12:50:07 PM PDT 24
Finished Jul 01 12:50:12 PM PDT 24
Peak memory 233744 kb
Host smart-5434f114-7709-46e9-a67d-086683edbf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441753313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2441753313
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.726389182
Short name T318
Test name
Test status
Simulation time 41633270 ps
CPU time 0.78 seconds
Started Jul 01 12:50:05 PM PDT 24
Finished Jul 01 12:50:07 PM PDT 24
Peak memory 215788 kb
Host smart-35810b63-ba55-4d49-b574-fe551788591c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726389182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.726389182
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.481163003
Short name T857
Test name
Test status
Simulation time 167773892 ps
CPU time 2.98 seconds
Started Jul 01 12:50:04 PM PDT 24
Finished Jul 01 12:50:08 PM PDT 24
Peak memory 224404 kb
Host smart-816b06d9-da8c-4ca6-ad02-0f0d24a2e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481163003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.481163003
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1515832990
Short name T126
Test name
Test status
Simulation time 7234196434 ps
CPU time 82.23 seconds
Started Jul 01 12:50:07 PM PDT 24
Finished Jul 01 12:51:30 PM PDT 24
Peak memory 232788 kb
Host smart-81860de2-17bc-4041-80fe-903c94417d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515832990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1515832990
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3559885913
Short name T696
Test name
Test status
Simulation time 34718100330 ps
CPU time 20.74 seconds
Started Jul 01 12:50:04 PM PDT 24
Finished Jul 01 12:50:26 PM PDT 24
Peak memory 240812 kb
Host smart-eba1b7e1-6225-4b5a-acb8-3a5eed42b343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559885913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3559885913
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2901985260
Short name T544
Test name
Test status
Simulation time 2253427425 ps
CPU time 8.43 seconds
Started Jul 01 12:50:07 PM PDT 24
Finished Jul 01 12:50:17 PM PDT 24
Peak memory 232880 kb
Host smart-673abbea-6587-4c75-8f43-dd8e50a6c746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901985260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2901985260
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3999737466
Short name T366
Test name
Test status
Simulation time 5132352517 ps
CPU time 8.4 seconds
Started Jul 01 12:50:08 PM PDT 24
Finished Jul 01 12:50:17 PM PDT 24
Peak memory 221664 kb
Host smart-4a9527ab-6ad1-4577-838e-95f492bee889
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3999737466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3999737466
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3762675471
Short name T770
Test name
Test status
Simulation time 130745174 ps
CPU time 0.93 seconds
Started Jul 01 12:50:05 PM PDT 24
Finished Jul 01 12:50:07 PM PDT 24
Peak memory 207528 kb
Host smart-d27a034e-b47a-4de9-b958-516969560474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762675471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3762675471
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1272265281
Short name T380
Test name
Test status
Simulation time 47228879545 ps
CPU time 18.98 seconds
Started Jul 01 12:50:06 PM PDT 24
Finished Jul 01 12:50:26 PM PDT 24
Peak memory 216392 kb
Host smart-6c0ce681-17b1-42da-9dc4-55c87e7bc46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272265281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1272265281
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.809166786
Short name T615
Test name
Test status
Simulation time 2014780230 ps
CPU time 3.79 seconds
Started Jul 01 12:50:04 PM PDT 24
Finished Jul 01 12:50:09 PM PDT 24
Peak memory 216228 kb
Host smart-99143099-25ca-4003-88a4-54a702cfd09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809166786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.809166786
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4107359401
Short name T469
Test name
Test status
Simulation time 34701858 ps
CPU time 0.88 seconds
Started Jul 01 12:50:08 PM PDT 24
Finished Jul 01 12:50:10 PM PDT 24
Peak memory 207008 kb
Host smart-4cb4e5e3-e484-4238-a826-88280da6a332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107359401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4107359401
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3543611225
Short name T439
Test name
Test status
Simulation time 62398818 ps
CPU time 0.84 seconds
Started Jul 01 12:50:08 PM PDT 24
Finished Jul 01 12:50:10 PM PDT 24
Peak memory 205980 kb
Host smart-829cec80-11d4-4903-b963-904c90f742d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543611225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3543611225
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3974021658
Short name T486
Test name
Test status
Simulation time 4547149236 ps
CPU time 16.52 seconds
Started Jul 01 12:50:06 PM PDT 24
Finished Jul 01 12:50:24 PM PDT 24
Peak memory 232660 kb
Host smart-a7d65aee-aff7-4d0b-a706-acdda524652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974021658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3974021658
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2569829152
Short name T316
Test name
Test status
Simulation time 12482369 ps
CPU time 0.77 seconds
Started Jul 01 12:50:13 PM PDT 24
Finished Jul 01 12:50:15 PM PDT 24
Peak memory 204968 kb
Host smart-0cd369a3-5f4a-4003-9758-adfd48fb24f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569829152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2569829152
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2062746492
Short name T182
Test name
Test status
Simulation time 41874646 ps
CPU time 2.62 seconds
Started Jul 01 12:50:09 PM PDT 24
Finished Jul 01 12:50:13 PM PDT 24
Peak memory 232704 kb
Host smart-42de874f-82dc-452e-b0bc-d3f7289ad1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062746492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2062746492
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.9174591
Short name T858
Test name
Test status
Simulation time 14858863 ps
CPU time 0.73 seconds
Started Jul 01 12:50:10 PM PDT 24
Finished Jul 01 12:50:12 PM PDT 24
Peak memory 205568 kb
Host smart-a074a746-9b1f-4364-a9b0-0d39832219c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9174591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.9174591
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.586195257
Short name T1002
Test name
Test status
Simulation time 2119829106 ps
CPU time 43.08 seconds
Started Jul 01 12:50:09 PM PDT 24
Finished Jul 01 12:50:53 PM PDT 24
Peak memory 240864 kb
Host smart-07e1eae8-1124-499f-94db-3465ce9da3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586195257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.586195257
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1234859235
Short name T280
Test name
Test status
Simulation time 218813432516 ps
CPU time 513.49 seconds
Started Jul 01 12:50:13 PM PDT 24
Finished Jul 01 12:58:48 PM PDT 24
Peak memory 256976 kb
Host smart-6aaf5a04-c6e5-425d-974d-93c3bfacd2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234859235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1234859235
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.823227811
Short name T386
Test name
Test status
Simulation time 187384205 ps
CPU time 4.15 seconds
Started Jul 01 12:50:08 PM PDT 24
Finished Jul 01 12:50:13 PM PDT 24
Peak memory 224512 kb
Host smart-c38f4a08-a510-4e0b-becf-fa84987caf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823227811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.823227811
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.143079178
Short name T277
Test name
Test status
Simulation time 15099408296 ps
CPU time 79.47 seconds
Started Jul 01 12:50:08 PM PDT 24
Finished Jul 01 12:51:29 PM PDT 24
Peak memory 253336 kb
Host smart-c347940b-680e-47f8-872c-b192730f9e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143079178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.143079178
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1885765102
Short name T86
Test name
Test status
Simulation time 1397570095 ps
CPU time 5.63 seconds
Started Jul 01 12:50:11 PM PDT 24
Finished Jul 01 12:50:18 PM PDT 24
Peak memory 232704 kb
Host smart-054f2e3b-b0d2-45dd-8209-5a09daa46357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885765102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1885765102
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.169245652
Short name T421
Test name
Test status
Simulation time 95757028 ps
CPU time 2.2 seconds
Started Jul 01 12:50:09 PM PDT 24
Finished Jul 01 12:50:13 PM PDT 24
Peak memory 224088 kb
Host smart-2d0b66ba-feb0-40d5-96d5-0878df38d714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169245652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.169245652
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.548045724
Short name T195
Test name
Test status
Simulation time 12787250923 ps
CPU time 9.56 seconds
Started Jul 01 12:50:09 PM PDT 24
Finished Jul 01 12:50:20 PM PDT 24
Peak memory 224644 kb
Host smart-549dac85-30aa-4978-be77-04b50cb11c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548045724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.548045724
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3214250971
Short name T681
Test name
Test status
Simulation time 3330170347 ps
CPU time 7.18 seconds
Started Jul 01 12:50:08 PM PDT 24
Finished Jul 01 12:50:17 PM PDT 24
Peak memory 224492 kb
Host smart-02d13227-5bb3-4128-b5d1-7ddfcbe9a763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214250971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3214250971
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3311734195
Short name T404
Test name
Test status
Simulation time 2129831523 ps
CPU time 18.91 seconds
Started Jul 01 12:50:10 PM PDT 24
Finished Jul 01 12:50:30 PM PDT 24
Peak memory 223348 kb
Host smart-280bde0b-fcff-4f70-9fe0-922059fb85d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3311734195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3311734195
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.536078644
Short name T941
Test name
Test status
Simulation time 21347726244 ps
CPU time 53.74 seconds
Started Jul 01 12:50:23 PM PDT 24
Finished Jul 01 12:51:19 PM PDT 24
Peak memory 256860 kb
Host smart-ac83855c-4f53-48b5-8a62-e1e4fd787126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536078644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.536078644
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1005220566
Short name T543
Test name
Test status
Simulation time 5601360841 ps
CPU time 26.03 seconds
Started Jul 01 12:50:11 PM PDT 24
Finished Jul 01 12:50:38 PM PDT 24
Peak memory 216456 kb
Host smart-1a1e1dbf-b73c-4adb-b26e-2c0a86da2627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005220566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1005220566
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2510358917
Short name T840
Test name
Test status
Simulation time 2227635267 ps
CPU time 4.05 seconds
Started Jul 01 12:50:10 PM PDT 24
Finished Jul 01 12:50:15 PM PDT 24
Peak memory 216184 kb
Host smart-d122df39-803b-433c-b844-d352bd4dddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510358917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2510358917
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1828003428
Short name T670
Test name
Test status
Simulation time 220871947 ps
CPU time 3.41 seconds
Started Jul 01 12:50:09 PM PDT 24
Finished Jul 01 12:50:14 PM PDT 24
Peak memory 216264 kb
Host smart-43318c82-3ee9-456b-a004-86e03277f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828003428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1828003428
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.803303421
Short name T663
Test name
Test status
Simulation time 71111587 ps
CPU time 0.95 seconds
Started Jul 01 12:50:11 PM PDT 24
Finished Jul 01 12:50:13 PM PDT 24
Peak memory 206956 kb
Host smart-4483f8ff-f43c-41ac-9406-9ab0bcabbc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803303421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.803303421
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.792207813
Short name T900
Test name
Test status
Simulation time 306347397 ps
CPU time 2.31 seconds
Started Jul 01 12:50:09 PM PDT 24
Finished Jul 01 12:50:13 PM PDT 24
Peak memory 224104 kb
Host smart-d1776b8d-8c8d-4b9b-b56d-edf687e802d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792207813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.792207813
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4183220334
Short name T814
Test name
Test status
Simulation time 13810058 ps
CPU time 0.75 seconds
Started Jul 01 12:50:21 PM PDT 24
Finished Jul 01 12:50:23 PM PDT 24
Peak memory 205560 kb
Host smart-d08246fc-f888-4b5e-82c5-ae9bfb8ea04f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183220334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4183220334
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3825714442
Short name T759
Test name
Test status
Simulation time 1561564662 ps
CPU time 6.09 seconds
Started Jul 01 12:50:14 PM PDT 24
Finished Jul 01 12:50:22 PM PDT 24
Peak memory 224528 kb
Host smart-4eceeb0a-3b5b-4001-9cb8-745222f7ead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825714442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3825714442
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2750854720
Short name T362
Test name
Test status
Simulation time 58136802 ps
CPU time 0.84 seconds
Started Jul 01 12:50:14 PM PDT 24
Finished Jul 01 12:50:16 PM PDT 24
Peak memory 206612 kb
Host smart-3f0279dd-aacd-4b37-ab95-f905375d925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750854720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2750854720
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3592371077
Short name T197
Test name
Test status
Simulation time 40789858199 ps
CPU time 139.41 seconds
Started Jul 01 12:50:21 PM PDT 24
Finished Jul 01 12:52:43 PM PDT 24
Peak memory 253528 kb
Host smart-2a6d6d51-1edd-4275-ba77-01eaa87685e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592371077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3592371077
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2599371353
Short name T279
Test name
Test status
Simulation time 59227653860 ps
CPU time 240.43 seconds
Started Jul 01 12:50:23 PM PDT 24
Finished Jul 01 12:54:26 PM PDT 24
Peak memory 255900 kb
Host smart-2cf94a95-7f83-42ca-ab6e-a155d8820fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599371353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2599371353
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1783032474
Short name T688
Test name
Test status
Simulation time 17516784391 ps
CPU time 42.86 seconds
Started Jul 01 12:50:22 PM PDT 24
Finished Jul 01 12:51:07 PM PDT 24
Peak memory 241076 kb
Host smart-b75763fd-db8b-4fb4-83ff-a502adf99614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783032474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1783032474
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1111791539
Short name T762
Test name
Test status
Simulation time 1095002146 ps
CPU time 7.4 seconds
Started Jul 01 12:50:23 PM PDT 24
Finished Jul 01 12:50:33 PM PDT 24
Peak memory 240888 kb
Host smart-3c2887ce-fa0b-4e82-8fba-f59ec889da74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111791539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1111791539
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.995337653
Short name T982
Test name
Test status
Simulation time 96693964048 ps
CPU time 337.92 seconds
Started Jul 01 12:50:13 PM PDT 24
Finished Jul 01 12:55:53 PM PDT 24
Peak memory 257400 kb
Host smart-4cb4dfdd-5433-4e3b-ac65-177019e5bc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995337653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.995337653
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3115441978
Short name T367
Test name
Test status
Simulation time 14487500625 ps
CPU time 26.73 seconds
Started Jul 01 12:50:23 PM PDT 24
Finished Jul 01 12:50:52 PM PDT 24
Peak memory 232820 kb
Host smart-5c2b425e-ab55-42f3-b55e-c8d797953deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115441978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3115441978
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2946746657
Short name T248
Test name
Test status
Simulation time 5637330521 ps
CPU time 32.43 seconds
Started Jul 01 12:50:16 PM PDT 24
Finished Jul 01 12:50:49 PM PDT 24
Peak memory 224620 kb
Host smart-948d5638-b1b4-405c-a4b8-b123c7bb23fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946746657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2946746657
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2631877460
Short name T127
Test name
Test status
Simulation time 2429287898 ps
CPU time 6.67 seconds
Started Jul 01 12:50:22 PM PDT 24
Finished Jul 01 12:50:31 PM PDT 24
Peak memory 224580 kb
Host smart-15cabe2c-86f1-48e6-ad7b-0ae64f5b12f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631877460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2631877460
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4083398924
Short name T879
Test name
Test status
Simulation time 856371488 ps
CPU time 4.83 seconds
Started Jul 01 12:50:15 PM PDT 24
Finished Jul 01 12:50:21 PM PDT 24
Peak memory 224364 kb
Host smart-19cee751-ffd7-4bee-a2af-e8ad776a0987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083398924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4083398924
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.712987772
Short name T350
Test name
Test status
Simulation time 944944669 ps
CPU time 11.92 seconds
Started Jul 01 12:50:16 PM PDT 24
Finished Jul 01 12:50:29 PM PDT 24
Peak memory 219236 kb
Host smart-04fad52b-9cd7-42f7-8351-d46989192d00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=712987772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.712987772
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1658219200
Short name T929
Test name
Test status
Simulation time 19123896499 ps
CPU time 26.25 seconds
Started Jul 01 12:50:18 PM PDT 24
Finished Jul 01 12:50:45 PM PDT 24
Peak memory 216500 kb
Host smart-daa1fe19-a0ec-46c4-8e3a-02dcd3b93018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658219200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1658219200
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4184890590
Short name T556
Test name
Test status
Simulation time 10043675306 ps
CPU time 6.7 seconds
Started Jul 01 12:50:23 PM PDT 24
Finished Jul 01 12:50:32 PM PDT 24
Peak memory 216344 kb
Host smart-60a44505-950e-4f0f-be85-360cbae58d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184890590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4184890590
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1280161670
Short name T323
Test name
Test status
Simulation time 56744067 ps
CPU time 0.77 seconds
Started Jul 01 12:50:13 PM PDT 24
Finished Jul 01 12:50:15 PM PDT 24
Peak memory 205964 kb
Host smart-aed26b09-d162-4173-9cfe-c755fdc01abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280161670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1280161670
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1099378283
Short name T636
Test name
Test status
Simulation time 18394268 ps
CPU time 0.75 seconds
Started Jul 01 12:50:15 PM PDT 24
Finished Jul 01 12:50:17 PM PDT 24
Peak memory 205964 kb
Host smart-fa0c4d6c-b354-45d9-9d07-def4d79f1a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099378283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1099378283
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.838170041
Short name T950
Test name
Test status
Simulation time 12265845595 ps
CPU time 41.54 seconds
Started Jul 01 12:50:15 PM PDT 24
Finished Jul 01 12:50:57 PM PDT 24
Peak memory 232760 kb
Host smart-5e0c312a-5bfe-425c-9fbf-45c8d646bed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838170041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.838170041
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1003504313
Short name T724
Test name
Test status
Simulation time 19896593 ps
CPU time 0.7 seconds
Started Jul 01 12:50:25 PM PDT 24
Finished Jul 01 12:50:29 PM PDT 24
Peak memory 205400 kb
Host smart-2bbf4a40-efc1-4eeb-b511-b2e7adc66493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003504313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1003504313
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1622330074
Short name T429
Test name
Test status
Simulation time 1666714596 ps
CPU time 7.92 seconds
Started Jul 01 12:50:18 PM PDT 24
Finished Jul 01 12:50:27 PM PDT 24
Peak memory 232588 kb
Host smart-46782afc-177b-4b35-8f0e-23b77789bf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622330074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1622330074
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4121975516
Short name T306
Test name
Test status
Simulation time 66863222 ps
CPU time 0.76 seconds
Started Jul 01 12:50:19 PM PDT 24
Finished Jul 01 12:50:21 PM PDT 24
Peak memory 206564 kb
Host smart-c7dde199-98e5-431a-bd98-4e8eb350ee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121975516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4121975516
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1618859374
Short name T285
Test name
Test status
Simulation time 34229410284 ps
CPU time 150.78 seconds
Started Jul 01 12:50:23 PM PDT 24
Finished Jul 01 12:52:56 PM PDT 24
Peak memory 250236 kb
Host smart-79063284-4baf-4422-a0bc-92c351c05d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618859374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1618859374
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3562906105
Short name T214
Test name
Test status
Simulation time 112016258047 ps
CPU time 529.46 seconds
Started Jul 01 12:50:19 PM PDT 24
Finished Jul 01 12:59:10 PM PDT 24
Peak memory 270208 kb
Host smart-b116198a-ba99-4a22-90f4-dba078c76af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562906105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3562906105
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.610958875
Short name T370
Test name
Test status
Simulation time 47738835054 ps
CPU time 124.34 seconds
Started Jul 01 12:50:22 PM PDT 24
Finished Jul 01 12:52:29 PM PDT 24
Peak memory 239404 kb
Host smart-c599d691-4be7-4b8b-bb8b-be7953044716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610958875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.610958875
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1813413328
Short name T511
Test name
Test status
Simulation time 132063524 ps
CPU time 2.67 seconds
Started Jul 01 12:50:23 PM PDT 24
Finished Jul 01 12:50:29 PM PDT 24
Peak memory 232712 kb
Host smart-377ff4ae-a286-4514-a90d-c4fdd87cdabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813413328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1813413328
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.4029179442
Short name T870
Test name
Test status
Simulation time 91309494711 ps
CPU time 318.39 seconds
Started Jul 01 12:50:20 PM PDT 24
Finished Jul 01 12:55:39 PM PDT 24
Peak memory 252412 kb
Host smart-6eed92c5-adc2-4a1d-aae3-be2606850c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029179442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.4029179442
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1037741894
Short name T526
Test name
Test status
Simulation time 301197598 ps
CPU time 3.36 seconds
Started Jul 01 12:50:17 PM PDT 24
Finished Jul 01 12:50:21 PM PDT 24
Peak memory 224508 kb
Host smart-2a9769b3-4aab-4890-a24f-aed7c6107b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037741894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1037741894
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2724418801
Short name T211
Test name
Test status
Simulation time 2765139771 ps
CPU time 28.68 seconds
Started Jul 01 12:50:20 PM PDT 24
Finished Jul 01 12:50:49 PM PDT 24
Peak memory 224584 kb
Host smart-2fd7322f-ce3f-4e2b-ab39-98cf71e71fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724418801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2724418801
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1454162270
Short name T644
Test name
Test status
Simulation time 10329645489 ps
CPU time 5.26 seconds
Started Jul 01 12:50:23 PM PDT 24
Finished Jul 01 12:50:31 PM PDT 24
Peak memory 224584 kb
Host smart-03d236c0-9af8-4540-a20b-e15287729fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454162270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1454162270
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.170864177
Short name T482
Test name
Test status
Simulation time 22437207251 ps
CPU time 20.88 seconds
Started Jul 01 12:50:18 PM PDT 24
Finished Jul 01 12:50:40 PM PDT 24
Peak memory 224656 kb
Host smart-e10ffe12-2222-4af4-9793-bb4beb35b6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170864177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.170864177
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1293469787
Short name T579
Test name
Test status
Simulation time 1072115772 ps
CPU time 5.07 seconds
Started Jul 01 12:50:21 PM PDT 24
Finished Jul 01 12:50:28 PM PDT 24
Peak memory 219360 kb
Host smart-7e8ac4fa-e725-40c3-acbf-f2be805b9e36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1293469787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1293469787
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3743311230
Short name T31
Test name
Test status
Simulation time 27201857798 ps
CPU time 244.59 seconds
Started Jul 01 12:50:25 PM PDT 24
Finished Jul 01 12:54:32 PM PDT 24
Peak memory 252408 kb
Host smart-39249a20-c476-447f-aeda-61212fe931b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743311230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3743311230
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2979047989
Short name T553
Test name
Test status
Simulation time 12779215921 ps
CPU time 34.07 seconds
Started Jul 01 12:50:21 PM PDT 24
Finished Jul 01 12:50:56 PM PDT 24
Peak memory 216352 kb
Host smart-fde6a1fe-971b-4a2d-bc8b-74d902e6f2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979047989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2979047989
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.226260336
Short name T638
Test name
Test status
Simulation time 1108274372 ps
CPU time 3.01 seconds
Started Jul 01 12:50:21 PM PDT 24
Finished Jul 01 12:50:26 PM PDT 24
Peak memory 216192 kb
Host smart-a4e97b79-a56f-48fa-a547-cf4e3b3c266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226260336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.226260336
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1781082665
Short name T895
Test name
Test status
Simulation time 50292136 ps
CPU time 1.34 seconds
Started Jul 01 12:50:23 PM PDT 24
Finished Jul 01 12:50:27 PM PDT 24
Peak memory 215852 kb
Host smart-d0cee847-1ee3-45a3-8c6c-e59a60133f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781082665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1781082665
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3396822980
Short name T985
Test name
Test status
Simulation time 166695888 ps
CPU time 0.85 seconds
Started Jul 01 12:50:21 PM PDT 24
Finished Jul 01 12:50:24 PM PDT 24
Peak memory 205952 kb
Host smart-f2aa40c2-e76d-4b66-b335-19496d7e5a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396822980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3396822980
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2147523358
Short name T477
Test name
Test status
Simulation time 2929656831 ps
CPU time 13.99 seconds
Started Jul 01 12:50:19 PM PDT 24
Finished Jul 01 12:50:34 PM PDT 24
Peak memory 240376 kb
Host smart-794cfc85-c215-453c-a83d-21e5f6d905a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147523358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2147523358
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.943652135
Short name T393
Test name
Test status
Simulation time 14310622 ps
CPU time 0.75 seconds
Started Jul 01 12:50:25 PM PDT 24
Finished Jul 01 12:50:29 PM PDT 24
Peak memory 205512 kb
Host smart-c450eb6d-5900-496e-b7fa-55251bff3bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943652135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.943652135
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.522968774
Short name T515
Test name
Test status
Simulation time 33388665 ps
CPU time 2.57 seconds
Started Jul 01 12:50:27 PM PDT 24
Finished Jul 01 12:50:32 PM PDT 24
Peak memory 232212 kb
Host smart-c1c7faab-a4c3-4e65-b3ca-1a8c27ddebbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522968774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.522968774
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.493856045
Short name T953
Test name
Test status
Simulation time 31073125 ps
CPU time 0.77 seconds
Started Jul 01 12:50:25 PM PDT 24
Finished Jul 01 12:50:29 PM PDT 24
Peak memory 206588 kb
Host smart-08d052d2-48ce-4084-9915-18242bf9c397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493856045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.493856045
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.4221377399
Short name T732
Test name
Test status
Simulation time 5033408463 ps
CPU time 65.9 seconds
Started Jul 01 12:50:27 PM PDT 24
Finished Jul 01 12:51:35 PM PDT 24
Peak memory 249836 kb
Host smart-781eeb66-0591-422a-a103-32bf8d7e3e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221377399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4221377399
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2972566344
Short name T916
Test name
Test status
Simulation time 7681344375 ps
CPU time 77.66 seconds
Started Jul 01 12:50:26 PM PDT 24
Finished Jul 01 12:51:46 PM PDT 24
Peak memory 268116 kb
Host smart-2f2feb7d-e837-4522-afb0-1a69176698c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972566344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2972566344
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.105692402
Short name T47
Test name
Test status
Simulation time 34669954258 ps
CPU time 67.08 seconds
Started Jul 01 12:50:25 PM PDT 24
Finished Jul 01 12:51:35 PM PDT 24
Peak memory 249256 kb
Host smart-9f700085-c20d-474d-93be-7043ea0631a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105692402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.105692402
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2662369439
Short name T328
Test name
Test status
Simulation time 4734683739 ps
CPU time 17.66 seconds
Started Jul 01 12:50:26 PM PDT 24
Finished Jul 01 12:50:46 PM PDT 24
Peak memory 235004 kb
Host smart-bf099303-d841-42b3-9f0c-d796119fe930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662369439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2662369439
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2532050963
Short name T176
Test name
Test status
Simulation time 22755998192 ps
CPU time 127.8 seconds
Started Jul 01 12:50:28 PM PDT 24
Finished Jul 01 12:52:38 PM PDT 24
Peak memory 265584 kb
Host smart-39ec70ab-23c2-4063-b082-ecce7009da7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532050963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2532050963
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3227044245
Short name T222
Test name
Test status
Simulation time 9090940993 ps
CPU time 13.38 seconds
Started Jul 01 12:50:27 PM PDT 24
Finished Jul 01 12:50:43 PM PDT 24
Peak memory 224444 kb
Host smart-587c8b78-0120-4dac-896d-a4cb27129c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227044245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3227044245
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2279478404
Short name T810
Test name
Test status
Simulation time 75056266 ps
CPU time 2.69 seconds
Started Jul 01 12:50:25 PM PDT 24
Finished Jul 01 12:50:31 PM PDT 24
Peak memory 232664 kb
Host smart-064a2674-c9cc-4c06-89b4-298f7a0f6b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279478404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2279478404
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2751453795
Short name T646
Test name
Test status
Simulation time 2977847051 ps
CPU time 13.59 seconds
Started Jul 01 12:50:25 PM PDT 24
Finished Jul 01 12:50:42 PM PDT 24
Peak memory 224604 kb
Host smart-d947b8e2-177e-4297-83eb-06d954055e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751453795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2751453795
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4213622843
Short name T832
Test name
Test status
Simulation time 1966102769 ps
CPU time 5.46 seconds
Started Jul 01 12:50:24 PM PDT 24
Finished Jul 01 12:50:32 PM PDT 24
Peak memory 232648 kb
Host smart-2552721e-5fc1-4646-819d-ef4ffac4d402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213622843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4213622843
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3736939654
Short name T583
Test name
Test status
Simulation time 46077209 ps
CPU time 0.95 seconds
Started Jul 01 12:50:26 PM PDT 24
Finished Jul 01 12:50:30 PM PDT 24
Peak memory 205684 kb
Host smart-0b0b4bf5-98ac-4a19-8233-7200abc32989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736939654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3736939654
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2594554831
Short name T779
Test name
Test status
Simulation time 26834991562 ps
CPU time 24.14 seconds
Started Jul 01 12:50:25 PM PDT 24
Finished Jul 01 12:50:52 PM PDT 24
Peak memory 216316 kb
Host smart-83bc0bb3-e537-4a2a-a1c4-482cf632226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594554831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2594554831
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1375876546
Short name T353
Test name
Test status
Simulation time 19917222173 ps
CPU time 11.17 seconds
Started Jul 01 12:50:25 PM PDT 24
Finished Jul 01 12:50:39 PM PDT 24
Peak memory 216340 kb
Host smart-5e0e8de3-1b9e-47a1-b9a7-ed40f25e2ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375876546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1375876546
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1782070541
Short name T25
Test name
Test status
Simulation time 431701138 ps
CPU time 3.06 seconds
Started Jul 01 12:50:26 PM PDT 24
Finished Jul 01 12:50:32 PM PDT 24
Peak memory 216184 kb
Host smart-c2cd405e-7b00-44d1-8b30-37e4bf8a6120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782070541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1782070541
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2247028824
Short name T331
Test name
Test status
Simulation time 73348076 ps
CPU time 0.93 seconds
Started Jul 01 12:50:27 PM PDT 24
Finished Jul 01 12:50:31 PM PDT 24
Peak memory 206280 kb
Host smart-c23b495c-c84f-49af-bdff-2b958f32f562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247028824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2247028824
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.380443360
Short name T788
Test name
Test status
Simulation time 80704942 ps
CPU time 2.5 seconds
Started Jul 01 12:50:27 PM PDT 24
Finished Jul 01 12:50:32 PM PDT 24
Peak memory 232288 kb
Host smart-772a0402-2459-4205-b2ca-f06f860dee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380443360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.380443360
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2768403562
Short name T6
Test name
Test status
Simulation time 22102238 ps
CPU time 0.73 seconds
Started Jul 01 12:50:29 PM PDT 24
Finished Jul 01 12:50:32 PM PDT 24
Peak memory 205892 kb
Host smart-d8ff4ff3-2eed-4004-9bde-6648e3bba29f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768403562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2768403562
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3103490445
Short name T591
Test name
Test status
Simulation time 713857208 ps
CPU time 6.43 seconds
Started Jul 01 12:50:31 PM PDT 24
Finished Jul 01 12:50:40 PM PDT 24
Peak memory 232620 kb
Host smart-b6429f1f-748b-4301-ac74-fb93cb239b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103490445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3103490445
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1505911671
Short name T378
Test name
Test status
Simulation time 28781724 ps
CPU time 0.77 seconds
Started Jul 01 12:50:25 PM PDT 24
Finished Jul 01 12:50:28 PM PDT 24
Peak memory 206948 kb
Host smart-edd2f762-01ec-4e07-9113-4df20cb67de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505911671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1505911671
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.528371965
Short name T665
Test name
Test status
Simulation time 56880552017 ps
CPU time 578.28 seconds
Started Jul 01 12:50:32 PM PDT 24
Finished Jul 01 01:00:12 PM PDT 24
Peak memory 256252 kb
Host smart-d417eae9-4f1a-444c-aeb1-c864d9885dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528371965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.528371965
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1862612059
Short name T35
Test name
Test status
Simulation time 1645753786 ps
CPU time 35.78 seconds
Started Jul 01 12:50:33 PM PDT 24
Finished Jul 01 12:51:10 PM PDT 24
Peak memory 257272 kb
Host smart-1a3e31b4-c31e-4712-925c-aa67d8cf590e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862612059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1862612059
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2576429306
Short name T753
Test name
Test status
Simulation time 1644526207 ps
CPU time 25.84 seconds
Started Jul 01 12:50:32 PM PDT 24
Finished Jul 01 12:50:59 PM PDT 24
Peak memory 224496 kb
Host smart-d76175bc-7723-484f-b83d-e93d537208ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576429306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2576429306
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.621363481
Short name T889
Test name
Test status
Simulation time 1637461818 ps
CPU time 38.32 seconds
Started Jul 01 12:50:30 PM PDT 24
Finished Jul 01 12:51:11 PM PDT 24
Peak memory 251076 kb
Host smart-1665754a-08a4-4175-8df8-a46296531ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621363481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.621363481
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2727006105
Short name T755
Test name
Test status
Simulation time 291065154 ps
CPU time 6.39 seconds
Started Jul 01 12:50:31 PM PDT 24
Finished Jul 01 12:50:39 PM PDT 24
Peak memory 232664 kb
Host smart-c352dc2b-13ad-4dd9-aa2a-ecd875fb1195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727006105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2727006105
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.960767467
Short name T776
Test name
Test status
Simulation time 3016030841 ps
CPU time 10.69 seconds
Started Jul 01 12:50:31 PM PDT 24
Finished Jul 01 12:50:44 PM PDT 24
Peak memory 234248 kb
Host smart-9b97e674-a93a-47dd-a0ef-404e281bcc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960767467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.960767467
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4052368141
Short name T699
Test name
Test status
Simulation time 663363410 ps
CPU time 3.45 seconds
Started Jul 01 12:50:31 PM PDT 24
Finished Jul 01 12:50:36 PM PDT 24
Peak memory 224464 kb
Host smart-d22e5fcf-5bb3-465f-ac26-3e44fcd35a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052368141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4052368141
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2924607790
Short name T388
Test name
Test status
Simulation time 8584682879 ps
CPU time 23.33 seconds
Started Jul 01 12:50:30 PM PDT 24
Finished Jul 01 12:50:55 PM PDT 24
Peak memory 232812 kb
Host smart-06bf8bbf-6369-4116-b21c-9ebc3c8ef27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924607790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2924607790
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.4157107574
Short name T379
Test name
Test status
Simulation time 1506275844 ps
CPU time 10.29 seconds
Started Jul 01 12:50:31 PM PDT 24
Finished Jul 01 12:50:43 PM PDT 24
Peak memory 220020 kb
Host smart-769c6599-d43d-4149-a078-8b1c40a958b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4157107574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.4157107574
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.191696840
Short name T166
Test name
Test status
Simulation time 37250572815 ps
CPU time 352.42 seconds
Started Jul 01 12:50:30 PM PDT 24
Finished Jul 01 12:56:24 PM PDT 24
Peak memory 257460 kb
Host smart-9b7ee81e-3a04-44e6-908f-cfe4c47f2fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191696840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.191696840
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2166572539
Short name T299
Test name
Test status
Simulation time 2419260444 ps
CPU time 19.7 seconds
Started Jul 01 12:50:26 PM PDT 24
Finished Jul 01 12:50:49 PM PDT 24
Peak memory 219328 kb
Host smart-24870492-1f5b-45c0-8798-28b4a89dbf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166572539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2166572539
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3239875202
Short name T791
Test name
Test status
Simulation time 1545818955 ps
CPU time 8.25 seconds
Started Jul 01 12:50:27 PM PDT 24
Finished Jul 01 12:50:38 PM PDT 24
Peak memory 216208 kb
Host smart-401e55f8-a7df-4e55-a228-26a41ac3365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239875202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3239875202
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1822060725
Short name T774
Test name
Test status
Simulation time 1486621314 ps
CPU time 4.57 seconds
Started Jul 01 12:50:26 PM PDT 24
Finished Jul 01 12:50:33 PM PDT 24
Peak memory 216112 kb
Host smart-58251114-938c-4412-a77b-505fc696a677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822060725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1822060725
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1565539439
Short name T493
Test name
Test status
Simulation time 52519209 ps
CPU time 0.76 seconds
Started Jul 01 12:50:26 PM PDT 24
Finished Jul 01 12:50:29 PM PDT 24
Peak memory 205980 kb
Host smart-ccfb0708-893e-4e5d-a484-865daf50a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565539439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1565539439
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.617870732
Short name T664
Test name
Test status
Simulation time 23625656804 ps
CPU time 22.22 seconds
Started Jul 01 12:50:31 PM PDT 24
Finished Jul 01 12:50:55 PM PDT 24
Peak memory 224440 kb
Host smart-89807414-c89c-4ecf-926e-9611b83650d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617870732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.617870732
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3634282762
Short name T343
Test name
Test status
Simulation time 58520139 ps
CPU time 0.7 seconds
Started Jul 01 12:50:38 PM PDT 24
Finished Jul 01 12:50:39 PM PDT 24
Peak memory 205544 kb
Host smart-d8159f05-ffa7-4492-959c-cc491d71316f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634282762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3634282762
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.320976601
Short name T1009
Test name
Test status
Simulation time 1284634303 ps
CPU time 11.66 seconds
Started Jul 01 12:50:36 PM PDT 24
Finished Jul 01 12:50:49 PM PDT 24
Peak memory 224428 kb
Host smart-c656ba43-f163-4a57-97aa-c6eff0935899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320976601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.320976601
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4141567545
Short name T716
Test name
Test status
Simulation time 26921564 ps
CPU time 0.76 seconds
Started Jul 01 12:50:31 PM PDT 24
Finished Jul 01 12:50:34 PM PDT 24
Peak memory 205848 kb
Host smart-f6f89213-324c-458c-90b9-b3d38ef87fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141567545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4141567545
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1507916612
Short name T451
Test name
Test status
Simulation time 26408633 ps
CPU time 0.79 seconds
Started Jul 01 12:50:37 PM PDT 24
Finished Jul 01 12:50:39 PM PDT 24
Peak memory 215784 kb
Host smart-4c99e301-7db1-48d3-975d-a5e0ed91015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507916612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1507916612
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4292847416
Short name T375
Test name
Test status
Simulation time 7226819818 ps
CPU time 80.79 seconds
Started Jul 01 12:50:36 PM PDT 24
Finished Jul 01 12:51:58 PM PDT 24
Peak memory 249308 kb
Host smart-1fa1c3f9-8a47-4f13-a06e-da4354c0c6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292847416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4292847416
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1784233578
Short name T627
Test name
Test status
Simulation time 313371261 ps
CPU time 3.86 seconds
Started Jul 01 12:50:35 PM PDT 24
Finished Jul 01 12:50:39 PM PDT 24
Peak memory 224516 kb
Host smart-efdce1c9-3657-40eb-85fe-be267b73b5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784233578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1784233578
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2940138065
Short name T200
Test name
Test status
Simulation time 85248659622 ps
CPU time 241.56 seconds
Started Jul 01 12:50:35 PM PDT 24
Finished Jul 01 12:54:38 PM PDT 24
Peak memory 253616 kb
Host smart-b579da4e-fea7-4820-965b-3085de8a00cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940138065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2940138065
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1000297392
Short name T874
Test name
Test status
Simulation time 687031339 ps
CPU time 4.94 seconds
Started Jul 01 12:50:33 PM PDT 24
Finished Jul 01 12:50:39 PM PDT 24
Peak memory 232728 kb
Host smart-9020fb2b-01a0-4246-bd8f-990d2678a307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000297392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1000297392
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2999160697
Short name T977
Test name
Test status
Simulation time 412073576 ps
CPU time 10.19 seconds
Started Jul 01 12:50:34 PM PDT 24
Finished Jul 01 12:50:45 PM PDT 24
Peak memory 224516 kb
Host smart-9097ddac-18e0-4ad5-b40e-54dcb09bfe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999160697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2999160697
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.4253845759
Short name T959
Test name
Test status
Simulation time 15725386509 ps
CPU time 15.76 seconds
Started Jul 01 12:50:31 PM PDT 24
Finished Jul 01 12:50:49 PM PDT 24
Peak memory 232972 kb
Host smart-8f6a0e8a-01fe-438c-a1ff-968ace7a2c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253845759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.4253845759
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3938442736
Short name T612
Test name
Test status
Simulation time 5363111193 ps
CPU time 9.66 seconds
Started Jul 01 12:50:34 PM PDT 24
Finished Jul 01 12:50:44 PM PDT 24
Peak memory 232784 kb
Host smart-bcd0cd24-e54a-4a17-b590-2fe49cb8343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938442736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3938442736
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1622156436
Short name T641
Test name
Test status
Simulation time 968579118 ps
CPU time 13.19 seconds
Started Jul 01 12:50:35 PM PDT 24
Finished Jul 01 12:50:50 PM PDT 24
Peak memory 222004 kb
Host smart-dc6e3659-fb20-43dc-b052-d9268c81f63e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1622156436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1622156436
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4162859992
Short name T523
Test name
Test status
Simulation time 8255497524 ps
CPU time 21.7 seconds
Started Jul 01 12:50:33 PM PDT 24
Finished Jul 01 12:50:56 PM PDT 24
Peak memory 216724 kb
Host smart-3ca0890b-283d-429b-82ff-8c48411cf8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162859992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4162859992
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1885971876
Short name T965
Test name
Test status
Simulation time 855341863 ps
CPU time 6.43 seconds
Started Jul 01 12:50:30 PM PDT 24
Finished Jul 01 12:50:39 PM PDT 24
Peak memory 216188 kb
Host smart-8e18ecbe-0888-426c-b21c-0ff34c5a5c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885971876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1885971876
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3087525968
Short name T932
Test name
Test status
Simulation time 606087464 ps
CPU time 2.15 seconds
Started Jul 01 12:50:30 PM PDT 24
Finished Jul 01 12:50:34 PM PDT 24
Peak memory 216144 kb
Host smart-66004d50-10ea-4bf2-a610-0deded2d6177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087525968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3087525968
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2759933357
Short name T517
Test name
Test status
Simulation time 15265018 ps
CPU time 0.72 seconds
Started Jul 01 12:50:31 PM PDT 24
Finished Jul 01 12:50:34 PM PDT 24
Peak memory 205992 kb
Host smart-48996989-8279-4914-b8f1-397e8b6c5279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759933357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2759933357
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.749199626
Short name T854
Test name
Test status
Simulation time 3257754131 ps
CPU time 8.75 seconds
Started Jul 01 12:50:35 PM PDT 24
Finished Jul 01 12:50:45 PM PDT 24
Peak memory 232792 kb
Host smart-cb695a5f-e460-4f34-9e1f-26960f6b0d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749199626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.749199626
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.357823557
Short name T531
Test name
Test status
Simulation time 13631973 ps
CPU time 0.73 seconds
Started Jul 01 12:50:42 PM PDT 24
Finished Jul 01 12:50:45 PM PDT 24
Peak memory 204632 kb
Host smart-4b8f680a-dbbe-4447-af3f-14fa3e18ec13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357823557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.357823557
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3141303758
Short name T490
Test name
Test status
Simulation time 27142128915 ps
CPU time 15.59 seconds
Started Jul 01 12:50:41 PM PDT 24
Finished Jul 01 12:50:59 PM PDT 24
Peak memory 232760 kb
Host smart-bbff49a9-4fdc-4d8f-99c2-89b041cb7c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141303758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3141303758
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.810409160
Short name T657
Test name
Test status
Simulation time 40479232 ps
CPU time 0.78 seconds
Started Jul 01 12:50:35 PM PDT 24
Finished Jul 01 12:50:37 PM PDT 24
Peak memory 206624 kb
Host smart-8778ffd2-3622-4c93-96f6-16b1e5984b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810409160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.810409160
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.49430271
Short name T767
Test name
Test status
Simulation time 4357363246 ps
CPU time 62.59 seconds
Started Jul 01 12:50:42 PM PDT 24
Finished Jul 01 12:51:46 PM PDT 24
Peak memory 271476 kb
Host smart-05f773fc-9601-48f4-bfb5-18b550f7f30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49430271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.49430271
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1670108365
Short name T16
Test name
Test status
Simulation time 404377739 ps
CPU time 6.35 seconds
Started Jul 01 12:50:42 PM PDT 24
Finished Jul 01 12:50:50 PM PDT 24
Peak memory 232708 kb
Host smart-3522d71b-5f02-4737-abb9-4e61a8ddee49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670108365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1670108365
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3282209707
Short name T167
Test name
Test status
Simulation time 35254362560 ps
CPU time 59.76 seconds
Started Jul 01 12:50:43 PM PDT 24
Finished Jul 01 12:51:44 PM PDT 24
Peak memory 251160 kb
Host smart-48d0e010-8fc0-44d0-af7f-f8483fff945a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282209707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3282209707
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1403196849
Short name T210
Test name
Test status
Simulation time 1057742604 ps
CPU time 11.49 seconds
Started Jul 01 12:50:35 PM PDT 24
Finished Jul 01 12:50:48 PM PDT 24
Peak memory 224456 kb
Host smart-b50b93cf-e7c5-4cbf-85e5-b8ff71675f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403196849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1403196849
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.582698253
Short name T38
Test name
Test status
Simulation time 6438331582 ps
CPU time 52.99 seconds
Started Jul 01 12:50:41 PM PDT 24
Finished Jul 01 12:51:36 PM PDT 24
Peak memory 240664 kb
Host smart-a4f2613a-9e39-436f-b299-fd08f82d6f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582698253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.582698253
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3612748001
Short name T992
Test name
Test status
Simulation time 3058934529 ps
CPU time 11.66 seconds
Started Jul 01 12:50:36 PM PDT 24
Finished Jul 01 12:50:48 PM PDT 24
Peak memory 233792 kb
Host smart-c4ab2971-aa4c-40a3-8680-495c07fa444f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612748001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3612748001
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3498220691
Short name T237
Test name
Test status
Simulation time 15742352878 ps
CPU time 12.65 seconds
Started Jul 01 12:50:38 PM PDT 24
Finished Jul 01 12:50:51 PM PDT 24
Peak memory 232800 kb
Host smart-27045d50-9231-4145-928d-95dd20f6cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498220691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3498220691
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3459982019
Short name T407
Test name
Test status
Simulation time 5330571506 ps
CPU time 15.92 seconds
Started Jul 01 12:50:40 PM PDT 24
Finished Jul 01 12:50:57 PM PDT 24
Peak memory 223108 kb
Host smart-14fa9b80-599e-4abc-8e45-21b585b1ea60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3459982019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3459982019
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2106103075
Short name T193
Test name
Test status
Simulation time 304756553847 ps
CPU time 875.62 seconds
Started Jul 01 12:50:40 PM PDT 24
Finished Jul 01 01:05:17 PM PDT 24
Peak memory 269016 kb
Host smart-27727969-4600-4e4a-bae5-bdbf66746b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106103075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2106103075
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3121451906
Short name T871
Test name
Test status
Simulation time 724128092 ps
CPU time 2.01 seconds
Started Jul 01 12:50:40 PM PDT 24
Finished Jul 01 12:50:43 PM PDT 24
Peak memory 216420 kb
Host smart-ae3f6762-e60a-4a2e-8c6e-bb0b64f3f2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121451906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3121451906
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1337407162
Short name T869
Test name
Test status
Simulation time 8400860727 ps
CPU time 14.22 seconds
Started Jul 01 12:50:35 PM PDT 24
Finished Jul 01 12:50:50 PM PDT 24
Peak memory 216260 kb
Host smart-7a233499-24f2-4816-8ff3-3302d39d62a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337407162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1337407162
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1474652979
Short name T669
Test name
Test status
Simulation time 18058748 ps
CPU time 1.01 seconds
Started Jul 01 12:50:35 PM PDT 24
Finished Jul 01 12:50:37 PM PDT 24
Peak memory 207260 kb
Host smart-3a3cd7b2-7adb-4cf9-a0ef-bb744ad75ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474652979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1474652979
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2310119783
Short name T894
Test name
Test status
Simulation time 183658345 ps
CPU time 0.85 seconds
Started Jul 01 12:50:38 PM PDT 24
Finished Jul 01 12:50:40 PM PDT 24
Peak memory 206400 kb
Host smart-b70629dd-f64c-48d8-80f4-5b8e110725a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310119783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2310119783
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3043778423
Short name T39
Test name
Test status
Simulation time 7446069592 ps
CPU time 24.32 seconds
Started Jul 01 12:50:41 PM PDT 24
Finished Jul 01 12:51:07 PM PDT 24
Peak memory 232764 kb
Host smart-1f8d74af-9166-47ca-93a7-3acbb488aa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043778423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3043778423
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.189924246
Short name T422
Test name
Test status
Simulation time 11989388 ps
CPU time 0.72 seconds
Started Jul 01 12:50:46 PM PDT 24
Finished Jul 01 12:50:48 PM PDT 24
Peak memory 205516 kb
Host smart-663998b1-b9bd-4a13-b76a-7f039e18100c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189924246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.189924246
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2097097815
Short name T898
Test name
Test status
Simulation time 113721159 ps
CPU time 2.11 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:50:51 PM PDT 24
Peak memory 224436 kb
Host smart-aa42c635-3c4a-4107-ba77-2916d8376cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097097815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2097097815
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.810556942
Short name T920
Test name
Test status
Simulation time 16054227 ps
CPU time 0.79 seconds
Started Jul 01 12:50:40 PM PDT 24
Finished Jul 01 12:50:42 PM PDT 24
Peak memory 206932 kb
Host smart-82312fc1-bdf6-4876-b278-47d437b91a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810556942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.810556942
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.788842436
Short name T994
Test name
Test status
Simulation time 14896559 ps
CPU time 0.77 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:50:50 PM PDT 24
Peak memory 215764 kb
Host smart-882c960e-8f53-4e5b-9c6a-21ba10b2d066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788842436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.788842436
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.59485736
Short name T666
Test name
Test status
Simulation time 19813289621 ps
CPU time 33.26 seconds
Started Jul 01 12:50:46 PM PDT 24
Finished Jul 01 12:51:21 PM PDT 24
Peak memory 249288 kb
Host smart-7603ee42-3ee5-4029-b373-bda6be7b36dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59485736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.59485736
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.437908125
Short name T260
Test name
Test status
Simulation time 11650045848 ps
CPU time 55.82 seconds
Started Jul 01 12:50:48 PM PDT 24
Finished Jul 01 12:51:46 PM PDT 24
Peak memory 252432 kb
Host smart-cb2cc3e5-ae2e-4c39-a12c-f3fae58e9b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437908125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.437908125
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3122260893
Short name T836
Test name
Test status
Simulation time 18268455117 ps
CPU time 67 seconds
Started Jul 01 12:50:51 PM PDT 24
Finished Jul 01 12:51:59 PM PDT 24
Peak memory 232808 kb
Host smart-051446f1-7504-4d4d-82f6-e67cb5b8b8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122260893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3122260893
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.4094708583
Short name T520
Test name
Test status
Simulation time 58293744288 ps
CPU time 61.04 seconds
Started Jul 01 12:50:48 PM PDT 24
Finished Jul 01 12:51:51 PM PDT 24
Peak memory 241020 kb
Host smart-d98e76e6-7dfb-481e-909f-47054f5f3e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094708583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.4094708583
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3833714253
Short name T841
Test name
Test status
Simulation time 224979266 ps
CPU time 6.87 seconds
Started Jul 01 12:50:41 PM PDT 24
Finished Jul 01 12:50:50 PM PDT 24
Peak memory 232656 kb
Host smart-b715fcb6-74f0-4a7c-88fc-c2cd0ce1b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833714253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3833714253
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2600432532
Short name T768
Test name
Test status
Simulation time 23111943680 ps
CPU time 84.8 seconds
Started Jul 01 12:50:42 PM PDT 24
Finished Jul 01 12:52:08 PM PDT 24
Peak memory 232828 kb
Host smart-95d5e5f8-8f5f-45d4-af10-0ee4cc2f9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600432532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2600432532
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3643910465
Short name T266
Test name
Test status
Simulation time 53686101877 ps
CPU time 24.73 seconds
Started Jul 01 12:50:40 PM PDT 24
Finished Jul 01 12:51:07 PM PDT 24
Peak memory 224608 kb
Host smart-2252fa97-3b4b-4f45-b9e0-1361da0e6be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643910465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3643910465
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.454133344
Short name T255
Test name
Test status
Simulation time 9047200346 ps
CPU time 15.4 seconds
Started Jul 01 12:50:44 PM PDT 24
Finished Jul 01 12:51:01 PM PDT 24
Peak memory 232988 kb
Host smart-2054090a-575f-4ebf-be83-e3f44ef6ccfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454133344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.454133344
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.919326360
Short name T877
Test name
Test status
Simulation time 441283866 ps
CPU time 4.22 seconds
Started Jul 01 12:50:45 PM PDT 24
Finished Jul 01 12:50:51 PM PDT 24
Peak memory 219268 kb
Host smart-81ba1bef-8796-48d1-95e4-c1d14fa447c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=919326360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.919326360
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.754255890
Short name T281
Test name
Test status
Simulation time 655226022858 ps
CPU time 461.58 seconds
Started Jul 01 12:50:51 PM PDT 24
Finished Jul 01 12:58:34 PM PDT 24
Peak memory 271684 kb
Host smart-aca59f30-2c26-41e8-acd3-e3e44d413837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754255890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.754255890
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3375958644
Short name T742
Test name
Test status
Simulation time 1161109966 ps
CPU time 12.55 seconds
Started Jul 01 12:50:41 PM PDT 24
Finished Jul 01 12:50:55 PM PDT 24
Peak memory 216232 kb
Host smart-20ddd62a-bd70-4546-8c23-fd3dec617825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375958644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3375958644
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3576226723
Short name T518
Test name
Test status
Simulation time 10450694 ps
CPU time 0.71 seconds
Started Jul 01 12:50:41 PM PDT 24
Finished Jul 01 12:50:43 PM PDT 24
Peak memory 205676 kb
Host smart-ffd2d0d2-b173-4bda-ab37-2e98181c4116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576226723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3576226723
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1126108475
Short name T8
Test name
Test status
Simulation time 69761761 ps
CPU time 1.85 seconds
Started Jul 01 12:50:41 PM PDT 24
Finished Jul 01 12:50:45 PM PDT 24
Peak memory 216276 kb
Host smart-9ca7f402-50dc-4843-a862-89ce742d3591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126108475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1126108475
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.269548007
Short name T801
Test name
Test status
Simulation time 137498240 ps
CPU time 0.97 seconds
Started Jul 01 12:50:43 PM PDT 24
Finished Jul 01 12:50:45 PM PDT 24
Peak memory 206532 kb
Host smart-cf4cbc40-4244-46ca-a7bf-e45b60d4d883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269548007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.269548007
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.4093812575
Short name T975
Test name
Test status
Simulation time 6837950150 ps
CPU time 22.9 seconds
Started Jul 01 12:50:40 PM PDT 24
Finished Jul 01 12:51:04 PM PDT 24
Peak memory 224620 kb
Host smart-4bde8458-d39a-4801-a653-0d4563d511cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093812575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4093812575
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2484265356
Short name T313
Test name
Test status
Simulation time 13993337 ps
CPU time 0.72 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:50:50 PM PDT 24
Peak memory 205860 kb
Host smart-27e9dc25-2eef-4414-b033-99688ce2073f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484265356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2484265356
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1359517662
Short name T494
Test name
Test status
Simulation time 154636265 ps
CPU time 2.14 seconds
Started Jul 01 12:50:48 PM PDT 24
Finished Jul 01 12:50:52 PM PDT 24
Peak memory 224512 kb
Host smart-26f8ff34-602a-4c45-a52a-2fe9a7b07552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359517662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1359517662
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1464725804
Short name T382
Test name
Test status
Simulation time 35052760 ps
CPU time 0.79 seconds
Started Jul 01 12:50:48 PM PDT 24
Finished Jul 01 12:50:50 PM PDT 24
Peak memory 206600 kb
Host smart-aea41908-7bbd-44d5-bd95-42602b3cbbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464725804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1464725804
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1174431670
Short name T798
Test name
Test status
Simulation time 470588087 ps
CPU time 8.84 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:50:58 PM PDT 24
Peak memory 233744 kb
Host smart-79055840-3bdd-4ddd-998b-cbfe5f66fd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174431670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1174431670
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1809073003
Short name T890
Test name
Test status
Simulation time 72317534885 ps
CPU time 500.47 seconds
Started Jul 01 12:50:46 PM PDT 24
Finished Jul 01 12:59:08 PM PDT 24
Peak memory 265676 kb
Host smart-b74debe9-b63a-43b6-8bb7-7a298281a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809073003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1809073003
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3321813721
Short name T997
Test name
Test status
Simulation time 3130190846 ps
CPU time 6.6 seconds
Started Jul 01 12:50:48 PM PDT 24
Finished Jul 01 12:50:56 PM PDT 24
Peak memory 217748 kb
Host smart-0deaedbd-e134-40e9-ac54-a9e4d69b1c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321813721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3321813721
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3361455073
Short name T410
Test name
Test status
Simulation time 2794025411 ps
CPU time 14.57 seconds
Started Jul 01 12:50:46 PM PDT 24
Finished Jul 01 12:51:02 PM PDT 24
Peak memory 232760 kb
Host smart-57bc8845-3442-4e14-95fe-558a8bcb5fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361455073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3361455073
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2367046882
Short name T180
Test name
Test status
Simulation time 650737135 ps
CPU time 9.87 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:50:59 PM PDT 24
Peak memory 224432 kb
Host smart-953ec7ff-9a38-4f4e-a353-37e6014194ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367046882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2367046882
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2936534049
Short name T478
Test name
Test status
Simulation time 386802671 ps
CPU time 2.86 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:50:52 PM PDT 24
Peak memory 224504 kb
Host smart-42b8eca5-9787-466e-9d52-373fa5c85e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936534049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2936534049
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3544144622
Short name T257
Test name
Test status
Simulation time 106925094 ps
CPU time 3.44 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:50:53 PM PDT 24
Peak memory 224496 kb
Host smart-59f1ea1a-4145-4cdc-b2a7-41084d8ca804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544144622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3544144622
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.459239483
Short name T942
Test name
Test status
Simulation time 8476751265 ps
CPU time 12.18 seconds
Started Jul 01 12:50:50 PM PDT 24
Finished Jul 01 12:51:03 PM PDT 24
Peak memory 224584 kb
Host smart-976934f6-f0d7-4359-bf3a-9489bbf684e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459239483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.459239483
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4197737097
Short name T964
Test name
Test status
Simulation time 512858033 ps
CPU time 5.61 seconds
Started Jul 01 12:50:45 PM PDT 24
Finished Jul 01 12:50:53 PM PDT 24
Peak memory 238092 kb
Host smart-41fdca2b-60aa-428a-b13a-206e036ee3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197737097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4197737097
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1898036175
Short name T873
Test name
Test status
Simulation time 8475659736 ps
CPU time 16.71 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:51:06 PM PDT 24
Peak memory 221748 kb
Host smart-e0814ac7-8a1d-40de-b6d8-68641eba6d4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1898036175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1898036175
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1392974502
Short name T156
Test name
Test status
Simulation time 40272717766 ps
CPU time 71.95 seconds
Started Jul 01 12:50:46 PM PDT 24
Finished Jul 01 12:51:59 PM PDT 24
Peak memory 249224 kb
Host smart-fb6512c7-6b86-4b0e-9d50-1a0efc042223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392974502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1392974502
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3312173357
Short name T596
Test name
Test status
Simulation time 970282340 ps
CPU time 10.65 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:50:59 PM PDT 24
Peak memory 216456 kb
Host smart-9dcf1c6d-9470-4c46-a197-aa1e6a4932f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312173357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3312173357
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1220771369
Short name T538
Test name
Test status
Simulation time 211558081 ps
CPU time 1.98 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:50:51 PM PDT 24
Peak memory 216204 kb
Host smart-ad9e8ccf-c447-450d-9bfa-88578a39b8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220771369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1220771369
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3174536460
Short name T978
Test name
Test status
Simulation time 167631226 ps
CPU time 2.88 seconds
Started Jul 01 12:50:49 PM PDT 24
Finished Jul 01 12:50:54 PM PDT 24
Peak memory 216252 kb
Host smart-b2e57985-0438-479d-b4a6-f247bc8e062a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174536460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3174536460
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3676888466
Short name T885
Test name
Test status
Simulation time 104937285 ps
CPU time 0.97 seconds
Started Jul 01 12:50:45 PM PDT 24
Finished Jul 01 12:50:47 PM PDT 24
Peak memory 205924 kb
Host smart-7d299c9b-90c9-4714-81e8-36ae3ec59dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676888466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3676888466
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1024987129
Short name T521
Test name
Test status
Simulation time 24224052922 ps
CPU time 13.43 seconds
Started Jul 01 12:50:47 PM PDT 24
Finished Jul 01 12:51:02 PM PDT 24
Peak memory 232768 kb
Host smart-edaea8cd-9595-4cf7-a56c-cf477f07b585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024987129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1024987129
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3681472978
Short name T424
Test name
Test status
Simulation time 14619101 ps
CPU time 0.75 seconds
Started Jul 01 12:46:53 PM PDT 24
Finished Jul 01 12:46:55 PM PDT 24
Peak memory 205880 kb
Host smart-3e230bcd-58ba-4d32-9e5a-b1336a966d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681472978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
681472978
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2319017358
Short name T37
Test name
Test status
Simulation time 112809386 ps
CPU time 2.27 seconds
Started Jul 01 12:46:54 PM PDT 24
Finished Jul 01 12:46:57 PM PDT 24
Peak memory 223864 kb
Host smart-04853309-7132-4371-a5d8-63a27ec5f2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319017358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2319017358
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2667472687
Short name T629
Test name
Test status
Simulation time 24587721 ps
CPU time 0.79 seconds
Started Jul 01 12:46:48 PM PDT 24
Finished Jul 01 12:46:50 PM PDT 24
Peak memory 206824 kb
Host smart-dd55f553-8c63-4f11-a4be-317aadaea9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667472687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2667472687
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3417499992
Short name T882
Test name
Test status
Simulation time 115675234425 ps
CPU time 260.88 seconds
Started Jul 01 12:46:53 PM PDT 24
Finished Jul 01 12:51:14 PM PDT 24
Peak memory 267776 kb
Host smart-2a71f870-72d0-4d90-9789-a5321413663b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417499992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3417499992
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1187681967
Short name T283
Test name
Test status
Simulation time 9373538472 ps
CPU time 99.32 seconds
Started Jul 01 12:46:54 PM PDT 24
Finished Jul 01 12:48:34 PM PDT 24
Peak memory 257136 kb
Host smart-08200def-2653-42da-b8c0-6630d2ad5810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187681967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1187681967
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.858094227
Short name T577
Test name
Test status
Simulation time 47488419520 ps
CPU time 120.01 seconds
Started Jul 01 12:46:52 PM PDT 24
Finished Jul 01 12:48:53 PM PDT 24
Peak memory 261640 kb
Host smart-65ad2fc6-e8de-4b11-9bf6-6a607fc31093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858094227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
858094227
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1590766391
Short name T338
Test name
Test status
Simulation time 439375499 ps
CPU time 7.17 seconds
Started Jul 01 12:46:53 PM PDT 24
Finished Jul 01 12:47:01 PM PDT 24
Peak memory 232596 kb
Host smart-b51b2d05-731f-46f2-8cb2-8090f28f79c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590766391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1590766391
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.754611050
Short name T91
Test name
Test status
Simulation time 9319314935 ps
CPU time 39.88 seconds
Started Jul 01 12:46:52 PM PDT 24
Finished Jul 01 12:47:33 PM PDT 24
Peak memory 249248 kb
Host smart-9286c0de-d748-441a-b6ab-8bc96b6768b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754611050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
754611050
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2249077500
Short name T354
Test name
Test status
Simulation time 6067537403 ps
CPU time 11.35 seconds
Started Jul 01 12:46:51 PM PDT 24
Finished Jul 01 12:47:03 PM PDT 24
Peak memory 228204 kb
Host smart-8ac44a81-1d86-4b5e-a9a4-8d6f5298561c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249077500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2249077500
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1296232643
Short name T452
Test name
Test status
Simulation time 1440634725 ps
CPU time 16.13 seconds
Started Jul 01 12:46:52 PM PDT 24
Finished Jul 01 12:47:09 PM PDT 24
Peak memory 232712 kb
Host smart-080bf5e0-5410-4acd-b0e0-c0f1ecd2cec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296232643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1296232643
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2872271325
Short name T239
Test name
Test status
Simulation time 8445147456 ps
CPU time 10.36 seconds
Started Jul 01 12:46:52 PM PDT 24
Finished Jul 01 12:47:04 PM PDT 24
Peak memory 233020 kb
Host smart-811fac35-0f55-40a7-97dd-f7eca4d245ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872271325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2872271325
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1152157890
Short name T781
Test name
Test status
Simulation time 650424661 ps
CPU time 3.14 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:46:51 PM PDT 24
Peak memory 232664 kb
Host smart-9b7fc27b-1568-4a0e-af2a-2609481ed32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152157890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1152157890
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3327151790
Short name T148
Test name
Test status
Simulation time 85784646 ps
CPU time 3.23 seconds
Started Jul 01 12:46:54 PM PDT 24
Finished Jul 01 12:46:58 PM PDT 24
Peak memory 220880 kb
Host smart-48307392-75f9-41e0-a90c-f5982a5053c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3327151790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3327151790
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3015455914
Short name T550
Test name
Test status
Simulation time 8072611917 ps
CPU time 41.24 seconds
Started Jul 01 12:46:53 PM PDT 24
Finished Jul 01 12:47:35 PM PDT 24
Peak memory 235680 kb
Host smart-40c1541e-766f-4e8a-b408-0806e565a65c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015455914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3015455914
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.134770663
Short name T936
Test name
Test status
Simulation time 70587710058 ps
CPU time 22.26 seconds
Started Jul 01 12:46:45 PM PDT 24
Finished Jul 01 12:47:09 PM PDT 24
Peak memory 216272 kb
Host smart-4ffd7528-1029-49ae-8410-31a0119f7c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134770663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.134770663
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1018215263
Short name T883
Test name
Test status
Simulation time 27019923 ps
CPU time 1.58 seconds
Started Jul 01 12:46:48 PM PDT 24
Finished Jul 01 12:46:50 PM PDT 24
Peak memory 207972 kb
Host smart-5a3cecb0-c767-4613-ab6c-1acb55abc3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018215263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1018215263
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3911289254
Short name T26
Test name
Test status
Simulation time 142683792 ps
CPU time 0.99 seconds
Started Jul 01 12:46:46 PM PDT 24
Finished Jul 01 12:46:49 PM PDT 24
Peak memory 206956 kb
Host smart-0033e44b-a951-451f-9aff-0e60d2f11ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911289254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3911289254
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.978052141
Short name T225
Test name
Test status
Simulation time 3213963762 ps
CPU time 7.78 seconds
Started Jul 01 12:46:52 PM PDT 24
Finished Jul 01 12:47:01 PM PDT 24
Peak memory 236792 kb
Host smart-dfd6a65a-6e15-4877-a0e7-5d7d90958648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978052141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.978052141
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.716106475
Short name T592
Test name
Test status
Simulation time 31007089 ps
CPU time 0.81 seconds
Started Jul 01 12:47:01 PM PDT 24
Finished Jul 01 12:47:03 PM PDT 24
Peak memory 205852 kb
Host smart-aa87e12b-01dc-4b64-b119-0334d11092d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716106475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.716106475
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3612413805
Short name T995
Test name
Test status
Simulation time 2365413748 ps
CPU time 5.72 seconds
Started Jul 01 12:46:58 PM PDT 24
Finished Jul 01 12:47:05 PM PDT 24
Peak memory 224548 kb
Host smart-64949e45-518d-45f0-ba8e-56857223e686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612413805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3612413805
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2696032310
Short name T983
Test name
Test status
Simulation time 60548460 ps
CPU time 0.77 seconds
Started Jul 01 12:46:52 PM PDT 24
Finished Jul 01 12:46:53 PM PDT 24
Peak memory 206616 kb
Host smart-a442fa57-8ee1-4cf5-81e3-f5d47c6ca7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696032310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2696032310
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2130555921
Short name T43
Test name
Test status
Simulation time 271311301431 ps
CPU time 657.06 seconds
Started Jul 01 12:46:57 PM PDT 24
Finished Jul 01 12:57:55 PM PDT 24
Peak memory 273528 kb
Host smart-291c4698-a560-43e9-890c-a4ba5b986f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130555921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2130555921
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2408159897
Short name T564
Test name
Test status
Simulation time 9953411571 ps
CPU time 126.31 seconds
Started Jul 01 12:47:00 PM PDT 24
Finished Jul 01 12:49:07 PM PDT 24
Peak memory 249152 kb
Host smart-f34710f8-e357-4f0d-962a-56726060486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408159897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2408159897
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1129473884
Short name T357
Test name
Test status
Simulation time 1763088288 ps
CPU time 9.03 seconds
Started Jul 01 12:46:59 PM PDT 24
Finished Jul 01 12:47:09 PM PDT 24
Peak memory 235828 kb
Host smart-bf97aa64-ca0b-400d-b45c-76c5832e2ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129473884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1129473884
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.649397430
Short name T259
Test name
Test status
Simulation time 3071844655 ps
CPU time 55.65 seconds
Started Jul 01 12:46:57 PM PDT 24
Finished Jul 01 12:47:54 PM PDT 24
Peak memory 245848 kb
Host smart-ea76e002-918c-42d3-86b1-7d89838ddf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649397430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
649397430
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3690707491
Short name T778
Test name
Test status
Simulation time 308370454 ps
CPU time 5.99 seconds
Started Jul 01 12:46:57 PM PDT 24
Finished Jul 01 12:47:04 PM PDT 24
Peak memory 232700 kb
Host smart-5a928942-2ca7-4790-83dc-19b4a85181d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690707491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3690707491
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3090951897
Short name T796
Test name
Test status
Simulation time 319589121 ps
CPU time 6.59 seconds
Started Jul 01 12:47:01 PM PDT 24
Finished Jul 01 12:47:08 PM PDT 24
Peak memory 232672 kb
Host smart-a46fb24a-6c17-42e0-865a-41470fbab638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090951897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3090951897
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1049095302
Short name T464
Test name
Test status
Simulation time 1392343677 ps
CPU time 5.93 seconds
Started Jul 01 12:46:59 PM PDT 24
Finished Jul 01 12:47:06 PM PDT 24
Peak memory 232616 kb
Host smart-6bfb6719-1b43-44d3-b2a1-08d6d9456c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049095302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1049095302
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.638084619
Short name T365
Test name
Test status
Simulation time 4416242506 ps
CPU time 5.45 seconds
Started Jul 01 12:46:57 PM PDT 24
Finished Jul 01 12:47:04 PM PDT 24
Peak memory 224632 kb
Host smart-d1022751-6999-4d93-8928-4a318950eadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638084619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.638084619
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.651260574
Short name T631
Test name
Test status
Simulation time 1772328133 ps
CPU time 9.13 seconds
Started Jul 01 12:46:58 PM PDT 24
Finished Jul 01 12:47:08 PM PDT 24
Peak memory 223116 kb
Host smart-e8805da5-a31e-4d3c-80f6-a8f7e95e26e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=651260574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.651260574
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3942252713
Short name T241
Test name
Test status
Simulation time 3735108459 ps
CPU time 33.01 seconds
Started Jul 01 12:46:58 PM PDT 24
Finished Jul 01 12:47:32 PM PDT 24
Peak memory 224656 kb
Host smart-fedcff15-0f69-4b0f-be84-dd591dfff4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942252713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3942252713
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1317766759
Short name T295
Test name
Test status
Simulation time 4324857332 ps
CPU time 17.63 seconds
Started Jul 01 12:46:53 PM PDT 24
Finished Jul 01 12:47:12 PM PDT 24
Peak memory 216320 kb
Host smart-c56444be-8593-4119-96b7-a5aea4de0595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317766759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1317766759
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3766612894
Short name T315
Test name
Test status
Simulation time 16271926101 ps
CPU time 6.54 seconds
Started Jul 01 12:46:59 PM PDT 24
Finished Jul 01 12:47:07 PM PDT 24
Peak memory 217860 kb
Host smart-a47f3caf-bf92-453c-9c48-8ebfab6343b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766612894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3766612894
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3583434045
Short name T325
Test name
Test status
Simulation time 115788900 ps
CPU time 0.74 seconds
Started Jul 01 12:46:59 PM PDT 24
Finished Jul 01 12:47:00 PM PDT 24
Peak memory 205620 kb
Host smart-8da23202-be94-48fe-905f-51986f16426b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583434045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3583434045
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1646327077
Short name T652
Test name
Test status
Simulation time 42416862 ps
CPU time 0.86 seconds
Started Jul 01 12:46:57 PM PDT 24
Finished Jul 01 12:46:58 PM PDT 24
Peak memory 205920 kb
Host smart-24303504-084e-449f-911c-688cae441846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646327077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1646327077
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2629272977
Short name T905
Test name
Test status
Simulation time 731769308 ps
CPU time 3.23 seconds
Started Jul 01 12:47:02 PM PDT 24
Finished Jul 01 12:47:07 PM PDT 24
Peak memory 226992 kb
Host smart-f05f2c10-8125-479f-867f-eeeb64b14fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629272977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2629272977
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2222032053
Short name T764
Test name
Test status
Simulation time 48478412 ps
CPU time 0.74 seconds
Started Jul 01 12:47:03 PM PDT 24
Finished Jul 01 12:47:05 PM PDT 24
Peak memory 204996 kb
Host smart-803ddc21-2f21-4404-ba38-ff7eab25e90e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222032053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
222032053
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3154768085
Short name T90
Test name
Test status
Simulation time 199201627 ps
CPU time 2.74 seconds
Started Jul 01 12:47:06 PM PDT 24
Finished Jul 01 12:47:10 PM PDT 24
Peak memory 224420 kb
Host smart-9a69efba-91dc-4e0e-94f1-4cb0240a7039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154768085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3154768085
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2283861729
Short name T775
Test name
Test status
Simulation time 63407948 ps
CPU time 0.82 seconds
Started Jul 01 12:47:00 PM PDT 24
Finished Jul 01 12:47:02 PM PDT 24
Peak memory 206628 kb
Host smart-0dc563d3-83ab-48da-beea-8ee9d0bf1f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283861729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2283861729
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3137162234
Short name T205
Test name
Test status
Simulation time 38746549256 ps
CPU time 201.66 seconds
Started Jul 01 12:47:03 PM PDT 24
Finished Jul 01 12:50:26 PM PDT 24
Peak memory 264280 kb
Host smart-ddd9eb24-3091-4eac-850a-31f2e4883454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137162234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3137162234
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.990246467
Short name T963
Test name
Test status
Simulation time 24354365901 ps
CPU time 207.5 seconds
Started Jul 01 12:47:04 PM PDT 24
Finished Jul 01 12:50:33 PM PDT 24
Peak memory 255412 kb
Host smart-59eb3914-133a-4812-9d3e-55a5ca078cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990246467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.990246467
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.4216287067
Short name T974
Test name
Test status
Simulation time 31856547737 ps
CPU time 115.12 seconds
Started Jul 01 12:47:03 PM PDT 24
Finished Jul 01 12:48:59 PM PDT 24
Peak memory 265108 kb
Host smart-00e84c33-6a6f-4ef5-a349-823532b9113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216287067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.4216287067
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3218307247
Short name T289
Test name
Test status
Simulation time 1068911905 ps
CPU time 11.29 seconds
Started Jul 01 12:47:04 PM PDT 24
Finished Jul 01 12:47:16 PM PDT 24
Peak memory 224676 kb
Host smart-080aad1b-588e-456b-a205-9030d05878aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218307247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3218307247
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3016199988
Short name T500
Test name
Test status
Simulation time 7559913400 ps
CPU time 33.12 seconds
Started Jul 01 12:47:04 PM PDT 24
Finished Jul 01 12:47:38 PM PDT 24
Peak memory 249848 kb
Host smart-a89a229d-9122-414b-923e-08b0405ddd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016199988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3016199988
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3048795513
Short name T201
Test name
Test status
Simulation time 749797223 ps
CPU time 8.82 seconds
Started Jul 01 12:46:58 PM PDT 24
Finished Jul 01 12:47:07 PM PDT 24
Peak memory 232648 kb
Host smart-5bdc13b6-e529-4c14-92a3-c2a51905fdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048795513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3048795513
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2542136730
Short name T541
Test name
Test status
Simulation time 240594317 ps
CPU time 2.72 seconds
Started Jul 01 12:46:59 PM PDT 24
Finished Jul 01 12:47:03 PM PDT 24
Peak memory 232628 kb
Host smart-f11f8342-ab7c-443a-bee3-7823c4953cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542136730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2542136730
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3932981482
Short name T547
Test name
Test status
Simulation time 715628626 ps
CPU time 7.09 seconds
Started Jul 01 12:47:02 PM PDT 24
Finished Jul 01 12:47:10 PM PDT 24
Peak memory 232712 kb
Host smart-598bb5e7-26e1-422f-afb4-e5851c4ec49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932981482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3932981482
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1609537844
Short name T535
Test name
Test status
Simulation time 6675831977 ps
CPU time 11.22 seconds
Started Jul 01 12:47:00 PM PDT 24
Finished Jul 01 12:47:12 PM PDT 24
Peak memory 240840 kb
Host smart-e3501f36-2335-4115-a6c4-fe330ec38711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609537844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1609537844
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1144428925
Short name T387
Test name
Test status
Simulation time 67247640 ps
CPU time 3.6 seconds
Started Jul 01 12:47:04 PM PDT 24
Finished Jul 01 12:47:09 PM PDT 24
Peak memory 223080 kb
Host smart-5e445d69-b757-4619-90ef-4545c259a2d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1144428925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1144428925
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1155729568
Short name T136
Test name
Test status
Simulation time 53670075234 ps
CPU time 176.56 seconds
Started Jul 01 12:47:04 PM PDT 24
Finished Jul 01 12:50:02 PM PDT 24
Peak memory 265688 kb
Host smart-fb38f14c-09c3-429b-9ae4-8e4485af8f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155729568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1155729568
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1742257567
Short name T298
Test name
Test status
Simulation time 5709489179 ps
CPU time 21.88 seconds
Started Jul 01 12:46:56 PM PDT 24
Finished Jul 01 12:47:19 PM PDT 24
Peak memory 216444 kb
Host smart-ebb2205c-1afd-42ef-94e9-eed4417a99c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742257567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1742257567
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3410889211
Short name T815
Test name
Test status
Simulation time 6960953750 ps
CPU time 4.58 seconds
Started Jul 01 12:46:58 PM PDT 24
Finished Jul 01 12:47:04 PM PDT 24
Peak memory 216240 kb
Host smart-a116b005-4cd3-4da9-9259-ecd6c2654055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410889211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3410889211
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2608197660
Short name T581
Test name
Test status
Simulation time 594432590 ps
CPU time 1.03 seconds
Started Jul 01 12:46:57 PM PDT 24
Finished Jul 01 12:46:59 PM PDT 24
Peak memory 206976 kb
Host smart-98a419a0-c74c-443a-82f0-1a84e0244d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608197660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2608197660
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1809103714
Short name T356
Test name
Test status
Simulation time 67479788 ps
CPU time 0.76 seconds
Started Jul 01 12:46:59 PM PDT 24
Finished Jul 01 12:47:00 PM PDT 24
Peak memory 205904 kb
Host smart-5c61f2c0-2723-4e7b-a610-618a390b99aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809103714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1809103714
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.891935939
Short name T738
Test name
Test status
Simulation time 172536985 ps
CPU time 2.2 seconds
Started Jul 01 12:47:01 PM PDT 24
Finished Jul 01 12:47:04 PM PDT 24
Peak memory 223764 kb
Host smart-214ac0ac-58f1-450e-8e05-926d577aa491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891935939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.891935939
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.591779644
Short name T470
Test name
Test status
Simulation time 54625507 ps
CPU time 0.74 seconds
Started Jul 01 12:47:08 PM PDT 24
Finished Jul 01 12:47:10 PM PDT 24
Peak memory 205528 kb
Host smart-f9318508-1000-40df-b112-567a548ab298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591779644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.591779644
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2786010109
Short name T792
Test name
Test status
Simulation time 209984453 ps
CPU time 3.75 seconds
Started Jul 01 12:47:15 PM PDT 24
Finished Jul 01 12:47:20 PM PDT 24
Peak memory 232692 kb
Host smart-ee8856d2-f926-4766-8026-53ad9a2f03c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786010109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2786010109
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.949218315
Short name T682
Test name
Test status
Simulation time 29716362 ps
CPU time 0.86 seconds
Started Jul 01 12:47:06 PM PDT 24
Finished Jul 01 12:47:08 PM PDT 24
Peak memory 206492 kb
Host smart-1caad6d0-949e-45c5-8450-b86f8931f9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949218315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.949218315
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.345109006
Short name T196
Test name
Test status
Simulation time 54565689764 ps
CPU time 73.58 seconds
Started Jul 01 12:47:12 PM PDT 24
Finished Jul 01 12:48:27 PM PDT 24
Peak memory 257388 kb
Host smart-a23132a7-755f-4825-94eb-4b546c769e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345109006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.345109006
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1300494141
Short name T207
Test name
Test status
Simulation time 116123206185 ps
CPU time 255.75 seconds
Started Jul 01 12:47:12 PM PDT 24
Finished Jul 01 12:51:29 PM PDT 24
Peak memory 268556 kb
Host smart-af2c898c-f708-4c46-a23a-45ddeb7888b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300494141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1300494141
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2101321555
Short name T574
Test name
Test status
Simulation time 33563448479 ps
CPU time 353.47 seconds
Started Jul 01 12:47:15 PM PDT 24
Finished Jul 01 12:53:10 PM PDT 24
Peak memory 265204 kb
Host smart-049c5de8-866a-4cc5-9460-e8d04f680234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101321555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2101321555
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2691612132
Short name T851
Test name
Test status
Simulation time 417979065 ps
CPU time 4.05 seconds
Started Jul 01 12:47:15 PM PDT 24
Finished Jul 01 12:47:21 PM PDT 24
Peak memory 224496 kb
Host smart-e77f5003-6a21-49e8-9377-c7c0e40a25bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691612132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2691612132
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2858057749
Short name T181
Test name
Test status
Simulation time 18107730415 ps
CPU time 71.61 seconds
Started Jul 01 12:47:08 PM PDT 24
Finished Jul 01 12:48:21 PM PDT 24
Peak memory 262744 kb
Host smart-c0cd8fc5-ba07-4613-93c5-162e7c8aba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858057749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2858057749
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2080288749
Short name T590
Test name
Test status
Simulation time 379662692 ps
CPU time 2.32 seconds
Started Jul 01 12:47:08 PM PDT 24
Finished Jul 01 12:47:11 PM PDT 24
Peak memory 224112 kb
Host smart-3bbc7302-2073-4c3c-afa7-6a8848fc88bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080288749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2080288749
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2101814668
Short name T506
Test name
Test status
Simulation time 28066428390 ps
CPU time 26.97 seconds
Started Jul 01 12:47:05 PM PDT 24
Finished Jul 01 12:47:33 PM PDT 24
Peak memory 224512 kb
Host smart-4b5c0da2-36a9-4c25-9806-03d71dc6bbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101814668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2101814668
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4062509670
Short name T254
Test name
Test status
Simulation time 8243962892 ps
CPU time 24.74 seconds
Started Jul 01 12:47:08 PM PDT 24
Finished Jul 01 12:47:34 PM PDT 24
Peak memory 241460 kb
Host smart-ac4dd965-a0a9-4aa4-9be2-d849e17164a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062509670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4062509670
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.864918726
Short name T946
Test name
Test status
Simulation time 495350263 ps
CPU time 5.63 seconds
Started Jul 01 12:47:08 PM PDT 24
Finished Jul 01 12:47:15 PM PDT 24
Peak memory 240748 kb
Host smart-eef953f5-5514-4ce2-9683-b55778c25bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864918726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.864918726
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4136033302
Short name T597
Test name
Test status
Simulation time 318741876 ps
CPU time 3.73 seconds
Started Jul 01 12:47:12 PM PDT 24
Finished Jul 01 12:47:17 PM PDT 24
Peak memory 218808 kb
Host smart-8a8437f1-0931-43a2-bd10-157b7b99a8c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4136033302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4136033302
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2732189353
Short name T158
Test name
Test status
Simulation time 57387940279 ps
CPU time 188.23 seconds
Started Jul 01 12:47:09 PM PDT 24
Finished Jul 01 12:50:18 PM PDT 24
Peak memory 253268 kb
Host smart-576fcded-ff48-403b-8205-20728fe7a2e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732189353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2732189353
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.96617941
Short name T860
Test name
Test status
Simulation time 14444872690 ps
CPU time 38.3 seconds
Started Jul 01 12:47:08 PM PDT 24
Finished Jul 01 12:47:48 PM PDT 24
Peak memory 216308 kb
Host smart-96476bc5-31bf-4f43-a3f4-8000e5204639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96617941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.96617941
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3723009261
Short name T859
Test name
Test status
Simulation time 5374418729 ps
CPU time 16.18 seconds
Started Jul 01 12:47:08 PM PDT 24
Finished Jul 01 12:47:26 PM PDT 24
Peak memory 216332 kb
Host smart-5791cc32-09af-4761-94db-625cbfc05eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723009261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3723009261
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1571173405
Short name T628
Test name
Test status
Simulation time 14277483 ps
CPU time 1 seconds
Started Jul 01 12:47:07 PM PDT 24
Finished Jul 01 12:47:10 PM PDT 24
Peak memory 207076 kb
Host smart-105c60d8-3016-4656-a9b0-4de4c9b93656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571173405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1571173405
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1190832554
Short name T11
Test name
Test status
Simulation time 34912601 ps
CPU time 0.72 seconds
Started Jul 01 12:47:06 PM PDT 24
Finished Jul 01 12:47:08 PM PDT 24
Peak memory 205920 kb
Host smart-24c3bdf4-6c9f-4580-a796-cb2cef749fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190832554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1190832554
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3234260765
Short name T481
Test name
Test status
Simulation time 66184153 ps
CPU time 2.17 seconds
Started Jul 01 12:47:09 PM PDT 24
Finished Jul 01 12:47:12 PM PDT 24
Peak memory 223988 kb
Host smart-d11a3dfe-875b-4739-a0a1-50506181336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234260765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3234260765
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1739298555
Short name T601
Test name
Test status
Simulation time 14524960 ps
CPU time 0.72 seconds
Started Jul 01 12:47:20 PM PDT 24
Finished Jul 01 12:47:22 PM PDT 24
Peak memory 205520 kb
Host smart-f9b3b713-9928-41f0-96e8-ba446949b2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739298555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
739298555
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.31074424
Short name T981
Test name
Test status
Simulation time 285887062 ps
CPU time 2.19 seconds
Started Jul 01 12:47:14 PM PDT 24
Finished Jul 01 12:47:17 PM PDT 24
Peak memory 223896 kb
Host smart-a53b2f52-e50f-45c7-b8fa-b41e90371764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31074424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.31074424
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2641957710
Short name T763
Test name
Test status
Simulation time 20088638 ps
CPU time 0.83 seconds
Started Jul 01 12:47:10 PM PDT 24
Finished Jul 01 12:47:12 PM PDT 24
Peak memory 206504 kb
Host smart-1a02133c-54b1-4043-afc2-400f1db3f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641957710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2641957710
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2330497867
Short name T527
Test name
Test status
Simulation time 15769671268 ps
CPU time 155.54 seconds
Started Jul 01 12:47:17 PM PDT 24
Finished Jul 01 12:49:54 PM PDT 24
Peak memory 251788 kb
Host smart-e87e1fe1-b39d-421d-be58-ede517d6808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330497867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2330497867
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4293138007
Short name T240
Test name
Test status
Simulation time 29479108377 ps
CPU time 354.95 seconds
Started Jul 01 12:47:17 PM PDT 24
Finished Jul 01 12:53:13 PM PDT 24
Peak memory 272268 kb
Host smart-4548938e-bf90-4a76-bcab-657f48310215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293138007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4293138007
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3825835155
Short name T943
Test name
Test status
Simulation time 2107142473 ps
CPU time 13.34 seconds
Started Jul 01 12:47:19 PM PDT 24
Finished Jul 01 12:47:34 PM PDT 24
Peak memory 233732 kb
Host smart-58719d72-a57e-4e82-8209-7b026b5c853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825835155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3825835155
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1096630734
Short name T476
Test name
Test status
Simulation time 13943425565 ps
CPU time 58.96 seconds
Started Jul 01 12:47:20 PM PDT 24
Finished Jul 01 12:48:23 PM PDT 24
Peak memory 254444 kb
Host smart-df002c1e-974b-4f25-b09b-3ae5294ccedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096630734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1096630734
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.491649131
Short name T966
Test name
Test status
Simulation time 283216762 ps
CPU time 4.15 seconds
Started Jul 01 12:47:13 PM PDT 24
Finished Jul 01 12:47:19 PM PDT 24
Peak memory 224348 kb
Host smart-255ed5d2-5d5a-4178-8bec-663c6357cfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491649131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.491649131
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.64108353
Short name T980
Test name
Test status
Simulation time 9122091261 ps
CPU time 65.2 seconds
Started Jul 01 12:47:15 PM PDT 24
Finished Jul 01 12:48:21 PM PDT 24
Peak memory 224596 kb
Host smart-2e853eaf-0c54-410c-9e0c-524518fed8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64108353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.64108353
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2575398619
Short name T449
Test name
Test status
Simulation time 2006591296 ps
CPU time 5.53 seconds
Started Jul 01 12:47:14 PM PDT 24
Finished Jul 01 12:47:21 PM PDT 24
Peak memory 232652 kb
Host smart-0c21740b-0e9b-4ad4-a727-2ce01f10a5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575398619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2575398619
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1797924649
Short name T746
Test name
Test status
Simulation time 2759065395 ps
CPU time 10.36 seconds
Started Jul 01 12:47:16 PM PDT 24
Finished Jul 01 12:47:28 PM PDT 24
Peak memory 234524 kb
Host smart-ab528a9e-5da7-4ffc-bebc-574884548e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797924649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1797924649
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.208793607
Short name T635
Test name
Test status
Simulation time 1060843905 ps
CPU time 8.4 seconds
Started Jul 01 12:47:18 PM PDT 24
Finished Jul 01 12:47:28 PM PDT 24
Peak memory 219024 kb
Host smart-0dbc4521-62b8-4374-8094-0d4be8a51b99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=208793607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.208793607
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1676005117
Short name T1004
Test name
Test status
Simulation time 221640703170 ps
CPU time 474.29 seconds
Started Jul 01 12:47:18 PM PDT 24
Finished Jul 01 12:55:14 PM PDT 24
Peak memory 273780 kb
Host smart-20534074-2859-4f9d-a96b-d598c813babe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676005117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1676005117
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2107643158
Short name T458
Test name
Test status
Simulation time 3531467650 ps
CPU time 14.07 seconds
Started Jul 01 12:47:14 PM PDT 24
Finished Jul 01 12:47:30 PM PDT 24
Peak memory 216684 kb
Host smart-f17aad33-8f5f-43f0-b636-9072edf8145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107643158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2107643158
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4250361662
Short name T372
Test name
Test status
Simulation time 351843852 ps
CPU time 2.77 seconds
Started Jul 01 12:47:12 PM PDT 24
Finished Jul 01 12:47:16 PM PDT 24
Peak memory 216192 kb
Host smart-7b578f17-82cd-4f8a-bf97-374b86e10a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250361662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4250361662
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.815711187
Short name T7
Test name
Test status
Simulation time 38385011 ps
CPU time 1.15 seconds
Started Jul 01 12:47:13 PM PDT 24
Finished Jul 01 12:47:16 PM PDT 24
Peak memory 208004 kb
Host smart-48aa3ea7-deae-4b47-ad01-a0295a1da5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815711187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.815711187
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.824528499
Short name T872
Test name
Test status
Simulation time 28351912 ps
CPU time 0.83 seconds
Started Jul 01 12:47:14 PM PDT 24
Finished Jul 01 12:47:17 PM PDT 24
Peak memory 205964 kb
Host smart-634245c5-6bcf-4d45-8898-003d4c64cecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824528499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.824528499
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3951846532
Short name T698
Test name
Test status
Simulation time 397170698 ps
CPU time 3.61 seconds
Started Jul 01 12:47:14 PM PDT 24
Finished Jul 01 12:47:19 PM PDT 24
Peak memory 224480 kb
Host smart-c41fe845-10d5-412d-895b-90bd687fc661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951846532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3951846532
Directory /workspace/9.spi_device_upload/latest
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