Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2805154	1			T1	7468		T2	12807		T3	20464
all_values[1]	2805154	1			T1	7468		T2	12807		T3	20464
all_values[2]	2805154	1			T1	7468		T2	12807		T3	20464
all_values[3]	2805154	1			T1	7468		T2	12807		T3	20464
all_values[4]	2805154	1			T1	7468		T2	12807		T3	20464
all_values[5]	2805154	1			T1	7468		T2	12807		T3	20464
all_values[6]	2805154	1			T1	7468		T2	12807		T3	20464
all_values[7]	2805154	1			T1	7468		T2	12807		T3	20464

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22197806

1

T1

59744

T2

102456

T3

163712

auto[1]

243426

1

T14

2111

T17

70

T19

10314

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22413832

1

T1

59744

T2

102431

T3

163672

auto[1]

27400

1

T2

25

T3

40

T6

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2763071	1			T1	7468		T2	12798		T3	20444
all_values[0]	auto[0]	auto[1]	13181	1			T2	9		T3	20		T14	79
all_values[0]	auto[1]	auto[0]	28559	1			T14	1		T17	6		T19	2052
all_values[0]	auto[1]	auto[1]	343	1			T17	4		T19	4		T21	4
all_values[1]	auto[0]	auto[0]	2782573	1			T1	7468		T2	12798		T3	20444
all_values[1]	auto[0]	auto[1]	8491	1			T2	9		T3	20		T14	15
all_values[1]	auto[1]	auto[0]	13905	1			T14	5		T17	1		T19	2050
all_values[1]	auto[1]	auto[1]	185	1			T14	2		T17	1		T19	7
all_values[2]	auto[0]	auto[0]	2783715	1			T1	7468		T2	12800		T3	20464
all_values[2]	auto[0]	auto[1]	3157	1			T2	7		T14	3		T15	46
all_values[2]	auto[1]	auto[0]	18038	1			T14	1017		T17	3		T19	4
all_values[2]	auto[1]	auto[1]	244	1			T14	17		T17	5		T19	2
all_values[3]	auto[0]	auto[0]	2772865	1			T1	7468		T2	12807		T3	20464
all_values[3]	auto[0]	auto[1]	178	1			T14	5		T17	2		T19	2
all_values[3]	auto[1]	auto[0]	31926	1			T14	5		T17	7		T19	2053
all_values[3]	auto[1]	auto[1]	185	1			T14	5		T17	4		T19	7
all_values[4]	auto[0]	auto[0]	2768052	1			T1	7468		T2	12807		T3	20464
all_values[4]	auto[0]	auto[1]	186	1			T6	1		T14	3		T55	2
all_values[4]	auto[1]	auto[0]	36712	1			T14	2		T17	3		T19	2053
all_values[4]	auto[1]	auto[1]	204	1			T14	4		T17	4		T19	7
all_values[5]	auto[0]	auto[0]	2751142	1			T1	7468		T2	12807		T3	20464
all_values[5]	auto[0]	auto[1]	150	1			T14	2		T17	6		T19	1
all_values[5]	auto[1]	auto[0]	53698	1			T14	1030		T17	9		T19	3
all_values[5]	auto[1]	auto[1]	164	1			T14	5		T19	5		T20	1
all_values[6]	auto[0]	auto[0]	2783755	1			T1	7468		T2	12807		T3	20464
all_values[6]	auto[0]	auto[1]	191	1			T14	1		T17	3		T19	8
all_values[6]	auto[1]	auto[0]	21040	1			T14	9		T17	6		T19	2050
all_values[6]	auto[1]	auto[1]	168	1			T14	1		T17	5		T19	5
all_values[7]	auto[0]	auto[0]	2766920	1			T1	7468		T2	12807		T3	20464
all_values[7]	auto[0]	auto[1]	179	1			T14	2		T17	2		T19	3
all_values[7]	auto[1]	auto[0]	37861	1			T14	8		T17	9		T19	8
all_values[7]	auto[1]	auto[1]	194	1			T17	3		T19	4		T20	3