Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34086	1			T2	52		T3	18		T7	2
auto[SpiFlashAddrCfg]	7743	1			T2	19		T3	4		T12	35
auto[SpiFlashAddr3b]	9512	1			T2	19		T3	12		T4	2
auto[SpiFlashAddr4b]	7769	1			T2	14		T3	10		T6	1

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34186

1

T2

59

T3

27

T4

2

auto[1]

24924

1

T2

45

T3

17

T7

8

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31138

1

T2

52

T3

26

T6

1

auto[1]

27972

1

T2

52

T3

18

T4

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39053	1			T2	59		T3	22		T7	2
values[1]	1121	1			T2	9		T12	4		T13	1
values[2]	1512	1			T2	2		T12	5		T39	4
values[3]	1514	1			T2	2		T3	3		T12	9
values[4]	1505	1			T2	2		T3	2		T12	12
values[5]	1487	1			T2	4		T3	1		T4	2
values[6]	1488	1			T2	6		T3	1		T12	12
values[7]	1513	1			T2	3		T3	3		T12	3
values[8]	9917	1			T2	17		T3	12		T6	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29888

1

T3

44

T7

8

T8

16

auto[1]

29222

1

T2

104

T4

2

T6

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55809

1

T2

93

T3

39

T4

2

write

3301

1

T2

11

T3

5

T8

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19818

1

T2

40

T3

16

T4

2

valids[0x1]

39292

1

T2

64

T3

28

T7

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1659	1			T2	4		T3	1		T8	2
internal_process_ops[0x5a]	1581	1			T2	3		T12	5		T13	1
internal_process_ops[0x05]	19682	1			T2	9		T3	4		T8	4
internal_process_ops[0x35]	1646	1			T2	4		T3	3		T12	2
internal_process_ops[0x15]	1624	1			T2	4		T3	2		T12	7
internal_process_ops[0x03]	1015	1			T8	2		T12	4		T14	5
internal_process_ops[0x0b]	1055	1			T3	2		T12	3		T13	2
internal_process_ops[0x3b]	1050	1			T2	1		T3	3		T6	1
internal_process_ops[0x6b]	1096	1			T2	1		T12	11		T13	3
internal_process_ops[0xbb]	1029	1			T2	1		T4	2		T7	2
internal_process_ops[0xeb]	1125	1			T3	2		T12	12		T13	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57508

1

T2

102

T3

41

T4

2

auto[1]

1602

1

T2

2

T3

3

T12

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56700

1

T2

101

T3

41

T4

2

auto[1]

2410

1

T2

3

T3

3

T12

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10223

1

T3

7

T8

6

T11

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5544

1

T3

9

T7

2

T12

18

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2071

1

T3

3

T12

16

T13

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1723

1

T3

1

T12

18

T14

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2628

1

T3

7

T12

17

T13

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2194

1

T3

3

T7

4

T12

23

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2076

1

T3

7

T8

4

T12

24

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1840

1

T3

2

T7

2

T12

14

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

98

1

T8

4

T12

4

T16

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T14

1

T15

1

T43

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

84

1

T3

2

T12

2

T14

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

103

1

T15

3

T41

1

T43

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

114

1

T39

2

T14

4

T28

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

88

1

T15

2

T83

4

T161

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

90

1

T15

2

T42

2

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

104

1

T12

1

T13

3

T15

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

130

1

T12

1

T13

1

T14

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

90

1

T3

2

T12

1

T14

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

114

1

T14

1

T15

1

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

101

1

T12

1

T15

1

T40

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

98

1

T8

2

T15

1

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

97

1

T3

1

T12

1

T14

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

89

1

T37

2

T43

1

T34

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

91

1

T14

5

T15

2

T37

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10454

1

T2

32

T26

74

T15

46

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7016

1

T2

14

T26

94

T15

33

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1568

1

T2

3

T26

11

T15

9

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1571

1

T2

16

T26

8

T15

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1953

1

T2

12

T4

2

T26

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1892

1

T2

6

T26

15

T15

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1572

1

T2

7

T6

1

T26

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1484

1

T2

3

T26

11

T15

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T2

2

T26

2

T16

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

125

1

T15

1

T75

8

T162

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

126

1

T2

4

T26

1

T76

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

105

1

T26

2

T15

1

T46

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

98

1

T26

5

T46

4

T75

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

102

1

T47

2

T75

1

T76

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

108

1

T46

2

T47

2

T69

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

106

1

T26

1

T15

2

T46

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

104

1

T2

1

T15

2

T75

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

81

1

T26

1

T46

2

T47

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

119

1

T15

2

T75

2

T76

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

106

1

T15

1

T47

3

T16

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

117

1

T2

2

T47

3

T16

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

91

1

T15

3

T47

2

T16

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T46

1

T75

3

T76

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T2

2

T46

1

T75

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3984	1			T3	5		T11	8		T12	37
auto[0]	values[0]	valids[0x1]	14770	1			T3	17		T7	2		T8	12
auto[0]	values[1]	valids[0x1]	543	1			T12	4		T13	1		T14	6
auto[0]	values[2]	valids[0x0]	557	1			T12	4		T39	4		T14	5
auto[0]	values[2]	valids[0x1]	302	1			T12	1		T14	2		T15	5
auto[0]	values[3]	valids[0x0]	552	1			T3	1		T12	6		T14	2
auto[0]	values[3]	valids[0x1]	355	1			T3	2		T12	3		T14	2
auto[0]	values[4]	valids[0x0]	590	1			T3	2		T12	11		T13	1
auto[0]	values[4]	valids[0x1]	284	1			T12	1		T15	5		T37	2
auto[0]	values[5]	valids[0x0]	515	1			T12	10		T13	1		T14	3
auto[0]	values[5]	valids[0x1]	327	1			T3	1		T12	6		T14	1
auto[0]	values[6]	valids[0x0]	552	1			T3	1		T12	8		T13	2
auto[0]	values[6]	valids[0x1]	293	1			T12	4		T13	1		T39	6
auto[0]	values[7]	valids[0x0]	553	1			T3	1		T12	2		T14	6
auto[0]	values[7]	valids[0x1]	279	1			T3	2		T12	1		T14	1
auto[0]	values[8]	valids[0x0]	3426	1			T3	6		T7	2		T8	2
auto[0]	values[8]	valids[0x1]	2006	1			T3	6		T7	4		T8	2
auto[1]	values[0]	valids[0x0]	4180	1			T2	22		T26	39		T15	27
auto[1]	values[0]	valids[0x1]	16119	1			T2	37		T26	146		T15	69
auto[1]	values[1]	valids[0x1]	578	1			T2	9		T26	6		T15	15
auto[1]	values[2]	valids[0x0]	383	1			T15	3		T46	6		T47	6
auto[1]	values[2]	valids[0x1]	270	1			T2	2		T26	3		T15	4
auto[1]	values[3]	valids[0x0]	379	1			T2	2		T26	1		T15	1
auto[1]	values[3]	valids[0x1]	228	1			T15	3		T46	2		T47	3
auto[1]	values[4]	valids[0x0]	362	1			T26	6		T15	7		T46	6
auto[1]	values[4]	valids[0x1]	269	1			T2	2		T26	5		T15	3
auto[1]	values[5]	valids[0x0]	366	1			T2	2		T4	2		T26	1
auto[1]	values[5]	valids[0x1]	279	1			T2	2		T26	9		T46	4
auto[1]	values[6]	valids[0x0]	386	1			T2	6		T26	5		T15	1
auto[1]	values[6]	valids[0x1]	257	1			T26	1		T46	1		T47	4
auto[1]	values[7]	valids[0x0]	419	1			T26	2		T15	3		T47	8
auto[1]	values[7]	valids[0x1]	262	1			T2	3		T15	2		T46	2
auto[1]	values[8]	valids[0x0]	2614	1			T2	8		T6	1		T26	16
auto[1]	values[8]	valids[0x1]	1871	1			T2	9		T26	12		T15	8