Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3236944

1

T2

3165

T3

4142

T4

19856

auto[1]

33932

1

T2

4

T3

4

T12

82

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

760249

1

T2

31

T3

15

T4

19856

auto[1]

2510627

1

T2

3138

T3

4131

T12

14796

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	593139	1			T2	512		T3	2207		T4	2612
auto[524288:1048575]	366725	1			T2	278		T3	259		T4	2
auto[1048576:1572863]	407432	1			T2	11		T3	1550		T4	10272
auto[1572864:2097151]	420545	1			T2	5		T3	1		T4	3592
auto[2097152:2621439]	365256	1			T3	128		T4	3377		T12	181
auto[2621440:3145727]	373848	1			T2	1587		T12	8		T13	4
auto[3145728:3670015]	386866	1			T2	258		T3	1		T12	526
auto[3670016:4194303]	357065	1			T2	518		T4	1		T12	325

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2545930

1

T2

3169

T3

4146

T4

15

auto[1]

724946

1

T4

19841

T6

58

T11

3198

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2823065

1

T2

2652

T3

4146

T4

19856

auto[1]

447811

1

T2

517

T11

1612

T12

34

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	137157	1			T3	4		T4	2612		T6	2
auto[0]	auto[0]	auto[0:524287]	auto[1]	385844	1			T2	512		T3	2199		T12	1860
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	63946	1			T2	8		T3	3		T4	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	248741	1			T2	269		T3	256		T13	256
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	103051	1			T2	4		T3	3		T4	10272
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	245725	1			T2	6		T3	1547		T12	3320
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	105824	1			T2	3		T3	1		T4	3592
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	257898	1			T2	1		T12	8713		T14	2831
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	92335	1			T4	3377		T12	45		T13	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	220828	1			T3	128		T12	128		T14	128
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	80974	1			T2	4		T12	6		T13	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	233802	1			T2	1581		T14	257		T26	258
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	73685	1			T2	2		T3	1		T12	10
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	230298	1			T2	256		T12	516		T13	464
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	82275	1			T2	2		T4	1		T12	40
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	233006	1			T12	259		T15	1217		T46	2404
auto[0]	auto[1]	auto[0:524287]	auto[0]	2147	1			T13	4		T14	1		T26	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	63071	1			T26	668		T46	1107		T47	1717
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	3000	1			T2	1		T15	2		T46	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	45839	1			T46	512		T37	2928		T16	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	565	1			T12	5		T14	2		T15	8
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	54192	1			T14	1		T15	2446		T42	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	4769	1			T11	1612		T47	10		T75	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	48992	1			T47	2169		T178	512		T48	13
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2661	1			T26	2		T15	2		T46	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	46282	1			T37	5		T76	431		T183	2092
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1311	1			T14	1		T15	2		T46	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53108	1			T14	512		T15	1		T46	257
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1191	1			T14	3		T26	3		T15	6
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	76862	1			T26	1		T15	3077		T42	512
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1016	1			T2	4		T12	11		T13	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	36549	1			T2	512		T14	1		T15	3
auto[1]	auto[0]	auto[0:524287]	auto[0]	560	1			T3	3		T12	6		T13	7
auto[1]	auto[0]	auto[0:524287]	auto[1]	3085	1			T3	1		T14	16		T26	12
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	434	1			T12	12		T14	1		T15	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4247	1			T14	13		T15	7		T46	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	421	1			T2	1		T12	3		T14	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2532	1			T14	6		T15	3		T46	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	409	1			T2	1		T12	20		T13	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2180	1			T15	2		T46	7		T37	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	485	1			T12	8		T26	4		T15	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1830	1			T26	41		T15	1		T46	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	449	1			T2	1		T14	1		T26	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3293	1			T2	1		T14	14		T26	28
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	353	1			T13	3		T15	5		T46	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3751	1			T13	48		T15	6		T46	29
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	428	1			T12	15		T15	2		T41	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3219	1			T15	6		T41	1		T40	6
auto[1]	auto[1]	auto[0:524287]	auto[0]	99	1			T46	2		T75	3		T48	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	1176	1			T46	1		T75	32		T48	17
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	78	1			T12	2		T37	5		T16	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	440	1			T37	3		T16	1		T178	27
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	97	1			T12	14		T14	1		T15	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	849	1			T14	5		T15	3		T42	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	91	1			T48	4		T162	1		T20	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	382	1			T48	12		T162	8		T20	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	151	1			T47	3		T37	2		T76	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	684	1			T37	1		T76	39		T183	36
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	98	1			T12	2		T15	1		T46	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	813	1			T76	41		T178	2		T156	16
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	108	1			T26	1		T15	1		T75	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	618	1			T15	1		T75	39		T76	11
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	81	1			T14	1		T162	2		T144	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	491	1			T14	19		T162	17		T144	10

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2082097	1			T2	2648		T3	4142		T4	15
auto[0]	auto[0]	auto[1]	713292	1			T4	19841		T6	58		T11	1587
auto[0]	auto[1]	auto[0]	430586	1			T2	517		T11	1		T12	16
auto[0]	auto[1]	auto[1]	10969	1			T11	1611		T46	1		T42	1
auto[1]	auto[0]	auto[0]	27118	1			T2	4		T3	4		T12	54
auto[1]	auto[0]	auto[1]	558	1			T12	10		T13	3		T26	3
auto[1]	auto[1]	auto[0]	6129	1			T12	17		T14	25		T26	1
auto[1]	auto[1]	auto[1]	127	1			T12	1		T14	1		T15	1