Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2805154	1			T1	7468		T2	12807		T3	20464
all_pins[1]	2805154	1			T1	7468		T2	12807		T3	20464
all_pins[2]	2805154	1			T1	7468		T2	12807		T3	20464
all_pins[3]	2805154	1			T1	7468		T2	12807		T3	20464
all_pins[4]	2805154	1			T1	7468		T2	12807		T3	20464
all_pins[5]	2805154	1			T1	7468		T2	12807		T3	20464
all_pins[6]	2805154	1			T1	7468		T2	12807		T3	20464
all_pins[7]	2805154	1			T1	7468		T2	12807		T3	20464

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22416225	1			T1	59744		T2	102456		T3	163712
values[0x1]	25007	1			T14	149		T17	26		T19	2076
transitions[0x0=>0x1]	23058	1			T14	145		T17	21		T19	2065
transitions[0x1=>0x0]	23068	1			T14	145		T17	21		T19	2066

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2804783	1			T1	7468		T2	12807		T3	20464
all_pins[0]	values[0x1]	371	1			T17	4		T19	4		T21	4
all_pins[0]	transitions[0x0=>0x1]	310	1			T17	4		T19	3		T21	3
all_pins[0]	transitions[0x1=>0x0]	136	1			T14	2		T17	1		T19	6
all_pins[1]	values[0x0]	2804957	1			T1	7468		T2	12807		T3	20464
all_pins[1]	values[0x1]	197	1			T14	2		T17	1		T19	7
all_pins[1]	transitions[0x0=>0x1]	137	1			T14	1		T17	1		T19	6
all_pins[1]	transitions[0x1=>0x0]	193	1			T14	17		T17	5		T19	1
all_pins[2]	values[0x0]	2804901	1			T1	7468		T2	12807		T3	20464
all_pins[2]	values[0x1]	253	1			T14	18		T17	5		T19	2
all_pins[2]	transitions[0x0=>0x1]	194	1			T14	17		T17	4		T19	2
all_pins[2]	transitions[0x1=>0x0]	126	1			T14	4		T17	3		T19	7
all_pins[3]	values[0x0]	2804969	1			T1	7468		T2	12807		T3	20464
all_pins[3]	values[0x1]	185	1			T14	5		T17	4		T19	7
all_pins[3]	transitions[0x0=>0x1]	127	1			T14	4		T17	1		T19	4
all_pins[3]	transitions[0x1=>0x0]	146	1			T14	3		T17	1		T19	4
all_pins[4]	values[0x0]	2804950	1			T1	7468		T2	12807		T3	20464
all_pins[4]	values[0x1]	204	1			T14	4		T17	4		T19	7
all_pins[4]	transitions[0x0=>0x1]	160	1			T14	3		T17	4		T19	6
all_pins[4]	transitions[0x1=>0x0]	2702	1			T14	118		T19	4		T20	857
all_pins[5]	values[0x0]	2802408	1			T1	7468		T2	12807		T3	20464
all_pins[5]	values[0x1]	2746	1			T14	119		T19	5		T20	857
all_pins[5]	transitions[0x0=>0x1]	1174	1			T14	119		T19	3		T20	15
all_pins[5]	transitions[0x1=>0x0]	19285	1			T14	1		T17	5		T19	2038
all_pins[6]	values[0x0]	2784297	1			T1	7468		T2	12807		T3	20464
all_pins[6]	values[0x1]	20857	1			T14	1		T17	5		T19	2040
all_pins[6]	transitions[0x0=>0x1]	20808	1			T14	1		T17	5		T19	2039
all_pins[6]	transitions[0x1=>0x0]	145	1			T17	3		T19	3		T20	3
all_pins[7]	values[0x0]	2804960	1			T1	7468		T2	12807		T3	20464
all_pins[7]	values[0x1]	194	1			T17	3		T19	4		T20	3
all_pins[7]	transitions[0x0=>0x1]	148	1			T17	2		T19	2		T20	3
all_pins[7]	transitions[0x1=>0x0]	335	1			T17	3		T19	3		T21	4