Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17811

1

T3

27

T8

16

T11

8

auto[1]

12077

1

T3

17

T7

8

T12

77

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3901	1			T3	24		T7	8		T11	8
values[1]	3469	1			T3	20		T15	70		T42	22
values[2]	4107	1			T12	40		T39	24		T14	34
values[3]	3333	1			T12	40		T13	20		T14	20
values[4]	3915	1			T8	16		T12	20		T14	20
values[5]	4055	1			T12	20		T14	26		T15	43
values[6]	3487	1			T12	40		T27	4		T15	42
values[7]	3621	1			T14	45		T15	62		T41	25

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3070	1			T12	40		T14	35		T23	26
values[1]	3612	1			T12	20		T39	24		T14	34
values[2]	4010	1			T12	40		T13	20		T27	4
values[3]	4131	1			T3	24		T11	8		T12	40
values[4]	4177	1			T14	40		T15	50		T53	12
values[5]	3790	1			T8	16		T14	45		T15	20
values[6]	3527	1			T3	20		T7	8		T12	20
values[7]	3571	1			T12	20		T13	20		T14	46

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	332	1			T14	25		T48	12		T83	10
auto[0]	values[0]	values[1]	151	1			T54	6		T40	11		T217	12
auto[0]	values[0]	values[2]	138	1			T13	9		T144	12		T31	7
auto[0]	values[0]	values[3]	363	1			T3	14		T11	8		T15	13
auto[0]	values[0]	values[4]	285	1			T14	13		T43	14		T218	2
auto[0]	values[0]	values[5]	405	1			T37	11		T111	2		T83	11
auto[0]	values[0]	values[6]	286	1			T219	25		T144	23		T202	10
auto[0]	values[0]	values[7]	193	1			T12	9		T43	6		T180	17
auto[0]	values[1]	values[0]	149	1			T42	11		T43	13		T144	9
auto[0]	values[1]	values[1]	219	1			T15	20		T220	50		T170	15
auto[0]	values[1]	values[2]	180	1			T40	14		T34	26		T174	9
auto[0]	values[1]	values[3]	303	1			T15	27		T43	27		T48	10
auto[0]	values[1]	values[4]	358	1			T31	12		T221	68		T222	10
auto[0]	values[1]	values[5]	206	1			T48	11		T83	12		T223	53
auto[0]	values[1]	values[6]	423	1			T3	13		T48	31		T34	8
auto[0]	values[1]	values[7]	257	1			T194	12		T224	12		T145	14
auto[0]	values[2]	values[0]	181	1			T12	12		T209	12		T205	8
auto[0]	values[2]	values[1]	340	1			T39	24		T14	24		T216	14
auto[0]	values[2]	values[2]	385	1			T12	16		T195	14		T48	12
auto[0]	values[2]	values[3]	667	1			T28	22		T37	9		T48	14
auto[0]	values[2]	values[4]	210	1			T15	15		T17	15		T48	9
auto[0]	values[2]	values[5]	193	1			T40	8		T83	11		T225	2
auto[0]	values[2]	values[6]	148	1			T15	19		T16	6		T145	12
auto[0]	values[2]	values[7]	388	1			T15	6		T34	11		T144	14
auto[0]	values[3]	values[0]	210	1			T34	11		T144	35		T226	26
auto[0]	values[3]	values[1]	290	1			T212	2		T48	43		T21	14
auto[0]	values[3]	values[2]	236	1			T12	13		T48	10		T71	8
auto[0]	values[3]	values[3]	177	1			T14	13		T126	23		T214	6
auto[0]	values[3]	values[4]	242	1			T34	24		T182	13		T145	7
auto[0]	values[3]	values[5]	224	1			T42	9		T48	26		T180	15
auto[0]	values[3]	values[6]	308	1			T12	12		T145	5		T125	13
auto[0]	values[3]	values[7]	393	1			T13	15		T42	14		T43	13
auto[0]	values[4]	values[0]	375	1			T23	26		T40	10		T174	21
auto[0]	values[4]	values[1]	298	1			T12	11		T17	16		T161	13
auto[0]	values[4]	values[2]	311	1			T15	14		T83	13		T155	20
auto[0]	values[4]	values[3]	378	1			T17	12		T180	14		T31	11
auto[0]	values[4]	values[4]	342	1			T15	15		T227	8		T21	9
auto[0]	values[4]	values[5]	276	1			T8	16		T21	17		T31	7
auto[0]	values[4]	values[6]	226	1			T208	10		T153	18		T181	6
auto[0]	values[4]	values[7]	184	1			T14	8		T197	35		T190	14
auto[0]	values[5]	values[0]	196	1			T48	13		T180	14		T157	10
auto[0]	values[5]	values[1]	209	1			T15	15		T144	26		T228	2
auto[0]	values[5]	values[2]	425	1			T83	18		T182	8		T145	7
auto[0]	values[5]	values[3]	211	1			T12	15		T229	8		T125	12
auto[0]	values[5]	values[4]	213	1			T230	20		T83	11		T231	24
auto[0]	values[5]	values[5]	383	1			T68	16		T84	10		T161	18
auto[0]	values[5]	values[6]	256	1			T37	10		T232	20		T201	15
auto[0]	values[5]	values[7]	297	1			T14	8		T15	15		T31	13
auto[0]	values[6]	values[0]	158	1			T12	10		T15	14		T210	6
auto[0]	values[6]	values[1]	430	1			T173	4		T174	11		T197	15
auto[0]	values[6]	values[2]	308	1			T27	4		T15	10		T16	17
auto[0]	values[6]	values[3]	217	1			T12	5		T180	29		T144	11
auto[0]	values[6]	values[4]	304	1			T53	12		T233	8		T145	52
auto[0]	values[6]	values[5]	215	1			T21	11		T182	14		T197	49
auto[0]	values[6]	values[6]	268	1			T42	6		T31	18		T145	13
auto[0]	values[6]	values[7]	242	1			T37	15		T17	11		T197	11
auto[0]	values[7]	values[0]	184	1			T34	14		T180	8		T202	20
auto[0]	values[7]	values[1]	246	1			T21	10		T144	23		T234	16
auto[0]	values[7]	values[2]	302	1			T15	13		T41	13		T17	11
auto[0]	values[7]	values[3]	319	1			T37	22		T235	14		T31	7
auto[0]	values[7]	values[4]	298	1			T236	8		T83	10		T144	13
auto[0]	values[7]	values[5]	350	1			T14	36		T15	9		T21	11
auto[0]	values[7]	values[6]	218	1			T161	14		T145	15		T201	10
auto[0]	values[7]	values[7]	332	1			T15	14		T40	14		T48	14
auto[1]	values[0]	values[0]	215	1			T14	10		T48	8		T83	10
auto[1]	values[0]	values[1]	231	1			T40	16		T237	9		T238	4
auto[1]	values[0]	values[2]	176	1			T13	11		T144	22		T31	13
auto[1]	values[0]	values[3]	193	1			T3	10		T15	7		T48	10
auto[1]	values[0]	values[4]	292	1			T14	27		T43	10		T44	14
auto[1]	values[0]	values[5]	260	1			T37	10		T83	9		T20	11
auto[1]	values[0]	values[6]	237	1			T7	8		T144	6		T202	10
auto[1]	values[0]	values[7]	144	1			T12	11		T43	17		T180	3
auto[1]	values[1]	values[0]	147	1			T42	11		T43	7		T144	11
auto[1]	values[1]	values[1]	79	1			T15	8		T73	6		T170	5
auto[1]	values[1]	values[2]	107	1			T40	6		T34	12		T174	11
auto[1]	values[1]	values[3]	232	1			T15	15		T43	3		T48	30
auto[1]	values[1]	values[4]	280	1			T239	14		T31	8		T222	10
auto[1]	values[1]	values[5]	91	1			T48	9		T83	8		T223	10
auto[1]	values[1]	values[6]	180	1			T3	7		T48	8		T34	15
auto[1]	values[1]	values[7]	258	1			T145	10		T206	8		T201	12
auto[1]	values[2]	values[0]	112	1			T12	8		T174	7		T144	15
auto[1]	values[2]	values[1]	101	1			T14	10		T182	10		T240	10
auto[1]	values[2]	values[2]	273	1			T12	4		T48	100		T144	9
auto[1]	values[2]	values[3]	189	1			T37	15		T48	8		T161	7
auto[1]	values[2]	values[4]	289	1			T15	15		T17	5		T48	11
auto[1]	values[2]	values[5]	312	1			T40	14		T83	9		T206	8
auto[1]	values[2]	values[6]	166	1			T15	10		T16	14		T145	12
auto[1]	values[2]	values[7]	153	1			T15	15		T34	17		T144	16
auto[1]	values[3]	values[0]	109	1			T34	11		T144	8		T241	7
auto[1]	values[3]	values[1]	192	1			T48	8		T21	6		T180	10
auto[1]	values[3]	values[2]	199	1			T12	7		T48	10		T83	9
auto[1]	values[3]	values[3]	198	1			T14	7		T126	4		T214	14
auto[1]	values[3]	values[4]	97	1			T34	11		T182	7		T145	13
auto[1]	values[3]	values[5]	154	1			T42	20		T48	6		T242	12
auto[1]	values[3]	values[6]	132	1			T12	8		T145	15		T125	7
auto[1]	values[3]	values[7]	172	1			T13	5		T42	18		T43	8
auto[1]	values[4]	values[0]	116	1			T40	10		T174	6		T127	9
auto[1]	values[4]	values[1]	165	1			T12	9		T17	4		T161	7
auto[1]	values[4]	values[2]	160	1			T15	7		T83	7		T31	18
auto[1]	values[4]	values[3]	301	1			T17	8		T180	9		T31	9
auto[1]	values[4]	values[4]	346	1			T15	5		T21	27		T144	7
auto[1]	values[4]	values[5]	175	1			T21	24		T31	60		T149	8
auto[1]	values[4]	values[6]	95	1			T70	8		T201	9		T241	15
auto[1]	values[4]	values[7]	167	1			T14	12		T197	14		T190	10
auto[1]	values[5]	values[0]	337	1			T48	19		T180	8		T126	52
auto[1]	values[5]	values[1]	232	1			T15	8		T144	7		T243	20
auto[1]	values[5]	values[2]	341	1			T83	22		T182	12		T145	13
auto[1]	values[5]	values[3]	87	1			T12	5		T125	21		T234	13
auto[1]	values[5]	values[4]	214	1			T83	9		T191	24		T244	6
auto[1]	values[5]	values[5]	271	1			T161	7		T182	7		T202	12
auto[1]	values[5]	values[6]	245	1			T37	10		T154	20		T201	13
auto[1]	values[5]	values[7]	138	1			T14	18		T15	5		T31	23
auto[1]	values[6]	values[0]	86	1			T12	10		T15	8		T245	10
auto[1]	values[6]	values[1]	276	1			T174	9		T197	50		T206	5
auto[1]	values[6]	values[2]	169	1			T15	10		T16	7		T34	8
auto[1]	values[6]	values[3]	154	1			T12	15		T180	9		T144	9
auto[1]	values[6]	values[4]	226	1			T145	10		T125	13		T201	10
auto[1]	values[6]	values[5]	109	1			T21	9		T182	6		T197	4
auto[1]	values[6]	values[6]	195	1			T42	19		T31	2		T145	9
auto[1]	values[6]	values[7]	130	1			T37	12		T17	9		T197	9
auto[1]	values[7]	values[0]	163	1			T34	20		T180	26		T202	10
auto[1]	values[7]	values[1]	153	1			T246	18		T21	10		T144	10
auto[1]	values[7]	values[2]	300	1			T15	7		T41	12		T17	16
auto[1]	values[7]	values[3]	142	1			T37	2		T31	13		T145	9
auto[1]	values[7]	values[4]	181	1			T83	10		T144	7		T31	13
auto[1]	values[7]	values[5]	166	1			T14	9		T15	11		T21	20
auto[1]	values[7]	values[6]	144	1			T161	6		T145	5		T201	10
auto[1]	values[7]	values[7]	123	1			T15	8		T40	12		T48	10