Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	442	1			T12	3		T14	1		T15	3
auto[ReadAddrCrossIntoMailbox]	283	1			T12	3		T14	1		T15	7
auto[ReadAddrCrossOutOfMailbox]	311	1			T12	3		T14	1		T15	3
auto[ReadAddrCrossAllMailbox]	221	1			T12	1		T13	1		T14	3
auto[ReadAddrOutsideMailbox]	3513	1			T3	7		T7	2		T8	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2285

1

T3

7

T7

1

T8

2

auto[1]

2485

1

T7

1

T8

2

T12

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	761	1			T8	2		T12	4		T14	5
read_ops[0x0b]	802	1			T3	2		T12	3		T13	2
read_ops[0x3b]	789	1			T3	3		T8	2		T12	7
read_ops[0x6b]	796	1			T12	11		T13	3		T39	2
read_ops[0xbb]	781	1			T7	2		T12	6		T13	2
read_ops[0xeb]	841	1			T3	2		T12	12		T13	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T83	1		T21	1		T182	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T12	1		T16	1		T83	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T48	1		T34	1		T202	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	40	1			T12	1		T15	2		T83	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T43	1		T48	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T15	1		T40	1		T48	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T48	1		T34	2		T83	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T180	1		T31	1		T202	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T8	1		T12	1		T14	4
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T8	1		T12	1		T14	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T40	1		T48	1		T34	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T48	1		T34	1		T144	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T15	1		T161	1		T240	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T15	1		T180	1		T144	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T17	1		T189	1		T126	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T12	1		T14	1		T16	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T48	3		T31	2		T189	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T13	1		T31	1		T206	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T3	2		T12	1		T14	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T12	1		T13	1		T14	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T210	1		T233	1		T20	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T15	1		T42	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T37	1		T20	1		T189	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T12	1		T14	1		T15	3
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T161	2		T174	1		T202	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T48	1		T83	1		T31	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T14	1		T161	1		T144	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T14	1		T83	1		T202	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T3	3		T8	1		T12	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T8	1		T12	4		T39	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T174	2		T206	1		T187	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T48	1		T31	2		T125	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T83	1		T144	1		T189	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T40	1		T145	1		T146	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	16	1			T12	1		T206	1		T190	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T15	1		T83	1		T182	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T42	1		T40	1		T126	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T12	1		T14	1		T34	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T12	5		T39	1		T14	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	328	1			T12	4		T13	3		T39	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T14	1		T43	1		T144	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T12	1		T15	2		T42	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T43	1		T48	1		T34	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T42	1		T83	1		T144	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T48	1		T34	1		T180	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T15	1		T42	1		T180	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T34	1		T83	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T34	1		T83	1		T240	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T7	1		T12	4		T14	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T7	1		T12	1		T13	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T144	1		T247	2		T202	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T12	1		T16	2		T48	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T21	1		T180	1		T144	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T12	1		T40	2		T206	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T42	1		T21	1		T144	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T12	1		T37	1		T180	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T144	3		T222	1		T248	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T15	1		T43	1		T48	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T3	2		T12	3		T13	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	331	1			T12	6		T39	1		T14	7