Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4089	1			T12	20		T13	40		T14	65
values[1]	3482	1			T8	16		T14	55		T28	22
values[2]	3567	1			T12	40		T14	34		T23	26
values[3]	3947	1			T3	44		T7	8		T12	20
values[4]	3104	1			T12	20		T15	20		T53	12
values[5]	3435	1			T12	60		T27	4		T15	43
values[6]	4307	1			T11	8		T39	24		T14	40
values[7]	3957	1			T12	20		T14	26		T15	90

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3647	1			T8	16		T12	40		T13	40
values[1]	3700	1			T3	24		T12	40		T15	20
values[2]	4344	1			T7	8		T11	8		T12	20
values[3]	3329	1			T14	40		T40	27		T212	2
values[4]	3728	1			T12	20		T39	24		T14	20
values[5]	3995	1			T3	20		T14	20		T15	71
values[6]	3537	1			T12	40		T15	48		T54	6
values[7]	3608	1			T12	20		T14	26		T15	43

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29116

1

T3

41

T7

8

T8

16

auto[1]

772

1

T3

3

T12

4

T13

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	385	1			T13	37		T15	29		T21	35
auto[0]	values[0]	values[1]	359	1			T12	19		T40	20		T83	19
auto[0]	values[0]	values[2]	901	1			T14	41		T15	22		T216	14
auto[0]	values[0]	values[3]	590	1			T182	20		T31	24		T221	68
auto[0]	values[0]	values[4]	490	1			T43	26		T246	16		T21	20
auto[0]	values[0]	values[5]	445	1			T14	20		T43	21		T180	20
auto[0]	values[0]	values[6]	215	1			T127	21		T249	24		T170	19
auto[0]	values[0]	values[7]	594	1			T48	67		T161	20		T31	89
auto[0]	values[1]	values[0]	450	1			T8	16		T14	34		T28	22
auto[0]	values[1]	values[1]	341	1			T182	24		T240	19		T189	21
auto[0]	values[1]	values[2]	777	1			T210	6		T44	10		T48	21
auto[0]	values[1]	values[3]	326	1			T83	20		T31	19		T181	6
auto[0]	values[1]	values[4]	532	1			T14	17		T42	25		T37	17
auto[0]	values[1]	values[5]	515	1			T15	40		T42	27		T174	20
auto[0]	values[1]	values[6]	206	1			T54	6		T31	18		T245	20
auto[0]	values[1]	values[7]	252	1			T206	23		T184	18		T128	29
auto[0]	values[2]	values[0]	665	1			T12	18		T14	34		T23	26
auto[0]	values[2]	values[1]	338	1			T236	8		T219	25		T21	19
auto[0]	values[2]	values[2]	391	1			T180	34		T144	33		T182	20
auto[0]	values[2]	values[3]	517	1			T71	8		T31	67		T202	20
auto[0]	values[2]	values[4]	266	1			T125	20		T234	47		T250	16
auto[0]	values[2]	values[5]	477	1			T37	21		T48	37		T83	37
auto[0]	values[2]	values[6]	396	1			T83	20		T84	10		T251	8
auto[0]	values[2]	values[7]	417	1			T12	19		T15	18		T252	145
auto[0]	values[3]	values[0]	315	1			T182	20		T253	20		T254	19
auto[0]	values[3]	values[1]	470	1			T3	21		T42	53		T48	20
auto[0]	values[3]	values[2]	401	1			T7	8		T232	20		T155	20
auto[0]	values[3]	values[3]	301	1			T17	20		T161	19		T255	14
auto[0]	values[3]	values[4]	591	1			T182	20		T197	65		T125	43
auto[0]	values[3]	values[5]	672	1			T3	20		T195	14		T34	23
auto[0]	values[3]	values[6]	505	1			T12	20		T37	25		T256	20
auto[0]	values[3]	values[7]	613	1			T153	18		T202	134		T257	8
auto[0]	values[4]	values[0]	398	1			T161	24		T182	42		T201	25
auto[0]	values[4]	values[1]	557	1			T15	20		T16	22		T34	37
auto[0]	values[4]	values[2]	375	1			T21	31		T180	22		T174	20
auto[0]	values[4]	values[3]	276	1			T212	2		T48	24		T258	12
auto[0]	values[4]	values[4]	254	1			T21	39		T259	22		T201	41
auto[0]	values[4]	values[5]	269	1			T53	12		T111	2		T247	6
auto[0]	values[4]	values[6]	534	1			T12	20		T40	20		T208	10
auto[0]	values[4]	values[7]	354	1			T180	20		T31	38		T145	20
auto[0]	values[5]	values[0]	433	1			T12	20		T192	20		T260	12
auto[0]	values[5]	values[1]	323	1			T12	20		T145	19		T206	79
auto[0]	values[5]	values[2]	427	1			T12	20		T15	21		T70	4
auto[0]	values[5]	values[3]	311	1			T31	49		T222	24		T261	12
auto[0]	values[5]	values[4]	553	1			T27	4		T15	20		T34	34
auto[0]	values[5]	values[5]	554	1			T43	20		T239	10		T262	20
auto[0]	values[5]	values[6]	497	1			T43	20		T48	30		T227	8
auto[0]	values[5]	values[7]	249	1			T161	20		T256	38		T263	10
auto[0]	values[6]	values[0]	470	1			T15	40		T37	24		T48	20
auto[0]	values[6]	values[1]	637	1			T40	22		T48	32		T34	20
auto[0]	values[6]	values[2]	541	1			T11	8		T240	19		T125	20
auto[0]	values[6]	values[3]	493	1			T14	40		T17	19		T48	110
auto[0]	values[6]	values[4]	388	1			T39	24		T217	12		T182	20
auto[0]	values[6]	values[5]	579	1			T43	22		T194	12		T73	4
auto[0]	values[6]	values[6]	551	1			T15	26		T37	23		T68	16
auto[0]	values[6]	values[7]	522	1			T15	21		T161	17		T202	20
auto[0]	values[7]	values[0]	444	1			T15	20		T41	22		T40	24
auto[0]	values[7]	values[1]	573	1			T17	47		T144	32		T197	53
auto[0]	values[7]	values[2]	416	1			T17	18		T48	20		T235	14
auto[0]	values[7]	values[3]	416	1			T40	27		T48	51		T34	35
auto[0]	values[7]	values[4]	559	1			T12	20		T15	19		T230	20
auto[0]	values[7]	values[5]	379	1			T15	29		T48	20		T225	2
auto[0]	values[7]	values[6]	546	1			T15	18		T205	8		T264	16
auto[0]	values[7]	values[7]	525	1			T14	25		T16	20		T209	12
auto[1]	values[0]	values[0]	12	1			T13	3		T21	1		T125	1
auto[1]	values[0]	values[1]	15	1			T12	1		T83	1		T144	4
auto[1]	values[0]	values[2]	24	1			T14	4		T206	3		T201	2
auto[1]	values[0]	values[3]	15	1			T31	1		T125	5		T265	3
auto[1]	values[0]	values[4]	12	1			T43	4		T246	2		T125	3
auto[1]	values[0]	values[5]	8	1			T43	2		T179	1		T266	3
auto[1]	values[0]	values[6]	10	1			T170	1		T128	3		T267	2
auto[1]	values[0]	values[7]	14	1			T48	3		T161	2		T31	3
auto[1]	values[1]	values[0]	10	1			T14	1		T154	2		T145	1
auto[1]	values[1]	values[1]	10	1			T182	2		T240	1		T189	1
auto[1]	values[1]	values[2]	14	1			T44	4		T48	1		T83	2
auto[1]	values[1]	values[3]	15	1			T31	1		T128	3		T268	1
auto[1]	values[1]	values[4]	15	1			T14	3		T37	3		T191	3
auto[1]	values[1]	values[5]	15	1			T15	1		T42	2		T254	3
auto[1]	values[1]	values[6]	2	1			T31	2		-	-		-	-
auto[1]	values[1]	values[7]	2	1			T269	2		-	-		-	-
auto[1]	values[2]	values[0]	23	1			T12	2		T197	5		T201	2
auto[1]	values[2]	values[1]	12	1			T21	1		T161	1		T126	1
auto[1]	values[2]	values[2]	13	1			T31	1		T206	2		T223	1
auto[1]	values[2]	values[3]	12	1			T31	2		T241	1		T270	1
auto[1]	values[2]	values[4]	10	1			T234	1		T250	4		T271	1
auto[1]	values[2]	values[5]	14	1			T48	2		T83	3		T145	3
auto[1]	values[2]	values[6]	5	1			T272	1		T273	1		T274	3
auto[1]	values[2]	values[7]	11	1			T12	1		T15	3		T245	4
auto[1]	values[3]	values[0]	5	1			T254	1		T275	1		T273	3
auto[1]	values[3]	values[1]	20	1			T3	3		T42	1		T222	2
auto[1]	values[3]	values[2]	7	1			T204	1		T244	5		T49	1
auto[1]	values[3]	values[3]	5	1			T161	1		T201	1		T146	1
auto[1]	values[3]	values[4]	11	1			T182	2		T126	1		T276	1
auto[1]	values[3]	values[5]	9	1			T145	1		T127	1		T148	1
auto[1]	values[3]	values[6]	13	1			T37	2		T265	2		T148	2
auto[1]	values[3]	values[7]	9	1			T202	5		T191	2		T275	1
auto[1]	values[4]	values[0]	6	1			T161	1		T182	1		T201	1
auto[1]	values[4]	values[1]	8	1			T16	2		T34	1		T223	3
auto[1]	values[4]	values[2]	13	1			T197	1		T213	4		T277	1
auto[1]	values[4]	values[3]	19	1			T278	2		T254	6		T223	4
auto[1]	values[4]	values[4]	12	1			T21	2		T201	5		T279	3
auto[1]	values[4]	values[5]	6	1			T214	1		T271	1		T280	1
auto[1]	values[4]	values[6]	17	1			T214	1		T250	6		T281	2
auto[1]	values[4]	values[7]	6	1			T191	3		T268	1		T282	1
auto[1]	values[5]	values[0]	3	1			T254	1		T283	2		-	-
auto[1]	values[5]	values[1]	14	1			T145	6		T206	2		T170	3
auto[1]	values[5]	values[2]	13	1			T15	2		T70	4		T148	2
auto[1]	values[5]	values[3]	11	1			T222	1		T284	2		T285	1
auto[1]	values[5]	values[4]	11	1			T127	1		T214	1		T223	1
auto[1]	values[5]	values[5]	29	1			T43	1		T239	4		T144	5
auto[1]	values[5]	values[6]	5	1			T48	2		T268	1		T286	1
auto[1]	values[5]	values[7]	2	1			T248	2		-	-		-	-
auto[1]	values[6]	values[0]	15	1			T15	2		T125	2		T126	3
auto[1]	values[6]	values[1]	8	1			T189	1		T256	3		T244	2
auto[1]	values[6]	values[2]	15	1			T240	1		T127	1		T277	2
auto[1]	values[6]	values[3]	19	1			T17	1		T48	2		T201	1
auto[1]	values[6]	values[4]	8	1			T182	1		T277	1		T248	2
auto[1]	values[6]	values[5]	15	1			T43	2		T73	2		T287	3
auto[1]	values[6]	values[6]	21	1			T15	2		T37	1		T144	1
auto[1]	values[6]	values[7]	25	1			T15	1		T161	3		T145	2
auto[1]	values[7]	values[0]	13	1			T41	3		T40	2		T145	2
auto[1]	values[7]	values[1]	15	1			T144	2		T170	2		T288	3
auto[1]	values[7]	values[2]	16	1			T17	2		T256	2		T149	1
auto[1]	values[7]	values[3]	3	1			T83	2		T270	1		-	-
auto[1]	values[7]	values[4]	16	1			T15	1		T174	3		T190	2
auto[1]	values[7]	values[5]	9	1			T15	1		T289	1		T272	4
auto[1]	values[7]	values[6]	14	1			T15	2		T83	2		T290	4
auto[1]	values[7]	values[7]	13	1			T14	1		T144	1		T31	1