Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	733	1			T14	14		T17	14		T19	18
all_values[1]	733	1			T14	14		T17	14		T19	18
all_values[2]	733	1			T14	14		T17	14		T19	18
all_values[3]	733	1			T14	14		T17	14		T19	18
all_values[4]	733	1			T14	14		T17	14		T19	18
all_values[5]	733	1			T14	14		T17	14		T19	18
all_values[6]	733	1			T14	14		T17	14		T19	18
all_values[7]	733	1			T14	14		T17	14		T19	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3145

1

T14

61

T17

63

T19

81

auto[1]

2719

1

T14

51

T17

49

T19

63

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2284

1

T14

57

T17

41

T19

49

auto[1]

3580

1

T14

55

T17

71

T19

95

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3301

1

T14

66

T17

64

T19

79

auto[1]

2563

1

T14

46

T17

48

T19

65

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	169	1			T14	8		T17	1		T19	1
all_values[0]	auto[0]	auto[0]	auto[1]	62	1			T17	2		T19	1		T144	1
all_values[0]	auto[0]	auto[1]	auto[0]	130	1			T14	2		T17	4		T19	2
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T17	1		T19	4		T21	2
all_values[0]	auto[1]	auto[0]	auto[1]	162	1			T14	4		T17	3		T19	9
all_values[0]	auto[1]	auto[1]	auto[1]	158	1			T17	3		T19	1		T21	3
all_values[1]	auto[0]	auto[0]	auto[0]	171	1			T14	3		T17	3		T19	1
all_values[1]	auto[0]	auto[0]	auto[1]	84	1			T17	5		T19	2		T21	1
all_values[1]	auto[0]	auto[1]	auto[0]	112	1			T14	4		T17	1		T19	1
all_values[1]	auto[0]	auto[1]	auto[1]	63	1			T19	1		T21	1		T144	3
all_values[1]	auto[1]	auto[0]	auto[1]	151	1			T14	4		T17	4		T19	7
all_values[1]	auto[1]	auto[1]	auto[1]	152	1			T14	3		T17	1		T19	6
all_values[2]	auto[0]	auto[0]	auto[0]	123	1			T14	3		T19	6		T20	1
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T14	2		T17	2		T19	2
all_values[2]	auto[0]	auto[1]	auto[0]	121	1			T14	2		T17	2		T19	3
all_values[2]	auto[0]	auto[1]	auto[1]	80	1			T14	1		T17	2		T19	1
all_values[2]	auto[1]	auto[0]	auto[1]	184	1			T14	1		T17	7		T19	4
all_values[2]	auto[1]	auto[1]	auto[1]	155	1			T14	5		T17	1		T19	2
all_values[3]	auto[0]	auto[0]	auto[0]	140	1			T14	3		T17	3		T19	3
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T14	1		T21	2		T144	1
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T14	1		T17	4		T19	3
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T14	2		T17	1		T19	4
all_values[3]	auto[1]	auto[0]	auto[1]	179	1			T14	4		T17	4		T19	4
all_values[3]	auto[1]	auto[1]	auto[1]	149	1			T14	3		T17	2		T19	4
all_values[4]	auto[0]	auto[0]	auto[0]	129	1			T14	5		T17	1		T19	3
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T14	1		T17	4		T19	3
all_values[4]	auto[0]	auto[1]	auto[0]	116	1			T14	2		T17	1		T19	2
all_values[4]	auto[0]	auto[1]	auto[1]	87	1			T17	2		T19	4		T21	1
all_values[4]	auto[1]	auto[0]	auto[1]	168	1			T14	1		T17	4		T19	3
all_values[4]	auto[1]	auto[1]	auto[1]	151	1			T14	5		T17	2		T19	3
all_values[5]	auto[0]	auto[0]	auto[0]	223	1			T14	3		T17	5		T19	10
all_values[5]	auto[0]	auto[1]	auto[0]	196	1			T14	4		T17	3		T19	2
all_values[5]	auto[1]	auto[0]	auto[1]	170	1			T14	3		T17	5		T19	3
all_values[5]	auto[1]	auto[1]	auto[1]	144	1			T14	4		T17	1		T19	3
all_values[6]	auto[0]	auto[0]	auto[0]	151	1			T14	2		T17	2		T19	2
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T17	1		T19	3		T144	3
all_values[6]	auto[0]	auto[1]	auto[0]	127	1			T14	5		T17	3		T19	2
all_values[6]	auto[0]	auto[1]	auto[1]	64	1			T14	1		T17	2		T19	3
all_values[6]	auto[1]	auto[0]	auto[1]	171	1			T14	3		T17	1		T19	5
all_values[6]	auto[1]	auto[1]	auto[1]	138	1			T14	3		T17	5		T19	3
all_values[7]	auto[0]	auto[0]	auto[0]	145	1			T14	7		T17	3		T19	5
all_values[7]	auto[0]	auto[0]	auto[1]	78	1			T14	1		T19	1		T21	1
all_values[7]	auto[0]	auto[1]	auto[0]	106	1			T14	3		T17	5		T19	3
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T17	1		T19	1		T20	3
all_values[7]	auto[1]	auto[0]	auto[1]	180	1			T14	2		T17	3		T19	3
all_values[7]	auto[1]	auto[1]	auto[1]	151	1			T14	1		T17	2		T19	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal