Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1783

1

T2

4

T3

5

T10

1

auto[1]

1767

1

T2

2

T3

4

T10

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1867

1

T2

4

T3

9

T14

6

auto[1]

1683

1

T2

2

T10

6

T29

41

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2806

1

T2

2

T3

4

T10

6

auto[1]

744

1

T2

4

T3

5

T14

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	709	1			T2	1		T3	4		T10	2
valid[1]	750	1			T2	1		T10	1		T29	11
valid[2]	725	1			T2	1		T10	2		T29	11
valid[3]	650	1			T2	2		T3	1		T10	1
valid[4]	716	1			T2	1		T3	4		T29	7

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	111	1			T3	2		T30	1		T45	1
auto[0]	auto[0]	valid[0]	auto[1]	156	1			T10	1		T29	2		T33	2
auto[0]	auto[0]	valid[1]	auto[0]	119	1			T14	1		T30	1		T45	1
auto[0]	auto[0]	valid[1]	auto[1]	179	1			T29	3		T33	4		T56	5
auto[0]	auto[0]	valid[2]	auto[0]	119	1			T15	1		T46	2		T52	3
auto[0]	auto[0]	valid[2]	auto[1]	158	1			T29	4		T33	1		T46	1
auto[0]	auto[0]	valid[3]	auto[0]	100	1			T14	1		T26	1		T52	3
auto[0]	auto[0]	valid[3]	auto[1]	151	1			T2	1		T29	1		T41	1
auto[0]	auto[0]	valid[4]	auto[0]	122	1			T3	2		T14	1		T52	4
auto[0]	auto[0]	valid[4]	auto[1]	182	1			T29	5		T33	3		T302	1
auto[0]	auto[1]	valid[0]	auto[0]	109	1			T14	1		T30	1		T15	2
auto[0]	auto[1]	valid[0]	auto[1]	179	1			T10	1		T29	4		T33	1
auto[0]	auto[1]	valid[1]	auto[0]	120	1			T30	1		T15	1		T52	1
auto[0]	auto[1]	valid[1]	auto[1]	169	1			T10	1		T29	8		T56	4
auto[0]	auto[1]	valid[2]	auto[0]	105	1			T14	1		T30	1		T41	1
auto[0]	auto[1]	valid[2]	auto[1]	191	1			T10	2		T29	7		T33	1
auto[0]	auto[1]	valid[3]	auto[0]	113	1			T30	1		T15	1		T46	1
auto[0]	auto[1]	valid[3]	auto[1]	154	1			T10	1		T29	5		T33	1
auto[0]	auto[1]	valid[4]	auto[0]	105	1			T26	1		T30	1		T52	1
auto[0]	auto[1]	valid[4]	auto[1]	164	1			T2	1		T29	2		T33	1
auto[1]	auto[0]	valid[0]	auto[0]	67	1			T46	1		T37	1		T16	1
auto[1]	auto[0]	valid[1]	auto[0]	87	1			T2	1		T52	1		T40	1
auto[1]	auto[0]	valid[2]	auto[0]	83	1			T2	1		T15	2		T52	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T2	1		T14	1		T30	3
auto[1]	auto[0]	valid[4]	auto[0]	75	1			T3	1		T46	1		T52	1
auto[1]	auto[1]	valid[0]	auto[0]	87	1			T2	1		T3	2		T15	2
auto[1]	auto[1]	valid[1]	auto[0]	76	1			T24	1		T15	3		T37	1
auto[1]	auto[1]	valid[2]	auto[0]	69	1			T52	1		T81	1		T305	1
auto[1]	auto[1]	valid[3]	auto[0]	58	1			T3	1		T16	2		T17	1
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T3	1		T30	1		T15	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal