Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48550

1

T1

14

T2

166

T3

161

auto[1]

17801

1

T2

27

T3

22

T10

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48214

1

T1

4

T2

128

T3

111

auto[1]

18137

1

T1

10

T2

65

T3

72

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34055	1			T1	8		T2	100		T3	106
others[1]	5699	1			T1	2		T2	21		T3	18
others[2]	5696	1			T1	3		T2	14		T3	9
others[3]	6428	1			T1	1		T2	20		T3	12
interest[1]	3603	1			T2	13		T3	10		T29	22
interest[4]	22174	1			T1	6		T2	66		T3	65
interest[64]	10870	1			T2	25		T3	28		T29	72

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15601	1			T1	2		T2	52		T3	53
auto[0]	auto[0]	others[1]	2637	1			T1	1		T2	10		T3	8
auto[0]	auto[0]	others[2]	2566	1			T2	9		T3	3		T14	8
auto[0]	auto[0]	others[3]	2979	1			T1	1		T2	13		T3	5
auto[0]	auto[0]	interest[1]	1675	1			T2	3		T3	6		T14	3
auto[0]	auto[0]	interest[4]	10033	1			T1	1		T2	31		T3	29
auto[0]	auto[0]	interest[64]	4955	1			T2	14		T3	14		T14	14
auto[0]	auto[1]	others[0]	9271	1			T2	16		T3	12		T10	6
auto[0]	auto[1]	others[1]	1471	1			T2	4		T3	4		T29	36
auto[0]	auto[1]	others[2]	1527	1			T2	1		T3	2		T29	21
auto[0]	auto[1]	others[3]	1662	1			T3	2		T29	39		T24	5
auto[0]	auto[1]	interest[1]	942	1			T29	22		T15	2		T41	3
auto[0]	auto[1]	interest[4]	6162	1			T2	13		T3	8		T10	6
auto[0]	auto[1]	interest[64]	2928	1			T2	6		T3	2		T29	72
auto[1]	auto[0]	others[0]	9183	1			T1	6		T2	32		T3	41
auto[1]	auto[0]	others[1]	1591	1			T1	1		T2	7		T3	6
auto[1]	auto[0]	others[2]	1603	1			T1	3		T2	4		T3	4
auto[1]	auto[0]	others[3]	1787	1			T2	7		T3	5		T14	3
auto[1]	auto[0]	interest[1]	986	1			T2	10		T3	4		T14	3
auto[1]	auto[0]	interest[4]	5979	1			T1	5		T2	22		T3	28
auto[1]	auto[0]	interest[64]	2987	1			T2	5		T3	12		T14	6

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal