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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 94.01 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T102 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1118759125 Jul 01 04:34:20 PM PDT 24 Jul 01 04:34:34 PM PDT 24 647116933 ps
T1039 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1818703301 Jul 01 04:34:11 PM PDT 24 Jul 01 04:34:36 PM PDT 24 847218025 ps
T1040 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2621445692 Jul 01 04:34:33 PM PDT 24 Jul 01 04:34:40 PM PDT 24 41412368 ps
T1041 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2268008574 Jul 01 04:34:25 PM PDT 24 Jul 01 04:34:36 PM PDT 24 31575274 ps
T1042 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1586729525 Jul 01 04:34:14 PM PDT 24 Jul 01 04:34:25 PM PDT 24 48588744 ps
T1043 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2545942026 Jul 01 04:34:23 PM PDT 24 Jul 01 04:34:34 PM PDT 24 110498387 ps
T1044 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1931134683 Jul 01 04:34:12 PM PDT 24 Jul 01 04:34:37 PM PDT 24 677314455 ps
T116 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2364882347 Jul 01 04:34:27 PM PDT 24 Jul 01 04:34:37 PM PDT 24 124666012 ps
T1045 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2780154546 Jul 01 04:34:22 PM PDT 24 Jul 01 04:34:33 PM PDT 24 189799774 ps
T92 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2874904011 Jul 01 04:34:29 PM PDT 24 Jul 01 04:34:41 PM PDT 24 271113424 ps
T117 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4250571375 Jul 01 04:34:38 PM PDT 24 Jul 01 04:34:47 PM PDT 24 103205300 ps
T1046 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2494859799 Jul 01 04:34:37 PM PDT 24 Jul 01 04:34:45 PM PDT 24 10839029 ps
T94 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3528185171 Jul 01 04:34:29 PM PDT 24 Jul 01 04:34:41 PM PDT 24 147062993 ps
T167 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3669565196 Jul 01 04:34:24 PM PDT 24 Jul 01 04:34:54 PM PDT 24 3804743077 ps
T1047 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.252413245 Jul 01 04:34:28 PM PDT 24 Jul 01 04:34:38 PM PDT 24 30944545 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3777312463 Jul 01 04:34:17 PM PDT 24 Jul 01 04:34:28 PM PDT 24 25531290 ps
T1049 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2124678446 Jul 01 04:34:41 PM PDT 24 Jul 01 04:34:52 PM PDT 24 13961351 ps
T106 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1423532081 Jul 01 04:34:32 PM PDT 24 Jul 01 04:34:42 PM PDT 24 154415002 ps
T143 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3480118633 Jul 01 04:34:25 PM PDT 24 Jul 01 04:34:35 PM PDT 24 179480955 ps
T95 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.307859762 Jul 01 04:34:09 PM PDT 24 Jul 01 04:34:19 PM PDT 24 349120271 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.50428200 Jul 01 04:34:41 PM PDT 24 Jul 01 04:34:53 PM PDT 24 30355998 ps
T118 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.201689343 Jul 01 04:34:10 PM PDT 24 Jul 01 04:34:20 PM PDT 24 27683522 ps
T1051 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2363398770 Jul 01 04:34:24 PM PDT 24 Jul 01 04:34:37 PM PDT 24 112254621 ps
T137 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.863006972 Jul 01 04:34:33 PM PDT 24 Jul 01 04:34:52 PM PDT 24 1333512514 ps
T1052 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3601105938 Jul 01 04:34:13 PM PDT 24 Jul 01 04:34:25 PM PDT 24 23951651 ps
T1053 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4123158452 Jul 01 04:34:44 PM PDT 24 Jul 01 04:34:55 PM PDT 24 13243430 ps
T119 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.204008060 Jul 01 04:34:17 PM PDT 24 Jul 01 04:34:29 PM PDT 24 75381176 ps
T1054 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1328938159 Jul 01 04:34:34 PM PDT 24 Jul 01 04:34:41 PM PDT 24 21989484 ps
T98 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2733925534 Jul 01 04:34:18 PM PDT 24 Jul 01 04:34:44 PM PDT 24 2097588026 ps
T1055 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3875201877 Jul 01 04:34:30 PM PDT 24 Jul 01 04:34:40 PM PDT 24 61363206 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.815150286 Jul 01 04:34:41 PM PDT 24 Jul 01 04:34:54 PM PDT 24 84890941 ps
T138 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1336807599 Jul 01 04:34:25 PM PDT 24 Jul 01 04:34:37 PM PDT 24 145092035 ps
T1057 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.714301497 Jul 01 04:34:42 PM PDT 24 Jul 01 04:34:54 PM PDT 24 42047702 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1842602887 Jul 01 04:34:11 PM PDT 24 Jul 01 04:34:27 PM PDT 24 476099178 ps
T1059 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.744918696 Jul 01 04:34:29 PM PDT 24 Jul 01 04:34:44 PM PDT 24 415510546 ps
T139 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1918996708 Jul 01 04:34:27 PM PDT 24 Jul 01 04:34:39 PM PDT 24 809370284 ps
T99 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.112077984 Jul 01 04:34:35 PM PDT 24 Jul 01 04:34:45 PM PDT 24 424773210 ps
T97 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3788457012 Jul 01 04:34:31 PM PDT 24 Jul 01 04:34:41 PM PDT 24 72600669 ps
T1060 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1029556523 Jul 01 04:34:35 PM PDT 24 Jul 01 04:34:42 PM PDT 24 64062849 ps
T93 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1144820124 Jul 01 04:34:26 PM PDT 24 Jul 01 04:34:38 PM PDT 24 369403320 ps
T96 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2824642591 Jul 01 04:34:33 PM PDT 24 Jul 01 04:34:44 PM PDT 24 255249840 ps
T1061 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3014547011 Jul 01 04:34:45 PM PDT 24 Jul 01 04:34:56 PM PDT 24 45331982 ps
T140 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3063858350 Jul 01 04:34:43 PM PDT 24 Jul 01 04:34:57 PM PDT 24 137148593 ps
T1062 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2399498291 Jul 01 04:34:30 PM PDT 24 Jul 01 04:34:45 PM PDT 24 729472159 ps
T141 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.208000498 Jul 01 04:34:16 PM PDT 24 Jul 01 04:34:28 PM PDT 24 368271335 ps
T104 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1864818688 Jul 01 04:34:46 PM PDT 24 Jul 01 04:35:00 PM PDT 24 278833991 ps
T1063 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2085505206 Jul 01 04:34:28 PM PDT 24 Jul 01 04:34:38 PM PDT 24 136899701 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.974985023 Jul 01 04:34:23 PM PDT 24 Jul 01 04:34:33 PM PDT 24 22899422 ps
T159 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2702229009 Jul 01 04:34:15 PM PDT 24 Jul 01 04:34:27 PM PDT 24 102246438 ps
T105 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1985579624 Jul 01 04:34:45 PM PDT 24 Jul 01 04:34:57 PM PDT 24 89518264 ps
T1065 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.327607985 Jul 01 04:34:26 PM PDT 24 Jul 01 04:34:36 PM PDT 24 170983243 ps
T168 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2142665858 Jul 01 04:34:28 PM PDT 24 Jul 01 04:34:55 PM PDT 24 310556999 ps
T120 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2905134211 Jul 01 04:34:30 PM PDT 24 Jul 01 04:34:39 PM PDT 24 26791644 ps
T1066 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3598084834 Jul 01 04:34:40 PM PDT 24 Jul 01 04:34:50 PM PDT 24 21084083 ps
T1067 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2293871346 Jul 01 04:34:14 PM PDT 24 Jul 01 04:34:26 PM PDT 24 33260070 ps
T1068 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4016773046 Jul 01 04:34:23 PM PDT 24 Jul 01 04:35:07 PM PDT 24 3671873405 ps
T160 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1330390644 Jul 01 04:34:30 PM PDT 24 Jul 01 04:34:39 PM PDT 24 73233673 ps
T1069 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3527351968 Jul 01 04:34:36 PM PDT 24 Jul 01 04:34:43 PM PDT 24 33853125 ps
T1070 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2848183912 Jul 01 04:34:45 PM PDT 24 Jul 01 04:34:56 PM PDT 24 18823947 ps
T1071 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2380466727 Jul 01 04:34:29 PM PDT 24 Jul 01 04:34:39 PM PDT 24 57484614 ps
T121 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3940943092 Jul 01 04:34:14 PM PDT 24 Jul 01 04:34:32 PM PDT 24 398118999 ps
T122 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2477412306 Jul 01 04:34:21 PM PDT 24 Jul 01 04:34:32 PM PDT 24 111902415 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2561741037 Jul 01 04:34:28 PM PDT 24 Jul 01 04:34:37 PM PDT 24 59141803 ps
T77 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1655825127 Jul 01 04:34:19 PM PDT 24 Jul 01 04:34:30 PM PDT 24 59974152 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3911235101 Jul 01 04:34:23 PM PDT 24 Jul 01 04:34:35 PM PDT 24 454267349 ps
T1074 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2776391899 Jul 01 04:34:44 PM PDT 24 Jul 01 04:34:55 PM PDT 24 35209698 ps
T107 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.51656534 Jul 01 04:34:08 PM PDT 24 Jul 01 04:34:18 PM PDT 24 58736566 ps
T163 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2615898862 Jul 01 04:34:28 PM PDT 24 Jul 01 04:34:38 PM PDT 24 172743676 ps
T1075 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2263267815 Jul 01 04:34:11 PM PDT 24 Jul 01 04:34:25 PM PDT 24 239897561 ps
T1076 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1811772574 Jul 01 04:34:26 PM PDT 24 Jul 01 04:34:43 PM PDT 24 231252843 ps
T1077 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1863247487 Jul 01 04:34:45 PM PDT 24 Jul 01 04:34:56 PM PDT 24 60404525 ps
T1078 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1242322537 Jul 01 04:34:24 PM PDT 24 Jul 01 04:34:34 PM PDT 24 17893145 ps
T1079 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2472172986 Jul 01 04:34:41 PM PDT 24 Jul 01 04:34:51 PM PDT 24 17383534 ps
T1080 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.371535883 Jul 01 04:34:36 PM PDT 24 Jul 01 04:34:44 PM PDT 24 42300769 ps
T1081 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.904667701 Jul 01 04:34:12 PM PDT 24 Jul 01 04:34:23 PM PDT 24 100357845 ps
T164 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.854738886 Jul 01 04:34:14 PM PDT 24 Jul 01 04:34:44 PM PDT 24 297232775 ps
T1082 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2874206781 Jul 01 04:34:40 PM PDT 24 Jul 01 04:34:50 PM PDT 24 13113631 ps
T1083 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1752817164 Jul 01 04:34:29 PM PDT 24 Jul 01 04:34:39 PM PDT 24 30898693 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1883804371 Jul 01 04:34:17 PM PDT 24 Jul 01 04:34:29 PM PDT 24 174864607 ps
T1085 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3573678514 Jul 01 04:34:47 PM PDT 24 Jul 01 04:34:57 PM PDT 24 14987877 ps
T1086 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3131649149 Jul 01 04:34:32 PM PDT 24 Jul 01 04:34:40 PM PDT 24 71026071 ps
T1087 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2109829443 Jul 01 04:34:36 PM PDT 24 Jul 01 04:34:46 PM PDT 24 193949665 ps
T1088 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.269651807 Jul 01 04:34:26 PM PDT 24 Jul 01 04:34:39 PM PDT 24 119415892 ps
T1089 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2767797632 Jul 01 04:34:15 PM PDT 24 Jul 01 04:34:33 PM PDT 24 115852650 ps
T1090 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.167662009 Jul 01 04:34:30 PM PDT 24 Jul 01 04:34:45 PM PDT 24 2484768418 ps
T1091 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2027854587 Jul 01 04:34:27 PM PDT 24 Jul 01 04:34:36 PM PDT 24 345731610 ps
T1092 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4155483226 Jul 01 04:34:47 PM PDT 24 Jul 01 04:34:58 PM PDT 24 41660061 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2479907316 Jul 01 04:34:27 PM PDT 24 Jul 01 04:34:36 PM PDT 24 14673191 ps
T1094 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1017952095 Jul 01 04:34:38 PM PDT 24 Jul 01 04:34:48 PM PDT 24 27867639 ps
T1095 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3525490488 Jul 01 04:34:34 PM PDT 24 Jul 01 04:34:48 PM PDT 24 271032002 ps
T1096 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3850634275 Jul 01 04:34:28 PM PDT 24 Jul 01 04:34:40 PM PDT 24 146272881 ps
T1097 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2419002633 Jul 01 04:34:37 PM PDT 24 Jul 01 04:34:46 PM PDT 24 202179758 ps
T78 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2025835584 Jul 01 04:34:19 PM PDT 24 Jul 01 04:34:30 PM PDT 24 94765659 ps
T123 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.566207714 Jul 01 04:34:13 PM PDT 24 Jul 01 04:34:26 PM PDT 24 187463004 ps
T1098 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2553536267 Jul 01 04:34:08 PM PDT 24 Jul 01 04:34:15 PM PDT 24 12776431 ps
T1099 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2207640223 Jul 01 04:34:34 PM PDT 24 Jul 01 04:34:42 PM PDT 24 124131723 ps
T1100 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1016955962 Jul 01 04:34:19 PM PDT 24 Jul 01 04:34:30 PM PDT 24 96242501 ps
T1101 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3623388786 Jul 01 04:34:21 PM PDT 24 Jul 01 04:34:38 PM PDT 24 557922893 ps
T1102 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2172009033 Jul 01 04:34:27 PM PDT 24 Jul 01 04:34:37 PM PDT 24 101143632 ps
T124 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3987221668 Jul 01 04:34:15 PM PDT 24 Jul 01 04:34:27 PM PDT 24 68036442 ps
T1103 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1160816433 Jul 01 04:34:18 PM PDT 24 Jul 01 04:34:28 PM PDT 24 76864025 ps
T1104 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1565826601 Jul 01 04:34:45 PM PDT 24 Jul 01 04:34:56 PM PDT 24 42336243 ps
T1105 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3766251773 Jul 01 04:34:27 PM PDT 24 Jul 01 04:34:50 PM PDT 24 1395799211 ps
T1106 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.744715017 Jul 01 04:34:19 PM PDT 24 Jul 01 04:34:31 PM PDT 24 89982541 ps
T1107 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.155861894 Jul 01 04:34:14 PM PDT 24 Jul 01 04:34:25 PM PDT 24 28868186 ps
T1108 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1794350968 Jul 01 04:34:13 PM PDT 24 Jul 01 04:34:24 PM PDT 24 40870731 ps
T1109 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.972935364 Jul 01 04:34:08 PM PDT 24 Jul 01 04:34:16 PM PDT 24 373608034 ps
T1110 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2258345807 Jul 01 04:34:31 PM PDT 24 Jul 01 04:34:41 PM PDT 24 395214769 ps
T79 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.799400356 Jul 01 04:34:22 PM PDT 24 Jul 01 04:34:31 PM PDT 24 18208263 ps
T1111 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2977037902 Jul 01 04:34:27 PM PDT 24 Jul 01 04:34:48 PM PDT 24 8676234725 ps
T1112 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3016465993 Jul 01 04:34:27 PM PDT 24 Jul 01 04:34:37 PM PDT 24 43666184 ps
T1113 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1086735120 Jul 01 04:34:28 PM PDT 24 Jul 01 04:34:40 PM PDT 24 586665491 ps
T1114 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.423564899 Jul 01 04:34:48 PM PDT 24 Jul 01 04:34:58 PM PDT 24 31791534 ps
T1115 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2688590008 Jul 01 04:34:21 PM PDT 24 Jul 01 04:34:31 PM PDT 24 55881345 ps
T1116 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3847357882 Jul 01 04:34:27 PM PDT 24 Jul 01 04:34:36 PM PDT 24 27803819 ps
T1117 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1638162374 Jul 01 04:34:30 PM PDT 24 Jul 01 04:34:52 PM PDT 24 1076089805 ps
T80 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1365229247 Jul 01 04:34:12 PM PDT 24 Jul 01 04:34:23 PM PDT 24 35356424 ps
T1118 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1364075808 Jul 01 04:34:25 PM PDT 24 Jul 01 04:34:35 PM PDT 24 111946606 ps
T1119 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2478698634 Jul 01 04:34:20 PM PDT 24 Jul 01 04:34:32 PM PDT 24 478460165 ps
T1120 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2587998444 Jul 01 04:34:29 PM PDT 24 Jul 01 04:34:40 PM PDT 24 95366998 ps
T1121 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.80563072 Jul 01 04:34:06 PM PDT 24 Jul 01 04:34:23 PM PDT 24 951260513 ps
T1122 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3539406367 Jul 01 04:34:43 PM PDT 24 Jul 01 04:34:58 PM PDT 24 1215543900 ps
T1123 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2102079370 Jul 01 04:34:21 PM PDT 24 Jul 01 04:34:44 PM PDT 24 1879240711 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2309139835 Jul 01 04:34:22 PM PDT 24 Jul 01 04:34:33 PM PDT 24 60975505 ps
T1125 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2385387186 Jul 01 04:34:23 PM PDT 24 Jul 01 04:34:36 PM PDT 24 125640981 ps
T1126 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.603637724 Jul 01 04:34:31 PM PDT 24 Jul 01 04:34:44 PM PDT 24 176043980 ps
T1127 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3721601558 Jul 01 04:34:33 PM PDT 24 Jul 01 04:34:40 PM PDT 24 18855057 ps
T1128 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3286986464 Jul 01 04:34:42 PM PDT 24 Jul 01 04:34:55 PM PDT 24 71985117 ps
T1129 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.185713921 Jul 01 04:34:36 PM PDT 24 Jul 01 04:34:44 PM PDT 24 12758208 ps
T1130 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3298601021 Jul 01 04:34:43 PM PDT 24 Jul 01 04:34:55 PM PDT 24 32355720 ps
T1131 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2925747335 Jul 01 04:34:22 PM PDT 24 Jul 01 04:34:31 PM PDT 24 12676048 ps

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3028423377
Short name T3
Test name
Test status
Simulation time 17551459948 ps
CPU time 162.95 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:27:42 PM PDT 24
Peak memory 257460 kb
Host smart-835f175b-7767-4c10-99c4-96ac0df21047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028423377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3028423377
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1643623063
Short name T15
Test name
Test status
Simulation time 253551556586 ps
CPU time 700.17 seconds
Started Jul 01 05:26:10 PM PDT 24
Finished Jul 01 05:37:53 PM PDT 24
Peak memory 288752 kb
Host smart-6d1b0070-73ab-4cba-af89-68ef1a29bd53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643623063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1643623063
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.4214375714
Short name T20
Test name
Test status
Simulation time 136428752069 ps
CPU time 200.95 seconds
Started Jul 01 05:25:58 PM PDT 24
Finished Jul 01 05:29:23 PM PDT 24
Peak memory 267856 kb
Host smart-facdc5f1-8b3a-4f0f-af9f-49b36d137299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214375714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.4214375714
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1391527818
Short name T110
Test name
Test status
Simulation time 1422192602 ps
CPU time 8.38 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:46 PM PDT 24
Peak memory 216980 kb
Host smart-3c929627-b5c3-49d4-8f43-c7ecba265a07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391527818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1391527818
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2594415217
Short name T144
Test name
Test status
Simulation time 39309195120 ps
CPU time 407.35 seconds
Started Jul 01 05:25:09 PM PDT 24
Finished Jul 01 05:32:05 PM PDT 24
Peak memory 268720 kb
Host smart-bd5dd34c-ca47-433a-96e9-2a8bd78cfd20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594415217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2594415217
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.170410396
Short name T62
Test name
Test status
Simulation time 19194299 ps
CPU time 0.85 seconds
Started Jul 01 05:23:58 PM PDT 24
Finished Jul 01 05:24:02 PM PDT 24
Peak memory 216108 kb
Host smart-90246754-c67a-4c38-988b-a1d6e2a12004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170410396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.170410396
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.959870600
Short name T145
Test name
Test status
Simulation time 340763383588 ps
CPU time 485.05 seconds
Started Jul 01 05:26:51 PM PDT 24
Finished Jul 01 05:34:58 PM PDT 24
Peak memory 272876 kb
Host smart-408d6cde-7325-451f-8bc3-2734730ba121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959870600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.959870600
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1305902114
Short name T48
Test name
Test status
Simulation time 10914268639 ps
CPU time 182.44 seconds
Started Jul 01 05:24:27 PM PDT 24
Finished Jul 01 05:27:32 PM PDT 24
Peak memory 264788 kb
Host smart-45478145-2cd1-4e88-bf58-5830f4b96b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305902114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1305902114
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3660542178
Short name T4
Test name
Test status
Simulation time 26775889487 ps
CPU time 75.49 seconds
Started Jul 01 05:27:06 PM PDT 24
Finished Jul 01 05:28:23 PM PDT 24
Peak memory 240940 kb
Host smart-968d60ff-c056-4d1f-8d38-039ecf172fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660542178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3660542178
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1040872490
Short name T86
Test name
Test status
Simulation time 87837053 ps
CPU time 3.81 seconds
Started Jul 01 04:34:25 PM PDT 24
Finished Jul 01 04:34:38 PM PDT 24
Peak memory 215960 kb
Host smart-3a6a1165-eed5-41d7-a9e0-d3f6a41e96ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040872490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1040872490
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.722603952
Short name T125
Test name
Test status
Simulation time 16649317347 ps
CPU time 106.68 seconds
Started Jul 01 05:27:24 PM PDT 24
Finished Jul 01 05:29:13 PM PDT 24
Peak memory 265216 kb
Host smart-7e0773ec-a3db-469b-a012-a3de75b9e141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722603952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.722603952
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2892705868
Short name T18
Test name
Test status
Simulation time 775186488 ps
CPU time 1.12 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:12 PM PDT 24
Peak memory 236680 kb
Host smart-7a0b221f-e9aa-4844-8caa-2e621030ba2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892705868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2892705868
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.557697648
Short name T127
Test name
Test status
Simulation time 76302814051 ps
CPU time 671.04 seconds
Started Jul 01 05:26:52 PM PDT 24
Finished Jul 01 05:38:05 PM PDT 24
Peak memory 249308 kb
Host smart-e2009fca-ef04-4c41-9545-51921f7c0381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557697648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.557697648
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3652095329
Short name T83
Test name
Test status
Simulation time 116770711665 ps
CPU time 258.91 seconds
Started Jul 01 05:26:52 PM PDT 24
Finished Jul 01 05:31:12 PM PDT 24
Peak memory 252676 kb
Host smart-3d7c0cad-9b85-4faf-a09f-4411a92757dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652095329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3652095329
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3458676199
Short name T223
Test name
Test status
Simulation time 11112826574 ps
CPU time 114.64 seconds
Started Jul 01 05:25:31 PM PDT 24
Finished Jul 01 05:27:30 PM PDT 24
Peak memory 268872 kb
Host smart-631c58a4-c319-4910-958f-147e431c595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458676199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3458676199
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.204008060
Short name T119
Test name
Test status
Simulation time 75381176 ps
CPU time 1.95 seconds
Started Jul 01 04:34:17 PM PDT 24
Finished Jul 01 04:34:29 PM PDT 24
Peak memory 215628 kb
Host smart-7606d357-9d72-4250-8e41-3f8333de61b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204008060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.204008060
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1438092748
Short name T161
Test name
Test status
Simulation time 156080192693 ps
CPU time 323.72 seconds
Started Jul 01 05:25:29 PM PDT 24
Finished Jul 01 05:30:57 PM PDT 24
Peak memory 257516 kb
Host smart-04432227-b723-40f6-b566-26b03cac1d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438092748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1438092748
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4199864160
Short name T191
Test name
Test status
Simulation time 76003008968 ps
CPU time 656.21 seconds
Started Jul 01 05:25:44 PM PDT 24
Finished Jul 01 05:36:42 PM PDT 24
Peak memory 273164 kb
Host smart-a1f99be2-33d2-4154-b1a0-114301ddef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199864160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4199864160
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1230627415
Short name T183
Test name
Test status
Simulation time 2627677742 ps
CPU time 33.55 seconds
Started Jul 01 05:25:19 PM PDT 24
Finished Jul 01 05:26:01 PM PDT 24
Peak memory 251972 kb
Host smart-98defeeb-0887-4fd9-acab-25dbcbba1465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230627415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1230627415
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.314920701
Short name T12
Test name
Test status
Simulation time 7518299169 ps
CPU time 71.82 seconds
Started Jul 01 05:26:44 PM PDT 24
Finished Jul 01 05:27:59 PM PDT 24
Peak memory 254936 kb
Host smart-8daf3f2c-80fa-424b-a92e-bf65f774a1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314920701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.314920701
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.393855098
Short name T128
Test name
Test status
Simulation time 631063934729 ps
CPU time 672 seconds
Started Jul 01 05:24:49 PM PDT 24
Finished Jul 01 05:36:04 PM PDT 24
Peak memory 283836 kb
Host smart-cf5c6512-4852-4dca-9af8-ad106d135a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393855098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.393855098
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.51656534
Short name T107
Test name
Test status
Simulation time 58736566 ps
CPU time 3.58 seconds
Started Jul 01 04:34:08 PM PDT 24
Finished Jul 01 04:34:18 PM PDT 24
Peak memory 215976 kb
Host smart-601aac54-7d98-472d-8c41-3635f646b750
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51656534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.51656534
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2299092301
Short name T222
Test name
Test status
Simulation time 21335918112 ps
CPU time 273.09 seconds
Started Jul 01 05:25:02 PM PDT 24
Finished Jul 01 05:29:42 PM PDT 24
Peak memory 253324 kb
Host smart-043d0e82-67a5-4784-ba68-ff8fc42328cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299092301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2299092301
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3669565196
Short name T167
Test name
Test status
Simulation time 3804743077 ps
CPU time 20.63 seconds
Started Jul 01 04:34:24 PM PDT 24
Finished Jul 01 04:34:54 PM PDT 24
Peak memory 215824 kb
Host smart-f7e63143-8861-4a0c-aa25-44c5cb06f227
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669565196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3669565196
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2561199421
Short name T21
Test name
Test status
Simulation time 152835156954 ps
CPU time 267.34 seconds
Started Jul 01 05:23:59 PM PDT 24
Finished Jul 01 05:28:29 PM PDT 24
Peak memory 233352 kb
Host smart-43a0b506-38be-4d23-b9d1-7337297a671f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561199421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2561199421
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2562786038
Short name T29
Test name
Test status
Simulation time 6008020666 ps
CPU time 12.32 seconds
Started Jul 01 05:25:58 PM PDT 24
Finished Jul 01 05:26:14 PM PDT 24
Peak memory 216496 kb
Host smart-f5dcb0a9-1703-4323-8da9-2406baa6fbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562786038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2562786038
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2554537043
Short name T254
Test name
Test status
Simulation time 461590418003 ps
CPU time 662.84 seconds
Started Jul 01 05:26:33 PM PDT 24
Finished Jul 01 05:37:39 PM PDT 24
Peak memory 265688 kb
Host smart-74aff8d5-0222-4c25-9e47-e3bc87ed2413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554537043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2554537043
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2230806400
Short name T58
Test name
Test status
Simulation time 11405964 ps
CPU time 0.81 seconds
Started Jul 01 05:23:58 PM PDT 24
Finished Jul 01 05:24:02 PM PDT 24
Peak memory 204996 kb
Host smart-cf155516-b016-4bdb-8033-b5b339676e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230806400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
230806400
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2859633734
Short name T250
Test name
Test status
Simulation time 17624308049 ps
CPU time 156.68 seconds
Started Jul 01 05:25:51 PM PDT 24
Finished Jul 01 05:28:32 PM PDT 24
Peak memory 267404 kb
Host smart-9f6ac318-19e8-441c-b84b-c3a1c1f4dbba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859633734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2859633734
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4277303489
Short name T274
Test name
Test status
Simulation time 29623355948 ps
CPU time 193.44 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:29:43 PM PDT 24
Peak memory 251076 kb
Host smart-9d7c7691-d220-4114-96b2-4ce79540458b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277303489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4277303489
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1462668216
Short name T280
Test name
Test status
Simulation time 39866318562 ps
CPU time 161.58 seconds
Started Jul 01 05:25:20 PM PDT 24
Finished Jul 01 05:28:09 PM PDT 24
Peak memory 262276 kb
Host smart-80d0488f-773b-4d32-b6d8-8b2845a0acd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462668216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1462668216
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3808152598
Short name T293
Test name
Test status
Simulation time 1541324127 ps
CPU time 15.12 seconds
Started Jul 01 05:27:28 PM PDT 24
Finished Jul 01 05:27:46 PM PDT 24
Peak memory 224476 kb
Host smart-a7b8153a-69fb-4e70-beee-1ad29ca54acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808152598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3808152598
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1098332883
Short name T16
Test name
Test status
Simulation time 118027099803 ps
CPU time 160.5 seconds
Started Jul 01 05:27:27 PM PDT 24
Finished Jul 01 05:30:10 PM PDT 24
Peak memory 256648 kb
Host smart-d6b28821-d8e4-4c29-b531-6b504edb9ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098332883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1098332883
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.605613878
Short name T36
Test name
Test status
Simulation time 43848274965 ps
CPU time 182.77 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:28:01 PM PDT 24
Peak memory 282068 kb
Host smart-0417ed79-2a6e-4297-9190-21887212f6d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605613878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.605613878
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.409482893
Short name T109
Test name
Test status
Simulation time 1165403408 ps
CPU time 20.43 seconds
Started Jul 01 04:34:14 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 216244 kb
Host smart-dd11ff81-3918-4db0-af8d-554a417de843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409482893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.409482893
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1702954420
Short name T177
Test name
Test status
Simulation time 12222692505 ps
CPU time 192.35 seconds
Started Jul 01 05:25:13 PM PDT 24
Finished Jul 01 05:28:35 PM PDT 24
Peak memory 272140 kb
Host smart-0d274458-efaa-41ee-a328-af85c768cc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702954420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1702954420
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.873921317
Short name T371
Test name
Test status
Simulation time 19212132048 ps
CPU time 93.51 seconds
Started Jul 01 05:25:36 PM PDT 24
Finished Jul 01 05:27:12 PM PDT 24
Peak memory 253352 kb
Host smart-62623b95-69ab-47d8-8195-cdd72898b93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873921317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.873921317
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3505343577
Short name T148
Test name
Test status
Simulation time 60816382624 ps
CPU time 231.34 seconds
Started Jul 01 05:26:43 PM PDT 24
Finished Jul 01 05:30:37 PM PDT 24
Peak memory 270580 kb
Host smart-85dcec91-fdd3-4cca-af17-f29f34d5ef8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505343577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3505343577
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.167662009
Short name T1090
Test name
Test status
Simulation time 2484768418 ps
CPU time 7.02 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:45 PM PDT 24
Peak memory 216164 kb
Host smart-4a6687c7-82b1-4e48-b726-76b45cce2920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167662009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.167662009
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2615898862
Short name T163
Test name
Test status
Simulation time 172743676 ps
CPU time 2.72 seconds
Started Jul 01 04:34:28 PM PDT 24
Finished Jul 01 04:34:38 PM PDT 24
Peak memory 218620 kb
Host smart-e94ca402-50ea-4943-81a8-e78832b211cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615898862 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2615898862
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1226949443
Short name T275
Test name
Test status
Simulation time 44419202929 ps
CPU time 365.26 seconds
Started Jul 01 05:23:57 PM PDT 24
Finished Jul 01 05:30:05 PM PDT 24
Peak memory 263600 kb
Host smart-047ef44d-4e0b-4dd4-96e6-121e44321518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226949443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1226949443
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.490763125
Short name T314
Test name
Test status
Simulation time 10206995292 ps
CPU time 83.22 seconds
Started Jul 01 05:24:41 PM PDT 24
Finished Jul 01 05:26:08 PM PDT 24
Peak memory 252672 kb
Host smart-cb2999f9-3409-4ac7-a8ee-473ca972ef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490763125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.490763125
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4214141977
Short name T49
Test name
Test status
Simulation time 80470856344 ps
CPU time 769.67 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:37:34 PM PDT 24
Peak memory 265808 kb
Host smart-5f09b194-77cf-4de8-b4ad-5fa981941eab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214141977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4214141977
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2629201578
Short name T266
Test name
Test status
Simulation time 5920040513 ps
CPU time 63.06 seconds
Started Jul 01 05:24:47 PM PDT 24
Finished Jul 01 05:25:54 PM PDT 24
Peak memory 249288 kb
Host smart-6c6fc6e4-56d9-49a7-b9a9-6d83fef1d1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629201578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2629201578
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1470252937
Short name T587
Test name
Test status
Simulation time 1386515807 ps
CPU time 22.01 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:21 PM PDT 24
Peak memory 237116 kb
Host smart-b5e06e34-3ee9-463e-9688-dba59d186df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470252937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1470252937
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1268948467
Short name T921
Test name
Test status
Simulation time 3367502917 ps
CPU time 86.39 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:26:25 PM PDT 24
Peak memory 265656 kb
Host smart-9d25d133-aed5-4ca8-a914-2c2b3611cd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268948467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1268948467
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3135917608
Short name T31
Test name
Test status
Simulation time 123200317618 ps
CPU time 382.33 seconds
Started Jul 01 05:25:25 PM PDT 24
Finished Jul 01 05:31:54 PM PDT 24
Peak memory 270572 kb
Host smart-62ac5918-b2ab-4d89-9272-c87f5862de26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135917608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3135917608
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.557251471
Short name T269
Test name
Test status
Simulation time 199415853130 ps
CPU time 381.28 seconds
Started Jul 01 05:24:03 PM PDT 24
Finished Jul 01 05:30:27 PM PDT 24
Peak memory 264488 kb
Host smart-a18c193b-ca39-44ff-8537-c1b1e32b43de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557251471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
557251471
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2932618464
Short name T291
Test name
Test status
Simulation time 435988141 ps
CPU time 11.92 seconds
Started Jul 01 05:27:03 PM PDT 24
Finished Jul 01 05:27:16 PM PDT 24
Peak memory 232756 kb
Host smart-a6e12d7f-a2fb-4c35-a6e8-ce5dd0c9fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932618464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2932618464
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.207099204
Short name T248
Test name
Test status
Simulation time 93222821327 ps
CPU time 307.6 seconds
Started Jul 01 05:27:19 PM PDT 24
Finished Jul 01 05:32:30 PM PDT 24
Peak memory 249288 kb
Host smart-3cf4a39f-41f0-4a23-ae51-65bd76deea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207099204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.207099204
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2680444177
Short name T459
Test name
Test status
Simulation time 763872350 ps
CPU time 5.95 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:04 PM PDT 24
Peak memory 224572 kb
Host smart-a36d352d-c8e4-4931-a288-e9d7b3b56fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680444177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2680444177
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2271427497
Short name T230
Test name
Test status
Simulation time 6171485165 ps
CPU time 16.98 seconds
Started Jul 01 05:25:07 PM PDT 24
Finished Jul 01 05:25:34 PM PDT 24
Peak memory 224656 kb
Host smart-75d5cb1b-6847-4f40-8856-488dcf410367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271427497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2271427497
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2025835584
Short name T78
Test name
Test status
Simulation time 94765659 ps
CPU time 1.43 seconds
Started Jul 01 04:34:19 PM PDT 24
Finished Jul 01 04:34:30 PM PDT 24
Peak memory 207500 kb
Host smart-65c57a11-a277-424f-856b-e061913f6651
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025835584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2025835584
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2824642591
Short name T96
Test name
Test status
Simulation time 255249840 ps
CPU time 4.32 seconds
Started Jul 01 04:34:33 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 215852 kb
Host smart-8bad5b1b-7185-462f-a7e2-744054d57c87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824642591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2824642591
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2733925534
Short name T98
Test name
Test status
Simulation time 2097588026 ps
CPU time 14.19 seconds
Started Jul 01 04:34:18 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 215768 kb
Host smart-56bf1f71-78c8-4437-925b-0a4f339d5878
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733925534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2733925534
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2767797632
Short name T1089
Test name
Test status
Simulation time 115852650 ps
CPU time 7.81 seconds
Started Jul 01 04:34:15 PM PDT 24
Finished Jul 01 04:34:33 PM PDT 24
Peak memory 207500 kb
Host smart-60a333a5-f181-4535-8fd1-a90ea9cb79ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767797632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2767797632
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.80563072
Short name T1121
Test name
Test status
Simulation time 951260513 ps
CPU time 11.36 seconds
Started Jul 01 04:34:06 PM PDT 24
Finished Jul 01 04:34:23 PM PDT 24
Peak memory 215556 kb
Host smart-f521534b-0ca6-4ad8-bd8b-2ee29001ae4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80563072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
bit_bash.80563072
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1655825127
Short name T77
Test name
Test status
Simulation time 59974152 ps
CPU time 1.1 seconds
Started Jul 01 04:34:19 PM PDT 24
Finished Jul 01 04:34:30 PM PDT 24
Peak memory 207408 kb
Host smart-a82b9d4c-95a3-4635-ad87-9907d7e4e2ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655825127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1655825127
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1016955962
Short name T1100
Test name
Test status
Simulation time 96242501 ps
CPU time 1.9 seconds
Started Jul 01 04:34:19 PM PDT 24
Finished Jul 01 04:34:30 PM PDT 24
Peak memory 216652 kb
Host smart-b7234a2e-58e1-44be-9851-569c4b7d1ae7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016955962 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1016955962
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1586729525
Short name T1042
Test name
Test status
Simulation time 48588744 ps
CPU time 0.82 seconds
Started Jul 01 04:34:14 PM PDT 24
Finished Jul 01 04:34:25 PM PDT 24
Peak memory 204340 kb
Host smart-a2765eeb-6da4-4966-bb8b-5a9115de40c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586729525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
586729525
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.201689343
Short name T118
Test name
Test status
Simulation time 27683522 ps
CPU time 1.68 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:20 PM PDT 24
Peak memory 215836 kb
Host smart-3f993e72-13c3-4bb7-a5c5-03184559dc3a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201689343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.201689343
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3777312463
Short name T1048
Test name
Test status
Simulation time 25531290 ps
CPU time 0.64 seconds
Started Jul 01 04:34:17 PM PDT 24
Finished Jul 01 04:34:28 PM PDT 24
Peak memory 203988 kb
Host smart-5256cce5-ba85-4b6b-a4c4-9167d3038d14
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777312463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3777312463
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3452828577
Short name T1036
Test name
Test status
Simulation time 112079661 ps
CPU time 1.7 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:21 PM PDT 24
Peak memory 215800 kb
Host smart-2935c6d6-6e9b-4559-9ad8-526feaa31d36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452828577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3452828577
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3142908240
Short name T91
Test name
Test status
Simulation time 77562184 ps
CPU time 2.16 seconds
Started Jul 01 04:34:18 PM PDT 24
Finished Jul 01 04:34:30 PM PDT 24
Peak memory 215980 kb
Host smart-598baf41-d424-465f-8740-ec005ba341e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142908240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
142908240
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3827949570
Short name T165
Test name
Test status
Simulation time 5150330585 ps
CPU time 20.27 seconds
Started Jul 01 04:34:20 PM PDT 24
Finished Jul 01 04:34:50 PM PDT 24
Peak memory 216056 kb
Host smart-b7cc1035-8573-4f99-8ba2-d482f53cf40e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827949570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3827949570
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1931134683
Short name T1044
Test name
Test status
Simulation time 677314455 ps
CPU time 15.24 seconds
Started Jul 01 04:34:12 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 215596 kb
Host smart-b421225c-c98a-4e03-9184-25d8b80e09db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931134683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1931134683
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2102079370
Short name T1123
Test name
Test status
Simulation time 1879240711 ps
CPU time 13.59 seconds
Started Jul 01 04:34:21 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 216804 kb
Host smart-32f6f413-748b-4bd8-8816-77240fdc701e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102079370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2102079370
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1583552752
Short name T101
Test name
Test status
Simulation time 133300987 ps
CPU time 3.66 seconds
Started Jul 01 04:34:22 PM PDT 24
Finished Jul 01 04:34:34 PM PDT 24
Peak memory 217244 kb
Host smart-da09c9c7-92ce-4149-94d3-000a22f170c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583552752 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1583552752
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2478698634
Short name T1119
Test name
Test status
Simulation time 478460165 ps
CPU time 2.69 seconds
Started Jul 01 04:34:20 PM PDT 24
Finished Jul 01 04:34:32 PM PDT 24
Peak memory 207448 kb
Host smart-4a2e9319-e544-4f4f-ae8e-da59bf880ae0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478698634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
478698634
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2553536267
Short name T1098
Test name
Test status
Simulation time 12776431 ps
CPU time 0.73 seconds
Started Jul 01 04:34:08 PM PDT 24
Finished Jul 01 04:34:15 PM PDT 24
Peak memory 204660 kb
Host smart-31354482-c643-468d-98ca-972ff8d405a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553536267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
553536267
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4250571375
Short name T117
Test name
Test status
Simulation time 103205300 ps
CPU time 2 seconds
Started Jul 01 04:34:38 PM PDT 24
Finished Jul 01 04:34:47 PM PDT 24
Peak memory 215664 kb
Host smart-531032b7-9957-4384-98cd-4006b73e67c5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250571375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4250571375
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.974985023
Short name T1064
Test name
Test status
Simulation time 22899422 ps
CPU time 0.71 seconds
Started Jul 01 04:34:23 PM PDT 24
Finished Jul 01 04:34:33 PM PDT 24
Peak memory 204404 kb
Host smart-70e85d01-1bfd-4050-9e22-70b722e05666
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974985023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.974985023
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2309139835
Short name T1124
Test name
Test status
Simulation time 60975505 ps
CPU time 1.74 seconds
Started Jul 01 04:34:22 PM PDT 24
Finished Jul 01 04:34:33 PM PDT 24
Peak memory 215692 kb
Host smart-3d2414e3-8705-4357-9bf6-7a7fd4e536c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309139835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2309139835
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1336807599
Short name T138
Test name
Test status
Simulation time 145092035 ps
CPU time 3.47 seconds
Started Jul 01 04:34:25 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 218128 kb
Host smart-1336a3f7-7f5b-422b-b2f0-5bab59ae7cda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336807599 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1336807599
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2780154546
Short name T1045
Test name
Test status
Simulation time 189799774 ps
CPU time 1.31 seconds
Started Jul 01 04:34:22 PM PDT 24
Finished Jul 01 04:34:33 PM PDT 24
Peak memory 207420 kb
Host smart-3fbe21b8-3ce8-48e9-bbdb-27b14f5927fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780154546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2780154546
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1087387468
Short name T1022
Test name
Test status
Simulation time 40772556 ps
CPU time 0.71 seconds
Started Jul 01 04:34:28 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 204292 kb
Host smart-cd3ca2f3-48ce-4f0d-85e3-ba7f168512bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087387468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1087387468
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1143899715
Short name T1028
Test name
Test status
Simulation time 44935360 ps
CPU time 2.84 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 215804 kb
Host smart-0fbcd6ed-ba0b-43af-9618-f358989d7989
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143899715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1143899715
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3788457012
Short name T97
Test name
Test status
Simulation time 72600669 ps
CPU time 2.25 seconds
Started Jul 01 04:34:31 PM PDT 24
Finished Jul 01 04:34:41 PM PDT 24
Peak memory 215924 kb
Host smart-bf9bca94-4ac5-4196-9ac4-a7a14a2dba81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788457012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3788457012
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1307461528
Short name T88
Test name
Test status
Simulation time 432360354 ps
CPU time 3.42 seconds
Started Jul 01 04:34:24 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 217380 kb
Host smart-38c5aa3e-ccc8-4bbb-8a6a-9b5d7f7dfa04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307461528 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1307461528
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2258345807
Short name T1110
Test name
Test status
Simulation time 395214769 ps
CPU time 2.62 seconds
Started Jul 01 04:34:31 PM PDT 24
Finished Jul 01 04:34:41 PM PDT 24
Peak memory 207460 kb
Host smart-8c6c4c8f-0850-4918-bdc3-5bddec11a1e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258345807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2258345807
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.202680523
Short name T1021
Test name
Test status
Simulation time 15274450 ps
CPU time 0.71 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:38 PM PDT 24
Peak memory 204628 kb
Host smart-047a2c7f-9979-4025-9ec6-57b8f1b2ef56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202680523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.202680523
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3063858350
Short name T140
Test name
Test status
Simulation time 137148593 ps
CPU time 3.19 seconds
Started Jul 01 04:34:43 PM PDT 24
Finished Jul 01 04:34:57 PM PDT 24
Peak memory 215652 kb
Host smart-51199029-ae15-4223-8d7a-2613a35e7bcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063858350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3063858350
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3528185171
Short name T94
Test name
Test status
Simulation time 147062993 ps
CPU time 3.15 seconds
Started Jul 01 04:34:29 PM PDT 24
Finished Jul 01 04:34:41 PM PDT 24
Peak memory 216108 kb
Host smart-cdf4a09c-48fe-4c89-8aa3-8812755873f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528185171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3528185171
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3525490488
Short name T1095
Test name
Test status
Simulation time 271032002 ps
CPU time 7.12 seconds
Started Jul 01 04:34:34 PM PDT 24
Finished Jul 01 04:34:48 PM PDT 24
Peak memory 215884 kb
Host smart-2ccb2abf-9c38-4923-88b5-1bc2d589b7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525490488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3525490488
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.815150286
Short name T1056
Test name
Test status
Simulation time 84890941 ps
CPU time 2.43 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:54 PM PDT 24
Peak memory 215988 kb
Host smart-95a4caaa-3ad7-42e9-a115-5b3739bb6785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815150286 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.815150286
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2905134211
Short name T120
Test name
Test status
Simulation time 26791644 ps
CPU time 1.77 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 215620 kb
Host smart-85ded335-15ae-4d34-aec4-3af3044bc74f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905134211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2905134211
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2448473180
Short name T1026
Test name
Test status
Simulation time 15208631 ps
CPU time 0.72 seconds
Started Jul 01 04:34:22 PM PDT 24
Finished Jul 01 04:34:32 PM PDT 24
Peak memory 204280 kb
Host smart-59f10ccf-f138-498a-8fe4-6c66de48b30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448473180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2448473180
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2363398770
Short name T1051
Test name
Test status
Simulation time 112254621 ps
CPU time 2.93 seconds
Started Jul 01 04:34:24 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 215668 kb
Host smart-e479c710-221b-4e9f-b8bc-4f5ed090e511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363398770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2363398770
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2399498291
Short name T1062
Test name
Test status
Simulation time 729472159 ps
CPU time 7 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:45 PM PDT 24
Peak memory 215700 kb
Host smart-758360fb-90c1-41f1-9439-8b9be46da839
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399498291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2399498291
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1423532081
Short name T106
Test name
Test status
Simulation time 154415002 ps
CPU time 2.81 seconds
Started Jul 01 04:34:32 PM PDT 24
Finished Jul 01 04:34:42 PM PDT 24
Peak memory 217464 kb
Host smart-2191d59e-acb1-4b80-bd6e-8e63f93193cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423532081 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1423532081
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2027854587
Short name T1091
Test name
Test status
Simulation time 345731610 ps
CPU time 1.26 seconds
Started Jul 01 04:34:27 PM PDT 24
Finished Jul 01 04:34:36 PM PDT 24
Peak memory 207404 kb
Host smart-e75474fd-d2e7-44de-a9d2-d531b80a0600
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027854587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2027854587
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3721601558
Short name T1127
Test name
Test status
Simulation time 18855057 ps
CPU time 0.78 seconds
Started Jul 01 04:34:33 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 204616 kb
Host smart-dde84751-08e9-462b-81df-21dfb28ca742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721601558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3721601558
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1542815918
Short name T129
Test name
Test status
Simulation time 103280529 ps
CPU time 3.26 seconds
Started Jul 01 04:34:28 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 215696 kb
Host smart-0235e6f1-d72b-4c69-af8d-b22829a51f6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542815918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1542815918
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1144820124
Short name T93
Test name
Test status
Simulation time 369403320 ps
CPU time 3.97 seconds
Started Jul 01 04:34:26 PM PDT 24
Finished Jul 01 04:34:38 PM PDT 24
Peak memory 215972 kb
Host smart-cc0c5b5f-43cf-4731-ba67-133c21c7d599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144820124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1144820124
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.682008956
Short name T60
Test name
Test status
Simulation time 741155880 ps
CPU time 11.66 seconds
Started Jul 01 04:34:22 PM PDT 24
Finished Jul 01 04:34:43 PM PDT 24
Peak memory 216040 kb
Host smart-f3897616-3eb0-4177-814a-3092e6fef324
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682008956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.682008956
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2087451579
Short name T100
Test name
Test status
Simulation time 84354621 ps
CPU time 3.19 seconds
Started Jul 01 04:34:29 PM PDT 24
Finished Jul 01 04:34:41 PM PDT 24
Peak memory 218212 kb
Host smart-bd506071-cad3-4305-aca0-10dfef7d1d20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087451579 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2087451579
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1784773135
Short name T114
Test name
Test status
Simulation time 77441166 ps
CPU time 2.1 seconds
Started Jul 01 04:34:31 PM PDT 24
Finished Jul 01 04:34:41 PM PDT 24
Peak memory 220336 kb
Host smart-e80bfe6f-55d3-42bc-bd6a-1e9ef1add953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784773135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1784773135
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2745123481
Short name T1031
Test name
Test status
Simulation time 13250619 ps
CPU time 0.71 seconds
Started Jul 01 04:34:22 PM PDT 24
Finished Jul 01 04:34:31 PM PDT 24
Peak memory 204604 kb
Host smart-241b56b2-6f8d-4162-a531-f8913c6cc66e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745123481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2745123481
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3331621335
Short name T1029
Test name
Test status
Simulation time 1050295510 ps
CPU time 2.92 seconds
Started Jul 01 04:34:24 PM PDT 24
Finished Jul 01 04:34:36 PM PDT 24
Peak memory 215836 kb
Host smart-805f4fc7-7776-4765-802b-ccdd1a23c3e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331621335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3331621335
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2109829443
Short name T1087
Test name
Test status
Simulation time 193949665 ps
CPU time 4.32 seconds
Started Jul 01 04:34:36 PM PDT 24
Finished Jul 01 04:34:46 PM PDT 24
Peak memory 216084 kb
Host smart-1b612e6b-e460-4db7-af90-1d535a5c5711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109829443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2109829443
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3766251773
Short name T1105
Test name
Test status
Simulation time 1395799211 ps
CPU time 15.19 seconds
Started Jul 01 04:34:27 PM PDT 24
Finished Jul 01 04:34:50 PM PDT 24
Peak memory 215792 kb
Host smart-3bdaa7a9-ce03-4635-84aa-35d673d11e31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766251773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3766251773
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3286986464
Short name T1128
Test name
Test status
Simulation time 71985117 ps
CPU time 2.02 seconds
Started Jul 01 04:34:42 PM PDT 24
Finished Jul 01 04:34:55 PM PDT 24
Peak memory 215620 kb
Host smart-594fc435-ab8b-43bb-a2ee-469d251ee422
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286986464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3286986464
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1364075808
Short name T1118
Test name
Test status
Simulation time 111946606 ps
CPU time 0.71 seconds
Started Jul 01 04:34:25 PM PDT 24
Finished Jul 01 04:34:35 PM PDT 24
Peak memory 204280 kb
Host smart-3bc13c8c-cb6f-4aaa-a6ec-92eaec640836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364075808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1364075808
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3875201877
Short name T1055
Test name
Test status
Simulation time 61363206 ps
CPU time 1.9 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 215796 kb
Host smart-efd38962-7bea-48e2-b8a2-69ab26dfc261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875201877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3875201877
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.744918696
Short name T1059
Test name
Test status
Simulation time 415510546 ps
CPU time 6.59 seconds
Started Jul 01 04:34:29 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 215864 kb
Host smart-db7f777b-f865-4821-89b6-8b2af67248e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744918696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.744918696
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3894946933
Short name T1035
Test name
Test status
Simulation time 101338364 ps
CPU time 2.22 seconds
Started Jul 01 04:34:29 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 216992 kb
Host smart-a1c4e24d-dd90-4f1b-91ff-00234c1f50b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894946933 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3894946933
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.252413245
Short name T1047
Test name
Test status
Simulation time 30944545 ps
CPU time 1.9 seconds
Started Jul 01 04:34:28 PM PDT 24
Finished Jul 01 04:34:38 PM PDT 24
Peak memory 215700 kb
Host smart-6a55e9c0-0566-4c36-974e-5d7892292674
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252413245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.252413245
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3462221895
Short name T1038
Test name
Test status
Simulation time 31182891 ps
CPU time 0.7 seconds
Started Jul 01 04:34:31 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 204524 kb
Host smart-7be372e1-88c9-46b0-924d-cd6038e3c3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462221895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3462221895
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1086735120
Short name T1113
Test name
Test status
Simulation time 586665491 ps
CPU time 4.13 seconds
Started Jul 01 04:34:28 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 215576 kb
Host smart-30fb6e92-70a0-4646-85ef-1218272c62c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086735120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1086735120
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1864818688
Short name T104
Test name
Test status
Simulation time 278833991 ps
CPU time 2.97 seconds
Started Jul 01 04:34:46 PM PDT 24
Finished Jul 01 04:35:00 PM PDT 24
Peak memory 216060 kb
Host smart-d6843669-af61-46de-8ffe-11b73a87f281
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864818688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1864818688
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2142665858
Short name T168
Test name
Test status
Simulation time 310556999 ps
CPU time 18.29 seconds
Started Jul 01 04:34:28 PM PDT 24
Finished Jul 01 04:34:55 PM PDT 24
Peak memory 215896 kb
Host smart-33029b04-5b95-490a-8beb-f0768efcf7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142665858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2142665858
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3697489227
Short name T89
Test name
Test status
Simulation time 175525236 ps
CPU time 1.58 seconds
Started Jul 01 04:34:39 PM PDT 24
Finished Jul 01 04:34:49 PM PDT 24
Peak memory 215864 kb
Host smart-509f7959-068f-4eab-a770-6a0479a7f565
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697489227 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3697489227
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2364882347
Short name T116
Test name
Test status
Simulation time 124666012 ps
CPU time 2.22 seconds
Started Jul 01 04:34:27 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 215508 kb
Host smart-3aa08568-a987-4c1f-9c63-1605f11c2528
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364882347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2364882347
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.50428200
Short name T1050
Test name
Test status
Simulation time 30355998 ps
CPU time 0.76 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:53 PM PDT 24
Peak memory 204420 kb
Host smart-be09deb2-ff9e-45a7-899a-f75789ec4c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50428200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.50428200
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.311731372
Short name T130
Test name
Test status
Simulation time 59470340 ps
CPU time 3.69 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:42 PM PDT 24
Peak memory 215568 kb
Host smart-1a4fca4b-286a-4502-a65f-69ebd44c24b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311731372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.311731372
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.112077984
Short name T99
Test name
Test status
Simulation time 424773210 ps
CPU time 2.87 seconds
Started Jul 01 04:34:35 PM PDT 24
Finished Jul 01 04:34:45 PM PDT 24
Peak memory 215964 kb
Host smart-e200030d-35d1-4719-a5c2-7843dad49a0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112077984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.112077984
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1623199963
Short name T103
Test name
Test status
Simulation time 89782448 ps
CPU time 2.87 seconds
Started Jul 01 04:34:29 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 216780 kb
Host smart-4ea58040-fe55-40e8-891e-9a25275f0fbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623199963 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1623199963
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2207640223
Short name T1099
Test name
Test status
Simulation time 124131723 ps
CPU time 2.01 seconds
Started Jul 01 04:34:34 PM PDT 24
Finished Jul 01 04:34:42 PM PDT 24
Peak memory 207452 kb
Host smart-33857ffa-7e50-4868-81be-72af90bab130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207640223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2207640223
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1328938159
Short name T1054
Test name
Test status
Simulation time 21989484 ps
CPU time 0.75 seconds
Started Jul 01 04:34:34 PM PDT 24
Finished Jul 01 04:34:41 PM PDT 24
Peak memory 204148 kb
Host smart-9c236ca5-9b63-431e-aa12-b4a760b8ab53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328938159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1328938159
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2419002633
Short name T1097
Test name
Test status
Simulation time 202179758 ps
CPU time 1.71 seconds
Started Jul 01 04:34:37 PM PDT 24
Finished Jul 01 04:34:46 PM PDT 24
Peak memory 215768 kb
Host smart-c3833f2f-ca89-42dd-8a5e-16cb85c97824
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419002633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2419002633
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1985579624
Short name T105
Test name
Test status
Simulation time 89518264 ps
CPU time 1.56 seconds
Started Jul 01 04:34:45 PM PDT 24
Finished Jul 01 04:34:57 PM PDT 24
Peak memory 215988 kb
Host smart-1214e024-41c9-4085-a661-a1730f41e886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985579624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1985579624
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1638162374
Short name T1117
Test name
Test status
Simulation time 1076089805 ps
CPU time 13.95 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:52 PM PDT 24
Peak memory 216080 kb
Host smart-b586f5dc-57d1-48c4-869b-4fdc348b3060
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638162374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1638162374
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2380466727
Short name T1071
Test name
Test status
Simulation time 57484614 ps
CPU time 1.75 seconds
Started Jul 01 04:34:29 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 215988 kb
Host smart-d7700a1e-2d6a-4594-80a3-b9282b5c4e27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380466727 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2380466727
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3074799630
Short name T112
Test name
Test status
Simulation time 930460449 ps
CPU time 1.87 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:53 PM PDT 24
Peak memory 207444 kb
Host smart-5fee704e-2536-4506-8e03-3c28d0eb2ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074799630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3074799630
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3847357882
Short name T1116
Test name
Test status
Simulation time 27803819 ps
CPU time 0.77 seconds
Started Jul 01 04:34:27 PM PDT 24
Finished Jul 01 04:34:36 PM PDT 24
Peak memory 204288 kb
Host smart-71579709-07d9-42bc-bbec-6a93ddb9f57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847357882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3847357882
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1330390644
Short name T160
Test name
Test status
Simulation time 73233673 ps
CPU time 1.83 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 216176 kb
Host smart-442efba4-4ef3-4428-b76b-f99c39a4d161
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330390644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1330390644
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.603637724
Short name T1126
Test name
Test status
Simulation time 176043980 ps
CPU time 4.75 seconds
Started Jul 01 04:34:31 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 215916 kb
Host smart-c320e4cd-7ef5-45b1-a714-bd98ca26b2b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603637724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.603637724
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1411717212
Short name T166
Test name
Test status
Simulation time 551881654 ps
CPU time 7.62 seconds
Started Jul 01 04:34:31 PM PDT 24
Finished Jul 01 04:34:47 PM PDT 24
Peak memory 216384 kb
Host smart-57b001d3-49fe-4cb0-8be1-1a43830ea579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411717212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1411717212
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1818703301
Short name T1039
Test name
Test status
Simulation time 847218025 ps
CPU time 15.06 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:34:36 PM PDT 24
Peak memory 207424 kb
Host smart-bcea4d7c-bcfb-4d7f-bb05-c06755fc78db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818703301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1818703301
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4016773046
Short name T1068
Test name
Test status
Simulation time 3671873405 ps
CPU time 34.67 seconds
Started Jul 01 04:34:23 PM PDT 24
Finished Jul 01 04:35:07 PM PDT 24
Peak memory 207688 kb
Host smart-5b24ff2f-7b66-4130-904b-aa94ecb59146
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016773046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4016773046
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.799400356
Short name T79
Test name
Test status
Simulation time 18208263 ps
CPU time 0.91 seconds
Started Jul 01 04:34:22 PM PDT 24
Finished Jul 01 04:34:31 PM PDT 24
Peak memory 207152 kb
Host smart-4ac730ba-dff9-4e68-b459-a3615f18dbf9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799400356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.799400356
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1253918545
Short name T108
Test name
Test status
Simulation time 27140060 ps
CPU time 1.62 seconds
Started Jul 01 04:34:17 PM PDT 24
Finished Jul 01 04:34:29 PM PDT 24
Peak memory 215740 kb
Host smart-4ba959c6-6037-4f65-b336-4c1ae6903ebb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253918545 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1253918545
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2545942026
Short name T1043
Test name
Test status
Simulation time 110498387 ps
CPU time 1.85 seconds
Started Jul 01 04:34:23 PM PDT 24
Finished Jul 01 04:34:34 PM PDT 24
Peak memory 215724 kb
Host smart-85103244-917b-4716-bf05-cdeaba73b637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545942026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
545942026
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.155861894
Short name T1107
Test name
Test status
Simulation time 28868186 ps
CPU time 0.79 seconds
Started Jul 01 04:34:14 PM PDT 24
Finished Jul 01 04:34:25 PM PDT 24
Peak memory 204192 kb
Host smart-38ada55f-0c1f-44ea-82d7-fda87b69d7c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155861894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.155861894
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.611017653
Short name T113
Test name
Test status
Simulation time 112513757 ps
CPU time 1.71 seconds
Started Jul 01 04:34:13 PM PDT 24
Finished Jul 01 04:34:25 PM PDT 24
Peak memory 215656 kb
Host smart-91ab74fb-1982-4a57-b4f5-4c40f31b9477
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611017653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.611017653
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1160816433
Short name T1103
Test name
Test status
Simulation time 76864025 ps
CPU time 0.65 seconds
Started Jul 01 04:34:18 PM PDT 24
Finished Jul 01 04:34:28 PM PDT 24
Peak memory 203980 kb
Host smart-c6188743-4961-4ffa-a386-0823ce255756
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160816433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1160816433
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2263267815
Short name T1075
Test name
Test status
Simulation time 239897561 ps
CPU time 3.97 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:34:25 PM PDT 24
Peak memory 215676 kb
Host smart-6d5fbe14-d9f1-428f-a6c5-bc427f62c57b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263267815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2263267815
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.307859762
Short name T95
Test name
Test status
Simulation time 349120271 ps
CPU time 3.55 seconds
Started Jul 01 04:34:09 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 215888 kb
Host smart-b140d96d-ef39-43f8-bb35-bc3c92a464dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307859762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.307859762
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1842602887
Short name T1058
Test name
Test status
Simulation time 476099178 ps
CPU time 6.19 seconds
Started Jul 01 04:34:11 PM PDT 24
Finished Jul 01 04:34:27 PM PDT 24
Peak memory 215864 kb
Host smart-32f96422-eb19-4d96-8df3-bc6a9100beb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842602887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1842602887
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4123158452
Short name T1053
Test name
Test status
Simulation time 13243430 ps
CPU time 0.71 seconds
Started Jul 01 04:34:44 PM PDT 24
Finished Jul 01 04:34:55 PM PDT 24
Peak memory 204280 kb
Host smart-e13197a4-385d-402c-93e1-b86705b6d06c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123158452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4123158452
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3598084834
Short name T1066
Test name
Test status
Simulation time 21084083 ps
CPU time 0.75 seconds
Started Jul 01 04:34:40 PM PDT 24
Finished Jul 01 04:34:50 PM PDT 24
Peak memory 204268 kb
Host smart-b19088a0-1e7d-4fa1-adb5-16615014bf62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598084834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3598084834
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2014298030
Short name T1033
Test name
Test status
Simulation time 15682097 ps
CPU time 0.7 seconds
Started Jul 01 04:34:40 PM PDT 24
Finished Jul 01 04:34:50 PM PDT 24
Peak memory 204456 kb
Host smart-261c71bb-44d7-4702-a0e6-cf6283c1ea46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014298030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2014298030
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1017952095
Short name T1094
Test name
Test status
Simulation time 27867639 ps
CPU time 0.75 seconds
Started Jul 01 04:34:38 PM PDT 24
Finished Jul 01 04:34:48 PM PDT 24
Peak memory 204328 kb
Host smart-d01271f6-321b-4e84-8c67-cc27afc92845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017952095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1017952095
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3467450860
Short name T1034
Test name
Test status
Simulation time 37748337 ps
CPU time 0.71 seconds
Started Jul 01 04:34:36 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 204308 kb
Host smart-35ac77c9-a1b3-448a-ab20-2446abe51644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467450860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3467450860
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.371535883
Short name T1080
Test name
Test status
Simulation time 42300769 ps
CPU time 0.73 seconds
Started Jul 01 04:34:36 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 204604 kb
Host smart-00269191-91f6-4b77-8772-48e4b3e26c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371535883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.371535883
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3527351968
Short name T1069
Test name
Test status
Simulation time 33853125 ps
CPU time 0.7 seconds
Started Jul 01 04:34:36 PM PDT 24
Finished Jul 01 04:34:43 PM PDT 24
Peak memory 204284 kb
Host smart-5ba078e2-a519-40f3-bf9d-10f71c5310b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527351968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3527351968
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1715255893
Short name T1024
Test name
Test status
Simulation time 15779927 ps
CPU time 0.76 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:53 PM PDT 24
Peak memory 204676 kb
Host smart-daae4561-e9eb-468a-aee4-f91e8ed25aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715255893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1715255893
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2720388680
Short name T1020
Test name
Test status
Simulation time 18210032 ps
CPU time 0.75 seconds
Started Jul 01 04:34:39 PM PDT 24
Finished Jul 01 04:34:50 PM PDT 24
Peak memory 204604 kb
Host smart-0febc3d7-b1fb-424c-a285-8f1c1bc35950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720388680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2720388680
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3014547011
Short name T1061
Test name
Test status
Simulation time 45331982 ps
CPU time 0.69 seconds
Started Jul 01 04:34:45 PM PDT 24
Finished Jul 01 04:34:56 PM PDT 24
Peak memory 204284 kb
Host smart-71edfc56-fa27-4b49-8995-3719dbc93e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014547011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3014547011
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1811772574
Short name T1076
Test name
Test status
Simulation time 231252843 ps
CPU time 8.24 seconds
Started Jul 01 04:34:26 PM PDT 24
Finished Jul 01 04:34:43 PM PDT 24
Peak memory 207516 kb
Host smart-dc4dff30-059d-4d18-ba16-af3f687c57cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811772574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1811772574
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2977037902
Short name T1111
Test name
Test status
Simulation time 8676234725 ps
CPU time 12.47 seconds
Started Jul 01 04:34:27 PM PDT 24
Finished Jul 01 04:34:48 PM PDT 24
Peak memory 207568 kb
Host smart-0a4066a5-c66a-4d6f-a6f1-b43e82ba95f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977037902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2977037902
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1365229247
Short name T80
Test name
Test status
Simulation time 35356424 ps
CPU time 1.14 seconds
Started Jul 01 04:34:12 PM PDT 24
Finished Jul 01 04:34:23 PM PDT 24
Peak memory 207476 kb
Host smart-057405fd-0de7-4d9d-bf7e-a029c9faf785
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365229247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1365229247
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3721865598
Short name T87
Test name
Test status
Simulation time 44942713 ps
CPU time 3.04 seconds
Started Jul 01 04:34:14 PM PDT 24
Finished Jul 01 04:34:28 PM PDT 24
Peak memory 217784 kb
Host smart-8746f631-5aa1-4b6b-94c1-3d756f96833e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721865598 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3721865598
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3987221668
Short name T124
Test name
Test status
Simulation time 68036442 ps
CPU time 1.29 seconds
Started Jul 01 04:34:15 PM PDT 24
Finished Jul 01 04:34:27 PM PDT 24
Peak memory 207500 kb
Host smart-2153aa50-cfad-4594-a911-d395713c174a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987221668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
987221668
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1016547097
Short name T1027
Test name
Test status
Simulation time 30893039 ps
CPU time 0.74 seconds
Started Jul 01 04:34:10 PM PDT 24
Finished Jul 01 04:34:19 PM PDT 24
Peak memory 204192 kb
Host smart-a3f33354-e4a2-4e2b-9420-e8ef9307ac06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016547097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
016547097
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3456188301
Short name T115
Test name
Test status
Simulation time 27621196 ps
CPU time 1.91 seconds
Started Jul 01 04:34:29 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 215704 kb
Host smart-c0a9d5ed-91a6-4483-b952-5fe3d34c0c87
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456188301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3456188301
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2561741037
Short name T1072
Test name
Test status
Simulation time 59141803 ps
CPU time 0.63 seconds
Started Jul 01 04:34:28 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 204060 kb
Host smart-535ac4cd-beb6-406d-9fe1-952ac7348531
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561741037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2561741037
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3911235101
Short name T1073
Test name
Test status
Simulation time 454267349 ps
CPU time 2.73 seconds
Started Jul 01 04:34:23 PM PDT 24
Finished Jul 01 04:34:35 PM PDT 24
Peak memory 215700 kb
Host smart-d5c5f05f-5b0b-4dd3-ab84-90dafe978c72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911235101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3911235101
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.972935364
Short name T1109
Test name
Test status
Simulation time 373608034 ps
CPU time 2.19 seconds
Started Jul 01 04:34:08 PM PDT 24
Finished Jul 01 04:34:16 PM PDT 24
Peak memory 215908 kb
Host smart-59b22f75-628f-48cd-b318-14e21818894a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972935364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.972935364
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.714301497
Short name T1057
Test name
Test status
Simulation time 42047702 ps
CPU time 0.74 seconds
Started Jul 01 04:34:42 PM PDT 24
Finished Jul 01 04:34:54 PM PDT 24
Peak memory 204280 kb
Host smart-c01cf94e-540a-430a-857e-69ea4a82ca74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714301497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.714301497
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3150294094
Short name T1023
Test name
Test status
Simulation time 38129462 ps
CPU time 0.67 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:52 PM PDT 24
Peak memory 204204 kb
Host smart-ece38e41-aac9-4c04-b0e1-b5b50af5d968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150294094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3150294094
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2621445692
Short name T1040
Test name
Test status
Simulation time 41412368 ps
CPU time 0.75 seconds
Started Jul 01 04:34:33 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 204276 kb
Host smart-9269cae4-009c-4c62-aa1e-fdf44a6153ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621445692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2621445692
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4155483226
Short name T1092
Test name
Test status
Simulation time 41660061 ps
CPU time 0.77 seconds
Started Jul 01 04:34:47 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 204444 kb
Host smart-55b9e2ef-8e80-422d-b1a7-80071d99f78f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155483226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4155483226
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1029556523
Short name T1060
Test name
Test status
Simulation time 64062849 ps
CPU time 0.76 seconds
Started Jul 01 04:34:35 PM PDT 24
Finished Jul 01 04:34:42 PM PDT 24
Peak memory 204284 kb
Host smart-e558ecb1-f5f7-4051-8288-c1f3bac69223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029556523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1029556523
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2472172986
Short name T1079
Test name
Test status
Simulation time 17383534 ps
CPU time 0.7 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:51 PM PDT 24
Peak memory 204604 kb
Host smart-92b4fa70-4ffd-42dd-9ddc-d4a1f066383f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472172986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2472172986
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1863247487
Short name T1077
Test name
Test status
Simulation time 60404525 ps
CPU time 0.72 seconds
Started Jul 01 04:34:45 PM PDT 24
Finished Jul 01 04:34:56 PM PDT 24
Peak memory 204276 kb
Host smart-c0e95f19-f76b-464e-837f-68898f68daca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863247487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1863247487
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1565826601
Short name T1104
Test name
Test status
Simulation time 42336243 ps
CPU time 0.73 seconds
Started Jul 01 04:34:45 PM PDT 24
Finished Jul 01 04:34:56 PM PDT 24
Peak memory 204328 kb
Host smart-67586b45-370d-40e6-bff3-56c7819ff355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565826601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1565826601
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.185713921
Short name T1129
Test name
Test status
Simulation time 12758208 ps
CPU time 0.69 seconds
Started Jul 01 04:34:36 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 204276 kb
Host smart-d5324932-d5fe-4a48-9e89-2c67762e251f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185713921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.185713921
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3131649149
Short name T1086
Test name
Test status
Simulation time 71026071 ps
CPU time 0.75 seconds
Started Jul 01 04:34:32 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 204184 kb
Host smart-37aaac4d-63bb-4836-b7b2-7e726d85ef35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131649149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3131649149
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3940943092
Short name T121
Test name
Test status
Simulation time 398118999 ps
CPU time 7.31 seconds
Started Jul 01 04:34:14 PM PDT 24
Finished Jul 01 04:34:32 PM PDT 24
Peak memory 207492 kb
Host smart-acd97ebb-2b87-4437-b4e1-69146e185091
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940943092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3940943092
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.863006972
Short name T137
Test name
Test status
Simulation time 1333512514 ps
CPU time 12.67 seconds
Started Jul 01 04:34:33 PM PDT 24
Finished Jul 01 04:34:52 PM PDT 24
Peak memory 207408 kb
Host smart-949b35a2-28c5-4a1c-84bd-b7defdc85734
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863006972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.863006972
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3750951129
Short name T1025
Test name
Test status
Simulation time 22697886 ps
CPU time 0.98 seconds
Started Jul 01 04:34:17 PM PDT 24
Finished Jul 01 04:34:28 PM PDT 24
Peak memory 207212 kb
Host smart-d3feb53c-7d9a-49e4-8143-22a459468904
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750951129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3750951129
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2702229009
Short name T159
Test name
Test status
Simulation time 102246438 ps
CPU time 1.76 seconds
Started Jul 01 04:34:15 PM PDT 24
Finished Jul 01 04:34:27 PM PDT 24
Peak memory 216956 kb
Host smart-494ab64b-fa5c-4762-b10b-e1723d5146b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702229009 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2702229009
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1883804371
Short name T1084
Test name
Test status
Simulation time 174864607 ps
CPU time 2.46 seconds
Started Jul 01 04:34:17 PM PDT 24
Finished Jul 01 04:34:29 PM PDT 24
Peak memory 215640 kb
Host smart-b459a616-9d4a-4c12-a1f2-96b7072da1f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883804371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
883804371
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2479907316
Short name T1093
Test name
Test status
Simulation time 14673191 ps
CPU time 0.74 seconds
Started Jul 01 04:34:27 PM PDT 24
Finished Jul 01 04:34:36 PM PDT 24
Peak memory 204288 kb
Host smart-caa01967-deba-48a6-bc25-277ec87110b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479907316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
479907316
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1752817164
Short name T1083
Test name
Test status
Simulation time 30898693 ps
CPU time 1.32 seconds
Started Jul 01 04:34:29 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 215676 kb
Host smart-aabf236f-8b1d-40f3-8258-4ae3d45a3e72
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752817164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1752817164
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1794350968
Short name T1108
Test name
Test status
Simulation time 40870731 ps
CPU time 0.64 seconds
Started Jul 01 04:34:13 PM PDT 24
Finished Jul 01 04:34:24 PM PDT 24
Peak memory 204048 kb
Host smart-153e15d0-6b22-4763-954c-c2d1aba21ec4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794350968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1794350968
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1918996708
Short name T139
Test name
Test status
Simulation time 809370284 ps
CPU time 4.17 seconds
Started Jul 01 04:34:27 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 215652 kb
Host smart-09e5e4cc-603c-4b52-bcdd-3404ba229b01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918996708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1918996708
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3016465993
Short name T1112
Test name
Test status
Simulation time 43666184 ps
CPU time 1.48 seconds
Started Jul 01 04:34:27 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 215988 kb
Host smart-c0df81d2-b5ad-445f-a4e0-dac4e3f33034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016465993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
016465993
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3164888369
Short name T61
Test name
Test status
Simulation time 1184589214 ps
CPU time 18.28 seconds
Started Jul 01 04:34:26 PM PDT 24
Finished Jul 01 04:34:53 PM PDT 24
Peak memory 216072 kb
Host smart-ed71501b-cbe5-4885-9055-268b62fa8778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164888369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3164888369
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2874206781
Short name T1082
Test name
Test status
Simulation time 13113631 ps
CPU time 0.74 seconds
Started Jul 01 04:34:40 PM PDT 24
Finished Jul 01 04:34:50 PM PDT 24
Peak memory 204208 kb
Host smart-50e7acaf-93fd-41de-945d-542505b91043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874206781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2874206781
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.423564899
Short name T1114
Test name
Test status
Simulation time 31791534 ps
CPU time 0.72 seconds
Started Jul 01 04:34:48 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 204276 kb
Host smart-2dcf35f8-d3fc-4540-8b9f-dd01432b086a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423564899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.423564899
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3886927410
Short name T1030
Test name
Test status
Simulation time 56058907 ps
CPU time 0.75 seconds
Started Jul 01 04:34:38 PM PDT 24
Finished Jul 01 04:34:48 PM PDT 24
Peak memory 204288 kb
Host smart-74dca1f5-42f2-4278-bd6f-01902a9d97d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886927410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3886927410
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3298601021
Short name T1130
Test name
Test status
Simulation time 32355720 ps
CPU time 0.76 seconds
Started Jul 01 04:34:43 PM PDT 24
Finished Jul 01 04:34:55 PM PDT 24
Peak memory 204236 kb
Host smart-e69c23b9-0239-41b1-994a-eb0a89574214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298601021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3298601021
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2124678446
Short name T1049
Test name
Test status
Simulation time 13961351 ps
CPU time 0.68 seconds
Started Jul 01 04:34:41 PM PDT 24
Finished Jul 01 04:34:52 PM PDT 24
Peak memory 204312 kb
Host smart-415c0a92-2a76-4d9f-b1f7-d87eca0ceefa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124678446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2124678446
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2494859799
Short name T1046
Test name
Test status
Simulation time 10839029 ps
CPU time 0.67 seconds
Started Jul 01 04:34:37 PM PDT 24
Finished Jul 01 04:34:45 PM PDT 24
Peak memory 204284 kb
Host smart-ca105c02-38a9-4780-958f-cb7b439b4ef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494859799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2494859799
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2848183912
Short name T1070
Test name
Test status
Simulation time 18823947 ps
CPU time 0.79 seconds
Started Jul 01 04:34:45 PM PDT 24
Finished Jul 01 04:34:56 PM PDT 24
Peak memory 204328 kb
Host smart-7b2d14da-e75b-41ce-ac4a-dd936f232543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848183912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2848183912
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2776391899
Short name T1074
Test name
Test status
Simulation time 35209698 ps
CPU time 0.72 seconds
Started Jul 01 04:34:44 PM PDT 24
Finished Jul 01 04:34:55 PM PDT 24
Peak memory 204604 kb
Host smart-c78edee8-4f2e-4334-bc99-3f87a6a7c153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776391899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2776391899
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3573678514
Short name T1085
Test name
Test status
Simulation time 14987877 ps
CPU time 0.73 seconds
Started Jul 01 04:34:47 PM PDT 24
Finished Jul 01 04:34:57 PM PDT 24
Peak memory 204288 kb
Host smart-46b69a68-4107-46e0-892e-0e56e844affa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573678514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3573678514
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3223689041
Short name T1032
Test name
Test status
Simulation time 37074945 ps
CPU time 0.72 seconds
Started Jul 01 04:34:46 PM PDT 24
Finished Jul 01 04:34:57 PM PDT 24
Peak memory 204172 kb
Host smart-b5024838-de17-49b1-af47-750cd574122b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223689041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3223689041
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1118759125
Short name T102
Test name
Test status
Simulation time 647116933 ps
CPU time 4.09 seconds
Started Jul 01 04:34:20 PM PDT 24
Finished Jul 01 04:34:34 PM PDT 24
Peak memory 218692 kb
Host smart-2e7c9dd0-aeae-483b-bbe9-d4652acf2388
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118759125 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1118759125
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.566207714
Short name T123
Test name
Test status
Simulation time 187463004 ps
CPU time 2.65 seconds
Started Jul 01 04:34:13 PM PDT 24
Finished Jul 01 04:34:26 PM PDT 24
Peak memory 215736 kb
Host smart-dc79bbd7-286b-423a-b0e3-b1cee01b2218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566207714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.566207714
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2293871346
Short name T1067
Test name
Test status
Simulation time 33260070 ps
CPU time 0.75 seconds
Started Jul 01 04:34:14 PM PDT 24
Finished Jul 01 04:34:26 PM PDT 24
Peak memory 204464 kb
Host smart-aafb6861-938a-4906-8fbf-f2578eac870b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293871346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
293871346
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.269651807
Short name T1088
Test name
Test status
Simulation time 119415892 ps
CPU time 3.76 seconds
Started Jul 01 04:34:26 PM PDT 24
Finished Jul 01 04:34:39 PM PDT 24
Peak memory 216040 kb
Host smart-88d06593-571c-41f7-bd63-f2fc2da386f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269651807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.269651807
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2874904011
Short name T92
Test name
Test status
Simulation time 271113424 ps
CPU time 4.19 seconds
Started Jul 01 04:34:29 PM PDT 24
Finished Jul 01 04:34:41 PM PDT 24
Peak memory 215932 kb
Host smart-d0d8608f-a5fd-4ff7-a739-81d3290a8aec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874904011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
874904011
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3156562516
Short name T59
Test name
Test status
Simulation time 1175985723 ps
CPU time 19 seconds
Started Jul 01 04:34:17 PM PDT 24
Finished Jul 01 04:34:46 PM PDT 24
Peak memory 215768 kb
Host smart-724df9f0-8d3e-44f8-a657-e2bb066420a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156562516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3156562516
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2268008574
Short name T1041
Test name
Test status
Simulation time 31575274 ps
CPU time 1.82 seconds
Started Jul 01 04:34:25 PM PDT 24
Finished Jul 01 04:34:36 PM PDT 24
Peak memory 215948 kb
Host smart-386380e0-8b52-40a8-bc11-1e6544025fe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268008574 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2268008574
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.904667701
Short name T1081
Test name
Test status
Simulation time 100357845 ps
CPU time 1.35 seconds
Started Jul 01 04:34:12 PM PDT 24
Finished Jul 01 04:34:23 PM PDT 24
Peak memory 215624 kb
Host smart-187df5fb-c0ba-4dac-a6a9-cc2454e32d05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904667701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.904667701
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2688590008
Short name T1115
Test name
Test status
Simulation time 55881345 ps
CPU time 0.71 seconds
Started Jul 01 04:34:21 PM PDT 24
Finished Jul 01 04:34:31 PM PDT 24
Peak memory 204216 kb
Host smart-b058cc7d-29ad-410d-a275-8688eb6c4eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688590008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
688590008
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1921908274
Short name T136
Test name
Test status
Simulation time 127283337 ps
CPU time 2.89 seconds
Started Jul 01 04:34:17 PM PDT 24
Finished Jul 01 04:34:30 PM PDT 24
Peak memory 215724 kb
Host smart-8e098192-cae6-4b27-8e04-6df4385addb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921908274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1921908274
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3480118633
Short name T143
Test name
Test status
Simulation time 179480955 ps
CPU time 1.47 seconds
Started Jul 01 04:34:25 PM PDT 24
Finished Jul 01 04:34:35 PM PDT 24
Peak memory 215912 kb
Host smart-aa7d2415-8918-4bcf-b05d-e6db72ebba4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480118633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
480118633
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3623388786
Short name T1101
Test name
Test status
Simulation time 557922893 ps
CPU time 7.73 seconds
Started Jul 01 04:34:21 PM PDT 24
Finished Jul 01 04:34:38 PM PDT 24
Peak memory 215864 kb
Host smart-91578170-4827-4394-9503-d7797c1832fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623388786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3623388786
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.744715017
Short name T1106
Test name
Test status
Simulation time 89982541 ps
CPU time 1.85 seconds
Started Jul 01 04:34:19 PM PDT 24
Finished Jul 01 04:34:31 PM PDT 24
Peak memory 216856 kb
Host smart-7e2f300f-410c-46e5-a5ef-7f229666c513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744715017 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.744715017
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.208000498
Short name T141
Test name
Test status
Simulation time 368271335 ps
CPU time 1.56 seconds
Started Jul 01 04:34:16 PM PDT 24
Finished Jul 01 04:34:28 PM PDT 24
Peak memory 207524 kb
Host smart-6de47bee-e625-4a0e-8ebd-59be14e6b6b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208000498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.208000498
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1242322537
Short name T1078
Test name
Test status
Simulation time 17893145 ps
CPU time 0.71 seconds
Started Jul 01 04:34:24 PM PDT 24
Finished Jul 01 04:34:34 PM PDT 24
Peak memory 204288 kb
Host smart-ac55ee10-9f63-4b49-a431-44207b8238e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242322537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
242322537
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3850634275
Short name T1096
Test name
Test status
Simulation time 146272881 ps
CPU time 3.69 seconds
Started Jul 01 04:34:28 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 215604 kb
Host smart-a5424dd3-65fc-4feb-a9bd-758bb18f94df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850634275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3850634275
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2587998444
Short name T1120
Test name
Test status
Simulation time 95366998 ps
CPU time 2.58 seconds
Started Jul 01 04:34:29 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 216896 kb
Host smart-bd7f9603-aa3f-487a-a160-09fd444672df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587998444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
587998444
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.854738886
Short name T164
Test name
Test status
Simulation time 297232775 ps
CPU time 19.75 seconds
Started Jul 01 04:34:14 PM PDT 24
Finished Jul 01 04:34:44 PM PDT 24
Peak memory 216152 kb
Host smart-8da794b1-dc03-4cdc-b100-f3fc7cfbbe9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854738886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.854738886
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2085505206
Short name T1063
Test name
Test status
Simulation time 136899701 ps
CPU time 1.97 seconds
Started Jul 01 04:34:28 PM PDT 24
Finished Jul 01 04:34:38 PM PDT 24
Peak memory 217120 kb
Host smart-7a3b3e36-12b8-4124-8456-3ec326f5c701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085505206 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2085505206
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.327607985
Short name T1065
Test name
Test status
Simulation time 170983243 ps
CPU time 1.41 seconds
Started Jul 01 04:34:26 PM PDT 24
Finished Jul 01 04:34:36 PM PDT 24
Peak memory 207292 kb
Host smart-605f2735-aaae-4ad8-bf80-773d64cf2a88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327607985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.327607985
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3601105938
Short name T1052
Test name
Test status
Simulation time 23951651 ps
CPU time 0.76 seconds
Started Jul 01 04:34:13 PM PDT 24
Finished Jul 01 04:34:25 PM PDT 24
Peak memory 204280 kb
Host smart-6e9f94a0-5a5d-4458-9da6-3ef17c11a25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601105938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
601105938
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2172009033
Short name T1102
Test name
Test status
Simulation time 101143632 ps
CPU time 1.78 seconds
Started Jul 01 04:34:27 PM PDT 24
Finished Jul 01 04:34:37 PM PDT 24
Peak memory 215736 kb
Host smart-cffee932-fcc5-4704-bdf0-25a837a5d2ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172009033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2172009033
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2385387186
Short name T1125
Test name
Test status
Simulation time 125640981 ps
CPU time 2 seconds
Started Jul 01 04:34:23 PM PDT 24
Finished Jul 01 04:34:36 PM PDT 24
Peak memory 216012 kb
Host smart-11a329a3-c237-4436-8f33-475e72fb5f46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385387186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
385387186
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.909584580
Short name T1037
Test name
Test status
Simulation time 317318180 ps
CPU time 17.73 seconds
Started Jul 01 04:34:31 PM PDT 24
Finished Jul 01 04:34:56 PM PDT 24
Peak memory 215692 kb
Host smart-2acf28f7-bdb5-4e66-8905-15b5ba67bd67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909584580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.909584580
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3539406367
Short name T1122
Test name
Test status
Simulation time 1215543900 ps
CPU time 4.05 seconds
Started Jul 01 04:34:43 PM PDT 24
Finished Jul 01 04:34:58 PM PDT 24
Peak memory 217768 kb
Host smart-c0940d13-eb47-4f66-a8e7-e49bf42b2914
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539406367 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3539406367
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2477412306
Short name T122
Test name
Test status
Simulation time 111902415 ps
CPU time 2.07 seconds
Started Jul 01 04:34:21 PM PDT 24
Finished Jul 01 04:34:32 PM PDT 24
Peak memory 215592 kb
Host smart-11abcaf8-ade3-4323-ba76-f06f4e799807
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477412306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
477412306
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2925747335
Short name T1131
Test name
Test status
Simulation time 12676048 ps
CPU time 0.74 seconds
Started Jul 01 04:34:22 PM PDT 24
Finished Jul 01 04:34:31 PM PDT 24
Peak memory 204288 kb
Host smart-b0a39cfc-a2c8-4655-a036-ad22e263d8f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925747335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
925747335
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3552864364
Short name T142
Test name
Test status
Simulation time 66178184 ps
CPU time 1.8 seconds
Started Jul 01 04:34:21 PM PDT 24
Finished Jul 01 04:34:32 PM PDT 24
Peak memory 215804 kb
Host smart-6a5f846a-a14e-48f3-8ee4-4d0940b744bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552864364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3552864364
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.247569273
Short name T90
Test name
Test status
Simulation time 60253919 ps
CPU time 1.98 seconds
Started Jul 01 04:34:30 PM PDT 24
Finished Jul 01 04:34:40 PM PDT 24
Peak memory 216188 kb
Host smart-b8e1698c-a2b7-4a36-9dda-34c282caaafc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247569273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.247569273
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3820326191
Short name T462
Test name
Test status
Simulation time 13286011 ps
CPU time 0.72 seconds
Started Jul 01 05:23:57 PM PDT 24
Finished Jul 01 05:24:01 PM PDT 24
Peak memory 204996 kb
Host smart-601d955f-5981-47cb-8919-4722e8cdc7ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820326191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
820326191
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4190834131
Short name T737
Test name
Test status
Simulation time 254476042 ps
CPU time 4.22 seconds
Started Jul 01 05:23:47 PM PDT 24
Finished Jul 01 05:23:52 PM PDT 24
Peak memory 224520 kb
Host smart-0276018c-ee23-4ea0-a8c5-df38b5cdb2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190834131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4190834131
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.579331751
Short name T508
Test name
Test status
Simulation time 24702717 ps
CPU time 0.73 seconds
Started Jul 01 05:23:48 PM PDT 24
Finished Jul 01 05:23:50 PM PDT 24
Peak memory 206620 kb
Host smart-954561ef-8aee-4b7d-bc71-4c11dd418069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579331751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.579331751
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.14001119
Short name T40
Test name
Test status
Simulation time 4103160811 ps
CPU time 68.78 seconds
Started Jul 01 05:23:59 PM PDT 24
Finished Jul 01 05:25:10 PM PDT 24
Peak memory 255984 kb
Host smart-a59fa036-27d5-4c36-8492-879018a6c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14001119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.14001119
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1219995622
Short name T897
Test name
Test status
Simulation time 25639470817 ps
CPU time 299.63 seconds
Started Jul 01 05:23:57 PM PDT 24
Finished Jul 01 05:28:59 PM PDT 24
Peak memory 252048 kb
Host smart-061c03e2-6f1f-47af-a9da-cca45ff41df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219995622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1219995622
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1052477261
Short name T985
Test name
Test status
Simulation time 8601900124 ps
CPU time 37.15 seconds
Started Jul 01 05:23:47 PM PDT 24
Finished Jul 01 05:24:25 PM PDT 24
Peak memory 240940 kb
Host smart-8972239d-c57e-4af0-91a5-684e4e6f6e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052477261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1052477261
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3150004485
Short name T663
Test name
Test status
Simulation time 2252718650 ps
CPU time 17.54 seconds
Started Jul 01 05:23:57 PM PDT 24
Finished Jul 01 05:24:17 PM PDT 24
Peak memory 235792 kb
Host smart-d380893e-9c86-4ea5-8adb-1a20f3a82fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150004485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3150004485
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.64719656
Short name T522
Test name
Test status
Simulation time 170529203 ps
CPU time 4.25 seconds
Started Jul 01 05:23:53 PM PDT 24
Finished Jul 01 05:23:58 PM PDT 24
Peak memory 224404 kb
Host smart-40f51cf3-f3e6-4d3a-afe6-7d4231bbfb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64719656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.64719656
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2990657586
Short name T874
Test name
Test status
Simulation time 3181282811 ps
CPU time 35.81 seconds
Started Jul 01 05:23:47 PM PDT 24
Finished Jul 01 05:24:24 PM PDT 24
Peak memory 240848 kb
Host smart-55d058f1-2386-43aa-afba-5efec8d52a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990657586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2990657586
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1458640534
Short name T873
Test name
Test status
Simulation time 34829601 ps
CPU time 2.39 seconds
Started Jul 01 05:23:55 PM PDT 24
Finished Jul 01 05:23:59 PM PDT 24
Peak memory 232412 kb
Host smart-629cf2ed-b80d-438d-a13c-62420ac11b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458640534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1458640534
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3338962556
Short name T634
Test name
Test status
Simulation time 2907701903 ps
CPU time 10.28 seconds
Started Jul 01 05:23:53 PM PDT 24
Finished Jul 01 05:24:04 PM PDT 24
Peak memory 224600 kb
Host smart-2b38cc70-ab31-4d14-90f5-0ce8ae3bcbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338962556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3338962556
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2792178974
Short name T353
Test name
Test status
Simulation time 2224428155 ps
CPU time 24.61 seconds
Started Jul 01 05:23:55 PM PDT 24
Finished Jul 01 05:24:21 PM PDT 24
Peak memory 219104 kb
Host smart-41888d01-49cf-4f8c-b3a8-be052bfbe914
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2792178974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2792178974
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.34763682
Short name T66
Test name
Test status
Simulation time 163571015 ps
CPU time 1.23 seconds
Started Jul 01 05:23:56 PM PDT 24
Finished Jul 01 05:23:58 PM PDT 24
Peak memory 236660 kb
Host smart-044dc6dd-6cf9-498f-b669-4e7bc413410f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34763682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.34763682
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2096522214
Short name T1007
Test name
Test status
Simulation time 22873954042 ps
CPU time 211.12 seconds
Started Jul 01 05:23:59 PM PDT 24
Finished Jul 01 05:27:33 PM PDT 24
Peak memory 252112 kb
Host smart-c26e099b-48cc-43e7-b2c7-0ef679493c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096522214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2096522214
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2840572641
Short name T769
Test name
Test status
Simulation time 2686603069 ps
CPU time 5.6 seconds
Started Jul 01 05:23:56 PM PDT 24
Finished Jul 01 05:24:03 PM PDT 24
Peak memory 216400 kb
Host smart-f360e073-f129-4ca7-a75b-a1a9f4faccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840572641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2840572641
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3134344066
Short name T981
Test name
Test status
Simulation time 16960164727 ps
CPU time 12.41 seconds
Started Jul 01 05:23:48 PM PDT 24
Finished Jul 01 05:24:02 PM PDT 24
Peak memory 216400 kb
Host smart-285df199-4364-474d-a200-098435a12961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134344066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3134344066
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2885988949
Short name T920
Test name
Test status
Simulation time 719828950 ps
CPU time 2.42 seconds
Started Jul 01 05:23:49 PM PDT 24
Finished Jul 01 05:23:53 PM PDT 24
Peak memory 216224 kb
Host smart-861b2083-2f70-4ed3-916b-b3069073413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885988949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2885988949
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2056135537
Short name T567
Test name
Test status
Simulation time 132850654 ps
CPU time 0.93 seconds
Started Jul 01 05:23:48 PM PDT 24
Finished Jul 01 05:23:50 PM PDT 24
Peak memory 206000 kb
Host smart-e6f6137c-c191-41af-aaa8-c60fe5d6bab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056135537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2056135537
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2529229607
Short name T586
Test name
Test status
Simulation time 737847420 ps
CPU time 4.19 seconds
Started Jul 01 05:23:48 PM PDT 24
Finished Jul 01 05:23:54 PM PDT 24
Peak memory 232776 kb
Host smart-eb97ffbd-5670-4860-a8c2-1527b54c05a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529229607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2529229607
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2896245414
Short name T857
Test name
Test status
Simulation time 29598498 ps
CPU time 2.28 seconds
Started Jul 01 05:24:00 PM PDT 24
Finished Jul 01 05:24:05 PM PDT 24
Peak memory 224564 kb
Host smart-8af55d59-17e8-40d5-b32e-35cc7fadae14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896245414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2896245414
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.958302381
Short name T500
Test name
Test status
Simulation time 69523846 ps
CPU time 0.77 seconds
Started Jul 01 05:24:00 PM PDT 24
Finished Jul 01 05:24:03 PM PDT 24
Peak memory 205592 kb
Host smart-5066a04a-a0b5-4fe7-8f83-2e71af913369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958302381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.958302381
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1708084650
Short name T162
Test name
Test status
Simulation time 15214471225 ps
CPU time 122.89 seconds
Started Jul 01 05:23:57 PM PDT 24
Finished Jul 01 05:26:03 PM PDT 24
Peak memory 249516 kb
Host smart-f0d56ce5-d802-48d9-aa40-7b355d553935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708084650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1708084650
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1959006966
Short name T984
Test name
Test status
Simulation time 680232911 ps
CPU time 7.2 seconds
Started Jul 01 05:23:56 PM PDT 24
Finished Jul 01 05:24:06 PM PDT 24
Peak memory 222852 kb
Host smart-3337e813-597d-4e7c-8f7b-50457f0a741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959006966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1959006966
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.4134432663
Short name T37
Test name
Test status
Simulation time 35128089063 ps
CPU time 332.85 seconds
Started Jul 01 05:23:58 PM PDT 24
Finished Jul 01 05:29:33 PM PDT 24
Peak memory 249424 kb
Host smart-cdaad8e6-c764-4ce3-bdbe-4ecada1e1234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134432663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.4134432663
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1948897049
Short name T971
Test name
Test status
Simulation time 53199892 ps
CPU time 2.75 seconds
Started Jul 01 05:23:55 PM PDT 24
Finished Jul 01 05:23:59 PM PDT 24
Peak memory 224448 kb
Host smart-a2c47d29-616f-4840-8e7a-f13abab80fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948897049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1948897049
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3324456673
Short name T211
Test name
Test status
Simulation time 17381290342 ps
CPU time 126.75 seconds
Started Jul 01 05:23:59 PM PDT 24
Finished Jul 01 05:26:08 PM PDT 24
Peak memory 257336 kb
Host smart-b6f8dca2-d669-4959-b724-098b6de6c225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324456673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3324456673
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2968561755
Short name T642
Test name
Test status
Simulation time 778781365 ps
CPU time 10.53 seconds
Started Jul 01 05:23:58 PM PDT 24
Finished Jul 01 05:24:12 PM PDT 24
Peak memory 232648 kb
Host smart-a70f7c82-78db-4c37-a4b1-248f2097b9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968561755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2968561755
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3338256735
Short name T854
Test name
Test status
Simulation time 2247042322 ps
CPU time 16.65 seconds
Started Jul 01 05:23:58 PM PDT 24
Finished Jul 01 05:24:18 PM PDT 24
Peak memory 232744 kb
Host smart-56ee475f-e0ea-484a-b5b7-ac388b25ecbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338256735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3338256735
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3200597606
Short name T664
Test name
Test status
Simulation time 4377367896 ps
CPU time 5.44 seconds
Started Jul 01 05:23:59 PM PDT 24
Finished Jul 01 05:24:07 PM PDT 24
Peak memory 232668 kb
Host smart-e124d87b-a8db-429d-aa0c-0b818b37244c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200597606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3200597606
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.733996966
Short name T989
Test name
Test status
Simulation time 22178519188 ps
CPU time 11.79 seconds
Started Jul 01 05:23:59 PM PDT 24
Finished Jul 01 05:24:13 PM PDT 24
Peak memory 239724 kb
Host smart-46c7e057-5b37-4811-9ee4-2c18c470d99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733996966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.733996966
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1158911744
Short name T877
Test name
Test status
Simulation time 4260038849 ps
CPU time 13.26 seconds
Started Jul 01 05:23:56 PM PDT 24
Finished Jul 01 05:24:10 PM PDT 24
Peak memory 219584 kb
Host smart-3c4e5810-61aa-4305-9468-6eb223b38deb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1158911744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1158911744
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1034591048
Short name T63
Test name
Test status
Simulation time 40198676 ps
CPU time 0.97 seconds
Started Jul 01 05:23:57 PM PDT 24
Finished Jul 01 05:24:00 PM PDT 24
Peak memory 236008 kb
Host smart-618fe3d4-898a-48cb-ab66-4d66136ce51a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034591048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1034591048
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3222093308
Short name T397
Test name
Test status
Simulation time 2659691740 ps
CPU time 15.89 seconds
Started Jul 01 05:23:57 PM PDT 24
Finished Jul 01 05:24:14 PM PDT 24
Peak memory 216412 kb
Host smart-5a8e9783-dc0c-44cf-a5e8-06d1da961eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222093308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3222093308
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1299228700
Short name T644
Test name
Test status
Simulation time 7137141774 ps
CPU time 11.66 seconds
Started Jul 01 05:24:00 PM PDT 24
Finished Jul 01 05:24:14 PM PDT 24
Peak memory 216460 kb
Host smart-9c0246b6-dd50-4358-a53d-e45600221b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299228700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1299228700
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4176066175
Short name T896
Test name
Test status
Simulation time 141681060 ps
CPU time 2.54 seconds
Started Jul 01 05:23:56 PM PDT 24
Finished Jul 01 05:24:00 PM PDT 24
Peak memory 216280 kb
Host smart-38caa3c6-e1d3-41fc-837c-df487947c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176066175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4176066175
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.978295216
Short name T1013
Test name
Test status
Simulation time 61663923 ps
CPU time 0.89 seconds
Started Jul 01 05:23:56 PM PDT 24
Finished Jul 01 05:23:58 PM PDT 24
Peak memory 206224 kb
Host smart-a10c358d-3a9e-4072-945f-6ba10b79544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978295216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.978295216
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.334076494
Short name T617
Test name
Test status
Simulation time 49130891 ps
CPU time 2.3 seconds
Started Jul 01 05:23:58 PM PDT 24
Finished Jul 01 05:24:03 PM PDT 24
Peak memory 224144 kb
Host smart-0e3bd078-7ef1-4d27-947e-aef194b3f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334076494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.334076494
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2222827908
Short name T444
Test name
Test status
Simulation time 15019621 ps
CPU time 0.72 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:24:44 PM PDT 24
Peak memory 205516 kb
Host smart-aa2af8b2-f0b8-428d-aadf-c29e4be5de86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222827908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2222827908
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1978815234
Short name T531
Test name
Test status
Simulation time 223056980 ps
CPU time 5.58 seconds
Started Jul 01 05:24:38 PM PDT 24
Finished Jul 01 05:24:46 PM PDT 24
Peak memory 224472 kb
Host smart-487c51db-970f-4d9a-932c-097523708ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978815234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1978815234
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2099472166
Short name T67
Test name
Test status
Simulation time 26852032 ps
CPU time 0.84 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:24:42 PM PDT 24
Peak memory 206692 kb
Host smart-0121a0ca-e2f7-477a-9b6a-6c54cba07f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099472166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2099472166
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1587640524
Short name T869
Test name
Test status
Simulation time 7502160611 ps
CPU time 62.04 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:25:46 PM PDT 24
Peak memory 241072 kb
Host smart-2c8f1fd0-10f5-4100-afe1-354f598b69d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587640524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1587640524
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1751235873
Short name T182
Test name
Test status
Simulation time 63661506654 ps
CPU time 473.32 seconds
Started Jul 01 05:24:47 PM PDT 24
Finished Jul 01 05:32:44 PM PDT 24
Peak memory 257432 kb
Host smart-ea544752-b2ab-42d7-964d-00c1e14914a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751235873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1751235873
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3783260211
Short name T913
Test name
Test status
Simulation time 599802872 ps
CPU time 4.66 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:24:46 PM PDT 24
Peak memory 224512 kb
Host smart-e39f7e30-f054-47ac-98ba-1569d79ba3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783260211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3783260211
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1005430564
Short name T288
Test name
Test status
Simulation time 190728929535 ps
CPU time 224.77 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:28:27 PM PDT 24
Peak memory 257404 kb
Host smart-41aaff2d-0f41-4cff-a88c-df6dcb96d360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005430564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1005430564
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3850134186
Short name T247
Test name
Test status
Simulation time 403971075 ps
CPU time 6.17 seconds
Started Jul 01 05:24:48 PM PDT 24
Finished Jul 01 05:24:57 PM PDT 24
Peak memory 232716 kb
Host smart-2d5be943-5651-4f8b-9bf7-01c34b1d4443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850134186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3850134186
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2566600567
Short name T610
Test name
Test status
Simulation time 3301344668 ps
CPU time 45.1 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:25:30 PM PDT 24
Peak memory 224636 kb
Host smart-1db72c0f-7bf0-40b1-9d4e-93bfe464c353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566600567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2566600567
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1758276449
Short name T255
Test name
Test status
Simulation time 3594436925 ps
CPU time 4.67 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:24:47 PM PDT 24
Peak memory 224524 kb
Host smart-7e21d18c-9007-4e11-a4ab-4ec4037ad545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758276449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1758276449
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2929826769
Short name T638
Test name
Test status
Simulation time 1907312517 ps
CPU time 7.73 seconds
Started Jul 01 05:24:48 PM PDT 24
Finished Jul 01 05:25:00 PM PDT 24
Peak memory 224520 kb
Host smart-a496512c-2c9b-44a8-8599-14659398d0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929826769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2929826769
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2166957778
Short name T863
Test name
Test status
Simulation time 4565558227 ps
CPU time 13.26 seconds
Started Jul 01 05:24:47 PM PDT 24
Finished Jul 01 05:25:04 PM PDT 24
Peak memory 220528 kb
Host smart-d8b5d346-a929-4191-a076-8fee93478f55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2166957778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2166957778
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.497098180
Short name T389
Test name
Test status
Simulation time 1630112267 ps
CPU time 10.24 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:24:55 PM PDT 24
Peak memory 216368 kb
Host smart-70ae41cc-c571-4810-981e-634558646071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497098180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.497098180
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1875973815
Short name T552
Test name
Test status
Simulation time 44244843 ps
CPU time 0.71 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:24:42 PM PDT 24
Peak memory 205704 kb
Host smart-c4cfcc6b-d771-40d9-8746-858d89475f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875973815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1875973815
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1034589941
Short name T533
Test name
Test status
Simulation time 17258960 ps
CPU time 0.86 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:24:45 PM PDT 24
Peak memory 205948 kb
Host smart-b425f047-316d-443b-9da5-fd8cd2ec7bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034589941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1034589941
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2497266121
Short name T337
Test name
Test status
Simulation time 52681253 ps
CPU time 0.76 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:24:45 PM PDT 24
Peak memory 205988 kb
Host smart-88d4c5be-0e41-4286-bfe0-8b930e64ae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497266121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2497266121
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1679874740
Short name T530
Test name
Test status
Simulation time 271756663 ps
CPU time 2.4 seconds
Started Jul 01 05:24:41 PM PDT 24
Finished Jul 01 05:24:48 PM PDT 24
Peak memory 224468 kb
Host smart-4ea955dd-6d6b-41de-86ee-51d640a92c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679874740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1679874740
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.280050840
Short name T892
Test name
Test status
Simulation time 74152217 ps
CPU time 0.76 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:24:44 PM PDT 24
Peak memory 204996 kb
Host smart-3b9daf42-cd60-43ef-9404-fb715ea40058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280050840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.280050840
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3799362765
Short name T155
Test name
Test status
Simulation time 1956000111 ps
CPU time 5.13 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:24:47 PM PDT 24
Peak memory 224620 kb
Host smart-7ada3b48-2106-45c0-a46b-b46c5af1c5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799362765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3799362765
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3172945737
Short name T415
Test name
Test status
Simulation time 20584182 ps
CPU time 0.81 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:24:42 PM PDT 24
Peak memory 206620 kb
Host smart-b9713bbc-f63c-4cca-b2de-d3ed64cf7e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172945737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3172945737
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.495824368
Short name T885
Test name
Test status
Simulation time 174879989 ps
CPU time 4.79 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:24:50 PM PDT 24
Peak memory 233872 kb
Host smart-210396a5-e6a7-43f3-b1ab-252ec7ccfa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495824368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.495824368
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3202597291
Short name T382
Test name
Test status
Simulation time 4201189726 ps
CPU time 68.48 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:25:53 PM PDT 24
Peak memory 241384 kb
Host smart-25698f67-5d34-4f15-a944-9e1e19a2dc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202597291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3202597291
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2504709542
Short name T303
Test name
Test status
Simulation time 100779332726 ps
CPU time 207.71 seconds
Started Jul 01 05:24:48 PM PDT 24
Finished Jul 01 05:28:19 PM PDT 24
Peak memory 253144 kb
Host smart-1e1f58f6-93ae-4b76-ba2a-25b7c9ef4927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504709542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2504709542
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2283673103
Short name T296
Test name
Test status
Simulation time 1014483045 ps
CPU time 19.43 seconds
Started Jul 01 05:24:48 PM PDT 24
Finished Jul 01 05:25:11 PM PDT 24
Peak memory 238712 kb
Host smart-f0808e11-c734-4e35-93d8-f66d2667df23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283673103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2283673103
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3573060171
Short name T746
Test name
Test status
Simulation time 174464884 ps
CPU time 3.94 seconds
Started Jul 01 05:24:41 PM PDT 24
Finished Jul 01 05:24:50 PM PDT 24
Peak memory 234240 kb
Host smart-f36166ea-ec1d-40d3-9966-2c7d48fd7532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573060171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3573060171
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4259271212
Short name T761
Test name
Test status
Simulation time 909402685 ps
CPU time 8.62 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:24:54 PM PDT 24
Peak memory 232812 kb
Host smart-fe2d49e8-2f1b-4737-a352-3bf454e2366f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259271212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4259271212
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.967661968
Short name T686
Test name
Test status
Simulation time 453862779 ps
CPU time 8.6 seconds
Started Jul 01 05:24:41 PM PDT 24
Finished Jul 01 05:24:54 PM PDT 24
Peak memory 224476 kb
Host smart-ea48a7e1-8926-48ac-bc71-c8710da6e438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967661968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.967661968
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2371692704
Short name T633
Test name
Test status
Simulation time 4736954759 ps
CPU time 11.01 seconds
Started Jul 01 05:24:41 PM PDT 24
Finished Jul 01 05:24:57 PM PDT 24
Peak memory 232768 kb
Host smart-c7db1257-43e6-48f2-8755-4b01c711b011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371692704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2371692704
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1542743244
Short name T623
Test name
Test status
Simulation time 15036357534 ps
CPU time 10.19 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:24:55 PM PDT 24
Peak memory 224648 kb
Host smart-dc2a9f21-e4e5-48eb-9d0d-b61080118168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542743244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1542743244
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3862086141
Short name T367
Test name
Test status
Simulation time 1658215378 ps
CPU time 8.71 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:24:52 PM PDT 24
Peak memory 223148 kb
Host smart-29535211-870f-4ecb-b2f3-ad342684921b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3862086141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3862086141
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1282508915
Short name T743
Test name
Test status
Simulation time 5706301006 ps
CPU time 61.93 seconds
Started Jul 01 05:24:49 PM PDT 24
Finished Jul 01 05:25:54 PM PDT 24
Peak memory 238216 kb
Host smart-453b1423-88ec-474d-90f2-4412f96e1509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282508915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1282508915
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.631743361
Short name T915
Test name
Test status
Simulation time 1019316745 ps
CPU time 14.22 seconds
Started Jul 01 05:24:39 PM PDT 24
Finished Jul 01 05:24:57 PM PDT 24
Peak memory 216400 kb
Host smart-648ddaf7-e96f-48b1-b4aa-bbabb7ac1e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631743361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.631743361
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4058159871
Short name T593
Test name
Test status
Simulation time 4175291260 ps
CPU time 7.82 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:24:52 PM PDT 24
Peak memory 216448 kb
Host smart-98d638e6-327a-488a-807b-50be5c08b29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058159871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4058159871
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3363342886
Short name T355
Test name
Test status
Simulation time 129099103 ps
CPU time 2.28 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:24:46 PM PDT 24
Peak memory 216328 kb
Host smart-7200f892-1293-4c6e-8427-570c585f0f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363342886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3363342886
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2578190344
Short name T933
Test name
Test status
Simulation time 60295668 ps
CPU time 0.86 seconds
Started Jul 01 05:24:40 PM PDT 24
Finished Jul 01 05:24:45 PM PDT 24
Peak memory 206000 kb
Host smart-b3df72b7-2a21-4a6f-b288-7e5da382c5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578190344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2578190344
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.884650312
Short name T219
Test name
Test status
Simulation time 1753338046 ps
CPU time 8.58 seconds
Started Jul 01 05:24:38 PM PDT 24
Finished Jul 01 05:24:48 PM PDT 24
Peak memory 232672 kb
Host smart-30037580-25ca-4ec7-a9f1-a6943f489ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884650312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.884650312
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3606031971
Short name T377
Test name
Test status
Simulation time 13473070 ps
CPU time 0.76 seconds
Started Jul 01 05:24:46 PM PDT 24
Finished Jul 01 05:24:49 PM PDT 24
Peak memory 205892 kb
Host smart-3f4771bb-1c7b-4ef7-bcc0-a87d2ca096c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606031971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3606031971
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3445150384
Short name T537
Test name
Test status
Simulation time 10249913140 ps
CPU time 23.03 seconds
Started Jul 01 05:24:50 PM PDT 24
Finished Jul 01 05:25:16 PM PDT 24
Peak memory 232752 kb
Host smart-fc761222-349f-4a12-966c-2230086d46f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445150384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3445150384
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1727322121
Short name T848
Test name
Test status
Simulation time 49784084 ps
CPU time 0.8 seconds
Started Jul 01 05:24:41 PM PDT 24
Finished Jul 01 05:24:47 PM PDT 24
Peak memory 206268 kb
Host smart-3cc8c9c6-b121-43c5-a818-ee197e8e7c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727322121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1727322121
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2765023756
Short name T354
Test name
Test status
Simulation time 2130014405 ps
CPU time 25.47 seconds
Started Jul 01 05:24:48 PM PDT 24
Finished Jul 01 05:25:17 PM PDT 24
Peak memory 249156 kb
Host smart-9f2a4d1e-66a7-4535-a61a-44e61059c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765023756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2765023756
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3572934834
Short name T46
Test name
Test status
Simulation time 27991618469 ps
CPU time 273.69 seconds
Started Jul 01 05:24:46 PM PDT 24
Finished Jul 01 05:29:22 PM PDT 24
Peak memory 249360 kb
Host smart-40c13ea5-ebe6-41f8-b258-6e31ac492c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572934834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3572934834
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4103060630
Short name T561
Test name
Test status
Simulation time 95075761 ps
CPU time 4.59 seconds
Started Jul 01 05:24:48 PM PDT 24
Finished Jul 01 05:24:56 PM PDT 24
Peak memory 235096 kb
Host smart-97c38f71-e5f8-4c13-b6a4-e0d22dc24e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103060630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4103060630
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3555560575
Short name T520
Test name
Test status
Simulation time 14669686190 ps
CPU time 53.63 seconds
Started Jul 01 05:24:50 PM PDT 24
Finished Jul 01 05:25:47 PM PDT 24
Peak memory 256800 kb
Host smart-22b8ee74-086c-4fd3-a655-162aed777cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555560575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3555560575
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1407800896
Short name T231
Test name
Test status
Simulation time 4904210830 ps
CPU time 9.68 seconds
Started Jul 01 05:24:48 PM PDT 24
Finished Jul 01 05:25:01 PM PDT 24
Peak memory 232820 kb
Host smart-25c44560-c9b1-4788-8a1d-4121c8931880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407800896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1407800896
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1451396268
Short name T783
Test name
Test status
Simulation time 2953702057 ps
CPU time 14.19 seconds
Started Jul 01 05:24:47 PM PDT 24
Finished Jul 01 05:25:04 PM PDT 24
Peak memory 232796 kb
Host smart-f38b435e-cad4-4994-ae2f-e1f20af9db20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451396268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1451396268
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.425979836
Short name T986
Test name
Test status
Simulation time 205737678 ps
CPU time 3.03 seconds
Started Jul 01 05:24:47 PM PDT 24
Finished Jul 01 05:24:54 PM PDT 24
Peak memory 232640 kb
Host smart-687ac3e5-202c-449c-bfc6-6c0d0bddbba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425979836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.425979836
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2497027632
Short name T669
Test name
Test status
Simulation time 6461464228 ps
CPU time 11.22 seconds
Started Jul 01 05:24:52 PM PDT 24
Finished Jul 01 05:25:05 PM PDT 24
Peak memory 238948 kb
Host smart-1f3df1cf-e929-458d-8cd9-4cb50a95f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497027632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2497027632
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.458086862
Short name T132
Test name
Test status
Simulation time 2199435126 ps
CPU time 7.24 seconds
Started Jul 01 05:24:57 PM PDT 24
Finished Jul 01 05:25:08 PM PDT 24
Peak memory 220268 kb
Host smart-8695f9f3-04c0-4dea-a7a2-7adc2cee8e00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=458086862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.458086862
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3006812947
Short name T418
Test name
Test status
Simulation time 2785388779 ps
CPU time 27.39 seconds
Started Jul 01 05:24:47 PM PDT 24
Finished Jul 01 05:25:17 PM PDT 24
Peak memory 216556 kb
Host smart-b9d1bde6-538e-498c-a184-bc57a8d6ead4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006812947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3006812947
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1449352487
Short name T513
Test name
Test status
Simulation time 11702411 ps
CPU time 0.73 seconds
Started Jul 01 05:24:47 PM PDT 24
Finished Jul 01 05:24:51 PM PDT 24
Peak memory 205736 kb
Host smart-e3100f4a-2f00-4df8-9451-c5ff0220cf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449352487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1449352487
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4145967377
Short name T601
Test name
Test status
Simulation time 322938526 ps
CPU time 1.32 seconds
Started Jul 01 05:24:57 PM PDT 24
Finished Jul 01 05:25:03 PM PDT 24
Peak memory 216328 kb
Host smart-9c120cbe-9a58-4257-a022-f039c0a8ddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145967377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4145967377
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2323044962
Short name T626
Test name
Test status
Simulation time 143907877 ps
CPU time 0.84 seconds
Started Jul 01 05:24:46 PM PDT 24
Finished Jul 01 05:24:49 PM PDT 24
Peak memory 206000 kb
Host smart-103c69c4-b71d-4045-b33f-005c8b2ac263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323044962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2323044962
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1353638038
Short name T864
Test name
Test status
Simulation time 4521242870 ps
CPU time 19.58 seconds
Started Jul 01 05:24:46 PM PDT 24
Finished Jul 01 05:25:09 PM PDT 24
Peak memory 232840 kb
Host smart-3197e7cc-c309-48a4-bce8-f87727ebe619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353638038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1353638038
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.737194066
Short name T859
Test name
Test status
Simulation time 14295213 ps
CPU time 0.7 seconds
Started Jul 01 05:24:56 PM PDT 24
Finished Jul 01 05:25:01 PM PDT 24
Peak memory 205628 kb
Host smart-50681346-c8d0-4f40-8f44-309158116e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737194066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.737194066
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2480582945
Short name T764
Test name
Test status
Simulation time 39735726 ps
CPU time 0.75 seconds
Started Jul 01 05:24:47 PM PDT 24
Finished Jul 01 05:24:52 PM PDT 24
Peak memory 206608 kb
Host smart-b069f967-a23d-4911-8fe1-4e328b1345d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480582945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2480582945
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.689167232
Short name T570
Test name
Test status
Simulation time 2606536195 ps
CPU time 20.58 seconds
Started Jul 01 05:24:58 PM PDT 24
Finished Jul 01 05:25:23 PM PDT 24
Peak memory 224584 kb
Host smart-2a16ff4b-dc77-4424-b2ac-f17b82f708a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689167232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.689167232
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.710785981
Short name T952
Test name
Test status
Simulation time 64002387907 ps
CPU time 311.81 seconds
Started Jul 01 05:24:56 PM PDT 24
Finished Jul 01 05:30:13 PM PDT 24
Peak memory 265640 kb
Host smart-8a2c637f-d5c2-44d1-b163-57e85f8e33e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710785981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.710785981
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3037613346
Short name T808
Test name
Test status
Simulation time 20570183685 ps
CPU time 80.95 seconds
Started Jul 01 05:24:54 PM PDT 24
Finished Jul 01 05:26:19 PM PDT 24
Peak memory 232884 kb
Host smart-61eb683c-4644-4f05-a10a-6d43839c885f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037613346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3037613346
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.351857714
Short name T828
Test name
Test status
Simulation time 707936237 ps
CPU time 4.57 seconds
Started Jul 01 05:24:58 PM PDT 24
Finished Jul 01 05:25:07 PM PDT 24
Peak memory 224516 kb
Host smart-8bcf420f-517a-4ad1-b5ef-c78320240439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351857714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.351857714
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.4098688842
Short name T271
Test name
Test status
Simulation time 2102266033 ps
CPU time 30.77 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:29 PM PDT 24
Peak memory 235592 kb
Host smart-955d9ba7-556d-4003-a9df-4fb74e282148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098688842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.4098688842
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.302786481
Short name T442
Test name
Test status
Simulation time 323486303 ps
CPU time 5.74 seconds
Started Jul 01 05:24:50 PM PDT 24
Finished Jul 01 05:24:59 PM PDT 24
Peak memory 224448 kb
Host smart-7bf5d838-0197-467e-a17a-05393218bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302786481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.302786481
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3362339885
Short name T534
Test name
Test status
Simulation time 3270738766 ps
CPU time 42.31 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:41 PM PDT 24
Peak memory 232792 kb
Host smart-819de27b-5c26-46b3-8976-fd68ce2afb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362339885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3362339885
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3995473873
Short name T521
Test name
Test status
Simulation time 3430806368 ps
CPU time 4.18 seconds
Started Jul 01 05:24:48 PM PDT 24
Finished Jul 01 05:24:56 PM PDT 24
Peak memory 232868 kb
Host smart-8f8ad14a-76e9-475e-a157-e1c2d77869e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995473873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3995473873
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.22837882
Short name T938
Test name
Test status
Simulation time 3451342512 ps
CPU time 12.49 seconds
Started Jul 01 05:24:46 PM PDT 24
Finished Jul 01 05:25:02 PM PDT 24
Peak memory 224648 kb
Host smart-b06a4231-cced-4f2f-ba79-51d095649aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22837882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.22837882
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2699632874
Short name T904
Test name
Test status
Simulation time 832431762 ps
CPU time 4.38 seconds
Started Jul 01 05:24:56 PM PDT 24
Finished Jul 01 05:25:04 PM PDT 24
Peak memory 219352 kb
Host smart-58c05fb8-b43c-47ea-9657-a647b26e8ddd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2699632874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2699632874
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1186102813
Short name T856
Test name
Test status
Simulation time 9904374394 ps
CPU time 28.21 seconds
Started Jul 01 05:24:46 PM PDT 24
Finished Jul 01 05:25:16 PM PDT 24
Peak memory 216592 kb
Host smart-e541f81c-14bc-409c-8fdb-e30e45c69482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186102813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1186102813
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1768864469
Short name T611
Test name
Test status
Simulation time 222810423 ps
CPU time 1.31 seconds
Started Jul 01 05:24:46 PM PDT 24
Finished Jul 01 05:24:51 PM PDT 24
Peak memory 207892 kb
Host smart-a3563d83-c913-4908-8b66-85815c4a2093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768864469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1768864469
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.659979970
Short name T468
Test name
Test status
Simulation time 21639578 ps
CPU time 0.86 seconds
Started Jul 01 05:24:47 PM PDT 24
Finished Jul 01 05:24:51 PM PDT 24
Peak memory 205996 kb
Host smart-dbeeacc0-0089-46e0-a534-c0f31ade0bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659979970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.659979970
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2524804711
Short name T645
Test name
Test status
Simulation time 43127425 ps
CPU time 0.83 seconds
Started Jul 01 05:24:45 PM PDT 24
Finished Jul 01 05:24:48 PM PDT 24
Peak memory 206040 kb
Host smart-4e311c11-2789-42ac-8ab0-9567db7308cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524804711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2524804711
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2425500687
Short name T711
Test name
Test status
Simulation time 14774094062 ps
CPU time 11.77 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:10 PM PDT 24
Peak memory 232824 kb
Host smart-b7353d8d-9e9c-47ea-9e57-8b7b706caeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425500687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2425500687
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2469716967
Short name T968
Test name
Test status
Simulation time 61799165 ps
CPU time 0.76 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:00 PM PDT 24
Peak memory 205544 kb
Host smart-2dbdef40-228b-4228-8399-0b72ca61871c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469716967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2469716967
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2632113765
Short name T84
Test name
Test status
Simulation time 14107809406 ps
CPU time 20.88 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:20 PM PDT 24
Peak memory 224636 kb
Host smart-f85aad3e-83bf-45df-b6e0-81e9e4aceec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632113765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2632113765
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.568787075
Short name T438
Test name
Test status
Simulation time 16270815 ps
CPU time 0.78 seconds
Started Jul 01 05:24:54 PM PDT 24
Finished Jul 01 05:24:57 PM PDT 24
Peak memory 206632 kb
Host smart-0fc6247b-6ff5-461f-a0bc-9f9eb32f0286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568787075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.568787075
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4195815498
Short name T824
Test name
Test status
Simulation time 2215239035 ps
CPU time 9.49 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:09 PM PDT 24
Peak memory 241056 kb
Host smart-b1caf5bc-0b63-4df6-86cd-a6419524c2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195815498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4195815498
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2222725764
Short name T929
Test name
Test status
Simulation time 53891276460 ps
CPU time 98.77 seconds
Started Jul 01 05:24:56 PM PDT 24
Finished Jul 01 05:26:39 PM PDT 24
Peak memory 249344 kb
Host smart-42f11747-8ff0-47a1-9350-29aa8428818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222725764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2222725764
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.845699178
Short name T480
Test name
Test status
Simulation time 932309387 ps
CPU time 10.12 seconds
Started Jul 01 05:24:56 PM PDT 24
Finished Jul 01 05:25:10 PM PDT 24
Peak memory 224484 kb
Host smart-7d9d1abc-4477-445f-bdb9-1bad6c6ea9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845699178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.845699178
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1674228133
Short name T736
Test name
Test status
Simulation time 29161630 ps
CPU time 2.32 seconds
Started Jul 01 05:24:56 PM PDT 24
Finished Jul 01 05:25:03 PM PDT 24
Peak memory 232352 kb
Host smart-d8933d94-e9bb-47f9-bc5e-f97313c94792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674228133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1674228133
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1217497032
Short name T614
Test name
Test status
Simulation time 1264928012 ps
CPU time 10.54 seconds
Started Jul 01 05:24:54 PM PDT 24
Finished Jul 01 05:25:07 PM PDT 24
Peak memory 224504 kb
Host smart-aa057347-a3a5-4853-aaf7-162db7ea5f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217497032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1217497032
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2618109366
Short name T400
Test name
Test status
Simulation time 225843331 ps
CPU time 5.35 seconds
Started Jul 01 05:24:54 PM PDT 24
Finished Jul 01 05:25:03 PM PDT 24
Peak memory 232756 kb
Host smart-a97f1d34-803a-4e21-9503-85500cbd7d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618109366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2618109366
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.398060088
Short name T466
Test name
Test status
Simulation time 2511772383 ps
CPU time 8.86 seconds
Started Jul 01 05:24:56 PM PDT 24
Finished Jul 01 05:25:09 PM PDT 24
Peak memory 220856 kb
Host smart-c0e98131-1afd-49c4-964e-90f57c30e887
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=398060088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.398060088
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1820046354
Short name T273
Test name
Test status
Simulation time 54753017631 ps
CPU time 160.97 seconds
Started Jul 01 05:24:54 PM PDT 24
Finished Jul 01 05:27:37 PM PDT 24
Peak memory 249304 kb
Host smart-7c4b5e52-6e3d-49ba-9d7a-57403b74cc95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820046354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1820046354
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1951572782
Short name T485
Test name
Test status
Simulation time 11116964797 ps
CPU time 32.89 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:32 PM PDT 24
Peak memory 216548 kb
Host smart-fde5234c-ea70-4e48-887a-de61b09f0124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951572782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1951572782
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3332463033
Short name T779
Test name
Test status
Simulation time 23538482 ps
CPU time 0.73 seconds
Started Jul 01 05:24:56 PM PDT 24
Finished Jul 01 05:25:02 PM PDT 24
Peak memory 205712 kb
Host smart-37c85ed3-32a2-41f9-acf3-4f8ab731d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332463033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3332463033
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.491199379
Short name T816
Test name
Test status
Simulation time 188687596 ps
CPU time 3.12 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:02 PM PDT 24
Peak memory 216256 kb
Host smart-2e5a5ab6-b9d4-48d7-a258-d9695abde02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491199379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.491199379
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.875038865
Short name T413
Test name
Test status
Simulation time 24640208 ps
CPU time 0.74 seconds
Started Jul 01 05:24:53 PM PDT 24
Finished Jul 01 05:24:55 PM PDT 24
Peak memory 205980 kb
Host smart-18c038ce-9059-43dd-b7ec-3e75ae264589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875038865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.875038865
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2117745386
Short name T895
Test name
Test status
Simulation time 409411649 ps
CPU time 2.57 seconds
Started Jul 01 05:24:57 PM PDT 24
Finished Jul 01 05:25:04 PM PDT 24
Peak memory 224160 kb
Host smart-a5c1a0ba-d96a-42f2-83f3-c04a1774f19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117745386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2117745386
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1172643927
Short name T591
Test name
Test status
Simulation time 121510543 ps
CPU time 0.73 seconds
Started Jul 01 05:25:05 PM PDT 24
Finished Jul 01 05:25:14 PM PDT 24
Peak memory 205532 kb
Host smart-da807c7e-baa2-4eed-aeed-f3df6006a314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172643927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1172643927
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3808728194
Short name T801
Test name
Test status
Simulation time 183749097 ps
CPU time 3.2 seconds
Started Jul 01 05:25:07 PM PDT 24
Finished Jul 01 05:25:20 PM PDT 24
Peak memory 224536 kb
Host smart-3eafacc1-0792-4c21-94e4-4dbb595bbb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808728194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3808728194
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1883060684
Short name T695
Test name
Test status
Simulation time 48221358 ps
CPU time 0.8 seconds
Started Jul 01 05:24:56 PM PDT 24
Finished Jul 01 05:25:02 PM PDT 24
Peak memory 206628 kb
Host smart-bd2ddfd5-1f5f-4c96-8c89-0340c2433cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883060684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1883060684
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3165960146
Short name T632
Test name
Test status
Simulation time 3385554661 ps
CPU time 58.34 seconds
Started Jul 01 05:25:00 PM PDT 24
Finished Jul 01 05:26:04 PM PDT 24
Peak memory 256040 kb
Host smart-d6bb266a-7b69-41e6-85f8-4080b596a2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165960146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3165960146
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1910437977
Short name T290
Test name
Test status
Simulation time 50574024457 ps
CPU time 121.18 seconds
Started Jul 01 05:25:02 PM PDT 24
Finished Jul 01 05:27:09 PM PDT 24
Peak memory 241112 kb
Host smart-615f48bf-15e9-40bc-9bcd-65745ed3630c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910437977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1910437977
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.200156161
Short name T583
Test name
Test status
Simulation time 390224246444 ps
CPU time 237.64 seconds
Started Jul 01 05:24:59 PM PDT 24
Finished Jul 01 05:29:01 PM PDT 24
Peak memory 252136 kb
Host smart-75159ffb-23fe-4384-9922-5175b385f0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200156161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.200156161
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1780718606
Short name T350
Test name
Test status
Simulation time 4445327948 ps
CPU time 6.35 seconds
Started Jul 01 05:25:02 PM PDT 24
Finished Jul 01 05:25:15 PM PDT 24
Peak memory 232912 kb
Host smart-579cb343-e045-408c-9a7e-c2e5df70f848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780718606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1780718606
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2956922027
Short name T171
Test name
Test status
Simulation time 10775411182 ps
CPU time 60.83 seconds
Started Jul 01 05:25:00 PM PDT 24
Finished Jul 01 05:26:06 PM PDT 24
Peak memory 239280 kb
Host smart-c24fbf80-05b4-4b90-99d4-ea983b91501e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956922027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2956922027
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2116129644
Short name T947
Test name
Test status
Simulation time 188787717 ps
CPU time 2.23 seconds
Started Jul 01 05:25:06 PM PDT 24
Finished Jul 01 05:25:17 PM PDT 24
Peak memory 224376 kb
Host smart-0e90faf6-a848-46f9-8615-50d7ae7eac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116129644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2116129644
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1377609005
Short name T493
Test name
Test status
Simulation time 4858793807 ps
CPU time 21 seconds
Started Jul 01 05:25:01 PM PDT 24
Finished Jul 01 05:25:29 PM PDT 24
Peak memory 240736 kb
Host smart-06606bd9-c43b-4428-83d7-dc0b456d7a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377609005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1377609005
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1176483108
Short name T70
Test name
Test status
Simulation time 7287005426 ps
CPU time 23.3 seconds
Started Jul 01 05:25:02 PM PDT 24
Finished Jul 01 05:25:33 PM PDT 24
Peak memory 233892 kb
Host smart-76c0ec59-e9e3-44d8-9748-d3564a7ce874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176483108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1176483108
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4018646712
Short name T733
Test name
Test status
Simulation time 885560016 ps
CPU time 7.94 seconds
Started Jul 01 05:25:05 PM PDT 24
Finished Jul 01 05:25:22 PM PDT 24
Peak memory 220228 kb
Host smart-1ad73338-4c3e-443d-b72c-eee346639f13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4018646712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4018646712
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2235923646
Short name T713
Test name
Test status
Simulation time 456024902 ps
CPU time 3.67 seconds
Started Jul 01 05:24:55 PM PDT 24
Finished Jul 01 05:25:03 PM PDT 24
Peak memory 218776 kb
Host smart-4f4d7583-c058-4970-ba5c-e7719619d8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235923646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2235923646
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2379335612
Short name T152
Test name
Test status
Simulation time 529900399 ps
CPU time 2.35 seconds
Started Jul 01 05:24:56 PM PDT 24
Finished Jul 01 05:25:03 PM PDT 24
Peak memory 216192 kb
Host smart-5f2a47c4-efe0-431e-9916-25c1f620a35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379335612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2379335612
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1020268956
Short name T745
Test name
Test status
Simulation time 684856409 ps
CPU time 2.07 seconds
Started Jul 01 05:25:02 PM PDT 24
Finished Jul 01 05:25:10 PM PDT 24
Peak memory 216184 kb
Host smart-d10ac7b5-c811-4306-801a-5f6db4ecde92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020268956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1020268956
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1590305755
Short name T585
Test name
Test status
Simulation time 16374028 ps
CPU time 0.7 seconds
Started Jul 01 05:25:00 PM PDT 24
Finished Jul 01 05:25:06 PM PDT 24
Peak memory 205988 kb
Host smart-d54d63cf-50a9-4ec7-becd-6f14d0b35575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590305755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1590305755
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.787126059
Short name T905
Test name
Test status
Simulation time 2612777625 ps
CPU time 13.49 seconds
Started Jul 01 05:25:02 PM PDT 24
Finished Jul 01 05:25:22 PM PDT 24
Peak memory 232812 kb
Host smart-075d0334-59de-4eae-99c6-7f8d5ae929b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787126059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.787126059
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1681673542
Short name T898
Test name
Test status
Simulation time 69743836 ps
CPU time 0.74 seconds
Started Jul 01 05:25:06 PM PDT 24
Finished Jul 01 05:25:17 PM PDT 24
Peak memory 205560 kb
Host smart-ba8fa71c-4231-4b25-bc08-16116f89a27a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681673542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1681673542
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3170012005
Short name T53
Test name
Test status
Simulation time 503462984 ps
CPU time 3.92 seconds
Started Jul 01 05:25:05 PM PDT 24
Finished Jul 01 05:25:18 PM PDT 24
Peak memory 232592 kb
Host smart-3a1acd47-79ce-45e3-a4a9-fcc7ccbd18eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170012005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3170012005
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.264657933
Short name T429
Test name
Test status
Simulation time 91123241 ps
CPU time 0.87 seconds
Started Jul 01 05:25:02 PM PDT 24
Finished Jul 01 05:25:11 PM PDT 24
Peak memory 207016 kb
Host smart-be9feb6d-e10c-4588-86e5-b317d32390ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264657933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.264657933
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2154210471
Short name T936
Test name
Test status
Simulation time 26444902365 ps
CPU time 87.24 seconds
Started Jul 01 05:25:07 PM PDT 24
Finished Jul 01 05:26:44 PM PDT 24
Peak memory 241076 kb
Host smart-d1ae613e-a084-4e14-8490-f111519f719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154210471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2154210471
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4165176905
Short name T241
Test name
Test status
Simulation time 16906026289 ps
CPU time 95.59 seconds
Started Jul 01 05:25:06 PM PDT 24
Finished Jul 01 05:26:51 PM PDT 24
Peak memory 241084 kb
Host smart-0dfc5702-3e73-4190-93e8-a8d0e334ca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165176905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4165176905
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1696697597
Short name T292
Test name
Test status
Simulation time 3826166162 ps
CPU time 42.41 seconds
Started Jul 01 05:25:06 PM PDT 24
Finished Jul 01 05:25:58 PM PDT 24
Peak memory 239076 kb
Host smart-833b55b5-66d9-43c6-9d3b-ecd689e2b34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696697597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1696697597
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2853280399
Short name T834
Test name
Test status
Simulation time 15508956763 ps
CPU time 70.89 seconds
Started Jul 01 05:25:10 PM PDT 24
Finished Jul 01 05:26:30 PM PDT 24
Peak memory 254116 kb
Host smart-f8d29a57-0ddc-4afd-b0d0-861c51daf806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853280399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2853280399
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2531994849
Short name T774
Test name
Test status
Simulation time 158476705 ps
CPU time 3.21 seconds
Started Jul 01 05:25:03 PM PDT 24
Finished Jul 01 05:25:14 PM PDT 24
Peak memory 224596 kb
Host smart-6a2304a9-7add-4d70-882c-06271315e0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531994849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2531994849
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3806596681
Short name T198
Test name
Test status
Simulation time 25941878778 ps
CPU time 51.13 seconds
Started Jul 01 05:25:04 PM PDT 24
Finished Jul 01 05:26:04 PM PDT 24
Peak memory 232844 kb
Host smart-48636b55-9358-4c53-bc24-9831911b426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806596681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3806596681
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3957486520
Short name T44
Test name
Test status
Simulation time 21160584962 ps
CPU time 20.88 seconds
Started Jul 01 05:25:03 PM PDT 24
Finished Jul 01 05:25:32 PM PDT 24
Peak memory 232820 kb
Host smart-e1e041ac-87bc-4989-881f-effe09c1cc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957486520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3957486520
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3197441324
Short name T995
Test name
Test status
Simulation time 2626238570 ps
CPU time 10.96 seconds
Started Jul 01 05:25:01 PM PDT 24
Finished Jul 01 05:25:19 PM PDT 24
Peak memory 248288 kb
Host smart-c8b50134-62fd-4099-ade0-efd6148204a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197441324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3197441324
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1997315021
Short name T38
Test name
Test status
Simulation time 502791161 ps
CPU time 6.34 seconds
Started Jul 01 05:25:06 PM PDT 24
Finished Jul 01 05:25:21 PM PDT 24
Peak memory 220724 kb
Host smart-f48b9137-26f2-4e48-8530-7dfcb57d41c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1997315021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1997315021
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.472466404
Short name T514
Test name
Test status
Simulation time 67222521 ps
CPU time 1.09 seconds
Started Jul 01 05:25:05 PM PDT 24
Finished Jul 01 05:25:15 PM PDT 24
Peak memory 207444 kb
Host smart-5669dbd8-4036-4ddd-bc9c-eb70efd6f9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472466404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.472466404
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.54762539
Short name T447
Test name
Test status
Simulation time 2315990734 ps
CPU time 18.26 seconds
Started Jul 01 05:25:01 PM PDT 24
Finished Jul 01 05:25:24 PM PDT 24
Peak memory 216700 kb
Host smart-17a5b494-e0b8-4f63-829c-f367ebc1223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54762539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.54762539
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.33957348
Short name T340
Test name
Test status
Simulation time 28980387617 ps
CPU time 19.89 seconds
Started Jul 01 05:25:02 PM PDT 24
Finished Jul 01 05:25:29 PM PDT 24
Peak memory 217764 kb
Host smart-15173fc6-265b-42dd-8ffb-8f0221eb7d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33957348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.33957348
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2312197064
Short name T45
Test name
Test status
Simulation time 318811126 ps
CPU time 3.73 seconds
Started Jul 01 05:25:01 PM PDT 24
Finished Jul 01 05:25:10 PM PDT 24
Peak memory 216292 kb
Host smart-6d3c8e57-10c5-406f-b844-778bf42fdb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312197064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2312197064
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1072014665
Short name T10
Test name
Test status
Simulation time 232785947 ps
CPU time 0.92 seconds
Started Jul 01 05:25:01 PM PDT 24
Finished Jul 01 05:25:08 PM PDT 24
Peak memory 206068 kb
Host smart-cb717ee0-532d-4a2b-9d3b-ba9ac7d68df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072014665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1072014665
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3105843504
Short name T752
Test name
Test status
Simulation time 5318819968 ps
CPU time 18.22 seconds
Started Jul 01 05:25:01 PM PDT 24
Finished Jul 01 05:25:25 PM PDT 24
Peak memory 237676 kb
Host smart-1f3ba4c0-2dc8-42ed-9a5f-9cff420df682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105843504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3105843504
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2021060645
Short name T575
Test name
Test status
Simulation time 39924877 ps
CPU time 0.74 seconds
Started Jul 01 05:25:05 PM PDT 24
Finished Jul 01 05:25:15 PM PDT 24
Peak memory 204996 kb
Host smart-21c40dff-620a-4ded-b51b-2c21142d7713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021060645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2021060645
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1869963366
Short name T990
Test name
Test status
Simulation time 742230604 ps
CPU time 6.69 seconds
Started Jul 01 05:25:08 PM PDT 24
Finished Jul 01 05:25:24 PM PDT 24
Peak memory 232692 kb
Host smart-6a4c96e1-d9ee-4602-ab01-18a24c196ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869963366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1869963366
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1337237482
Short name T529
Test name
Test status
Simulation time 45242285 ps
CPU time 0.77 seconds
Started Jul 01 05:25:14 PM PDT 24
Finished Jul 01 05:25:24 PM PDT 24
Peak memory 205484 kb
Host smart-3ebaa9b4-3d16-4cb6-bcbf-3b560a7306be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337237482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1337237482
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.4095928362
Short name T351
Test name
Test status
Simulation time 27784832943 ps
CPU time 70.8 seconds
Started Jul 01 05:25:05 PM PDT 24
Finished Jul 01 05:26:25 PM PDT 24
Peak memory 255056 kb
Host smart-7a0c3d17-b727-4c59-85a4-2a3851f75451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095928362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.4095928362
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.426042846
Short name T926
Test name
Test status
Simulation time 9987592158 ps
CPU time 148.7 seconds
Started Jul 01 05:25:07 PM PDT 24
Finished Jul 01 05:27:46 PM PDT 24
Peak memory 256604 kb
Host smart-68168de2-a903-4625-ade2-ca5e7dfb28b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426042846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.426042846
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3865995670
Short name T24
Test name
Test status
Simulation time 122829117 ps
CPU time 2.66 seconds
Started Jul 01 05:25:13 PM PDT 24
Finished Jul 01 05:25:25 PM PDT 24
Peak memory 219252 kb
Host smart-33f7b618-ed47-4301-9a92-9f62fb49e90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865995670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3865995670
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.551252109
Short name T871
Test name
Test status
Simulation time 39297893 ps
CPU time 2.49 seconds
Started Jul 01 05:25:07 PM PDT 24
Finished Jul 01 05:25:20 PM PDT 24
Peak memory 224512 kb
Host smart-d1f06601-e418-457d-82ee-670b0a582c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551252109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.551252109
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.978353640
Short name T812
Test name
Test status
Simulation time 128436664 ps
CPU time 0.82 seconds
Started Jul 01 05:25:10 PM PDT 24
Finished Jul 01 05:25:20 PM PDT 24
Peak memory 215900 kb
Host smart-1cd31efa-88dd-4b6b-bb9f-56432d89a5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978353640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.978353640
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3711578579
Short name T505
Test name
Test status
Simulation time 143874935 ps
CPU time 4.35 seconds
Started Jul 01 05:25:06 PM PDT 24
Finished Jul 01 05:25:19 PM PDT 24
Peak memory 232836 kb
Host smart-304a4a12-f67a-4c18-a259-b7bc568323f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711578579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3711578579
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.890231184
Short name T901
Test name
Test status
Simulation time 536859060 ps
CPU time 14.03 seconds
Started Jul 01 05:25:11 PM PDT 24
Finished Jul 01 05:25:34 PM PDT 24
Peak memory 251320 kb
Host smart-3451e709-8bd1-4ff5-879c-1d56d52e2451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890231184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.890231184
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3254888848
Short name T862
Test name
Test status
Simulation time 5098853680 ps
CPU time 6.85 seconds
Started Jul 01 05:25:06 PM PDT 24
Finished Jul 01 05:25:22 PM PDT 24
Peak memory 232776 kb
Host smart-0aa00397-0312-4dae-bf52-9af5ae2bd841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254888848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3254888848
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.992521136
Short name T597
Test name
Test status
Simulation time 116260317 ps
CPU time 2.55 seconds
Started Jul 01 05:25:07 PM PDT 24
Finished Jul 01 05:25:19 PM PDT 24
Peak memory 224472 kb
Host smart-0b3064a1-e5ba-4395-bf27-e47fad50387b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992521136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.992521136
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4193545522
Short name T133
Test name
Test status
Simulation time 316033137 ps
CPU time 3.75 seconds
Started Jul 01 05:25:08 PM PDT 24
Finished Jul 01 05:25:21 PM PDT 24
Peak memory 220708 kb
Host smart-57f9d70e-cfd5-480d-b356-b8136dc03b07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4193545522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4193545522
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1514742271
Short name T424
Test name
Test status
Simulation time 4730628303 ps
CPU time 6.34 seconds
Started Jul 01 05:25:06 PM PDT 24
Finished Jul 01 05:25:21 PM PDT 24
Peak memory 216596 kb
Host smart-1b091133-4708-4dde-9786-58d87ec9d1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514742271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1514742271
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3565211082
Short name T730
Test name
Test status
Simulation time 1217495147 ps
CPU time 6.86 seconds
Started Jul 01 05:25:11 PM PDT 24
Finished Jul 01 05:25:27 PM PDT 24
Peak memory 216144 kb
Host smart-399d7b0f-905d-4028-85eb-c9c42bd0b08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565211082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3565211082
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2035971487
Short name T431
Test name
Test status
Simulation time 13530346 ps
CPU time 0.69 seconds
Started Jul 01 05:25:08 PM PDT 24
Finished Jul 01 05:25:19 PM PDT 24
Peak memory 205716 kb
Host smart-97ae6a56-1f8f-4116-a73e-f359dff4dd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035971487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2035971487
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4248277600
Short name T563
Test name
Test status
Simulation time 48697904 ps
CPU time 0.87 seconds
Started Jul 01 05:25:13 PM PDT 24
Finished Jul 01 05:25:23 PM PDT 24
Peak memory 206064 kb
Host smart-093a383f-79b5-4019-93af-b47f7df4d1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248277600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4248277600
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.367375000
Short name T554
Test name
Test status
Simulation time 2862422977 ps
CPU time 8.01 seconds
Started Jul 01 05:25:08 PM PDT 24
Finished Jul 01 05:25:26 PM PDT 24
Peak memory 232896 kb
Host smart-5fd3e720-3aea-4205-82f2-732209d18d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367375000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.367375000
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3085864699
Short name T539
Test name
Test status
Simulation time 22146467 ps
CPU time 0.78 seconds
Started Jul 01 05:25:18 PM PDT 24
Finished Jul 01 05:25:27 PM PDT 24
Peak memory 205052 kb
Host smart-511873f2-078a-47ef-9de8-9dbd0daf9e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085864699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3085864699
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1168299172
Short name T829
Test name
Test status
Simulation time 979665084 ps
CPU time 8.47 seconds
Started Jul 01 05:25:13 PM PDT 24
Finished Jul 01 05:25:31 PM PDT 24
Peak memory 224468 kb
Host smart-adf83bfe-904e-48f4-9c16-20cd23ec187c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168299172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1168299172
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3208160035
Short name T649
Test name
Test status
Simulation time 18918291 ps
CPU time 0.79 seconds
Started Jul 01 05:25:07 PM PDT 24
Finished Jul 01 05:25:18 PM PDT 24
Peak memory 206940 kb
Host smart-2ee925d1-2216-4963-9fa1-e7910a7d3c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208160035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3208160035
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2222747440
Short name T69
Test name
Test status
Simulation time 12536597785 ps
CPU time 19 seconds
Started Jul 01 05:25:12 PM PDT 24
Finished Jul 01 05:25:41 PM PDT 24
Peak memory 232996 kb
Host smart-76afb640-e106-45bf-b98c-1eabd28bb289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222747440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2222747440
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2458728270
Short name T648
Test name
Test status
Simulation time 1203795947 ps
CPU time 18.12 seconds
Started Jul 01 05:25:15 PM PDT 24
Finished Jul 01 05:25:42 PM PDT 24
Peak memory 236804 kb
Host smart-85ea4670-fe3a-47a3-884c-f5df1deb0fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458728270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2458728270
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.430126749
Short name T655
Test name
Test status
Simulation time 320551920 ps
CPU time 7.02 seconds
Started Jul 01 05:25:13 PM PDT 24
Finished Jul 01 05:25:30 PM PDT 24
Peak memory 224516 kb
Host smart-ac7fcce7-0b39-45a2-bf1a-17c04b3504d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430126749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.430126749
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.897654226
Short name T380
Test name
Test status
Simulation time 46821835281 ps
CPU time 96.13 seconds
Started Jul 01 05:25:13 PM PDT 24
Finished Jul 01 05:26:59 PM PDT 24
Peak memory 249304 kb
Host smart-7474e1ee-6637-4f40-ae2f-ded1d368f2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897654226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.897654226
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3206979945
Short name T443
Test name
Test status
Simulation time 667259596 ps
CPU time 4.27 seconds
Started Jul 01 05:25:13 PM PDT 24
Finished Jul 01 05:25:27 PM PDT 24
Peak memory 224452 kb
Host smart-302a218f-02e2-409b-9ce0-efe4cf14d2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206979945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3206979945
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1567025118
Short name T470
Test name
Test status
Simulation time 27420901640 ps
CPU time 16.22 seconds
Started Jul 01 05:25:14 PM PDT 24
Finished Jul 01 05:25:39 PM PDT 24
Peak memory 232856 kb
Host smart-2aa880fa-ed7a-4974-b46f-b984ed4b9b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567025118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1567025118
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4023156653
Short name T284
Test name
Test status
Simulation time 6168899775 ps
CPU time 17.47 seconds
Started Jul 01 05:25:16 PM PDT 24
Finished Jul 01 05:25:42 PM PDT 24
Peak memory 240596 kb
Host smart-07e67ecc-1c53-498f-be04-3c595cd8e16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023156653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4023156653
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.51666512
Short name T253
Test name
Test status
Simulation time 726847372 ps
CPU time 8.3 seconds
Started Jul 01 05:25:12 PM PDT 24
Finished Jul 01 05:25:30 PM PDT 24
Peak memory 232632 kb
Host smart-6899a21b-8699-4734-97ce-d501d4908c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51666512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.51666512
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.195934349
Short name T725
Test name
Test status
Simulation time 12533693280 ps
CPU time 13.45 seconds
Started Jul 01 05:25:13 PM PDT 24
Finished Jul 01 05:25:36 PM PDT 24
Peak memory 221792 kb
Host smart-fff2f50a-eeaa-4994-bc0f-0f37dcdbf163
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=195934349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.195934349
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3146650642
Short name T304
Test name
Test status
Simulation time 868029698 ps
CPU time 6.34 seconds
Started Jul 01 05:25:12 PM PDT 24
Finished Jul 01 05:25:28 PM PDT 24
Peak memory 216284 kb
Host smart-6b4abc41-06dd-4ccc-b5f7-e65b92b86471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146650642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3146650642
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3711021404
Short name T481
Test name
Test status
Simulation time 105863129910 ps
CPU time 14.68 seconds
Started Jul 01 05:25:13 PM PDT 24
Finished Jul 01 05:25:37 PM PDT 24
Peak memory 218036 kb
Host smart-8615bfb4-7bc0-4afc-aed4-01ba9c2df8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711021404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3711021404
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1835002694
Short name T750
Test name
Test status
Simulation time 17458256 ps
CPU time 0.93 seconds
Started Jul 01 05:25:12 PM PDT 24
Finished Jul 01 05:25:23 PM PDT 24
Peak memory 206808 kb
Host smart-7e191b14-4dc8-4fd1-8603-c9924c31762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835002694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1835002694
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2730431821
Short name T491
Test name
Test status
Simulation time 197105007 ps
CPU time 0.76 seconds
Started Jul 01 05:25:13 PM PDT 24
Finished Jul 01 05:25:24 PM PDT 24
Peak memory 206000 kb
Host smart-5aed21f6-fbb4-4e9f-8ad9-49c90e4f6478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730431821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2730431821
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3567927826
Short name T855
Test name
Test status
Simulation time 572006043 ps
CPU time 9.65 seconds
Started Jul 01 05:25:17 PM PDT 24
Finished Jul 01 05:25:35 PM PDT 24
Peak memory 235640 kb
Host smart-15b151fa-6ec7-412c-a9c9-e6a8362d3306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567927826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3567927826
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2693635856
Short name T738
Test name
Test status
Simulation time 11079401 ps
CPU time 0.72 seconds
Started Jul 01 05:25:18 PM PDT 24
Finished Jul 01 05:25:27 PM PDT 24
Peak memory 204964 kb
Host smart-9f8d806a-aeec-4488-83d8-f106554aa540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693635856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2693635856
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3783875502
Short name T1011
Test name
Test status
Simulation time 232608263 ps
CPU time 3.43 seconds
Started Jul 01 05:25:21 PM PDT 24
Finished Jul 01 05:25:32 PM PDT 24
Peak memory 232676 kb
Host smart-f739b61d-7583-46cf-9c80-3b61888bf7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783875502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3783875502
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1656280952
Short name T446
Test name
Test status
Simulation time 19519969 ps
CPU time 0.79 seconds
Started Jul 01 05:25:18 PM PDT 24
Finished Jul 01 05:25:27 PM PDT 24
Peak memory 206940 kb
Host smart-18ff9928-2327-457f-b954-564a26e2458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656280952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1656280952
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4112623851
Short name T503
Test name
Test status
Simulation time 10153733848 ps
CPU time 50.48 seconds
Started Jul 01 05:25:19 PM PDT 24
Finished Jul 01 05:26:18 PM PDT 24
Peak memory 249260 kb
Host smart-750890b3-9f93-4ebc-976e-e90d894ad01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112623851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4112623851
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1282811648
Short name T2
Test name
Test status
Simulation time 19642616647 ps
CPU time 111.17 seconds
Started Jul 01 05:25:21 PM PDT 24
Finished Jul 01 05:27:20 PM PDT 24
Peak memory 241100 kb
Host smart-b9f7e9b2-029a-45a9-8911-2496c8148819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282811648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1282811648
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2630295902
Short name T465
Test name
Test status
Simulation time 7001268532 ps
CPU time 81.84 seconds
Started Jul 01 05:25:17 PM PDT 24
Finished Jul 01 05:26:47 PM PDT 24
Peak memory 241084 kb
Host smart-1400d1a0-e7aa-4e55-bf15-65188512b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630295902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2630295902
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2905536594
Short name T297
Test name
Test status
Simulation time 5677427056 ps
CPU time 13.08 seconds
Started Jul 01 05:25:18 PM PDT 24
Finished Jul 01 05:25:40 PM PDT 24
Peak memory 237868 kb
Host smart-2033644e-d3d0-4455-87c8-edc610facec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905536594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2905536594
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3674865639
Short name T887
Test name
Test status
Simulation time 15744598893 ps
CPU time 109.51 seconds
Started Jul 01 05:25:20 PM PDT 24
Finished Jul 01 05:27:18 PM PDT 24
Peak memory 249228 kb
Host smart-718ac203-5e87-4de8-842a-d0e1ed979056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674865639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3674865639
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1852520123
Short name T1005
Test name
Test status
Simulation time 1798653632 ps
CPU time 5.12 seconds
Started Jul 01 05:25:19 PM PDT 24
Finished Jul 01 05:25:32 PM PDT 24
Peak memory 224500 kb
Host smart-bf311213-31cc-4ea8-bc66-b103b1341671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852520123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1852520123
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1635440464
Short name T907
Test name
Test status
Simulation time 134746362 ps
CPU time 2.52 seconds
Started Jul 01 05:25:20 PM PDT 24
Finished Jul 01 05:25:31 PM PDT 24
Peak memory 232296 kb
Host smart-ddb79234-3e1b-46ec-ab94-152693ca30f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635440464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1635440464
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3810093723
Short name T73
Test name
Test status
Simulation time 1523372738 ps
CPU time 6.07 seconds
Started Jul 01 05:25:19 PM PDT 24
Finished Jul 01 05:25:33 PM PDT 24
Peak memory 224464 kb
Host smart-29b342f1-0852-45ef-84f6-8a2095c6965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810093723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3810093723
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1729553513
Short name T228
Test name
Test status
Simulation time 174827398 ps
CPU time 2.18 seconds
Started Jul 01 05:25:19 PM PDT 24
Finished Jul 01 05:25:29 PM PDT 24
Peak memory 224448 kb
Host smart-0c7e7521-3a83-4b66-86cc-29e850d520e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729553513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1729553513
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4227695365
Short name T931
Test name
Test status
Simulation time 364750274 ps
CPU time 4.37 seconds
Started Jul 01 05:25:18 PM PDT 24
Finished Jul 01 05:25:31 PM PDT 24
Peak memory 220664 kb
Host smart-b2fb4d8e-a1ec-404e-9db8-dde035157889
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4227695365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4227695365
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1165585911
Short name T206
Test name
Test status
Simulation time 36070149898 ps
CPU time 196.68 seconds
Started Jul 01 05:25:19 PM PDT 24
Finished Jul 01 05:28:44 PM PDT 24
Peak memory 257400 kb
Host smart-2c8a52e1-bcc1-4a38-964c-e394c6379e7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165585911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1165585911
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2232239776
Short name T504
Test name
Test status
Simulation time 4932114843 ps
CPU time 15.23 seconds
Started Jul 01 05:25:19 PM PDT 24
Finished Jul 01 05:25:43 PM PDT 24
Peak memory 216304 kb
Host smart-e3b57c34-e042-4994-8f42-ed026202f6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232239776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2232239776
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1400540441
Short name T322
Test name
Test status
Simulation time 1149520046 ps
CPU time 8.2 seconds
Started Jul 01 05:25:17 PM PDT 24
Finished Jul 01 05:25:33 PM PDT 24
Peak memory 216224 kb
Host smart-e69384d4-2a39-44da-a2e0-0401294f4b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400540441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1400540441
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2777245507
Short name T545
Test name
Test status
Simulation time 362009291 ps
CPU time 3.22 seconds
Started Jul 01 05:25:18 PM PDT 24
Finished Jul 01 05:25:29 PM PDT 24
Peak memory 216240 kb
Host smart-27236299-1438-47d4-9ef3-34066058927c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777245507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2777245507
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2735649644
Short name T335
Test name
Test status
Simulation time 30566461 ps
CPU time 0.82 seconds
Started Jul 01 05:25:18 PM PDT 24
Finished Jul 01 05:25:27 PM PDT 24
Peak memory 206000 kb
Host smart-1d830ad0-fa47-4067-b05a-2201fdc7c54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735649644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2735649644
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.392146225
Short name T861
Test name
Test status
Simulation time 3722704675 ps
CPU time 19.64 seconds
Started Jul 01 05:25:21 PM PDT 24
Finished Jul 01 05:25:48 PM PDT 24
Peak memory 232796 kb
Host smart-7e8c1183-805e-41f7-a434-831961120ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392146225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.392146225
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2856491300
Short name T316
Test name
Test status
Simulation time 21110103 ps
CPU time 0.73 seconds
Started Jul 01 05:24:03 PM PDT 24
Finished Jul 01 05:24:06 PM PDT 24
Peak memory 205544 kb
Host smart-f9a7fb9f-e55a-4bc4-8949-584d1bdd6a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856491300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
856491300
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.833319864
Short name T258
Test name
Test status
Simulation time 719991749 ps
CPU time 5.36 seconds
Started Jul 01 05:24:02 PM PDT 24
Finished Jul 01 05:24:10 PM PDT 24
Peak memory 224576 kb
Host smart-65869f59-a01d-4f7b-9dd3-b5e4cf18f058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833319864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.833319864
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3561223693
Short name T656
Test name
Test status
Simulation time 24947574 ps
CPU time 0.77 seconds
Started Jul 01 05:23:57 PM PDT 24
Finished Jul 01 05:24:01 PM PDT 24
Peak memory 205908 kb
Host smart-3d016e08-3ebd-4d8b-9f9e-006a5c5a6ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561223693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3561223693
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.587797258
Short name T287
Test name
Test status
Simulation time 5237514423 ps
CPU time 90.54 seconds
Started Jul 01 05:24:11 PM PDT 24
Finished Jul 01 05:25:44 PM PDT 24
Peak memory 255556 kb
Host smart-b009aa7b-2719-46c2-bd36-770e602d5dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587797258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.587797258
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2921487780
Short name T685
Test name
Test status
Simulation time 71889012059 ps
CPU time 365.23 seconds
Started Jul 01 05:24:02 PM PDT 24
Finished Jul 01 05:30:10 PM PDT 24
Peak memory 255388 kb
Host smart-09a7ed19-885a-482d-afcd-d3c9695763ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921487780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2921487780
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1713342776
Short name T441
Test name
Test status
Simulation time 19366242500 ps
CPU time 177.95 seconds
Started Jul 01 05:24:03 PM PDT 24
Finished Jul 01 05:27:03 PM PDT 24
Peak memory 250280 kb
Host smart-cff3b328-02c8-4956-bf17-2bad7285bcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713342776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1713342776
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3205910182
Short name T6
Test name
Test status
Simulation time 91117768 ps
CPU time 4.24 seconds
Started Jul 01 05:24:00 PM PDT 24
Finished Jul 01 05:24:07 PM PDT 24
Peak memory 224456 kb
Host smart-bfa1560d-7bce-4fd2-a2ba-578672bc4c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205910182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3205910182
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2900936329
Short name T437
Test name
Test status
Simulation time 20297125122 ps
CPU time 50.97 seconds
Started Jul 01 05:24:03 PM PDT 24
Finished Jul 01 05:24:56 PM PDT 24
Peak memory 250360 kb
Host smart-6812ad91-8415-40d3-895f-2d39bdb29972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900936329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2900936329
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3748098012
Short name T949
Test name
Test status
Simulation time 10651747705 ps
CPU time 14.78 seconds
Started Jul 01 05:24:11 PM PDT 24
Finished Jul 01 05:24:28 PM PDT 24
Peak memory 224436 kb
Host smart-cdc05405-6e45-4175-9ae1-94bedf367246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748098012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3748098012
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.4194506801
Short name T770
Test name
Test status
Simulation time 3594501717 ps
CPU time 23.12 seconds
Started Jul 01 05:24:02 PM PDT 24
Finished Jul 01 05:24:28 PM PDT 24
Peak memory 232892 kb
Host smart-f1c83872-e48f-49c5-bb32-f27ea115af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194506801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4194506801
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2375533543
Short name T246
Test name
Test status
Simulation time 4391316527 ps
CPU time 16.25 seconds
Started Jul 01 05:24:06 PM PDT 24
Finished Jul 01 05:24:23 PM PDT 24
Peak memory 232768 kb
Host smart-61fea8a5-9a51-4ec8-bc57-229b646d5051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375533543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2375533543
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.743953239
Short name T882
Test name
Test status
Simulation time 22642953311 ps
CPU time 31.74 seconds
Started Jul 01 05:23:58 PM PDT 24
Finished Jul 01 05:24:32 PM PDT 24
Peak memory 240856 kb
Host smart-3fa7494a-87bf-4fed-8a05-16891fd7ec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743953239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.743953239
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1691994316
Short name T511
Test name
Test status
Simulation time 4252992720 ps
CPU time 12.19 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:25 PM PDT 24
Peak memory 223192 kb
Host smart-b6999672-7f81-4978-942a-542adec9d7bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1691994316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1691994316
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2521430095
Short name T64
Test name
Test status
Simulation time 193979400 ps
CPU time 1.12 seconds
Started Jul 01 05:24:02 PM PDT 24
Finished Jul 01 05:24:06 PM PDT 24
Peak memory 235996 kb
Host smart-c6469d0c-9d35-4230-a704-fe2fc35d56fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521430095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2521430095
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1231861269
Short name T652
Test name
Test status
Simulation time 5391881479 ps
CPU time 42.37 seconds
Started Jul 01 05:24:02 PM PDT 24
Finished Jul 01 05:24:48 PM PDT 24
Peak memory 241112 kb
Host smart-5e919cd9-b89c-4f98-b3e4-3a7f154610dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231861269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1231861269
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2164146061
Short name T543
Test name
Test status
Simulation time 13122832800 ps
CPU time 37.06 seconds
Started Jul 01 05:23:55 PM PDT 24
Finished Jul 01 05:24:32 PM PDT 24
Peak memory 216388 kb
Host smart-aeb128f9-656f-4a2e-9a6e-8add925b2a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164146061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2164146061
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1165612150
Short name T475
Test name
Test status
Simulation time 4552609054 ps
CPU time 13.57 seconds
Started Jul 01 05:23:57 PM PDT 24
Finished Jul 01 05:24:13 PM PDT 24
Peak memory 216404 kb
Host smart-c4d4e851-f036-4140-957e-4a6318628a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165612150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1165612150
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2564998171
Short name T849
Test name
Test status
Simulation time 86310858 ps
CPU time 1.52 seconds
Started Jul 01 05:23:56 PM PDT 24
Finished Jul 01 05:23:58 PM PDT 24
Peak memory 216212 kb
Host smart-77d3fe28-9baf-45fd-81e4-ffbd8c63bc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564998171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2564998171
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1789160561
Short name T334
Test name
Test status
Simulation time 217282977 ps
CPU time 0.91 seconds
Started Jul 01 05:23:57 PM PDT 24
Finished Jul 01 05:24:01 PM PDT 24
Peak memory 205988 kb
Host smart-b4b5a817-7fa7-4e58-9b72-d09d3529647e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789160561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1789160561
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.4036089910
Short name T953
Test name
Test status
Simulation time 1405289154 ps
CPU time 6.46 seconds
Started Jul 01 05:24:08 PM PDT 24
Finished Jul 01 05:24:15 PM PDT 24
Peak memory 232640 kb
Host smart-e74e9784-02e9-47d5-827e-bc89851b74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036089910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4036089910
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2871746149
Short name T722
Test name
Test status
Simulation time 62748192 ps
CPU time 0.72 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:32 PM PDT 24
Peak memory 205000 kb
Host smart-315a6f85-a269-412c-8442-f3483fd7bf49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871746149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2871746149
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1075454355
Short name T1019
Test name
Test status
Simulation time 139570632 ps
CPU time 2.48 seconds
Started Jul 01 05:25:23 PM PDT 24
Finished Jul 01 05:25:32 PM PDT 24
Peak memory 224500 kb
Host smart-f6a6833a-c9a3-40f5-9e17-bc50adc8f4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075454355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1075454355
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3921647063
Short name T778
Test name
Test status
Simulation time 71632026 ps
CPU time 0.81 seconds
Started Jul 01 05:25:19 PM PDT 24
Finished Jul 01 05:25:28 PM PDT 24
Peak memory 206672 kb
Host smart-84798d91-cc1a-49de-bd21-6398399f1234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921647063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3921647063
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3800490676
Short name T542
Test name
Test status
Simulation time 665839142 ps
CPU time 16.21 seconds
Started Jul 01 05:25:23 PM PDT 24
Finished Jul 01 05:25:46 PM PDT 24
Peak memory 249240 kb
Host smart-5ee6a57b-c6e7-496e-b04f-1dfdb5fefe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800490676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3800490676
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.360783064
Short name T190
Test name
Test status
Simulation time 270092962166 ps
CPU time 311.93 seconds
Started Jul 01 05:25:26 PM PDT 24
Finished Jul 01 05:30:44 PM PDT 24
Peak memory 265280 kb
Host smart-5a0d67b7-233d-4e66-b28c-b58193014cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360783064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.360783064
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3142806779
Short name T992
Test name
Test status
Simulation time 18562844099 ps
CPU time 207.69 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:28:58 PM PDT 24
Peak memory 250748 kb
Host smart-d2f70d69-faac-469f-9c49-c183bc282e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142806779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3142806779
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2463387475
Short name T653
Test name
Test status
Simulation time 495331292 ps
CPU time 6.06 seconds
Started Jul 01 05:25:23 PM PDT 24
Finished Jul 01 05:25:35 PM PDT 24
Peak memory 224444 kb
Host smart-3f63ed80-2544-487d-ae9a-7d6f5076f429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463387475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2463387475
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3857600245
Short name T568
Test name
Test status
Simulation time 14531686 ps
CPU time 0.82 seconds
Started Jul 01 05:25:28 PM PDT 24
Finished Jul 01 05:25:34 PM PDT 24
Peak memory 215808 kb
Host smart-88c9e5ba-d33b-4b49-8619-28b6d3060f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857600245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3857600245
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.400695988
Short name T987
Test name
Test status
Simulation time 11046067797 ps
CPU time 9.38 seconds
Started Jul 01 05:25:23 PM PDT 24
Finished Jul 01 05:25:39 PM PDT 24
Peak memory 232832 kb
Host smart-bd032144-051f-45fa-a312-bc8205edeece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400695988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.400695988
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.231383823
Short name T647
Test name
Test status
Simulation time 3074304010 ps
CPU time 20.75 seconds
Started Jul 01 05:25:25 PM PDT 24
Finished Jul 01 05:25:52 PM PDT 24
Peak memory 240976 kb
Host smart-a5d7f2d4-3ef2-4ce8-9682-d90da973410a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231383823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.231383823
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2208876161
Short name T455
Test name
Test status
Simulation time 220170685 ps
CPU time 5.62 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:36 PM PDT 24
Peak memory 233644 kb
Host smart-9f0111f1-9760-454d-b16f-23880fc6a6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208876161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2208876161
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.254209333
Short name T39
Test name
Test status
Simulation time 7563788694 ps
CPU time 17.01 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:47 PM PDT 24
Peak memory 224632 kb
Host smart-fc4a2e3a-c32a-4386-8d47-201595710ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254209333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.254209333
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.409606613
Short name T806
Test name
Test status
Simulation time 1106439985 ps
CPU time 5.87 seconds
Started Jul 01 05:25:26 PM PDT 24
Finished Jul 01 05:25:38 PM PDT 24
Peak memory 222616 kb
Host smart-e1294bf1-5e75-4404-ae66-4b5810ff7102
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=409606613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.409606613
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1341481487
Short name T451
Test name
Test status
Simulation time 356371499 ps
CPU time 3.66 seconds
Started Jul 01 05:25:19 PM PDT 24
Finished Jul 01 05:25:31 PM PDT 24
Peak memory 217440 kb
Host smart-63a74536-3df6-4ca3-9b7b-f3ed069a2b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341481487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1341481487
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3082813987
Short name T832
Test name
Test status
Simulation time 18874926148 ps
CPU time 12.2 seconds
Started Jul 01 05:25:19 PM PDT 24
Finished Jul 01 05:25:39 PM PDT 24
Peak memory 217400 kb
Host smart-e7a57471-3a17-4847-8155-3747bdb99235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082813987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3082813987
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.372660001
Short name T574
Test name
Test status
Simulation time 1039833098 ps
CPU time 2.54 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:33 PM PDT 24
Peak memory 216264 kb
Host smart-ce5f0f31-5b28-4c4c-b6d8-2a1a0757c195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372660001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.372660001
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2234211198
Short name T408
Test name
Test status
Simulation time 184596305 ps
CPU time 0.85 seconds
Started Jul 01 05:25:22 PM PDT 24
Finished Jul 01 05:25:30 PM PDT 24
Peak memory 206008 kb
Host smart-4532be5e-a22c-48b2-840d-65bc7a92ac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234211198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2234211198
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2568006610
Short name T173
Test name
Test status
Simulation time 269852005 ps
CPU time 2.45 seconds
Started Jul 01 05:25:25 PM PDT 24
Finished Jul 01 05:25:33 PM PDT 24
Peak memory 224528 kb
Host smart-69033dbc-2991-443c-8b37-a1c86f3d72eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568006610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2568006610
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1911493360
Short name T358
Test name
Test status
Simulation time 15297368 ps
CPU time 0.75 seconds
Started Jul 01 05:25:32 PM PDT 24
Finished Jul 01 05:25:36 PM PDT 24
Peak memory 205896 kb
Host smart-dd4ea4b0-eb54-4f05-bbab-7f08f8d57e01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911493360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1911493360
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.980938909
Short name T11
Test name
Test status
Simulation time 1810297792 ps
CPU time 7.91 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:39 PM PDT 24
Peak memory 224512 kb
Host smart-e934e266-b632-4fde-9248-10a7ac222f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980938909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.980938909
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4013632172
Short name T944
Test name
Test status
Simulation time 24560281 ps
CPU time 0.82 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:31 PM PDT 24
Peak memory 206644 kb
Host smart-248a4f7c-a4d7-410a-8298-c5073fac9d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013632172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4013632172
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1267245615
Short name T390
Test name
Test status
Simulation time 17730308756 ps
CPU time 61.21 seconds
Started Jul 01 05:25:30 PM PDT 24
Finished Jul 01 05:26:36 PM PDT 24
Peak memory 249308 kb
Host smart-2020c6f4-ccba-4f33-8bfb-562ca94272bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267245615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1267245615
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3458241823
Short name T158
Test name
Test status
Simulation time 30940971672 ps
CPU time 129.81 seconds
Started Jul 01 05:25:34 PM PDT 24
Finished Jul 01 05:27:47 PM PDT 24
Peak memory 249056 kb
Host smart-33976ab6-1a9c-4ddb-88a0-79ebb28e24f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458241823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3458241823
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1312387321
Short name T477
Test name
Test status
Simulation time 666390505 ps
CPU time 9.23 seconds
Started Jul 01 05:25:30 PM PDT 24
Finished Jul 01 05:25:44 PM PDT 24
Peak memory 224512 kb
Host smart-00663261-fffd-404a-9ff2-69934200868e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312387321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1312387321
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3142642053
Short name T548
Test name
Test status
Simulation time 8969023267 ps
CPU time 31.57 seconds
Started Jul 01 05:25:29 PM PDT 24
Finished Jul 01 05:26:06 PM PDT 24
Peak memory 240984 kb
Host smart-6354a06d-1708-4d9c-8818-045a49e6eb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142642053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3142642053
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3860926100
Short name T962
Test name
Test status
Simulation time 264066786 ps
CPU time 4.66 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:35 PM PDT 24
Peak memory 232716 kb
Host smart-b48d7eef-8d47-487f-9ef2-9d40c42372e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860926100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3860926100
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3748201987
Short name T203
Test name
Test status
Simulation time 1302827776 ps
CPU time 10.06 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:40 PM PDT 24
Peak memory 232788 kb
Host smart-26ef68fb-9f80-4002-8e48-6af6e9bf8551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748201987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3748201987
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1095877805
Short name T398
Test name
Test status
Simulation time 29868122 ps
CPU time 2.23 seconds
Started Jul 01 05:25:22 PM PDT 24
Finished Jul 01 05:25:31 PM PDT 24
Peak memory 222928 kb
Host smart-5032462a-2a6e-4ef2-8285-841c67eb2242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095877805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1095877805
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4165112641
Short name T199
Test name
Test status
Simulation time 5433126006 ps
CPU time 8.07 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:38 PM PDT 24
Peak memory 224676 kb
Host smart-82a64ceb-a65d-4a65-8432-e4a308118b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165112641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4165112641
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.268482215
Short name T571
Test name
Test status
Simulation time 3006360377 ps
CPU time 17.94 seconds
Started Jul 01 05:25:29 PM PDT 24
Finished Jul 01 05:25:52 PM PDT 24
Peak memory 222352 kb
Host smart-bba0ca56-25d9-4817-8420-0cd6667b8030
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=268482215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.268482215
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3789973543
Short name T846
Test name
Test status
Simulation time 321699014474 ps
CPU time 648.78 seconds
Started Jul 01 05:25:31 PM PDT 24
Finished Jul 01 05:36:24 PM PDT 24
Peak memory 282132 kb
Host smart-35c60a4f-06b5-484b-9457-c17ff0fb252d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789973543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3789973543
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2596811241
Short name T305
Test name
Test status
Simulation time 6518828399 ps
CPU time 34.6 seconds
Started Jul 01 05:25:28 PM PDT 24
Finished Jul 01 05:26:07 PM PDT 24
Peak memory 216288 kb
Host smart-cbf89591-4eaf-4401-b437-9937f824ac5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596811241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2596811241
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1723444950
Short name T406
Test name
Test status
Simulation time 696407324 ps
CPU time 2.66 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:33 PM PDT 24
Peak memory 216232 kb
Host smart-c93dfbdf-66db-4678-80b0-a2a9a2064da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723444950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1723444950
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.538380632
Short name T728
Test name
Test status
Simulation time 36091985 ps
CPU time 0.85 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:30 PM PDT 24
Peak memory 207056 kb
Host smart-bef30146-8572-44d3-a8f5-884dcfbfb293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538380632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.538380632
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2922749941
Short name T791
Test name
Test status
Simulation time 122913733 ps
CPU time 0.92 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:31 PM PDT 24
Peak memory 206092 kb
Host smart-f009e4b6-f1d4-429e-9537-75fde7263ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922749941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2922749941
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.853561533
Short name T257
Test name
Test status
Simulation time 1321720464 ps
CPU time 3.75 seconds
Started Jul 01 05:25:24 PM PDT 24
Finished Jul 01 05:25:34 PM PDT 24
Peak memory 232664 kb
Host smart-bada9818-c936-4789-9a31-e4bdb0080068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853561533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.853561533
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3778868941
Short name T819
Test name
Test status
Simulation time 40757071 ps
CPU time 0.72 seconds
Started Jul 01 05:25:30 PM PDT 24
Finished Jul 01 05:25:35 PM PDT 24
Peak memory 205568 kb
Host smart-994f48a3-e7f5-4671-b373-01f204a256b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778868941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3778868941
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.484169343
Short name T865
Test name
Test status
Simulation time 354822716 ps
CPU time 3.1 seconds
Started Jul 01 05:25:30 PM PDT 24
Finished Jul 01 05:25:38 PM PDT 24
Peak memory 232688 kb
Host smart-59818fa1-fd49-44e5-86c0-6b8349ce73ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484169343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.484169343
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.894740708
Short name T718
Test name
Test status
Simulation time 100305766 ps
CPU time 0.85 seconds
Started Jul 01 05:25:32 PM PDT 24
Finished Jul 01 05:25:37 PM PDT 24
Peak memory 206984 kb
Host smart-f922e4a0-d9bf-4ae8-8fd8-d59be9236533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894740708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.894740708
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2957392024
Short name T908
Test name
Test status
Simulation time 8689792344 ps
CPU time 111.46 seconds
Started Jul 01 05:25:31 PM PDT 24
Finished Jul 01 05:27:27 PM PDT 24
Peak memory 249304 kb
Host smart-f08cca66-8413-4aa0-97ec-87c1486e96a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957392024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2957392024
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3865521777
Short name T512
Test name
Test status
Simulation time 7364384025 ps
CPU time 74.7 seconds
Started Jul 01 05:25:33 PM PDT 24
Finished Jul 01 05:26:52 PM PDT 24
Peak memory 232848 kb
Host smart-6fd48e4d-6c30-4870-9567-1e899fbf3bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865521777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3865521777
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2193456699
Short name T715
Test name
Test status
Simulation time 1274921485 ps
CPU time 8.79 seconds
Started Jul 01 05:25:30 PM PDT 24
Finished Jul 01 05:25:44 PM PDT 24
Peak memory 240908 kb
Host smart-c7c2b552-baef-4cc2-ac4a-ad440ef16726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193456699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2193456699
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.23506171
Short name T934
Test name
Test status
Simulation time 44273873851 ps
CPU time 160.71 seconds
Started Jul 01 05:25:30 PM PDT 24
Finished Jul 01 05:28:15 PM PDT 24
Peak memory 266004 kb
Host smart-0e114f21-eafd-4a93-ac6a-90b27b6c056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23506171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.23506171
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2115251393
Short name T497
Test name
Test status
Simulation time 435972880 ps
CPU time 4.19 seconds
Started Jul 01 05:25:31 PM PDT 24
Finished Jul 01 05:25:39 PM PDT 24
Peak memory 232652 kb
Host smart-df2bfc09-7506-43fc-af11-79258339b07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115251393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2115251393
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2662958988
Short name T903
Test name
Test status
Simulation time 6776983748 ps
CPU time 69.66 seconds
Started Jul 01 05:25:30 PM PDT 24
Finished Jul 01 05:26:45 PM PDT 24
Peak memory 224744 kb
Host smart-bde4a4d5-a165-4c45-b114-67cc459057fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662958988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2662958988
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4252575750
Short name T935
Test name
Test status
Simulation time 119946762 ps
CPU time 2.2 seconds
Started Jul 01 05:25:33 PM PDT 24
Finished Jul 01 05:25:39 PM PDT 24
Peak memory 232360 kb
Host smart-8fb6100a-20ae-4b1b-9790-6368a58bc7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252575750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4252575750
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2370413729
Short name T815
Test name
Test status
Simulation time 5773938758 ps
CPU time 9.54 seconds
Started Jul 01 05:25:33 PM PDT 24
Finished Jul 01 05:25:46 PM PDT 24
Peak memory 248876 kb
Host smart-a818f4ab-d2bb-43eb-82d0-ed0472236975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370413729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2370413729
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4003688116
Short name T785
Test name
Test status
Simulation time 7833159766 ps
CPU time 15.47 seconds
Started Jul 01 05:25:30 PM PDT 24
Finished Jul 01 05:25:50 PM PDT 24
Peak memory 223316 kb
Host smart-437581d3-3e81-4417-a41e-86de69ec4a63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4003688116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4003688116
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3294983840
Short name T17
Test name
Test status
Simulation time 38655546754 ps
CPU time 140.74 seconds
Started Jul 01 05:25:32 PM PDT 24
Finished Jul 01 05:27:56 PM PDT 24
Peak memory 249332 kb
Host smart-75ce6025-5f81-4af1-8605-6865aff3cc77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294983840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3294983840
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2169857030
Short name T631
Test name
Test status
Simulation time 4067813391 ps
CPU time 24.75 seconds
Started Jul 01 05:25:29 PM PDT 24
Finished Jul 01 05:25:58 PM PDT 24
Peak memory 220280 kb
Host smart-f4c15bbe-218c-4599-90f5-f89faf4c029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169857030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2169857030
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2034237852
Short name T416
Test name
Test status
Simulation time 1381592866 ps
CPU time 5.12 seconds
Started Jul 01 05:25:33 PM PDT 24
Finished Jul 01 05:25:42 PM PDT 24
Peak memory 216152 kb
Host smart-a6caf424-a6fe-45f8-b90e-0be99002732c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034237852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2034237852
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3755044889
Short name T453
Test name
Test status
Simulation time 49698631 ps
CPU time 1.46 seconds
Started Jul 01 05:25:33 PM PDT 24
Finished Jul 01 05:25:38 PM PDT 24
Peak memory 216268 kb
Host smart-9e90f8a9-1f89-496d-b129-7f6104358999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755044889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3755044889
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.814415112
Short name T456
Test name
Test status
Simulation time 714237783 ps
CPU time 0.94 seconds
Started Jul 01 05:25:31 PM PDT 24
Finished Jul 01 05:25:37 PM PDT 24
Peak memory 205904 kb
Host smart-59e8210d-bbc8-48c9-b71c-e65f039eae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814415112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.814415112
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2774063000
Short name T185
Test name
Test status
Simulation time 235260879 ps
CPU time 2.92 seconds
Started Jul 01 05:25:32 PM PDT 24
Finished Jul 01 05:25:39 PM PDT 24
Peak memory 224416 kb
Host smart-31f2652f-4b9a-4561-902a-9aaab9006de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774063000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2774063000
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2593139507
Short name T378
Test name
Test status
Simulation time 17502802 ps
CPU time 0.7 seconds
Started Jul 01 05:25:40 PM PDT 24
Finished Jul 01 05:25:42 PM PDT 24
Peak memory 204840 kb
Host smart-c5d3394d-2f2c-4b44-a38e-352f8205638b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593139507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2593139507
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2974457003
Short name T866
Test name
Test status
Simulation time 5016471228 ps
CPU time 11.69 seconds
Started Jul 01 05:25:38 PM PDT 24
Finished Jul 01 05:25:52 PM PDT 24
Peak memory 224720 kb
Host smart-46ecf9ac-1bd6-42ed-b633-18c2bc28e054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974457003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2974457003
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1411905264
Short name T506
Test name
Test status
Simulation time 20941172 ps
CPU time 0.81 seconds
Started Jul 01 05:25:37 PM PDT 24
Finished Jul 01 05:25:41 PM PDT 24
Peak memory 206888 kb
Host smart-e66b085f-56e5-4215-990a-8febe4f25979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411905264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1411905264
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3550726456
Short name T50
Test name
Test status
Simulation time 41082574513 ps
CPU time 391.83 seconds
Started Jul 01 05:25:36 PM PDT 24
Finished Jul 01 05:32:10 PM PDT 24
Peak memory 257508 kb
Host smart-b7d36b4c-af2c-4f11-a376-3f986cede1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550726456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3550726456
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1058390900
Short name T771
Test name
Test status
Simulation time 4119715370 ps
CPU time 24.78 seconds
Started Jul 01 05:25:39 PM PDT 24
Finished Jul 01 05:26:06 PM PDT 24
Peak memory 217692 kb
Host smart-b2fba9cd-1729-4aa0-8db5-003e425bd962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058390900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1058390900
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2069841383
Short name T298
Test name
Test status
Simulation time 10722928002 ps
CPU time 16.06 seconds
Started Jul 01 05:25:37 PM PDT 24
Finished Jul 01 05:25:55 PM PDT 24
Peak memory 240996 kb
Host smart-45e5ac63-cf51-4bdd-8985-94b680be2e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069841383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2069841383
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.862285371
Short name T172
Test name
Test status
Simulation time 11632919864 ps
CPU time 76.33 seconds
Started Jul 01 05:25:37 PM PDT 24
Finished Jul 01 05:26:56 PM PDT 24
Peak memory 241184 kb
Host smart-e04e73ee-cd37-48c7-ab8d-97eef1647274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862285371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.862285371
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1105377137
Short name T872
Test name
Test status
Simulation time 6220862288 ps
CPU time 15.39 seconds
Started Jul 01 05:25:37 PM PDT 24
Finished Jul 01 05:25:56 PM PDT 24
Peak memory 232828 kb
Host smart-63cbf27c-c42c-43e2-9166-f1eb0d35498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105377137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1105377137
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4228242059
Short name T838
Test name
Test status
Simulation time 1293312790 ps
CPU time 14.2 seconds
Started Jul 01 05:25:37 PM PDT 24
Finished Jul 01 05:25:54 PM PDT 24
Peak memory 240600 kb
Host smart-7981d019-9e6e-429c-91aa-5275e5f671c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228242059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4228242059
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3624105199
Short name T891
Test name
Test status
Simulation time 1469702574 ps
CPU time 4.37 seconds
Started Jul 01 05:25:37 PM PDT 24
Finished Jul 01 05:25:44 PM PDT 24
Peak memory 224508 kb
Host smart-4941facb-ba4a-4118-864c-269b8d75d1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624105199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3624105199
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.887431760
Short name T494
Test name
Test status
Simulation time 648217109 ps
CPU time 8.69 seconds
Started Jul 01 05:25:37 PM PDT 24
Finished Jul 01 05:25:48 PM PDT 24
Peak memory 232736 kb
Host smart-0b56b322-855e-4d6a-8354-725a79a1a17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887431760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.887431760
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3067331609
Short name T694
Test name
Test status
Simulation time 734165097 ps
CPU time 10.35 seconds
Started Jul 01 05:25:37 PM PDT 24
Finished Jul 01 05:25:50 PM PDT 24
Peak memory 219428 kb
Host smart-bead8fab-622f-469e-a2f0-af9b1eabdb37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3067331609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3067331609
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2765633936
Short name T276
Test name
Test status
Simulation time 101686874837 ps
CPU time 151.56 seconds
Started Jul 01 05:25:38 PM PDT 24
Finished Jul 01 05:28:12 PM PDT 24
Peak memory 265240 kb
Host smart-5c436bfe-b4cd-403e-b093-47306829197c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765633936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2765633936
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2047200479
Short name T697
Test name
Test status
Simulation time 14969385348 ps
CPU time 30.61 seconds
Started Jul 01 05:25:36 PM PDT 24
Finished Jul 01 05:26:10 PM PDT 24
Peak memory 217660 kb
Host smart-42b6b031-d2c6-4d8a-871c-5384c2e8642f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047200479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2047200479
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1676767433
Short name T599
Test name
Test status
Simulation time 419870810 ps
CPU time 3.96 seconds
Started Jul 01 05:25:38 PM PDT 24
Finished Jul 01 05:25:45 PM PDT 24
Peak memory 216188 kb
Host smart-70abc1ae-9056-4bb7-a6b3-8415de930188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676767433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1676767433
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2202465956
Short name T980
Test name
Test status
Simulation time 75025168 ps
CPU time 0.72 seconds
Started Jul 01 05:25:38 PM PDT 24
Finished Jul 01 05:25:41 PM PDT 24
Peak memory 205676 kb
Host smart-7ed6371b-298a-400c-90bf-2633d5111931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202465956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2202465956
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.366184874
Short name T396
Test name
Test status
Simulation time 236850593 ps
CPU time 0.83 seconds
Started Jul 01 05:25:37 PM PDT 24
Finished Jul 01 05:25:41 PM PDT 24
Peak memory 206044 kb
Host smart-4972a996-5490-4a02-a6c0-6cbbe57e4cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366184874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.366184874
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.739023797
Short name T535
Test name
Test status
Simulation time 69112657 ps
CPU time 2.85 seconds
Started Jul 01 05:25:37 PM PDT 24
Finished Jul 01 05:25:43 PM PDT 24
Peak memory 232412 kb
Host smart-e8fdc2d8-65e5-4a19-aaf1-b5d45c796395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739023797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.739023797
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2989077901
Short name T365
Test name
Test status
Simulation time 28853811 ps
CPU time 0.69 seconds
Started Jul 01 05:25:44 PM PDT 24
Finished Jul 01 05:25:47 PM PDT 24
Peak memory 204996 kb
Host smart-12a62a1f-9e42-46a7-80c0-a61280b6f55e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989077901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2989077901
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2587268688
Short name T724
Test name
Test status
Simulation time 208578540 ps
CPU time 3.4 seconds
Started Jul 01 05:25:43 PM PDT 24
Finished Jul 01 05:25:48 PM PDT 24
Peak memory 232640 kb
Host smart-42ee7e58-a214-4fe9-bea4-959d7f243c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587268688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2587268688
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.531273383
Short name T629
Test name
Test status
Simulation time 15601112 ps
CPU time 0.83 seconds
Started Jul 01 05:25:38 PM PDT 24
Finished Jul 01 05:25:41 PM PDT 24
Peak memory 206632 kb
Host smart-4b8db104-ad2f-4c35-b93d-ae8aede9ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531273383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.531273383
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1398516239
Short name T370
Test name
Test status
Simulation time 5087741726 ps
CPU time 50.67 seconds
Started Jul 01 05:25:42 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 251300 kb
Host smart-671b8162-4169-4042-b980-aa8962646e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398516239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1398516239
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1769434080
Short name T34
Test name
Test status
Simulation time 8915782467 ps
CPU time 153.7 seconds
Started Jul 01 05:25:46 PM PDT 24
Finished Jul 01 05:28:21 PM PDT 24
Peak memory 254772 kb
Host smart-d46bb393-2ee6-4017-92e4-35a029efe6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769434080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1769434080
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3097792104
Short name T550
Test name
Test status
Simulation time 605399346 ps
CPU time 15.05 seconds
Started Jul 01 05:25:47 PM PDT 24
Finished Jul 01 05:26:04 PM PDT 24
Peak memory 232660 kb
Host smart-ef0093c4-b8ee-4fe4-8782-981e432ce92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097792104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3097792104
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.429859942
Short name T553
Test name
Test status
Simulation time 38191113207 ps
CPU time 149.48 seconds
Started Jul 01 05:25:43 PM PDT 24
Finished Jul 01 05:28:14 PM PDT 24
Peak memory 253556 kb
Host smart-0c85aeaf-55b1-4f4f-b541-48bb23402990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429859942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.429859942
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3960478873
Short name T187
Test name
Test status
Simulation time 120919800 ps
CPU time 4.71 seconds
Started Jul 01 05:25:42 PM PDT 24
Finished Jul 01 05:25:48 PM PDT 24
Peak memory 232664 kb
Host smart-58605190-f80a-4420-9d8b-4b1467709ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960478873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3960478873
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1115043115
Short name T195
Test name
Test status
Simulation time 40491345296 ps
CPU time 89.02 seconds
Started Jul 01 05:25:44 PM PDT 24
Finished Jul 01 05:27:15 PM PDT 24
Peak memory 240892 kb
Host smart-f7c5c8a4-7ca8-4043-a7f3-916363da1cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115043115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1115043115
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3195808343
Short name T547
Test name
Test status
Simulation time 485939186 ps
CPU time 5.61 seconds
Started Jul 01 05:25:46 PM PDT 24
Finished Jul 01 05:25:53 PM PDT 24
Peak memory 232676 kb
Host smart-698ed130-cdfd-4ae7-adb6-a377a7304709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195808343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3195808343
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2710963648
Short name T232
Test name
Test status
Simulation time 3775287087 ps
CPU time 10.14 seconds
Started Jul 01 05:25:43 PM PDT 24
Finished Jul 01 05:25:55 PM PDT 24
Peak memory 240576 kb
Host smart-4c312f56-040d-4ede-8b65-5ef74c95a633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710963648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2710963648
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3049217209
Short name T131
Test name
Test status
Simulation time 1695227453 ps
CPU time 14.33 seconds
Started Jul 01 05:25:43 PM PDT 24
Finished Jul 01 05:26:00 PM PDT 24
Peak memory 221740 kb
Host smart-4eea1388-ffff-476d-a827-cf0319d7fe75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3049217209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3049217209
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.4118199506
Short name T993
Test name
Test status
Simulation time 55166345153 ps
CPU time 118.12 seconds
Started Jul 01 05:25:42 PM PDT 24
Finished Jul 01 05:27:42 PM PDT 24
Peak memory 268328 kb
Host smart-ce74c8d3-b25f-4a8f-8f83-98f21da66690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118199506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.4118199506
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.415633328
Short name T608
Test name
Test status
Simulation time 22470911174 ps
CPU time 13.22 seconds
Started Jul 01 05:25:40 PM PDT 24
Finished Jul 01 05:25:55 PM PDT 24
Peak memory 216240 kb
Host smart-304f0ac4-a1b5-4cc3-aacd-44a8f5a22b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415633328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.415633328
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.423660927
Short name T321
Test name
Test status
Simulation time 37815206 ps
CPU time 0.77 seconds
Started Jul 01 05:25:36 PM PDT 24
Finished Jul 01 05:25:39 PM PDT 24
Peak memory 205808 kb
Host smart-e187f0c4-c363-4091-8358-a62482014015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423660927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.423660927
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2576882536
Short name T538
Test name
Test status
Simulation time 153287301 ps
CPU time 0.88 seconds
Started Jul 01 05:25:43 PM PDT 24
Finished Jul 01 05:25:46 PM PDT 24
Peak memory 206624 kb
Host smart-c19e322a-0a81-450d-ba2e-147fd3a0bda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576882536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2576882536
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.11106739
Short name T474
Test name
Test status
Simulation time 22706362 ps
CPU time 0.78 seconds
Started Jul 01 05:25:39 PM PDT 24
Finished Jul 01 05:25:42 PM PDT 24
Peak memory 205992 kb
Host smart-af27a87f-f23d-4885-b0d5-7e63a628c304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11106739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.11106739
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3018922654
Short name T220
Test name
Test status
Simulation time 11693790324 ps
CPU time 7.35 seconds
Started Jul 01 05:25:43 PM PDT 24
Finished Jul 01 05:25:52 PM PDT 24
Peak memory 224628 kb
Host smart-de4571a2-b892-41d5-945b-d66f7c36c045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018922654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3018922654
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1457932247
Short name T72
Test name
Test status
Simulation time 15061016 ps
CPU time 0.88 seconds
Started Jul 01 05:25:52 PM PDT 24
Finished Jul 01 05:25:57 PM PDT 24
Peak memory 205068 kb
Host smart-c6b20b19-49cd-480e-a6c9-2095d274a6d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457932247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1457932247
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3759583036
Short name T667
Test name
Test status
Simulation time 406730902 ps
CPU time 6.98 seconds
Started Jul 01 05:25:49 PM PDT 24
Finished Jul 01 05:25:58 PM PDT 24
Peak memory 232800 kb
Host smart-d2fbe3da-cc43-4892-9c65-b0bb6d2cffad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759583036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3759583036
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2430692147
Short name T329
Test name
Test status
Simulation time 110248611 ps
CPU time 0.84 seconds
Started Jul 01 05:25:42 PM PDT 24
Finished Jul 01 05:25:45 PM PDT 24
Peak memory 206936 kb
Host smart-53f74f80-ca97-4645-aecf-df7f90db63af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430692147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2430692147
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.68576936
Short name T802
Test name
Test status
Simulation time 172502828619 ps
CPU time 295.03 seconds
Started Jul 01 05:25:48 PM PDT 24
Finished Jul 01 05:30:45 PM PDT 24
Peak memory 254616 kb
Host smart-5eb3f3e9-16b2-403b-80ab-364c02a9e6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68576936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.68576936
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.474916308
Short name T860
Test name
Test status
Simulation time 26115755557 ps
CPU time 276.1 seconds
Started Jul 01 05:25:49 PM PDT 24
Finished Jul 01 05:30:27 PM PDT 24
Peak memory 253264 kb
Host smart-8332bf9b-538e-4256-a7c7-3fb61e900357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474916308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.474916308
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1083473783
Short name T875
Test name
Test status
Simulation time 97879794100 ps
CPU time 45.23 seconds
Started Jul 01 05:25:50 PM PDT 24
Finished Jul 01 05:26:37 PM PDT 24
Peak memory 241128 kb
Host smart-d4b8d7e3-5376-42f5-96b6-fedcc4ba5943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083473783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1083473783
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3508728724
Short name T612
Test name
Test status
Simulation time 273826349 ps
CPU time 6.43 seconds
Started Jul 01 05:25:48 PM PDT 24
Finished Jul 01 05:25:57 PM PDT 24
Peak memory 239916 kb
Host smart-d7f05c61-44ff-4559-bbc7-e2c102c26a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508728724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3508728724
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3017294032
Short name T268
Test name
Test status
Simulation time 25720604238 ps
CPU time 234.52 seconds
Started Jul 01 05:25:47 PM PDT 24
Finished Jul 01 05:29:44 PM PDT 24
Peak memory 261648 kb
Host smart-b951ba97-e7d4-484b-857a-56d5fa45282a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017294032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3017294032
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2153207494
Short name T858
Test name
Test status
Simulation time 469242589 ps
CPU time 5.12 seconds
Started Jul 01 05:25:43 PM PDT 24
Finished Jul 01 05:25:50 PM PDT 24
Peak memory 232648 kb
Host smart-c4d957b2-d1e0-4682-b682-e51421050484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153207494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2153207494
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1670392631
Short name T800
Test name
Test status
Simulation time 2363522503 ps
CPU time 13.76 seconds
Started Jul 01 05:25:46 PM PDT 24
Finished Jul 01 05:26:01 PM PDT 24
Peak memory 224640 kb
Host smart-50faf7cb-ba2c-43e6-a793-37843289c2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670392631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1670392631
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3056722657
Short name T804
Test name
Test status
Simulation time 1455691765 ps
CPU time 2.48 seconds
Started Jul 01 05:26:00 PM PDT 24
Finished Jul 01 05:26:05 PM PDT 24
Peak memory 223880 kb
Host smart-f9457198-9644-4fa4-b533-fc2aa7ebc819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056722657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3056722657
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1059555259
Short name T209
Test name
Test status
Simulation time 539134463 ps
CPU time 7.52 seconds
Started Jul 01 05:25:47 PM PDT 24
Finished Jul 01 05:25:56 PM PDT 24
Peak memory 238652 kb
Host smart-ecbe0d71-708d-4efc-b6ca-ccd9150ce540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059555259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1059555259
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2971470342
Short name T372
Test name
Test status
Simulation time 678554559 ps
CPU time 8.42 seconds
Started Jul 01 05:25:47 PM PDT 24
Finished Jul 01 05:25:58 PM PDT 24
Peak memory 222828 kb
Host smart-67009374-b4d1-40d9-9eec-ece03237528a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2971470342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2971470342
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1258037905
Short name T762
Test name
Test status
Simulation time 12896143096 ps
CPU time 18.86 seconds
Started Jul 01 05:25:42 PM PDT 24
Finished Jul 01 05:26:03 PM PDT 24
Peak memory 216324 kb
Host smart-98358096-f08a-4e7f-be26-90c7b7380029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258037905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1258037905
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3821493453
Short name T765
Test name
Test status
Simulation time 6243214573 ps
CPU time 9.38 seconds
Started Jul 01 05:25:47 PM PDT 24
Finished Jul 01 05:25:58 PM PDT 24
Peak memory 216332 kb
Host smart-8323c341-e7d7-4eec-811c-186c755e6c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821493453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3821493453
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3072805383
Short name T923
Test name
Test status
Simulation time 33511717 ps
CPU time 0.93 seconds
Started Jul 01 05:25:43 PM PDT 24
Finished Jul 01 05:25:46 PM PDT 24
Peak memory 206680 kb
Host smart-27473b47-917c-422e-8fdc-608d02a3f77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072805383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3072805383
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1438370848
Short name T646
Test name
Test status
Simulation time 159711726 ps
CPU time 0.82 seconds
Started Jul 01 05:25:42 PM PDT 24
Finished Jul 01 05:25:44 PM PDT 24
Peak memory 206068 kb
Host smart-218cfdcc-c806-426e-91f9-20db61be5044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438370848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1438370848
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2726882323
Short name T207
Test name
Test status
Simulation time 6464455369 ps
CPU time 21.62 seconds
Started Jul 01 05:25:48 PM PDT 24
Finished Jul 01 05:26:12 PM PDT 24
Peak memory 224644 kb
Host smart-2349f8a3-414d-472d-9f7c-663b20041166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726882323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2726882323
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4006986138
Short name T943
Test name
Test status
Simulation time 45054747 ps
CPU time 0.74 seconds
Started Jul 01 05:25:58 PM PDT 24
Finished Jul 01 05:26:02 PM PDT 24
Peak memory 204980 kb
Host smart-6aefa89f-640b-4931-9d64-acfe5751998b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006986138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4006986138
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3065107949
Short name T1006
Test name
Test status
Simulation time 791842923 ps
CPU time 8.82 seconds
Started Jul 01 05:25:55 PM PDT 24
Finished Jul 01 05:26:07 PM PDT 24
Peak memory 224440 kb
Host smart-f580e4fe-a03f-4798-aed0-24d261c8f7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065107949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3065107949
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.557762805
Short name T404
Test name
Test status
Simulation time 15283310 ps
CPU time 0.79 seconds
Started Jul 01 05:25:48 PM PDT 24
Finished Jul 01 05:25:51 PM PDT 24
Peak memory 206628 kb
Host smart-40651f16-8d03-42ac-94d8-387b26990863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557762805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.557762805
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1226638927
Short name T256
Test name
Test status
Simulation time 49536252635 ps
CPU time 348.54 seconds
Started Jul 01 05:25:55 PM PDT 24
Finished Jul 01 05:31:48 PM PDT 24
Peak memory 266828 kb
Host smart-d2ab59b3-e4dd-4094-8f29-5e5f8da3e594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226638927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1226638927
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.562682158
Short name T42
Test name
Test status
Simulation time 69828080702 ps
CPU time 167.93 seconds
Started Jul 01 05:25:56 PM PDT 24
Finished Jul 01 05:28:48 PM PDT 24
Peak memory 254324 kb
Host smart-0f671a18-21c0-4bd4-b7c1-5c98f210de8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562682158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.562682158
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1976753924
Short name T1017
Test name
Test status
Simulation time 8706320702 ps
CPU time 73.46 seconds
Started Jul 01 05:25:54 PM PDT 24
Finished Jul 01 05:27:12 PM PDT 24
Peak memory 249428 kb
Host smart-1135cd80-eeab-4cf1-8fd0-4e9414493ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976753924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1976753924
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.349461264
Short name T868
Test name
Test status
Simulation time 492182075 ps
CPU time 7.03 seconds
Started Jul 01 05:25:56 PM PDT 24
Finished Jul 01 05:26:07 PM PDT 24
Peak memory 240856 kb
Host smart-c9725b41-7cf8-48e6-9e05-e1f31fe9e1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349461264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.349461264
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.885212583
Short name T499
Test name
Test status
Simulation time 10341788892 ps
CPU time 76.36 seconds
Started Jul 01 05:25:56 PM PDT 24
Finished Jul 01 05:27:16 PM PDT 24
Peak memory 260992 kb
Host smart-3537bab9-0920-460a-9975-4304eca08bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885212583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.885212583
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2263134531
Short name T842
Test name
Test status
Simulation time 1633442756 ps
CPU time 15.18 seconds
Started Jul 01 05:25:57 PM PDT 24
Finished Jul 01 05:26:16 PM PDT 24
Peak memory 224468 kb
Host smart-f91c9e53-be78-47a9-9bcf-b199c81f68d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263134531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2263134531
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1050170964
Short name T472
Test name
Test status
Simulation time 11509878761 ps
CPU time 24.65 seconds
Started Jul 01 05:25:55 PM PDT 24
Finished Jul 01 05:26:23 PM PDT 24
Peak memory 224688 kb
Host smart-248d57b0-f787-4d4c-9539-c64a063a7285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050170964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1050170964
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3319947193
Short name T603
Test name
Test status
Simulation time 1239556429 ps
CPU time 4.31 seconds
Started Jul 01 05:25:51 PM PDT 24
Finished Jul 01 05:25:59 PM PDT 24
Peak memory 232620 kb
Host smart-d3f43da9-d1af-4bb4-95f5-691b9638a22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319947193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3319947193
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2339992850
Short name T519
Test name
Test status
Simulation time 6401638469 ps
CPU time 9.81 seconds
Started Jul 01 05:25:49 PM PDT 24
Finished Jul 01 05:26:01 PM PDT 24
Peak memory 240652 kb
Host smart-e18a4bbe-756f-495e-85ac-930a976a4285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339992850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2339992850
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4174984841
Short name T822
Test name
Test status
Simulation time 1350604193 ps
CPU time 7.88 seconds
Started Jul 01 05:25:55 PM PDT 24
Finished Jul 01 05:26:07 PM PDT 24
Peak memory 220328 kb
Host smart-83a9c920-6107-4d16-8adb-2d2164a5db4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4174984841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4174984841
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3135886681
Short name T627
Test name
Test status
Simulation time 147075707 ps
CPU time 0.72 seconds
Started Jul 01 05:25:50 PM PDT 24
Finished Jul 01 05:25:52 PM PDT 24
Peak memory 205812 kb
Host smart-77d11585-d40f-4815-8ce8-908dc37e22c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135886681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3135886681
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2773160347
Short name T714
Test name
Test status
Simulation time 1751747690 ps
CPU time 10.32 seconds
Started Jul 01 05:25:50 PM PDT 24
Finished Jul 01 05:26:03 PM PDT 24
Peak memory 216160 kb
Host smart-4dbbf640-2847-4b85-b9d0-842555afa090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773160347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2773160347
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.715303895
Short name T781
Test name
Test status
Simulation time 124035024 ps
CPU time 1.58 seconds
Started Jul 01 05:25:51 PM PDT 24
Finished Jul 01 05:25:56 PM PDT 24
Peak memory 216208 kb
Host smart-a33c8ef7-b567-4950-9eb8-0039e3c014c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715303895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.715303895
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3447286568
Short name T524
Test name
Test status
Simulation time 312892919 ps
CPU time 0.93 seconds
Started Jul 01 05:25:48 PM PDT 24
Finished Jul 01 05:25:51 PM PDT 24
Peak memory 205996 kb
Host smart-b2d83ad3-8598-4c40-bef0-a0ad7af096ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447286568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3447286568
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3777995356
Short name T890
Test name
Test status
Simulation time 2400171873 ps
CPU time 4.18 seconds
Started Jul 01 05:25:55 PM PDT 24
Finished Jul 01 05:26:03 PM PDT 24
Peak memory 224596 kb
Host smart-d94367fb-8b66-4728-be48-d6ef12ed2449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777995356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3777995356
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2852727152
Short name T364
Test name
Test status
Simulation time 81293770 ps
CPU time 0.72 seconds
Started Jul 01 05:26:00 PM PDT 24
Finished Jul 01 05:26:04 PM PDT 24
Peak memory 204992 kb
Host smart-d974ae6b-65ab-491a-9673-8d2c754c75d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852727152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2852727152
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3290678807
Short name T640
Test name
Test status
Simulation time 331738287 ps
CPU time 5.47 seconds
Started Jul 01 05:25:57 PM PDT 24
Finished Jul 01 05:26:06 PM PDT 24
Peak memory 232680 kb
Host smart-711830b8-c941-4e15-a093-f91d877c62c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290678807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3290678807
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3481036540
Short name T74
Test name
Test status
Simulation time 57699359 ps
CPU time 0.8 seconds
Started Jul 01 05:25:57 PM PDT 24
Finished Jul 01 05:26:02 PM PDT 24
Peak memory 205600 kb
Host smart-73679d03-baf4-4286-8f6f-ee7c9d5c49b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481036540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3481036540
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1902335389
Short name T912
Test name
Test status
Simulation time 24452317975 ps
CPU time 46.05 seconds
Started Jul 01 05:26:01 PM PDT 24
Finished Jul 01 05:26:50 PM PDT 24
Peak memory 241012 kb
Host smart-49f3764b-ea56-4376-8d88-5ddf1f6127a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902335389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1902335389
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.486992364
Short name T717
Test name
Test status
Simulation time 6997830220 ps
CPU time 106.11 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:27:55 PM PDT 24
Peak memory 251592 kb
Host smart-441ecf07-3044-4a76-b85f-0220a6252e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486992364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.486992364
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.820414790
Short name T789
Test name
Test status
Simulation time 22887552621 ps
CPU time 181.75 seconds
Started Jul 01 05:26:01 PM PDT 24
Finished Jul 01 05:29:06 PM PDT 24
Peak memory 251496 kb
Host smart-81d73115-032c-42d4-a058-ccb9e7637c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820414790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.820414790
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3556964663
Short name T200
Test name
Test status
Simulation time 378310975 ps
CPU time 4.39 seconds
Started Jul 01 05:25:55 PM PDT 24
Finished Jul 01 05:26:04 PM PDT 24
Peak memory 233720 kb
Host smart-6747f49c-2255-4e25-88ca-8c35ac44ec3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556964663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3556964663
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3701265729
Short name T1000
Test name
Test status
Simulation time 7724409490 ps
CPU time 27.23 seconds
Started Jul 01 05:25:57 PM PDT 24
Finished Jul 01 05:26:28 PM PDT 24
Peak memory 234376 kb
Host smart-e8425bb5-24b1-4876-8f1c-7838045bb301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701265729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3701265729
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1548397063
Short name T361
Test name
Test status
Simulation time 8334127221 ps
CPU time 11.69 seconds
Started Jul 01 05:25:56 PM PDT 24
Finished Jul 01 05:26:12 PM PDT 24
Peak memory 224500 kb
Host smart-677d807b-0717-404c-83d3-c3641c6a1352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548397063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1548397063
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2840912918
Short name T680
Test name
Test status
Simulation time 150477206 ps
CPU time 2.66 seconds
Started Jul 01 05:25:56 PM PDT 24
Finished Jul 01 05:26:03 PM PDT 24
Peak memory 224464 kb
Host smart-1e4bc760-a1ea-456f-aed1-47da9c3357ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840912918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2840912918
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2492267017
Short name T213
Test name
Test status
Simulation time 608779776 ps
CPU time 5.7 seconds
Started Jul 01 05:25:58 PM PDT 24
Finished Jul 01 05:26:07 PM PDT 24
Peak memory 224624 kb
Host smart-faa4e8d8-4e34-410a-8e51-5fd10d2c45db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492267017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2492267017
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1747499803
Short name T972
Test name
Test status
Simulation time 2268182773 ps
CPU time 9.1 seconds
Started Jul 01 05:25:56 PM PDT 24
Finished Jul 01 05:26:09 PM PDT 24
Peak memory 232784 kb
Host smart-0505ba49-cda9-4975-8be5-8721e76f82e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747499803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1747499803
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3687451918
Short name T5
Test name
Test status
Simulation time 354817030 ps
CPU time 6.6 seconds
Started Jul 01 05:25:55 PM PDT 24
Finished Jul 01 05:26:05 PM PDT 24
Peak memory 220456 kb
Host smart-f1476c8a-009e-4107-92c6-0cec21a5e7ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3687451918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3687451918
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3031010204
Short name T387
Test name
Test status
Simulation time 22973399143 ps
CPU time 63.95 seconds
Started Jul 01 05:26:02 PM PDT 24
Finished Jul 01 05:27:08 PM PDT 24
Peak memory 235268 kb
Host smart-3d53a996-0ab9-4c9e-908a-c894f6bde083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031010204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3031010204
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2369187119
Short name T394
Test name
Test status
Simulation time 2042128981 ps
CPU time 11.92 seconds
Started Jul 01 05:25:56 PM PDT 24
Finished Jul 01 05:26:12 PM PDT 24
Peak memory 216340 kb
Host smart-c470d718-c3a7-417b-acc3-f395829f9077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369187119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2369187119
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1260451636
Short name T710
Test name
Test status
Simulation time 1305981585 ps
CPU time 3.93 seconds
Started Jul 01 05:25:55 PM PDT 24
Finished Jul 01 05:26:02 PM PDT 24
Peak memory 216268 kb
Host smart-6512fd73-1fc8-49f6-892b-34fd751f7d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260451636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1260451636
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3203255894
Short name T852
Test name
Test status
Simulation time 213730483 ps
CPU time 0.98 seconds
Started Jul 01 05:25:57 PM PDT 24
Finished Jul 01 05:26:01 PM PDT 24
Peak memory 205992 kb
Host smart-c141205e-21f8-46c5-874f-ebd408b2d71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203255894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3203255894
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2494341385
Short name T975
Test name
Test status
Simulation time 69934197 ps
CPU time 2.22 seconds
Started Jul 01 05:25:55 PM PDT 24
Finished Jul 01 05:26:01 PM PDT 24
Peak memory 223040 kb
Host smart-b6f56912-b18e-4647-9466-8b315dc77e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494341385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2494341385
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4277382699
Short name T22
Test name
Test status
Simulation time 16844144 ps
CPU time 0.75 seconds
Started Jul 01 05:26:03 PM PDT 24
Finished Jul 01 05:26:06 PM PDT 24
Peak memory 205892 kb
Host smart-2ec17d2b-0263-4855-8f5b-4f2310d08b32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277382699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4277382699
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1851190574
Short name T954
Test name
Test status
Simulation time 200114895 ps
CPU time 3.89 seconds
Started Jul 01 05:26:00 PM PDT 24
Finished Jul 01 05:26:07 PM PDT 24
Peak memory 232784 kb
Host smart-93347210-d0f1-4f83-a452-73a7505f432d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851190574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1851190574
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.17075514
Short name T708
Test name
Test status
Simulation time 25820326 ps
CPU time 0.82 seconds
Started Jul 01 05:26:02 PM PDT 24
Finished Jul 01 05:26:05 PM PDT 24
Peak memory 206580 kb
Host smart-67a24793-5b68-4c5b-887f-c6d07b0cb190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17075514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.17075514
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1534849099
Short name T174
Test name
Test status
Simulation time 933592619 ps
CPU time 18.86 seconds
Started Jul 01 05:26:01 PM PDT 24
Finished Jul 01 05:26:23 PM PDT 24
Peak memory 232740 kb
Host smart-0c34e8fb-0f8a-4aa2-a71e-aa2fe7546244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534849099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1534849099
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3705414979
Short name T883
Test name
Test status
Simulation time 8763832694 ps
CPU time 144.25 seconds
Started Jul 01 05:26:00 PM PDT 24
Finished Jul 01 05:28:28 PM PDT 24
Peak memory 261724 kb
Host smart-8ad623f2-49c8-4f32-947e-38bc14af5a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705414979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3705414979
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3990123525
Short name T939
Test name
Test status
Simulation time 3748235218 ps
CPU time 38.23 seconds
Started Jul 01 05:26:02 PM PDT 24
Finished Jul 01 05:26:43 PM PDT 24
Peak memory 224748 kb
Host smart-d0485d88-16f8-45f4-ae18-ff2de9eaf4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990123525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3990123525
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2759575137
Short name T436
Test name
Test status
Simulation time 1456239089 ps
CPU time 18.23 seconds
Started Jul 01 05:26:00 PM PDT 24
Finished Jul 01 05:26:21 PM PDT 24
Peak memory 250092 kb
Host smart-44980b23-0f1b-4cd3-9325-0352a24f70ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759575137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2759575137
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2358554172
Short name T675
Test name
Test status
Simulation time 1792688471 ps
CPU time 36.84 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:26:46 PM PDT 24
Peak memory 249096 kb
Host smart-87dfd799-0b7a-4d88-b9fc-73386df81c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358554172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2358554172
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2077556597
Short name T541
Test name
Test status
Simulation time 2542697256 ps
CPU time 23.83 seconds
Started Jul 01 05:26:03 PM PDT 24
Finished Jul 01 05:26:29 PM PDT 24
Peak memory 224572 kb
Host smart-97578291-6d31-46f6-ad65-a7a4c2021479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077556597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2077556597
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1732011884
Short name T82
Test name
Test status
Simulation time 10909799104 ps
CPU time 34.57 seconds
Started Jul 01 05:26:06 PM PDT 24
Finished Jul 01 05:26:43 PM PDT 24
Peak memory 248432 kb
Host smart-6d2d0905-90cf-4864-ae27-19dc950ee7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732011884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1732011884
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1385909303
Short name T924
Test name
Test status
Simulation time 644103451 ps
CPU time 3.42 seconds
Started Jul 01 05:26:01 PM PDT 24
Finished Jul 01 05:26:07 PM PDT 24
Peak memory 224568 kb
Host smart-f863870b-5afb-4290-81b6-a7a3befc20b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385909303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1385909303
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2861788455
Short name T68
Test name
Test status
Simulation time 4788126383 ps
CPU time 6.11 seconds
Started Jul 01 05:26:05 PM PDT 24
Finished Jul 01 05:26:12 PM PDT 24
Peak memory 224744 kb
Host smart-5195a167-514f-41bf-a040-09f3cbd60bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861788455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2861788455
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.637436997
Short name T919
Test name
Test status
Simulation time 92388306 ps
CPU time 3.77 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:26:13 PM PDT 24
Peak memory 222736 kb
Host smart-ec97163c-bc78-4a69-86c6-4f1e7acdd209
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=637436997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.637436997
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2912218140
Short name T420
Test name
Test status
Simulation time 20365829222 ps
CPU time 192.19 seconds
Started Jul 01 05:26:01 PM PDT 24
Finished Jul 01 05:29:16 PM PDT 24
Peak memory 257488 kb
Host smart-9e3a8c61-e70c-4a1d-93b0-d4900a52d972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912218140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2912218140
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2608404103
Short name T590
Test name
Test status
Simulation time 21303347068 ps
CPU time 27.61 seconds
Started Jul 01 05:26:05 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 216396 kb
Host smart-4dc47b17-9353-4c5a-899d-12bc70f78ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608404103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2608404103
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.528590247
Short name T922
Test name
Test status
Simulation time 10876007823 ps
CPU time 8.73 seconds
Started Jul 01 05:26:00 PM PDT 24
Finished Jul 01 05:26:12 PM PDT 24
Peak memory 216304 kb
Host smart-b5b1e6f0-5f98-457a-9c7c-ea59ea5279b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528590247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.528590247
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4197803945
Short name T918
Test name
Test status
Simulation time 171341642 ps
CPU time 7.34 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:26:16 PM PDT 24
Peak memory 216188 kb
Host smart-cbb444b5-0094-4b62-a1d2-96bf6e9052af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197803945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4197803945
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2677338305
Short name T751
Test name
Test status
Simulation time 17904805 ps
CPU time 0.79 seconds
Started Jul 01 05:26:03 PM PDT 24
Finished Jul 01 05:26:06 PM PDT 24
Peak memory 206004 kb
Host smart-4fe8f087-3059-4474-82a2-c4b61cd95bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677338305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2677338305
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2944735204
Short name T347
Test name
Test status
Simulation time 3588679513 ps
CPU time 8.38 seconds
Started Jul 01 05:26:04 PM PDT 24
Finished Jul 01 05:26:15 PM PDT 24
Peak memory 240940 kb
Host smart-71450c3d-a563-46e8-ab69-5398913ab5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944735204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2944735204
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1812845470
Short name T809
Test name
Test status
Simulation time 13689991 ps
CPU time 0.76 seconds
Started Jul 01 05:26:09 PM PDT 24
Finished Jul 01 05:26:12 PM PDT 24
Peak memory 205960 kb
Host smart-34155d3c-f393-4d29-888c-4ce646a92ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812845470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1812845470
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2648015064
Short name T264
Test name
Test status
Simulation time 258398848 ps
CPU time 4.05 seconds
Started Jul 01 05:26:06 PM PDT 24
Finished Jul 01 05:26:11 PM PDT 24
Peak memory 232744 kb
Host smart-034c8b1b-ecd4-4737-883e-31eec76c1009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648015064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2648015064
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3945517360
Short name T564
Test name
Test status
Simulation time 18587897 ps
CPU time 0.79 seconds
Started Jul 01 05:26:03 PM PDT 24
Finished Jul 01 05:26:06 PM PDT 24
Peak memory 206592 kb
Host smart-7c437723-e153-4666-a38b-e321cbedc85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945517360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3945517360
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1882755497
Short name T201
Test name
Test status
Simulation time 157518509436 ps
CPU time 291.4 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:31:01 PM PDT 24
Peak memory 257416 kb
Host smart-2ce6b045-b9ee-4ea3-b315-b40c463d3d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882755497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1882755497
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1718949427
Short name T237
Test name
Test status
Simulation time 20065701157 ps
CPU time 87.91 seconds
Started Jul 01 05:26:10 PM PDT 24
Finished Jul 01 05:27:40 PM PDT 24
Peak memory 238584 kb
Host smart-032a6c39-3c1a-4e6f-bc3d-f4c17ddf9273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718949427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1718949427
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.4284035068
Short name T312
Test name
Test status
Simulation time 15798443341 ps
CPU time 79.11 seconds
Started Jul 01 05:26:11 PM PDT 24
Finished Jul 01 05:27:32 PM PDT 24
Peak memory 249044 kb
Host smart-db7b7ce2-0903-4c26-bbd9-4f06e272a30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284035068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.4284035068
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3324594686
Short name T620
Test name
Test status
Simulation time 108664473 ps
CPU time 5.9 seconds
Started Jul 01 05:26:09 PM PDT 24
Finished Jul 01 05:26:17 PM PDT 24
Peak memory 232788 kb
Host smart-3f8e1543-9ef7-4d1c-84e6-14e087819a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324594686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3324594686
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3043863065
Short name T600
Test name
Test status
Simulation time 13139368 ps
CPU time 0.75 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:26:10 PM PDT 24
Peak memory 215816 kb
Host smart-d96b32f7-4337-4ac1-89f5-116ba7cf353a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043863065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3043863065
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1290286970
Short name T525
Test name
Test status
Simulation time 3887298133 ps
CPU time 13.38 seconds
Started Jul 01 05:26:08 PM PDT 24
Finished Jul 01 05:26:23 PM PDT 24
Peak memory 224648 kb
Host smart-7149b790-2bf4-4a9b-b59d-7d607949ff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290286970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1290286970
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1214638710
Short name T739
Test name
Test status
Simulation time 3159032204 ps
CPU time 15.92 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:26:25 PM PDT 24
Peak memory 232884 kb
Host smart-01f2ef65-c1fc-4062-b7a0-9ce0297e6792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214638710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1214638710
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2565116711
Short name T239
Test name
Test status
Simulation time 34096072247 ps
CPU time 23.38 seconds
Started Jul 01 05:26:08 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 232836 kb
Host smart-268d1432-6239-4b48-b140-fc0feee5ce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565116711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2565116711
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.191137091
Short name T8
Test name
Test status
Simulation time 4701805524 ps
CPU time 4.81 seconds
Started Jul 01 05:26:10 PM PDT 24
Finished Jul 01 05:26:17 PM PDT 24
Peak memory 224624 kb
Host smart-9f68b3a4-9d23-4121-96f0-60230cb474b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191137091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.191137091
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2148200556
Short name T660
Test name
Test status
Simulation time 876229190 ps
CPU time 5.13 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:26:14 PM PDT 24
Peak memory 223216 kb
Host smart-0c138d8f-4f80-43dd-b115-1502764df2ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2148200556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2148200556
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4025421761
Short name T309
Test name
Test status
Simulation time 1233124570 ps
CPU time 15.79 seconds
Started Jul 01 05:26:02 PM PDT 24
Finished Jul 01 05:26:20 PM PDT 24
Peak memory 216352 kb
Host smart-74c23c1d-066e-4f16-ae1b-d721c50d7c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025421761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4025421761
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1026764136
Short name T788
Test name
Test status
Simulation time 1180466870 ps
CPU time 2.7 seconds
Started Jul 01 05:26:18 PM PDT 24
Finished Jul 01 05:26:22 PM PDT 24
Peak memory 216200 kb
Host smart-f6809f63-0bce-4c43-98ae-1ffe2bad8c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026764136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1026764136
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.4271127304
Short name T979
Test name
Test status
Simulation time 12475943 ps
CPU time 0.8 seconds
Started Jul 01 05:26:08 PM PDT 24
Finished Jul 01 05:26:12 PM PDT 24
Peak memory 206004 kb
Host smart-8105253c-64d7-46a0-88af-620373be8b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271127304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4271127304
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2913840133
Short name T878
Test name
Test status
Simulation time 198004285 ps
CPU time 0.96 seconds
Started Jul 01 05:26:11 PM PDT 24
Finished Jul 01 05:26:14 PM PDT 24
Peak memory 206884 kb
Host smart-40a32a67-0f27-402c-9605-95a570e03974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913840133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2913840133
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1777661992
Short name T216
Test name
Test status
Simulation time 29191971175 ps
CPU time 22.57 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:26:32 PM PDT 24
Peak memory 232832 kb
Host smart-fce1f88e-fe9c-45a8-9c00-ab81ec55e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777661992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1777661992
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1374464691
Short name T850
Test name
Test status
Simulation time 14128195 ps
CPU time 0.73 seconds
Started Jul 01 05:24:04 PM PDT 24
Finished Jul 01 05:24:07 PM PDT 24
Peak memory 205620 kb
Host smart-4a22fbf4-2584-4212-8911-92ad0ef6872f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374464691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
374464691
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2206708889
Short name T432
Test name
Test status
Simulation time 1976612441 ps
CPU time 14.81 seconds
Started Jul 01 05:24:04 PM PDT 24
Finished Jul 01 05:24:21 PM PDT 24
Peak memory 224516 kb
Host smart-c42b3098-94c5-42ea-b5a8-cc2a173340bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206708889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2206708889
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3454357503
Short name T342
Test name
Test status
Simulation time 34960031 ps
CPU time 0.8 seconds
Started Jul 01 05:24:11 PM PDT 24
Finished Jul 01 05:24:14 PM PDT 24
Peak memory 206492 kb
Host smart-a6f769c1-5666-4874-b334-6e872e4701d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454357503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3454357503
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1197839663
Short name T1004
Test name
Test status
Simulation time 7498739775 ps
CPU time 61.1 seconds
Started Jul 01 05:24:03 PM PDT 24
Finished Jul 01 05:25:06 PM PDT 24
Peak memory 224616 kb
Host smart-5e32ad8b-2a22-482a-b199-bae758a2286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197839663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1197839663
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.903936132
Short name T569
Test name
Test status
Simulation time 10504657525 ps
CPU time 22.73 seconds
Started Jul 01 05:24:01 PM PDT 24
Finished Jul 01 05:24:27 PM PDT 24
Peak memory 217688 kb
Host smart-3798430c-a3af-49fe-a4c7-279f4816d3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903936132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.903936132
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1211338366
Short name T215
Test name
Test status
Simulation time 36723519859 ps
CPU time 127.67 seconds
Started Jul 01 05:24:01 PM PDT 24
Finished Jul 01 05:26:12 PM PDT 24
Peak memory 257496 kb
Host smart-7f1a86e5-9719-49c3-85c3-68566479330b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211338366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1211338366
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.828542711
Short name T294
Test name
Test status
Simulation time 299935774 ps
CPU time 8.5 seconds
Started Jul 01 05:24:03 PM PDT 24
Finished Jul 01 05:24:14 PM PDT 24
Peak memory 233948 kb
Host smart-218dbd73-1e89-40fa-8600-bd442e611581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828542711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.828542711
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.31240245
Short name T930
Test name
Test status
Simulation time 2860452363 ps
CPU time 10.74 seconds
Started Jul 01 05:24:04 PM PDT 24
Finished Jul 01 05:24:17 PM PDT 24
Peak memory 224616 kb
Host smart-19853e2a-3dd3-4d42-a152-e5598330071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31240245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.31240245
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.302855889
Short name T458
Test name
Test status
Simulation time 373008433 ps
CPU time 4.84 seconds
Started Jul 01 05:24:02 PM PDT 24
Finished Jul 01 05:24:10 PM PDT 24
Peak memory 224528 kb
Host smart-e530ae32-b2be-4bb9-8a31-a5c2b1bd1c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302855889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.302855889
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1977016456
Short name T766
Test name
Test status
Simulation time 35751687 ps
CPU time 2.53 seconds
Started Jul 01 05:24:03 PM PDT 24
Finished Jul 01 05:24:08 PM PDT 24
Peak memory 232404 kb
Host smart-a5dec2c5-142c-4c02-b837-eb49de3ff257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977016456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1977016456
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1069183859
Short name T836
Test name
Test status
Simulation time 10002590674 ps
CPU time 11.31 seconds
Started Jul 01 05:24:03 PM PDT 24
Finished Jul 01 05:24:17 PM PDT 24
Peak memory 232840 kb
Host smart-6d5b6013-4a3f-4ca3-90c0-dd293463f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069183859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1069183859
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.625574956
Short name T845
Test name
Test status
Simulation time 162288059 ps
CPU time 3.57 seconds
Started Jul 01 05:24:02 PM PDT 24
Finished Jul 01 05:24:09 PM PDT 24
Peak memory 222800 kb
Host smart-b2982882-2925-47df-9fd9-bb4175f3371c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=625574956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.625574956
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1026689615
Short name T65
Test name
Test status
Simulation time 485968901 ps
CPU time 1.22 seconds
Started Jul 01 05:24:02 PM PDT 24
Finished Jul 01 05:24:06 PM PDT 24
Peak memory 236136 kb
Host smart-e87e144f-93f6-4171-8ac9-b1b3a67c6e7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026689615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1026689615
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4258870246
Short name T469
Test name
Test status
Simulation time 7847828738 ps
CPU time 11.86 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:24 PM PDT 24
Peak memory 224540 kb
Host smart-2fd258f3-a1ae-4f77-a285-22adc38b62a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258870246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4258870246
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2407424695
Short name T435
Test name
Test status
Simulation time 23777845 ps
CPU time 0.71 seconds
Started Jul 01 05:24:05 PM PDT 24
Finished Jul 01 05:24:07 PM PDT 24
Peak memory 205744 kb
Host smart-b12ddcd1-c1ee-4517-8572-0709345e374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407424695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2407424695
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.53824021
Short name T362
Test name
Test status
Simulation time 5839102095 ps
CPU time 15.94 seconds
Started Jul 01 05:24:01 PM PDT 24
Finished Jul 01 05:24:20 PM PDT 24
Peak memory 216384 kb
Host smart-5a84afee-5871-4bb0-a69b-065e865591d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53824021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.53824021
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3035279753
Short name T449
Test name
Test status
Simulation time 611099147 ps
CPU time 1.1 seconds
Started Jul 01 05:24:01 PM PDT 24
Finished Jul 01 05:24:05 PM PDT 24
Peak memory 207972 kb
Host smart-4e09932b-3b4e-48e6-bfd7-45192b14068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035279753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3035279753
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2947615638
Short name T502
Test name
Test status
Simulation time 127045282 ps
CPU time 0.92 seconds
Started Jul 01 05:24:02 PM PDT 24
Finished Jul 01 05:24:05 PM PDT 24
Peak memory 207012 kb
Host smart-59810bba-1829-4e48-9122-db129ab54f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947615638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2947615638
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.127158285
Short name T186
Test name
Test status
Simulation time 573748787 ps
CPU time 5.45 seconds
Started Jul 01 05:24:02 PM PDT 24
Finished Jul 01 05:24:10 PM PDT 24
Peak memory 224448 kb
Host smart-103b8021-6941-44d3-8409-3d98a0d3b066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127158285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.127158285
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.661434652
Short name T516
Test name
Test status
Simulation time 42126479 ps
CPU time 0.73 seconds
Started Jul 01 05:26:08 PM PDT 24
Finished Jul 01 05:26:11 PM PDT 24
Peak memory 205580 kb
Host smart-43eeea5f-f675-4c37-a67e-b235f94f9371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661434652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.661434652
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.331961151
Short name T967
Test name
Test status
Simulation time 190658167 ps
CPU time 3.48 seconds
Started Jul 01 05:26:08 PM PDT 24
Finished Jul 01 05:26:14 PM PDT 24
Peak memory 232712 kb
Host smart-87f728b4-09ed-4009-ba17-041f99fa6dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331961151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.331961151
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3014454859
Short name T955
Test name
Test status
Simulation time 37233582 ps
CPU time 0.75 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:26:10 PM PDT 24
Peak memory 205632 kb
Host smart-36d1a109-8e4a-423c-8a09-9b61dd42f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014454859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3014454859
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1793728794
Short name T391
Test name
Test status
Simulation time 23800499306 ps
CPU time 70.6 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:27:19 PM PDT 24
Peak memory 249540 kb
Host smart-41f6f6ec-257c-4592-a9f4-5c2834dd81ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793728794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1793728794
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3090219269
Short name T517
Test name
Test status
Simulation time 45205398259 ps
CPU time 174.06 seconds
Started Jul 01 05:26:08 PM PDT 24
Finished Jul 01 05:29:05 PM PDT 24
Peak memory 253308 kb
Host smart-a6a22fba-5267-4380-8b57-5c4e47649ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090219269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3090219269
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1600056848
Short name T991
Test name
Test status
Simulation time 72073038859 ps
CPU time 192.67 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:29:22 PM PDT 24
Peak memory 250648 kb
Host smart-5b846a85-2bed-421e-a547-8174ecc261da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600056848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1600056848
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1212009834
Short name T1001
Test name
Test status
Simulation time 3163240778 ps
CPU time 17.68 seconds
Started Jul 01 05:26:07 PM PDT 24
Finished Jul 01 05:26:27 PM PDT 24
Peak memory 234040 kb
Host smart-5bad382d-4d3c-4272-9330-9b553461dc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212009834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1212009834
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.814540681
Short name T240
Test name
Test status
Simulation time 4492007842 ps
CPU time 41.51 seconds
Started Jul 01 05:26:06 PM PDT 24
Finished Jul 01 05:26:49 PM PDT 24
Peak memory 250572 kb
Host smart-c1db7d35-ea47-44df-a2db-7a15fe7dbd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814540681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.814540681
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2292723073
Short name T549
Test name
Test status
Simulation time 319988707 ps
CPU time 6.26 seconds
Started Jul 01 05:26:08 PM PDT 24
Finished Jul 01 05:26:17 PM PDT 24
Peak memory 232708 kb
Host smart-9e4ff965-4e04-40d5-a7f3-473abd246025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292723073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2292723073
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1656990835
Short name T698
Test name
Test status
Simulation time 1328800993 ps
CPU time 18.33 seconds
Started Jul 01 05:26:06 PM PDT 24
Finished Jul 01 05:26:26 PM PDT 24
Peak memory 224520 kb
Host smart-468d9b4b-f016-4657-b2d8-3e3831618d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656990835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1656990835
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1241798155
Short name T560
Test name
Test status
Simulation time 143319435 ps
CPU time 2.23 seconds
Started Jul 01 05:26:11 PM PDT 24
Finished Jul 01 05:26:15 PM PDT 24
Peak memory 223944 kb
Host smart-fee5f7f8-c7e5-490a-8211-96b54d146306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241798155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1241798155
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2259680124
Short name T588
Test name
Test status
Simulation time 926623980 ps
CPU time 6.17 seconds
Started Jul 01 05:26:08 PM PDT 24
Finished Jul 01 05:26:17 PM PDT 24
Peak memory 224492 kb
Host smart-7fc10ff4-007f-42ae-bda5-c10583671121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259680124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2259680124
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.866367715
Short name T464
Test name
Test status
Simulation time 1241827475 ps
CPU time 9.13 seconds
Started Jul 01 05:26:10 PM PDT 24
Finished Jul 01 05:26:21 PM PDT 24
Peak memory 220572 kb
Host smart-9dd9634a-65a7-4bc4-bd5e-679052befed6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=866367715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.866367715
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.762567548
Short name T146
Test name
Test status
Simulation time 64612896422 ps
CPU time 576.26 seconds
Started Jul 01 05:26:08 PM PDT 24
Finished Jul 01 05:35:46 PM PDT 24
Peak memory 264528 kb
Host smart-3f7426cd-6cae-4051-a51a-a41ea5c644a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762567548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.762567548
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3630508509
Short name T621
Test name
Test status
Simulation time 2143530559 ps
CPU time 29.72 seconds
Started Jul 01 05:26:10 PM PDT 24
Finished Jul 01 05:26:42 PM PDT 24
Peak memory 216440 kb
Host smart-186bd4be-34c3-48db-8c8b-b783b4983fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630508509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3630508509
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.381677763
Short name T637
Test name
Test status
Simulation time 4381174044 ps
CPU time 7.62 seconds
Started Jul 01 05:26:08 PM PDT 24
Finished Jul 01 05:26:18 PM PDT 24
Peak memory 216404 kb
Host smart-bbc2e71c-af9d-4dec-9140-5948ffe68746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381677763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.381677763
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1955867981
Short name T336
Test name
Test status
Simulation time 29961278 ps
CPU time 1.1 seconds
Started Jul 01 05:26:06 PM PDT 24
Finished Jul 01 05:26:09 PM PDT 24
Peak memory 207104 kb
Host smart-21c84eb8-cc3d-4978-a810-3a00d6e67978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955867981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1955867981
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2833565902
Short name T333
Test name
Test status
Simulation time 88081824 ps
CPU time 0.79 seconds
Started Jul 01 05:26:09 PM PDT 24
Finished Jul 01 05:26:12 PM PDT 24
Peak memory 206044 kb
Host smart-47d681d7-68de-4141-9773-02ce2cef92ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833565902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2833565902
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3828166676
Short name T821
Test name
Test status
Simulation time 91601892 ps
CPU time 2.42 seconds
Started Jul 01 05:26:09 PM PDT 24
Finished Jul 01 05:26:14 PM PDT 24
Peak memory 224064 kb
Host smart-ad20c090-7c75-4b4f-822f-f34bb2f4776a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828166676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3828166676
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2278731422
Short name T339
Test name
Test status
Simulation time 23989747 ps
CPU time 0.78 seconds
Started Jul 01 05:26:24 PM PDT 24
Finished Jul 01 05:26:29 PM PDT 24
Peak memory 205560 kb
Host smart-869402c6-9a8a-4cfe-a7e5-22e0add85df0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278731422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2278731422
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2248390811
Short name T315
Test name
Test status
Simulation time 65090462 ps
CPU time 2.38 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:26:32 PM PDT 24
Peak memory 232396 kb
Host smart-ff5a18cd-711c-40c9-9e11-518dbbada8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248390811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2248390811
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3110902000
Short name T847
Test name
Test status
Simulation time 61114748 ps
CPU time 0.74 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:27 PM PDT 24
Peak memory 205592 kb
Host smart-311a2877-ca33-47f7-8d59-24763ad0841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110902000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3110902000
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.463444033
Short name T283
Test name
Test status
Simulation time 71329391553 ps
CPU time 310.37 seconds
Started Jul 01 05:26:21 PM PDT 24
Finished Jul 01 05:31:33 PM PDT 24
Peak memory 257328 kb
Host smart-62486cf4-4cd4-4d37-a405-e6d2fdce84f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463444033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.463444033
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2187381537
Short name T960
Test name
Test status
Simulation time 45988591257 ps
CPU time 269.23 seconds
Started Jul 01 05:26:27 PM PDT 24
Finished Jul 01 05:31:00 PM PDT 24
Peak memory 272876 kb
Host smart-e6a42d7c-a5d0-40b5-b56d-9c9d6c78f3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187381537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2187381537
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.477152176
Short name T301
Test name
Test status
Simulation time 3953845266 ps
CPU time 82.34 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:27:47 PM PDT 24
Peak memory 256920 kb
Host smart-acab7cb1-342d-4d93-a77d-b0337d2cc218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477152176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.477152176
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.628709862
Short name T609
Test name
Test status
Simulation time 633240013 ps
CPU time 4.38 seconds
Started Jul 01 05:26:21 PM PDT 24
Finished Jul 01 05:26:28 PM PDT 24
Peak memory 224584 kb
Host smart-e31aa85e-ac70-4bc5-85fa-7d07657a6067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628709862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.628709862
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.4220495135
Short name T245
Test name
Test status
Simulation time 1392082304 ps
CPU time 18.89 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:47 PM PDT 24
Peak memory 249068 kb
Host smart-79a95822-c0db-4246-bf9d-c5fe194d0e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220495135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.4220495135
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1879343798
Short name T208
Test name
Test status
Simulation time 2832090788 ps
CPU time 19.19 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:46 PM PDT 24
Peak memory 228424 kb
Host smart-f38a869b-1ace-4549-afa7-ee85f19b4287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879343798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1879343798
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.464564745
Short name T181
Test name
Test status
Simulation time 15793635753 ps
CPU time 31.03 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:26:57 PM PDT 24
Peak memory 232800 kb
Host smart-33bc35fe-0c84-4310-ba05-e95ad33db25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464564745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.464564745
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2051743656
Short name T747
Test name
Test status
Simulation time 3872526884 ps
CPU time 4.99 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:26:30 PM PDT 24
Peak memory 232792 kb
Host smart-f3457016-87ca-4dc2-be95-5780e72ddf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051743656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2051743656
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3591027709
Short name T224
Test name
Test status
Simulation time 4081299232 ps
CPU time 15.25 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:26:40 PM PDT 24
Peak memory 232796 kb
Host smart-c8c0568e-ade3-4a1c-812d-28b1101b865b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591027709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3591027709
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.383936736
Short name T467
Test name
Test status
Simulation time 1402942260 ps
CPU time 6.9 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:26:37 PM PDT 24
Peak memory 218888 kb
Host smart-d0e6e90b-dbca-4060-96a4-ee0385d44b0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=383936736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.383936736
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1251066756
Short name T14
Test name
Test status
Simulation time 2207194725 ps
CPU time 52.53 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:27:18 PM PDT 24
Peak memory 253716 kb
Host smart-f9586a1c-473e-4f8c-b50b-b5a3e986c9ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251066756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1251066756
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3553745361
Short name T52
Test name
Test status
Simulation time 1987114834 ps
CPU time 28.6 seconds
Started Jul 01 05:26:21 PM PDT 24
Finished Jul 01 05:26:53 PM PDT 24
Peak memory 219436 kb
Host smart-71a5db70-5806-424b-a6f1-38c5333e48a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553745361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3553745361
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.873020905
Short name T839
Test name
Test status
Simulation time 20168173854 ps
CPU time 12.92 seconds
Started Jul 01 05:26:25 PM PDT 24
Finished Jul 01 05:26:42 PM PDT 24
Peak memory 216240 kb
Host smart-8f89e011-0e12-41dd-a08b-35ba31b64587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873020905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.873020905
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1084824998
Short name T818
Test name
Test status
Simulation time 81866252 ps
CPU time 5.12 seconds
Started Jul 01 05:26:24 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 216232 kb
Host smart-bd135e75-ac3a-44dd-82af-d8994eef5f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084824998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1084824998
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.510931359
Short name T814
Test name
Test status
Simulation time 190874313 ps
CPU time 0.89 seconds
Started Jul 01 05:26:21 PM PDT 24
Finished Jul 01 05:26:24 PM PDT 24
Peak memory 206232 kb
Host smart-aa7a636e-b281-46d2-8e90-ed7f935481aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510931359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.510931359
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3892409266
Short name T674
Test name
Test status
Simulation time 3037464269 ps
CPU time 11.14 seconds
Started Jul 01 05:26:25 PM PDT 24
Finished Jul 01 05:26:40 PM PDT 24
Peak memory 232752 kb
Host smart-c54e4701-fee0-4c9a-a689-a0bca6652615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892409266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3892409266
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1351659703
Short name T379
Test name
Test status
Simulation time 249485040 ps
CPU time 0.73 seconds
Started Jul 01 05:26:21 PM PDT 24
Finished Jul 01 05:26:24 PM PDT 24
Peak memory 205576 kb
Host smart-44e4cea1-8e4d-4241-917b-62ab59d1575e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351659703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1351659703
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3971159946
Short name T344
Test name
Test status
Simulation time 1435816235 ps
CPU time 3.6 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:31 PM PDT 24
Peak memory 232680 kb
Host smart-5ddf4263-ae95-4ce4-b45e-b201330b9c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971159946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3971159946
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3601408665
Short name T817
Test name
Test status
Simulation time 47954059 ps
CPU time 0.87 seconds
Started Jul 01 05:26:21 PM PDT 24
Finished Jul 01 05:26:24 PM PDT 24
Peak memory 206596 kb
Host smart-ba19ded3-ea57-44ed-8dd9-abf84aac816a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601408665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3601408665
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3037670409
Short name T562
Test name
Test status
Simulation time 15360031350 ps
CPU time 113.23 seconds
Started Jul 01 05:26:24 PM PDT 24
Finished Jul 01 05:28:22 PM PDT 24
Peak memory 251868 kb
Host smart-4a85bf27-1582-4a5c-921e-9af290c37e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037670409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3037670409
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2626691385
Short name T795
Test name
Test status
Simulation time 4219291561 ps
CPU time 67.85 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:27:35 PM PDT 24
Peak memory 249988 kb
Host smart-dad2a5d8-0c73-4b75-bd55-9d130d5c78ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626691385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2626691385
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1140314102
Short name T265
Test name
Test status
Simulation time 485483525959 ps
CPU time 381.21 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:32:47 PM PDT 24
Peak memory 262036 kb
Host smart-1df2ef7c-3528-4498-8128-7865d82ae057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140314102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1140314102
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2038794625
Short name T421
Test name
Test status
Simulation time 3066618285 ps
CPU time 6.94 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 237548 kb
Host smart-68fbf9e2-fb6b-48c3-9020-a9f316372620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038794625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2038794625
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2212763747
Short name T170
Test name
Test status
Simulation time 2347637492 ps
CPU time 60.04 seconds
Started Jul 01 05:26:25 PM PDT 24
Finished Jul 01 05:27:29 PM PDT 24
Peak memory 254132 kb
Host smart-a025f148-dc2f-41b1-8f55-bacadc7fdb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212763747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2212763747
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1801613256
Short name T54
Test name
Test status
Simulation time 724395889 ps
CPU time 4.55 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:32 PM PDT 24
Peak memory 224528 kb
Host smart-9f1096ae-2c75-4387-9ab3-dbe4d2d15e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801613256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1801613256
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1837501137
Short name T510
Test name
Test status
Simulation time 21666636854 ps
CPU time 17.21 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:26:47 PM PDT 24
Peak memory 232808 kb
Host smart-4c2bb335-8b64-4596-8ea4-c3563669c6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837501137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1837501137
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1074841253
Short name T657
Test name
Test status
Simulation time 3757838040 ps
CPU time 14.2 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:26:44 PM PDT 24
Peak memory 234868 kb
Host smart-3a6450ee-84bb-4763-b4ef-b2e1337a9b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074841253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1074841253
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1550765408
Short name T884
Test name
Test status
Simulation time 355383657 ps
CPU time 3.33 seconds
Started Jul 01 05:26:27 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 224444 kb
Host smart-b3541a85-92bc-40d1-a066-05eb93a14580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550765408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1550765408
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3204652682
Short name T767
Test name
Test status
Simulation time 587522838 ps
CPU time 4.04 seconds
Started Jul 01 05:26:20 PM PDT 24
Finished Jul 01 05:26:26 PM PDT 24
Peak memory 223240 kb
Host smart-e8794abe-9ea7-4bae-8e2b-fe80f4d78215
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3204652682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3204652682
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1922630638
Short name T619
Test name
Test status
Simulation time 636582438507 ps
CPU time 544.07 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:35:34 PM PDT 24
Peak memory 273856 kb
Host smart-e1c368c6-f9aa-459c-a6a3-749d188fa1cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922630638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1922630638
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3377587986
Short name T704
Test name
Test status
Simulation time 14791027 ps
CPU time 0.75 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:27 PM PDT 24
Peak memory 205728 kb
Host smart-e44ea12f-ccc1-4dd1-a721-d2adfe151d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377587986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3377587986
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3593781387
Short name T363
Test name
Test status
Simulation time 16179142579 ps
CPU time 10.72 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:26:41 PM PDT 24
Peak memory 216364 kb
Host smart-e5ffa39f-2de7-4ed2-9620-42124f2de465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593781387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3593781387
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1131039194
Short name T523
Test name
Test status
Simulation time 1346966050 ps
CPU time 4.08 seconds
Started Jul 01 05:26:21 PM PDT 24
Finished Jul 01 05:26:27 PM PDT 24
Peak memory 216272 kb
Host smart-0bfefcf3-85fe-4b6c-a4b0-971fc4458c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131039194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1131039194
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1289134617
Short name T33
Test name
Test status
Simulation time 185795302 ps
CPU time 0.94 seconds
Started Jul 01 05:26:20 PM PDT 24
Finished Jul 01 05:26:22 PM PDT 24
Peak memory 206992 kb
Host smart-8bf60226-1303-4e56-aa95-6d456ed5f47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289134617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1289134617
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1709888343
Short name T225
Test name
Test status
Simulation time 130176285 ps
CPU time 2.66 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:26:33 PM PDT 24
Peak memory 224504 kb
Host smart-e102fb63-d8d6-47ec-a0f5-c44e356581d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709888343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1709888343
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4003917726
Short name T831
Test name
Test status
Simulation time 12469559 ps
CPU time 0.7 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:27 PM PDT 24
Peak memory 204988 kb
Host smart-84a099b7-7a3b-46d1-9094-4d016cbb6877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003917726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4003917726
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1689402018
Short name T176
Test name
Test status
Simulation time 1220148482 ps
CPU time 6.02 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:33 PM PDT 24
Peak memory 232708 kb
Host smart-a0158cd3-8e12-48f0-b147-478a3fd17e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689402018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1689402018
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4219393037
Short name T825
Test name
Test status
Simulation time 24152030 ps
CPU time 0.75 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:26:25 PM PDT 24
Peak memory 205984 kb
Host smart-14ddb633-3f2c-4b9b-816f-eca8da03b169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219393037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4219393037
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2928868006
Short name T286
Test name
Test status
Simulation time 8148317073 ps
CPU time 84.9 seconds
Started Jul 01 05:26:21 PM PDT 24
Finished Jul 01 05:27:49 PM PDT 24
Peak memory 257408 kb
Host smart-bcc7ed60-f365-4e8e-a5b4-e048cdc8e798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928868006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2928868006
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2846540455
Short name T178
Test name
Test status
Simulation time 41151422626 ps
CPU time 283.91 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:31:09 PM PDT 24
Peak memory 251904 kb
Host smart-6dc5c533-b581-499b-9aaa-c64bfd06249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846540455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2846540455
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3945665364
Short name T635
Test name
Test status
Simulation time 499666619 ps
CPU time 8.68 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:36 PM PDT 24
Peak memory 217480 kb
Host smart-9ad1b98f-8321-48d2-a74b-2aed5464a787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945665364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3945665364
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.637062034
Short name T807
Test name
Test status
Simulation time 64634115 ps
CPU time 3.21 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:26:28 PM PDT 24
Peak memory 232712 kb
Host smart-a4dd84a6-bcd1-452a-b7b9-33fc987b62c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637062034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.637062034
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1701091112
Short name T332
Test name
Test status
Simulation time 5311099247 ps
CPU time 13.47 seconds
Started Jul 01 05:26:27 PM PDT 24
Finished Jul 01 05:26:44 PM PDT 24
Peak memory 224628 kb
Host smart-aa5c5dfa-8acf-436e-b2f3-86444f727572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701091112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1701091112
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2731018473
Short name T71
Test name
Test status
Simulation time 384598999 ps
CPU time 6.88 seconds
Started Jul 01 05:26:21 PM PDT 24
Finished Jul 01 05:26:30 PM PDT 24
Peak memory 232724 kb
Host smart-f2e2c82e-bd41-461a-8ee8-1062d9166761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731018473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2731018473
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2582497992
Short name T616
Test name
Test status
Simulation time 131632559 ps
CPU time 5.39 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:26:31 PM PDT 24
Peak memory 236024 kb
Host smart-0d3c6610-b965-4a05-a1f6-e0370260edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582497992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2582497992
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3728883578
Short name T243
Test name
Test status
Simulation time 2608003227 ps
CPU time 9.09 seconds
Started Jul 01 05:26:24 PM PDT 24
Finished Jul 01 05:26:38 PM PDT 24
Peak memory 232792 kb
Host smart-d593bf3a-9432-48e9-a06a-85b6671e2a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728883578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3728883578
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1625263152
Short name T678
Test name
Test status
Simulation time 339268498 ps
CPU time 5.42 seconds
Started Jul 01 05:26:25 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 224588 kb
Host smart-fafda5dc-8f4b-45d4-834b-020a4bd50469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625263152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1625263152
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2722538740
Short name T509
Test name
Test status
Simulation time 443481636 ps
CPU time 7.65 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:35 PM PDT 24
Peak memory 220276 kb
Host smart-c6c4cf09-aa94-4472-87b5-9aac5804ae2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2722538740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2722538740
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2023227320
Short name T482
Test name
Test status
Simulation time 11102293621 ps
CPU time 149.26 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:28:59 PM PDT 24
Peak memory 265716 kb
Host smart-8302106b-5e2f-4c13-b6d5-984c19e20b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023227320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2023227320
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.76042134
Short name T853
Test name
Test status
Simulation time 53215934590 ps
CPU time 34.78 seconds
Started Jul 01 05:26:24 PM PDT 24
Finished Jul 01 05:27:03 PM PDT 24
Peak memory 216316 kb
Host smart-48674730-2ef5-4ab1-b95f-bfd42922a5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76042134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.76042134
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1839655685
Short name T526
Test name
Test status
Simulation time 580812850 ps
CPU time 4.11 seconds
Started Jul 01 05:26:22 PM PDT 24
Finished Jul 01 05:26:29 PM PDT 24
Peak memory 216260 kb
Host smart-45e7f92a-d1e9-4d5a-b928-bb04c1a73517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839655685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1839655685
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1887342926
Short name T719
Test name
Test status
Simulation time 44173511 ps
CPU time 0.79 seconds
Started Jul 01 05:26:20 PM PDT 24
Finished Jul 01 05:26:22 PM PDT 24
Peak memory 206080 kb
Host smart-1deb391f-acbf-4eaf-9629-982415d71ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887342926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1887342926
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3825134220
Short name T625
Test name
Test status
Simulation time 53821990 ps
CPU time 0.73 seconds
Started Jul 01 05:26:23 PM PDT 24
Finished Jul 01 05:26:29 PM PDT 24
Peak memory 206068 kb
Host smart-e40bd18c-4eaf-4297-b150-977cb03031d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825134220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3825134220
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2333898865
Short name T27
Test name
Test status
Simulation time 291787189 ps
CPU time 3.94 seconds
Started Jul 01 05:26:24 PM PDT 24
Finished Jul 01 05:26:33 PM PDT 24
Peak memory 224488 kb
Host smart-f756deb9-cbc8-4a57-ba10-c9e8597a7d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333898865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2333898865
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4107638812
Short name T376
Test name
Test status
Simulation time 45089362 ps
CPU time 0.74 seconds
Started Jul 01 05:26:31 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 205000 kb
Host smart-c8099d58-d324-4a27-b6da-2d0f155a7ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107638812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4107638812
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2665792999
Short name T956
Test name
Test status
Simulation time 511219971 ps
CPU time 2.34 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:26:32 PM PDT 24
Peak memory 232708 kb
Host smart-91c03a2a-69f3-4703-b43f-34583f075a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665792999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2665792999
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1581903576
Short name T879
Test name
Test status
Simulation time 16897884 ps
CPU time 0.81 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:26:31 PM PDT 24
Peak memory 206616 kb
Host smart-207e7cb3-5520-4740-8679-e2bca5c5bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581903576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1581903576
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3928697874
Short name T51
Test name
Test status
Simulation time 79917067764 ps
CPU time 423.82 seconds
Started Jul 01 05:26:29 PM PDT 24
Finished Jul 01 05:33:36 PM PDT 24
Peak memory 257416 kb
Host smart-8bc7f7be-2add-4289-af39-9c48218a29ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928697874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3928697874
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3478506590
Short name T299
Test name
Test status
Simulation time 6596623880 ps
CPU time 26.98 seconds
Started Jul 01 05:26:26 PM PDT 24
Finished Jul 01 05:26:57 PM PDT 24
Peak memory 217780 kb
Host smart-8824a699-075c-450d-bf2d-c39c3309ec7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478506590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3478506590
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2823436907
Short name T375
Test name
Test status
Simulation time 44559384 ps
CPU time 3.14 seconds
Started Jul 01 05:26:27 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 224476 kb
Host smart-f62d086d-7cd4-415d-9d5f-df059ccd89f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823436907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2823436907
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1208180162
Short name T594
Test name
Test status
Simulation time 6342219046 ps
CPU time 42.77 seconds
Started Jul 01 05:26:28 PM PDT 24
Finished Jul 01 05:27:14 PM PDT 24
Peak memory 234864 kb
Host smart-26cdd0c7-604e-47ad-aa27-042dba1ecf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208180162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1208180162
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.172638626
Short name T369
Test name
Test status
Simulation time 286912453 ps
CPU time 4.2 seconds
Started Jul 01 05:26:25 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 224476 kb
Host smart-f15d7f58-055a-430d-a8f6-0e0a997b6ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172638626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.172638626
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2787805591
Short name T833
Test name
Test status
Simulation time 5843255813 ps
CPU time 16.94 seconds
Started Jul 01 05:26:32 PM PDT 24
Finished Jul 01 05:26:51 PM PDT 24
Peak memory 239632 kb
Host smart-7ea6fcf4-9994-4a9e-ab66-867840d443b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787805591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2787805591
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.978544041
Short name T242
Test name
Test status
Simulation time 838999981 ps
CPU time 5.18 seconds
Started Jul 01 05:26:27 PM PDT 24
Finished Jul 01 05:26:36 PM PDT 24
Peak memory 224480 kb
Host smart-070ff707-0551-4ead-aa49-819716c7cf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978544041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.978544041
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1561888775
Short name T496
Test name
Test status
Simulation time 1203774943 ps
CPU time 2.94 seconds
Started Jul 01 05:26:29 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 224492 kb
Host smart-2f12e2ba-dbb4-4783-b994-646b9a38aba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561888775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1561888775
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3124734598
Short name T786
Test name
Test status
Simulation time 1494209581 ps
CPU time 13.23 seconds
Started Jul 01 05:26:31 PM PDT 24
Finished Jul 01 05:26:46 PM PDT 24
Peak memory 222528 kb
Host smart-d93b0cbb-589a-4f18-a723-7f18d7353c34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3124734598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3124734598
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1619989183
Short name T149
Test name
Test status
Simulation time 75872330107 ps
CPU time 144.03 seconds
Started Jul 01 05:26:25 PM PDT 24
Finished Jul 01 05:28:53 PM PDT 24
Peak memory 255508 kb
Host smart-c6790ba9-f737-4005-91ff-6a439c06cae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619989183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1619989183
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2626163909
Short name T662
Test name
Test status
Simulation time 71347360 ps
CPU time 1.66 seconds
Started Jul 01 05:26:25 PM PDT 24
Finished Jul 01 05:26:31 PM PDT 24
Peak memory 216584 kb
Host smart-c53e97a7-2848-4068-bb00-02c932f0e30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626163909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2626163909
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3120446314
Short name T56
Test name
Test status
Simulation time 1048164500 ps
CPU time 4.68 seconds
Started Jul 01 05:26:27 PM PDT 24
Finished Jul 01 05:26:35 PM PDT 24
Peak memory 216264 kb
Host smart-6aef2576-e5de-4841-b689-cc47c31d38b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120446314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3120446314
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.584653449
Short name T1
Test name
Test status
Simulation time 1855417922 ps
CPU time 9.5 seconds
Started Jul 01 05:26:28 PM PDT 24
Finished Jul 01 05:26:40 PM PDT 24
Peak memory 216240 kb
Host smart-6bf4cd04-729e-4228-9b80-cc801c5fb198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584653449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.584653449
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.906238501
Short name T729
Test name
Test status
Simulation time 111320491 ps
CPU time 1.05 seconds
Started Jul 01 05:26:25 PM PDT 24
Finished Jul 01 05:26:30 PM PDT 24
Peak memory 207020 kb
Host smart-40a24675-9547-40e9-b38c-98fdba02409a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906238501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.906238501
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.885235077
Short name T252
Test name
Test status
Simulation time 501693203 ps
CPU time 9.53 seconds
Started Jul 01 05:26:29 PM PDT 24
Finished Jul 01 05:26:40 PM PDT 24
Peak memory 236852 kb
Host smart-cf294c0c-7c36-4d72-93be-6124ce949d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885235077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.885235077
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.53524167
Short name T426
Test name
Test status
Simulation time 57448500 ps
CPU time 0.74 seconds
Started Jul 01 05:26:34 PM PDT 24
Finished Jul 01 05:26:37 PM PDT 24
Peak memory 204996 kb
Host smart-7b420ab6-600f-45e6-a55d-235dd4410fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53524167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.53524167
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1996738292
Short name T318
Test name
Test status
Simulation time 1393159711 ps
CPU time 10 seconds
Started Jul 01 05:26:33 PM PDT 24
Finished Jul 01 05:26:46 PM PDT 24
Peak memory 224512 kb
Host smart-2f18bfff-3e68-4487-a27a-808bd1ce5e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996738292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1996738292
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.237566499
Short name T950
Test name
Test status
Simulation time 19786604 ps
CPU time 0.85 seconds
Started Jul 01 05:26:27 PM PDT 24
Finished Jul 01 05:26:31 PM PDT 24
Peak memory 206940 kb
Host smart-f96fb0d0-cc73-4af4-9833-f5371e77742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237566499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.237566499
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2788086053
Short name T965
Test name
Test status
Simulation time 5830640785 ps
CPU time 60.29 seconds
Started Jul 01 05:26:34 PM PDT 24
Finished Jul 01 05:27:36 PM PDT 24
Peak memory 254296 kb
Host smart-a492948a-428f-4241-b773-89d94b72f08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788086053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2788086053
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3326827728
Short name T544
Test name
Test status
Simulation time 4177444126 ps
CPU time 41.25 seconds
Started Jul 01 05:26:31 PM PDT 24
Finished Jul 01 05:27:14 PM PDT 24
Peak memory 250884 kb
Host smart-a37bc54f-9b01-43a3-984d-6cffa3acc3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326827728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3326827728
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1076818279
Short name T1012
Test name
Test status
Simulation time 5304252522 ps
CPU time 70.94 seconds
Started Jul 01 05:26:34 PM PDT 24
Finished Jul 01 05:27:47 PM PDT 24
Peak memory 253252 kb
Host smart-8a8a5917-534e-48c7-a374-f0530dc59c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076818279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1076818279
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2020467962
Short name T55
Test name
Test status
Simulation time 426631785 ps
CPU time 11.86 seconds
Started Jul 01 05:26:33 PM PDT 24
Finished Jul 01 05:26:47 PM PDT 24
Peak memory 224516 kb
Host smart-f251f926-593b-433e-8dd8-faf0896c7954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020467962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2020467962
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.60973880
Short name T592
Test name
Test status
Simulation time 26334428042 ps
CPU time 189.17 seconds
Started Jul 01 05:26:33 PM PDT 24
Finished Jul 01 05:29:44 PM PDT 24
Peak memory 254596 kb
Host smart-b67a06d5-d5d9-4e93-9a23-802a696d39dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60973880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.60973880
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2567876283
Short name T937
Test name
Test status
Simulation time 800678281 ps
CPU time 8.18 seconds
Started Jul 01 05:26:32 PM PDT 24
Finished Jul 01 05:26:42 PM PDT 24
Peak memory 224508 kb
Host smart-8dc069a3-092c-4de8-89a8-8f884e18517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567876283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2567876283
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2435944757
Short name T260
Test name
Test status
Simulation time 792916363 ps
CPU time 9.31 seconds
Started Jul 01 05:26:33 PM PDT 24
Finished Jul 01 05:26:45 PM PDT 24
Peak memory 240072 kb
Host smart-cbd72856-51d5-4219-9e5c-96642af296f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435944757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2435944757
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2944316067
Short name T278
Test name
Test status
Simulation time 2797708934 ps
CPU time 9.98 seconds
Started Jul 01 05:26:31 PM PDT 24
Finished Jul 01 05:26:43 PM PDT 24
Peak memory 224716 kb
Host smart-2c397ffb-d209-414d-8912-b9a545b12ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944316067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2944316067
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3918345443
Short name T184
Test name
Test status
Simulation time 1405634488 ps
CPU time 10.84 seconds
Started Jul 01 05:26:37 PM PDT 24
Finished Jul 01 05:26:50 PM PDT 24
Peak memory 232748 kb
Host smart-221766b7-eecb-442a-9504-4b0afe91a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918345443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3918345443
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1422652462
Short name T602
Test name
Test status
Simulation time 464736986 ps
CPU time 7.97 seconds
Started Jul 01 05:26:36 PM PDT 24
Finished Jul 01 05:26:45 PM PDT 24
Peak memory 223072 kb
Host smart-b348177a-f99d-465c-b6ed-96c9644162e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1422652462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1422652462
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3657850348
Short name T352
Test name
Test status
Simulation time 179744936 ps
CPU time 0.73 seconds
Started Jul 01 05:26:31 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 205852 kb
Host smart-f84b3d6a-80c6-4d43-a207-f4bfcccfdbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657850348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3657850348
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.868289708
Short name T682
Test name
Test status
Simulation time 1353564707 ps
CPU time 6.04 seconds
Started Jul 01 05:26:30 PM PDT 24
Finished Jul 01 05:26:38 PM PDT 24
Peak memory 216192 kb
Host smart-91ba28f5-8400-412e-a7cf-6bb76372f1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868289708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.868289708
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2940007634
Short name T313
Test name
Test status
Simulation time 126622290 ps
CPU time 1.13 seconds
Started Jul 01 05:26:33 PM PDT 24
Finished Jul 01 05:26:37 PM PDT 24
Peak memory 207528 kb
Host smart-4c47c34e-27f4-4ee3-b331-bd9743b71660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940007634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2940007634
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.903203218
Short name T684
Test name
Test status
Simulation time 193631499 ps
CPU time 0.92 seconds
Started Jul 01 05:26:35 PM PDT 24
Finished Jul 01 05:26:38 PM PDT 24
Peak memory 206000 kb
Host smart-10a8e25f-6ee5-435d-9270-4044c8dc2eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903203218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.903203218
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3832898948
Short name T661
Test name
Test status
Simulation time 210031501 ps
CPU time 4.77 seconds
Started Jul 01 05:26:32 PM PDT 24
Finished Jul 01 05:26:39 PM PDT 24
Peak memory 224572 kb
Host smart-e60754ba-a55f-49fa-a681-1476c9f7b3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832898948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3832898948
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2928259272
Short name T57
Test name
Test status
Simulation time 66116535 ps
CPU time 0.73 seconds
Started Jul 01 05:26:38 PM PDT 24
Finished Jul 01 05:26:40 PM PDT 24
Peak memory 205560 kb
Host smart-5aeed950-9b0c-4663-8a24-7c4fd4bd649d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928259272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2928259272
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3592052463
Short name T688
Test name
Test status
Simulation time 147669237 ps
CPU time 3.26 seconds
Started Jul 01 05:26:40 PM PDT 24
Finished Jul 01 05:26:44 PM PDT 24
Peak memory 232680 kb
Host smart-146a858b-7875-4594-9c63-5c5d93fc1320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592052463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3592052463
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.236349679
Short name T471
Test name
Test status
Simulation time 17364806 ps
CPU time 0.83 seconds
Started Jul 01 05:26:32 PM PDT 24
Finished Jul 01 05:26:35 PM PDT 24
Peak memory 206624 kb
Host smart-a9f179fd-c02c-4b11-9a92-6a2342f3a81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236349679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.236349679
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4041047063
Short name T234
Test name
Test status
Simulation time 20788899692 ps
CPU time 95.65 seconds
Started Jul 01 05:26:43 PM PDT 24
Finished Jul 01 05:28:21 PM PDT 24
Peak memory 238760 kb
Host smart-dad319c9-965a-4383-93f6-bca780c8b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041047063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4041047063
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4262938855
Short name T281
Test name
Test status
Simulation time 94863099506 ps
CPU time 273.93 seconds
Started Jul 01 05:26:43 PM PDT 24
Finished Jul 01 05:31:20 PM PDT 24
Peak memory 269980 kb
Host smart-d049ce16-ff14-42d5-9f50-28b474469f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262938855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4262938855
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.929781025
Short name T156
Test name
Test status
Simulation time 2476838536 ps
CPU time 52.67 seconds
Started Jul 01 05:26:38 PM PDT 24
Finished Jul 01 05:27:33 PM PDT 24
Peak memory 257396 kb
Host smart-9c155e3c-9c71-4dbc-b125-e2eb7e3d8d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929781025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.929781025
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2141345161
Short name T1010
Test name
Test status
Simulation time 804339503 ps
CPU time 17.37 seconds
Started Jul 01 05:26:43 PM PDT 24
Finished Jul 01 05:27:04 PM PDT 24
Peak memory 249092 kb
Host smart-621d4bdb-63fa-42da-a89f-e1df3f1ea183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141345161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2141345161
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2250448705
Short name T636
Test name
Test status
Simulation time 335496699 ps
CPU time 0.83 seconds
Started Jul 01 05:26:37 PM PDT 24
Finished Jul 01 05:26:39 PM PDT 24
Peak memory 215996 kb
Host smart-a66f50e3-c114-42ef-ae1b-5cb549700f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250448705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2250448705
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1087371528
Short name T840
Test name
Test status
Simulation time 415505455 ps
CPU time 6.38 seconds
Started Jul 01 05:26:40 PM PDT 24
Finished Jul 01 05:26:47 PM PDT 24
Peak memory 232632 kb
Host smart-beccecf3-d1e6-400e-8390-356c75889df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087371528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1087371528
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1803817340
Short name T566
Test name
Test status
Simulation time 22843265569 ps
CPU time 93.45 seconds
Started Jul 01 05:26:37 PM PDT 24
Finished Jul 01 05:28:12 PM PDT 24
Peak memory 241032 kb
Host smart-58e70eee-c969-4436-a972-5d45ab3a5dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803817340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1803817340
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.129759594
Short name T851
Test name
Test status
Simulation time 3476120412 ps
CPU time 4.05 seconds
Started Jul 01 05:26:32 PM PDT 24
Finished Jul 01 05:26:38 PM PDT 24
Peak memory 224620 kb
Host smart-ce1861c1-3847-4cbc-9b91-822318c603eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129759594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.129759594
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1091380468
Short name T212
Test name
Test status
Simulation time 244720473 ps
CPU time 3.19 seconds
Started Jul 01 05:26:37 PM PDT 24
Finished Jul 01 05:26:42 PM PDT 24
Peak memory 232672 kb
Host smart-82a5ee40-fe34-43e1-8e91-167bd51bf9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091380468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1091380468
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3009701293
Short name T555
Test name
Test status
Simulation time 2934068856 ps
CPU time 7.66 seconds
Started Jul 01 05:26:38 PM PDT 24
Finished Jul 01 05:26:48 PM PDT 24
Peak memory 220480 kb
Host smart-4ef36b13-d690-4626-b632-9b763b8a1ec1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3009701293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3009701293
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3963665538
Short name T1008
Test name
Test status
Simulation time 19904060857 ps
CPU time 26.03 seconds
Started Jul 01 05:26:37 PM PDT 24
Finished Jul 01 05:27:04 PM PDT 24
Peak memory 216392 kb
Host smart-d3342d1f-0764-43a6-a691-ac0ccb44fe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963665538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3963665538
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2865347340
Short name T388
Test name
Test status
Simulation time 3322480294 ps
CPU time 14.18 seconds
Started Jul 01 05:26:31 PM PDT 24
Finished Jul 01 05:26:47 PM PDT 24
Peak memory 216324 kb
Host smart-d46fc5f3-81b8-4c6e-a574-162911048713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865347340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2865347340
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3960027115
Short name T741
Test name
Test status
Simulation time 15083476 ps
CPU time 1.05 seconds
Started Jul 01 05:26:33 PM PDT 24
Finished Jul 01 05:26:37 PM PDT 24
Peak memory 207916 kb
Host smart-21c4ab4f-8b1d-46dc-86d2-24f2e1c51fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960027115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3960027115
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.280509657
Short name T356
Test name
Test status
Simulation time 75808440 ps
CPU time 1.05 seconds
Started Jul 01 05:26:31 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 206040 kb
Host smart-53ce8868-62c5-44a1-abbf-85141c689e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280509657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.280509657
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3416284325
Short name T837
Test name
Test status
Simulation time 5938153361 ps
CPU time 10.99 seconds
Started Jul 01 05:26:38 PM PDT 24
Finished Jul 01 05:26:50 PM PDT 24
Peak memory 224588 kb
Host smart-3ae91ab6-73aa-4c6a-a367-8c2cf7232cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416284325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3416284325
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3914472319
Short name T911
Test name
Test status
Simulation time 98774762 ps
CPU time 0.75 seconds
Started Jul 01 05:26:46 PM PDT 24
Finished Jul 01 05:26:51 PM PDT 24
Peak memory 205508 kb
Host smart-98af360b-2e3f-446e-9790-9d40570f2725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914472319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3914472319
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.567595843
Short name T261
Test name
Test status
Simulation time 132015645 ps
CPU time 2.89 seconds
Started Jul 01 05:26:48 PM PDT 24
Finished Jul 01 05:26:55 PM PDT 24
Peak memory 224468 kb
Host smart-84c76ce6-e6d5-40eb-aab1-a257cc0d95e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567595843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.567595843
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.812736497
Short name T582
Test name
Test status
Simulation time 19108328 ps
CPU time 0.76 seconds
Started Jul 01 05:26:37 PM PDT 24
Finished Jul 01 05:26:40 PM PDT 24
Peak memory 205600 kb
Host smart-5d0c8470-da05-42a1-974e-1fca1d2e03bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812736497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.812736497
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.571718941
Short name T285
Test name
Test status
Simulation time 356419739673 ps
CPU time 234.75 seconds
Started Jul 01 05:26:44 PM PDT 24
Finished Jul 01 05:30:43 PM PDT 24
Peak memory 239360 kb
Host smart-e8b4ad64-0ca3-4cbe-b0ac-e9cb04fcb3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571718941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.571718941
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3040736105
Short name T899
Test name
Test status
Simulation time 90673468266 ps
CPU time 407.03 seconds
Started Jul 01 05:26:43 PM PDT 24
Finished Jul 01 05:33:34 PM PDT 24
Peak memory 257420 kb
Host smart-3eacc9d5-3a08-4f9a-a67a-1823e089af5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040736105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3040736105
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1145142535
Short name T307
Test name
Test status
Simulation time 5813231206 ps
CPU time 49.5 seconds
Started Jul 01 05:26:43 PM PDT 24
Finished Jul 01 05:27:35 PM PDT 24
Peak memory 257180 kb
Host smart-dc195cc4-b470-4be0-96ef-cf256fa22fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145142535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1145142535
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3757474750
Short name T672
Test name
Test status
Simulation time 1497408439 ps
CPU time 14.79 seconds
Started Jul 01 05:26:47 PM PDT 24
Finished Jul 01 05:27:05 PM PDT 24
Peak memory 236164 kb
Host smart-a653eab0-6faa-46e1-803b-6e76474c80a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757474750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3757474750
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1415323322
Short name T945
Test name
Test status
Simulation time 6213755015 ps
CPU time 11.13 seconds
Started Jul 01 05:26:37 PM PDT 24
Finished Jul 01 05:26:49 PM PDT 24
Peak memory 232828 kb
Host smart-bf5e681c-403c-4284-8805-fc5f7cb9f1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415323322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1415323322
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3510927869
Short name T454
Test name
Test status
Simulation time 14163950682 ps
CPU time 40.88 seconds
Started Jul 01 05:26:37 PM PDT 24
Finished Jul 01 05:27:20 PM PDT 24
Peak memory 240644 kb
Host smart-54023ba4-7dbd-44ab-9230-a94fb8145e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510927869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3510927869
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1559847306
Short name T596
Test name
Test status
Simulation time 8215592346 ps
CPU time 6.84 seconds
Started Jul 01 05:26:40 PM PDT 24
Finished Jul 01 05:26:48 PM PDT 24
Peak memory 224600 kb
Host smart-99e057ff-68c0-4778-8662-7f02e25bd3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559847306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1559847306
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2996366754
Short name T259
Test name
Test status
Simulation time 4268530249 ps
CPU time 15.45 seconds
Started Jul 01 05:26:42 PM PDT 24
Finished Jul 01 05:27:00 PM PDT 24
Peak memory 238456 kb
Host smart-938ffff0-ca2e-45da-bd36-cfd4cac59311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996366754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2996366754
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3991142499
Short name T425
Test name
Test status
Simulation time 2038318447 ps
CPU time 6.16 seconds
Started Jul 01 05:26:46 PM PDT 24
Finished Jul 01 05:26:56 PM PDT 24
Peak memory 222604 kb
Host smart-6cb5d511-bdd7-4030-8a7f-8d05e427a243
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3991142499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3991142499
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1076456133
Short name T756
Test name
Test status
Simulation time 209777260 ps
CPU time 1.09 seconds
Started Jul 01 05:26:44 PM PDT 24
Finished Jul 01 05:26:48 PM PDT 24
Peak memory 215236 kb
Host smart-887fac51-b357-4c8b-8c3c-c19f6bb49906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076456133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1076456133
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.648426157
Short name T673
Test name
Test status
Simulation time 18102582352 ps
CPU time 7.49 seconds
Started Jul 01 05:26:38 PM PDT 24
Finished Jul 01 05:26:47 PM PDT 24
Peak memory 216384 kb
Host smart-2c9f2530-b79a-46f9-8c5e-c7890a27b100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648426157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.648426157
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2021406400
Short name T639
Test name
Test status
Simulation time 940526250 ps
CPU time 3.68 seconds
Started Jul 01 05:26:36 PM PDT 24
Finished Jul 01 05:26:41 PM PDT 24
Peak memory 216164 kb
Host smart-e15fa9bb-b183-47de-9730-13b91ceee062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021406400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2021406400
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1241391057
Short name T25
Test name
Test status
Simulation time 130462173 ps
CPU time 2.48 seconds
Started Jul 01 05:26:37 PM PDT 24
Finished Jul 01 05:26:41 PM PDT 24
Peak memory 208132 kb
Host smart-556827db-46d9-417a-9092-e3863de52bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241391057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1241391057
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3566283823
Short name T902
Test name
Test status
Simulation time 181007361 ps
CPU time 0.99 seconds
Started Jul 01 05:26:38 PM PDT 24
Finished Jul 01 05:26:41 PM PDT 24
Peak memory 207020 kb
Host smart-a34dbb39-b11a-4971-9bd2-56aa73a647cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566283823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3566283823
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3568666434
Short name T427
Test name
Test status
Simulation time 10835657284 ps
CPU time 21.6 seconds
Started Jul 01 05:26:43 PM PDT 24
Finished Jul 01 05:27:08 PM PDT 24
Peak memory 240868 kb
Host smart-1a4628b7-59ca-48ab-bb5f-89ee35c4a250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568666434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3568666434
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.482636522
Short name T1016
Test name
Test status
Simulation time 14021485 ps
CPU time 0.78 seconds
Started Jul 01 05:26:53 PM PDT 24
Finished Jul 01 05:26:55 PM PDT 24
Peak memory 205000 kb
Host smart-93a82938-cb23-4bde-99b7-b73118b6b122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482636522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.482636522
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2546897475
Short name T251
Test name
Test status
Simulation time 890977741 ps
CPU time 9.9 seconds
Started Jul 01 05:26:43 PM PDT 24
Finished Jul 01 05:26:57 PM PDT 24
Peak memory 224496 kb
Host smart-42cccd49-1cfd-4341-8bb9-8197f583ab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546897475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2546897475
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1810097695
Short name T651
Test name
Test status
Simulation time 122341782 ps
CPU time 0.85 seconds
Started Jul 01 05:26:44 PM PDT 24
Finished Jul 01 05:26:49 PM PDT 24
Peak memory 206720 kb
Host smart-ceef12f9-5a07-4290-81f9-0d3519696417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810097695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1810097695
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4063233563
Short name T581
Test name
Test status
Simulation time 11336315142 ps
CPU time 53.39 seconds
Started Jul 01 05:26:44 PM PDT 24
Finished Jul 01 05:27:41 PM PDT 24
Peak memory 235992 kb
Host smart-b2ddf20b-6799-48d2-9e2b-18c80cf147ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063233563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4063233563
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1726828101
Short name T75
Test name
Test status
Simulation time 66290734144 ps
CPU time 143.91 seconds
Started Jul 01 05:26:45 PM PDT 24
Finished Jul 01 05:29:13 PM PDT 24
Peak memory 257448 kb
Host smart-cf2146b5-ccf3-40ba-b955-411f56c777d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726828101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1726828101
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2906080965
Short name T409
Test name
Test status
Simulation time 2876611626 ps
CPU time 7.61 seconds
Started Jul 01 05:26:44 PM PDT 24
Finished Jul 01 05:26:56 PM PDT 24
Peak memory 235320 kb
Host smart-9eaec28e-141b-4dce-ba67-c867844f6be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906080965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2906080965
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.720853720
Short name T295
Test name
Test status
Simulation time 1339102173 ps
CPU time 9.3 seconds
Started Jul 01 05:26:46 PM PDT 24
Finished Jul 01 05:27:00 PM PDT 24
Peak memory 224468 kb
Host smart-b0e30ac0-045b-46cd-a63e-ac68385c2cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720853720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.720853720
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2623616347
Short name T405
Test name
Test status
Simulation time 8162668559 ps
CPU time 17.96 seconds
Started Jul 01 05:26:43 PM PDT 24
Finished Jul 01 05:27:05 PM PDT 24
Peak memory 236068 kb
Host smart-926d44a2-d844-49e0-a51c-c82a72ed843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623616347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2623616347
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1988009644
Short name T233
Test name
Test status
Simulation time 3333352504 ps
CPU time 20.57 seconds
Started Jul 01 05:26:44 PM PDT 24
Finished Jul 01 05:27:09 PM PDT 24
Peak memory 232852 kb
Host smart-2d11f004-3d35-4d88-8bdc-00daa357ba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988009644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1988009644
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.710756389
Short name T942
Test name
Test status
Simulation time 52974116 ps
CPU time 3.16 seconds
Started Jul 01 05:26:45 PM PDT 24
Finished Jul 01 05:26:52 PM PDT 24
Peak memory 232776 kb
Host smart-94ec494b-6889-4dd1-bbd9-0028af62ef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710756389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.710756389
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.943905564
Short name T565
Test name
Test status
Simulation time 10676337365 ps
CPU time 9.13 seconds
Started Jul 01 05:26:45 PM PDT 24
Finished Jul 01 05:26:58 PM PDT 24
Peak memory 224584 kb
Host smart-37fdb6cc-2462-4424-a772-42703ab29163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943905564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.943905564
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2492995100
Short name T576
Test name
Test status
Simulation time 15502023460 ps
CPU time 10.82 seconds
Started Jul 01 05:26:42 PM PDT 24
Finished Jul 01 05:26:56 PM PDT 24
Peak memory 240464 kb
Host smart-8b75a372-d602-49d7-8b6f-22de3f03993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492995100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2492995100
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2539813740
Short name T782
Test name
Test status
Simulation time 506674550 ps
CPU time 7.47 seconds
Started Jul 01 05:26:44 PM PDT 24
Finished Jul 01 05:26:55 PM PDT 24
Peak memory 223052 kb
Host smart-c17a98e5-2d75-4f67-be8e-394dbafb2571
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2539813740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2539813740
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4231613562
Short name T793
Test name
Test status
Simulation time 38829987685 ps
CPU time 48.22 seconds
Started Jul 01 05:26:52 PM PDT 24
Finished Jul 01 05:27:41 PM PDT 24
Peak memory 241040 kb
Host smart-90b51afb-3a0d-4e12-83c2-3fc12fd2aca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231613562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4231613562
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.818769387
Short name T683
Test name
Test status
Simulation time 8095185467 ps
CPU time 24.02 seconds
Started Jul 01 05:26:44 PM PDT 24
Finished Jul 01 05:27:12 PM PDT 24
Peak memory 220068 kb
Host smart-a7f6d289-87be-4a38-af71-dfae637ad068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818769387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.818769387
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1217812790
Short name T702
Test name
Test status
Simulation time 1782212562 ps
CPU time 9.82 seconds
Started Jul 01 05:26:45 PM PDT 24
Finished Jul 01 05:26:58 PM PDT 24
Peak memory 216172 kb
Host smart-8deac87f-1dcf-45d6-9130-339523368ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217812790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1217812790
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3029115328
Short name T658
Test name
Test status
Simulation time 12769799 ps
CPU time 0.71 seconds
Started Jul 01 05:26:45 PM PDT 24
Finished Jul 01 05:26:50 PM PDT 24
Peak memory 205672 kb
Host smart-4fc9f559-07aa-4b1f-abc7-a0baa0388363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029115328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3029115328
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.781929329
Short name T578
Test name
Test status
Simulation time 27629500 ps
CPU time 0.76 seconds
Started Jul 01 05:26:44 PM PDT 24
Finished Jul 01 05:26:48 PM PDT 24
Peak memory 206072 kb
Host smart-d74a533c-973f-47ab-838c-1781bb87dd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781929329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.781929329
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2984620762
Short name T969
Test name
Test status
Simulation time 113797294 ps
CPU time 2.86 seconds
Started Jul 01 05:26:45 PM PDT 24
Finished Jul 01 05:26:52 PM PDT 24
Peak memory 240940 kb
Host smart-fb9adda3-04c3-4c7b-b67e-10217a5702f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984620762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2984620762
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.912630727
Short name T507
Test name
Test status
Simulation time 21501733 ps
CPU time 0.76 seconds
Started Jul 01 05:26:51 PM PDT 24
Finished Jul 01 05:26:54 PM PDT 24
Peak memory 205600 kb
Host smart-d24cb206-f8c2-464a-814f-6a1f8b07bd59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912630727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.912630727
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3144773599
Short name T175
Test name
Test status
Simulation time 820808299 ps
CPU time 7.89 seconds
Started Jul 01 05:26:49 PM PDT 24
Finished Jul 01 05:27:00 PM PDT 24
Peak memory 232692 kb
Host smart-aeacf6ff-1351-4685-87f5-9fb82ce0481e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144773599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3144773599
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3102334321
Short name T320
Test name
Test status
Simulation time 62601097 ps
CPU time 0.76 seconds
Started Jul 01 05:26:50 PM PDT 24
Finished Jul 01 05:26:53 PM PDT 24
Peak memory 206620 kb
Host smart-d089a7d0-9e4f-4b06-8458-2a02683d3335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102334321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3102334321
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2803251539
Short name T721
Test name
Test status
Simulation time 28341421735 ps
CPU time 263.56 seconds
Started Jul 01 05:26:49 PM PDT 24
Finished Jul 01 05:31:15 PM PDT 24
Peak memory 264580 kb
Host smart-ff6f7179-8a7b-4e82-bbce-65b8468db92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803251539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2803251539
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.912680500
Short name T179
Test name
Test status
Simulation time 2801830638 ps
CPU time 50.01 seconds
Started Jul 01 05:26:49 PM PDT 24
Finished Jul 01 05:27:42 PM PDT 24
Peak memory 249204 kb
Host smart-fdc86125-a03f-46b6-966c-024f6bcc8857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912680500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.912680500
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2805211009
Short name T134
Test name
Test status
Simulation time 3177079332 ps
CPU time 22.99 seconds
Started Jul 01 05:26:50 PM PDT 24
Finished Jul 01 05:27:15 PM PDT 24
Peak memory 234904 kb
Host smart-ad909cac-682a-4870-a44a-c0f4230e2c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805211009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2805211009
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.755612285
Short name T445
Test name
Test status
Simulation time 17876262947 ps
CPU time 132.84 seconds
Started Jul 01 05:26:50 PM PDT 24
Finished Jul 01 05:29:05 PM PDT 24
Peak memory 249204 kb
Host smart-e756061b-5a9c-4b39-b527-cf17e9b1b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755612285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.755612285
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.488848157
Short name T419
Test name
Test status
Simulation time 31193203 ps
CPU time 2.66 seconds
Started Jul 01 05:26:57 PM PDT 24
Finished Jul 01 05:27:01 PM PDT 24
Peak memory 232412 kb
Host smart-a49b69c5-1606-4b88-9e3c-977bea55b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488848157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.488848157
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2885539138
Short name T263
Test name
Test status
Simulation time 1749700822 ps
CPU time 9.96 seconds
Started Jul 01 05:26:53 PM PDT 24
Finished Jul 01 05:27:04 PM PDT 24
Peak memory 229956 kb
Host smart-d974b19f-d8eb-4a57-a7dd-dc3a8615e790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885539138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2885539138
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3745684269
Short name T659
Test name
Test status
Simulation time 420559099 ps
CPU time 2.31 seconds
Started Jul 01 05:26:51 PM PDT 24
Finished Jul 01 05:26:55 PM PDT 24
Peak memory 224120 kb
Host smart-a25bc9ba-0e79-47d0-b84b-673cc8f2eb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745684269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3745684269
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1288149295
Short name T229
Test name
Test status
Simulation time 169395363 ps
CPU time 2.8 seconds
Started Jul 01 05:26:57 PM PDT 24
Finished Jul 01 05:27:02 PM PDT 24
Peak memory 232772 kb
Host smart-7b606efb-6a6a-43e0-904e-dff3918891c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288149295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1288149295
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2191044244
Short name T712
Test name
Test status
Simulation time 284091121 ps
CPU time 3.74 seconds
Started Jul 01 05:26:50 PM PDT 24
Finished Jul 01 05:26:56 PM PDT 24
Peak memory 222768 kb
Host smart-c212ed65-5261-4b97-9c5d-640f48be6fa9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2191044244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2191044244
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1265755719
Short name T341
Test name
Test status
Simulation time 1933979318 ps
CPU time 10.11 seconds
Started Jul 01 05:26:51 PM PDT 24
Finished Jul 01 05:27:03 PM PDT 24
Peak memory 219312 kb
Host smart-892cddaa-5e39-458e-b794-7e52ef9c2c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265755719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1265755719
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4098360957
Short name T706
Test name
Test status
Simulation time 32102045011 ps
CPU time 24.99 seconds
Started Jul 01 05:26:50 PM PDT 24
Finished Jul 01 05:27:17 PM PDT 24
Peak memory 216400 kb
Host smart-1a481941-2516-450a-b557-6d3f4f8cd45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098360957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4098360957
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.20509961
Short name T430
Test name
Test status
Simulation time 495277867 ps
CPU time 1.72 seconds
Started Jul 01 05:26:50 PM PDT 24
Finished Jul 01 05:26:54 PM PDT 24
Peak memory 216256 kb
Host smart-155c5fa3-d4b9-493a-834a-798fd0a90a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20509961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.20509961
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4111622833
Short name T414
Test name
Test status
Simulation time 79310200 ps
CPU time 0.84 seconds
Started Jul 01 05:26:53 PM PDT 24
Finished Jul 01 05:26:55 PM PDT 24
Peak memory 206004 kb
Host smart-e8274ef6-73f9-4a93-9545-4d08b6b80b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111622833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4111622833
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2627761076
Short name T487
Test name
Test status
Simulation time 39639418533 ps
CPU time 35.91 seconds
Started Jul 01 05:26:52 PM PDT 24
Finished Jul 01 05:27:29 PM PDT 24
Peak memory 232756 kb
Host smart-4f678a5b-b426-41d4-b737-6e0ef30051c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627761076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2627761076
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3514323865
Short name T867
Test name
Test status
Simulation time 31535150 ps
CPU time 0.75 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:12 PM PDT 24
Peak memory 205548 kb
Host smart-a143989d-cef3-4fa8-8094-15eaa08f8b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514323865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
514323865
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1624530252
Short name T963
Test name
Test status
Simulation time 41783738 ps
CPU time 2.41 seconds
Started Jul 01 05:24:09 PM PDT 24
Finished Jul 01 05:24:13 PM PDT 24
Peak memory 224552 kb
Host smart-c9d8fede-86de-43e7-929f-f4a9e2a2d0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624530252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1624530252
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3294811481
Short name T9
Test name
Test status
Simulation time 17653103 ps
CPU time 0.81 seconds
Started Jul 01 05:24:09 PM PDT 24
Finished Jul 01 05:24:12 PM PDT 24
Peak memory 206640 kb
Host smart-03a93f0f-18a8-4dc0-9c3a-5870f4640b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294811481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3294811481
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4058240735
Short name T197
Test name
Test status
Simulation time 3607585456 ps
CPU time 52.77 seconds
Started Jul 01 05:24:09 PM PDT 24
Finished Jul 01 05:25:04 PM PDT 24
Peak memory 256148 kb
Host smart-adebc2a6-9c86-4714-bd5b-13f8d68b3d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058240735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4058240735
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1873198685
Short name T41
Test name
Test status
Simulation time 12898724741 ps
CPU time 28.54 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:41 PM PDT 24
Peak memory 240372 kb
Host smart-218baf77-c946-43f9-90e8-aa2a36b6722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873198685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1873198685
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1904423998
Short name T300
Test name
Test status
Simulation time 7584280747 ps
CPU time 19.96 seconds
Started Jul 01 05:24:11 PM PDT 24
Finished Jul 01 05:24:33 PM PDT 24
Peak memory 217876 kb
Host smart-31ceb307-9be7-4ef3-a974-08cc290474e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904423998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1904423998
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2491681431
Short name T692
Test name
Test status
Simulation time 7651658795 ps
CPU time 28.21 seconds
Started Jul 01 05:24:11 PM PDT 24
Finished Jul 01 05:24:42 PM PDT 24
Peak memory 249212 kb
Host smart-4d313b18-9317-4167-9af7-6bce5f281e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491681431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2491681431
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1280701721
Short name T169
Test name
Test status
Simulation time 15949112501 ps
CPU time 90.94 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:25:43 PM PDT 24
Peak memory 252988 kb
Host smart-f23e7e6c-d1e7-4672-a14d-8f43dde23dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280701721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1280701721
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.91348742
Short name T654
Test name
Test status
Simulation time 3896328168 ps
CPU time 13.94 seconds
Started Jul 01 05:24:08 PM PDT 24
Finished Jul 01 05:24:22 PM PDT 24
Peak memory 232852 kb
Host smart-bd9e2d4d-9d17-43e6-b8a7-ba3aba8f27c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91348742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.91348742
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.978056680
Short name T641
Test name
Test status
Simulation time 1808218826 ps
CPU time 7.47 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:21 PM PDT 24
Peak memory 234436 kb
Host smart-db8bc03d-9830-4dcd-8abd-12c2e7bb6a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978056680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.978056680
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3254179526
Short name T628
Test name
Test status
Simulation time 622579949 ps
CPU time 3.3 seconds
Started Jul 01 05:24:11 PM PDT 24
Finished Jul 01 05:24:17 PM PDT 24
Peak memory 224476 kb
Host smart-72ecd498-36ed-43ce-94ee-4e72b8359d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254179526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3254179526
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2306918235
Short name T196
Test name
Test status
Simulation time 6693159297 ps
CPU time 9.78 seconds
Started Jul 01 05:24:24 PM PDT 24
Finished Jul 01 05:24:35 PM PDT 24
Peak memory 224600 kb
Host smart-a3080b7d-a331-4617-a684-edcec590e4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306918235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2306918235
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2034962607
Short name T476
Test name
Test status
Simulation time 316207691 ps
CPU time 4.26 seconds
Started Jul 01 05:24:24 PM PDT 24
Finished Jul 01 05:24:30 PM PDT 24
Peak memory 220544 kb
Host smart-532482d4-e566-4cd0-a92c-ddefd044186e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2034962607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2034962607
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3633063513
Short name T151
Test name
Test status
Simulation time 79635447612 ps
CPU time 246.71 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:28:19 PM PDT 24
Peak memory 257500 kb
Host smart-da6fb7d6-23aa-4331-bc11-27826e952a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633063513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3633063513
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2920357801
Short name T558
Test name
Test status
Simulation time 10885832055 ps
CPU time 31.05 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:44 PM PDT 24
Peak memory 216396 kb
Host smart-7d733804-6b59-474f-ba10-f6bfc9e237c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920357801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2920357801
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3131695976
Short name T696
Test name
Test status
Simulation time 32440855055 ps
CPU time 17.2 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:29 PM PDT 24
Peak memory 216408 kb
Host smart-03f6e56e-f22b-482e-94b7-f8367ab7ccc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131695976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3131695976
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1203546108
Short name T461
Test name
Test status
Simulation time 266633877 ps
CPU time 3.46 seconds
Started Jul 01 05:24:24 PM PDT 24
Finished Jul 01 05:24:30 PM PDT 24
Peak memory 216252 kb
Host smart-c9bb07e4-85c7-42c6-b32b-8ab60c553bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203546108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1203546108
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.563100568
Short name T910
Test name
Test status
Simulation time 17387452 ps
CPU time 0.72 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:13 PM PDT 24
Peak memory 205704 kb
Host smart-5b872d17-3b28-44f0-b74b-dca4daddccfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563100568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.563100568
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3492669420
Short name T624
Test name
Test status
Simulation time 182595252 ps
CPU time 2.65 seconds
Started Jul 01 05:24:09 PM PDT 24
Finished Jul 01 05:24:13 PM PDT 24
Peak memory 224504 kb
Host smart-ff07271f-da58-4620-98aa-4c2588822f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492669420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3492669420
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2945122492
Short name T317
Test name
Test status
Simulation time 14471811 ps
CPU time 0.75 seconds
Started Jul 01 05:27:03 PM PDT 24
Finished Jul 01 05:27:04 PM PDT 24
Peak memory 204988 kb
Host smart-39e9435a-eac1-4540-84a4-bb488a10b1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945122492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2945122492
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2793732604
Short name T775
Test name
Test status
Simulation time 228094333 ps
CPU time 4.38 seconds
Started Jul 01 05:26:56 PM PDT 24
Finished Jul 01 05:27:02 PM PDT 24
Peak memory 224456 kb
Host smart-6ec7bf1e-3404-4c71-b485-305877b6166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793732604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2793732604
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1402215992
Short name T559
Test name
Test status
Simulation time 66962183 ps
CPU time 0.77 seconds
Started Jul 01 05:26:50 PM PDT 24
Finished Jul 01 05:26:53 PM PDT 24
Peak memory 207020 kb
Host smart-aa26a484-ee15-437a-b6a8-80050464219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402215992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1402215992
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.183549558
Short name T214
Test name
Test status
Simulation time 86325245962 ps
CPU time 305.81 seconds
Started Jul 01 05:26:55 PM PDT 24
Finished Jul 01 05:32:03 PM PDT 24
Peak memory 263396 kb
Host smart-f8f1fc10-cb1b-437d-820f-e4509c1fbfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183549558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.183549558
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3010083454
Short name T311
Test name
Test status
Simulation time 14765806087 ps
CPU time 192.49 seconds
Started Jul 01 05:26:55 PM PDT 24
Finished Jul 01 05:30:10 PM PDT 24
Peak memory 266080 kb
Host smart-05313528-d005-4b43-8a78-bab214fb785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010083454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3010083454
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2270323810
Short name T813
Test name
Test status
Simulation time 35187879268 ps
CPU time 133.99 seconds
Started Jul 01 05:27:02 PM PDT 24
Finished Jul 01 05:29:17 PM PDT 24
Peak memory 250880 kb
Host smart-626838be-f279-4714-97a5-513dc2db88da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270323810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2270323810
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1233787914
Short name T687
Test name
Test status
Simulation time 39251191684 ps
CPU time 28.56 seconds
Started Jul 01 05:26:57 PM PDT 24
Finished Jul 01 05:27:27 PM PDT 24
Peak memory 232840 kb
Host smart-62e1a4a7-28f7-4d8d-b453-f532bede6a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233787914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1233787914
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1877673586
Short name T1003
Test name
Test status
Simulation time 244040730 ps
CPU time 5.62 seconds
Started Jul 01 05:26:56 PM PDT 24
Finished Jul 01 05:27:04 PM PDT 24
Peak memory 232652 kb
Host smart-d3ee01b4-5056-43ac-a33d-0deffd8af7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877673586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1877673586
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1667107093
Short name T490
Test name
Test status
Simulation time 1414401400 ps
CPU time 14.94 seconds
Started Jul 01 05:26:55 PM PDT 24
Finished Jul 01 05:27:12 PM PDT 24
Peak memory 240820 kb
Host smart-4e8cbfff-a594-421e-9525-1c5207e73251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667107093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1667107093
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1294539162
Short name T154
Test name
Test status
Simulation time 32717499876 ps
CPU time 18.73 seconds
Started Jul 01 05:26:54 PM PDT 24
Finished Jul 01 05:27:14 PM PDT 24
Peak memory 224692 kb
Host smart-9650ed60-c0b2-4a7b-bc9f-25bd90b479e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294539162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1294539162
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1691896657
Short name T540
Test name
Test status
Simulation time 13706391461 ps
CPU time 14.14 seconds
Started Jul 01 05:26:55 PM PDT 24
Finished Jul 01 05:27:11 PM PDT 24
Peak memory 232836 kb
Host smart-6b1c59ea-36fe-40cb-a724-fe44b1236ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691896657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1691896657
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3473427385
Short name T515
Test name
Test status
Simulation time 539300713 ps
CPU time 3.93 seconds
Started Jul 01 05:26:55 PM PDT 24
Finished Jul 01 05:27:01 PM PDT 24
Peak memory 223236 kb
Host smart-52367192-4d41-43d8-bdc3-5d8fc961b46d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3473427385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3473427385
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1436413070
Short name T270
Test name
Test status
Simulation time 81705096959 ps
CPU time 244.08 seconds
Started Jul 01 05:27:01 PM PDT 24
Finished Jul 01 05:31:07 PM PDT 24
Peak memory 257528 kb
Host smart-3bfb9262-2ab1-45e1-a0ea-c8698222567d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436413070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1436413070
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3704034899
Short name T310
Test name
Test status
Simulation time 655096602 ps
CPU time 10.31 seconds
Started Jul 01 05:26:56 PM PDT 24
Finished Jul 01 05:27:08 PM PDT 24
Peak memory 216360 kb
Host smart-544cf5b3-ea74-4158-b5f7-953ee5f868eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704034899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3704034899
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.205777482
Short name T422
Test name
Test status
Simulation time 10874665498 ps
CPU time 15.94 seconds
Started Jul 01 05:26:57 PM PDT 24
Finished Jul 01 05:27:15 PM PDT 24
Peak memory 216396 kb
Host smart-529914ab-18f6-44ac-8e95-b06dcbf84409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205777482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.205777482
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2573598685
Short name T880
Test name
Test status
Simulation time 18852583 ps
CPU time 0.71 seconds
Started Jul 01 05:26:54 PM PDT 24
Finished Jul 01 05:26:56 PM PDT 24
Peak memory 205708 kb
Host smart-4ae084b1-641c-43b1-a1c0-9b46ba5aca38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573598685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2573598685
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3553800992
Short name T749
Test name
Test status
Simulation time 194250216 ps
CPU time 0.85 seconds
Started Jul 01 05:26:55 PM PDT 24
Finished Jul 01 05:26:58 PM PDT 24
Peak memory 206000 kb
Host smart-2ce24f54-4bbd-4964-8041-4af35c1808b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553800992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3553800992
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3816002445
Short name T527
Test name
Test status
Simulation time 2768701236 ps
CPU time 11.04 seconds
Started Jul 01 05:26:55 PM PDT 24
Finished Jul 01 05:27:08 PM PDT 24
Peak memory 239928 kb
Host smart-a4f342e9-858a-40e4-81d1-13375552daa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816002445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3816002445
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.873085371
Short name T773
Test name
Test status
Simulation time 78967023 ps
CPU time 0.75 seconds
Started Jul 01 05:27:10 PM PDT 24
Finished Jul 01 05:27:12 PM PDT 24
Peak memory 204996 kb
Host smart-f02049fb-a5b8-49bc-9e10-12593239da02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873085371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.873085371
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.4186371005
Short name T153
Test name
Test status
Simulation time 4027855526 ps
CPU time 11.17 seconds
Started Jul 01 05:27:04 PM PDT 24
Finished Jul 01 05:27:16 PM PDT 24
Peak memory 224568 kb
Host smart-dfe71100-a4df-41d8-8657-184bd6711e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186371005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4186371005
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3498195424
Short name T473
Test name
Test status
Simulation time 20683309 ps
CPU time 0.87 seconds
Started Jul 01 05:27:02 PM PDT 24
Finished Jul 01 05:27:04 PM PDT 24
Peak memory 206600 kb
Host smart-de0d73f8-36a9-4545-b151-8fae8786191b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498195424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3498195424
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3712347578
Short name T76
Test name
Test status
Simulation time 4322657928 ps
CPU time 52.18 seconds
Started Jul 01 05:26:59 PM PDT 24
Finished Jul 01 05:27:52 PM PDT 24
Peak memory 263468 kb
Host smart-6b2b88e2-2ab1-4323-8fb7-f64dd24d2f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712347578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3712347578
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4138276995
Short name T666
Test name
Test status
Simulation time 24177526067 ps
CPU time 29.79 seconds
Started Jul 01 05:27:01 PM PDT 24
Finished Jul 01 05:27:32 PM PDT 24
Peak memory 217848 kb
Host smart-dffc8d06-75c8-436f-837e-16fc6504da1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138276995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4138276995
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1958592112
Short name T909
Test name
Test status
Simulation time 7854715816 ps
CPU time 33.03 seconds
Started Jul 01 05:27:06 PM PDT 24
Finished Jul 01 05:27:40 PM PDT 24
Peak memory 249212 kb
Host smart-ae4bb2d7-c921-40ed-bbb2-37f9e8c42f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958592112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1958592112
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1034439519
Short name T47
Test name
Test status
Simulation time 79561655096 ps
CPU time 124.47 seconds
Started Jul 01 05:27:01 PM PDT 24
Finished Jul 01 05:29:07 PM PDT 24
Peak memory 249312 kb
Host smart-18df6c38-5dd0-4177-a6cd-9508afdafb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034439519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1034439519
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1255954818
Short name T732
Test name
Test status
Simulation time 3157900368 ps
CPU time 5.77 seconds
Started Jul 01 05:27:02 PM PDT 24
Finished Jul 01 05:27:09 PM PDT 24
Peak memory 232860 kb
Host smart-97b93e9f-807a-46e4-b700-e656e013c78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255954818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1255954818
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4206291809
Short name T941
Test name
Test status
Simulation time 12836081546 ps
CPU time 29.16 seconds
Started Jul 01 05:27:02 PM PDT 24
Finished Jul 01 05:27:32 PM PDT 24
Peak memory 232860 kb
Host smart-5c96f0ee-a01f-4a33-9614-24b5208fb1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206291809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4206291809
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3353877424
Short name T691
Test name
Test status
Simulation time 9443981537 ps
CPU time 28.47 seconds
Started Jul 01 05:27:03 PM PDT 24
Finished Jul 01 05:27:33 PM PDT 24
Peak memory 232904 kb
Host smart-5009b561-3a3a-4b6c-b351-a575f7896c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353877424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3353877424
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2258588189
Short name T218
Test name
Test status
Simulation time 429124235 ps
CPU time 2.41 seconds
Started Jul 01 05:27:01 PM PDT 24
Finished Jul 01 05:27:04 PM PDT 24
Peak memory 224452 kb
Host smart-0d75eb87-0b61-4f76-a121-977b166ad420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258588189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2258588189
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1636359032
Short name T914
Test name
Test status
Simulation time 1015302189 ps
CPU time 8.82 seconds
Started Jul 01 05:27:02 PM PDT 24
Finished Jul 01 05:27:11 PM PDT 24
Peak memory 222148 kb
Host smart-5a4184a2-7e54-4b24-8faf-d99c4a6f82f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1636359032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1636359032
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1759995156
Short name T893
Test name
Test status
Simulation time 60563858717 ps
CPU time 485.81 seconds
Started Jul 01 05:27:07 PM PDT 24
Finished Jul 01 05:35:14 PM PDT 24
Peak memory 257084 kb
Host smart-c9a13700-4d50-456c-b89c-9251dd52b03b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759995156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1759995156
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2565799771
Short name T723
Test name
Test status
Simulation time 1529977478 ps
CPU time 8.39 seconds
Started Jul 01 05:27:01 PM PDT 24
Finished Jul 01 05:27:11 PM PDT 24
Peak memory 216216 kb
Host smart-89f932b7-bd89-4424-8251-bdafaa6340ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565799771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2565799771
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1380075136
Short name T434
Test name
Test status
Simulation time 9720195192 ps
CPU time 3.61 seconds
Started Jul 01 05:27:02 PM PDT 24
Finished Jul 01 05:27:07 PM PDT 24
Peak memory 217260 kb
Host smart-f51afa0e-9771-4b9f-927c-92b7901f9dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380075136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1380075136
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.916097374
Short name T780
Test name
Test status
Simulation time 54067398 ps
CPU time 1.4 seconds
Started Jul 01 05:27:04 PM PDT 24
Finished Jul 01 05:27:06 PM PDT 24
Peak memory 207956 kb
Host smart-da999429-572a-423a-8526-eb9b031b58e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916097374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.916097374
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3415467911
Short name T689
Test name
Test status
Simulation time 32056943 ps
CPU time 0.85 seconds
Started Jul 01 05:27:00 PM PDT 24
Finished Jul 01 05:27:02 PM PDT 24
Peak memory 206060 kb
Host smart-93cf9138-ae08-4a3d-9234-322a3efcbdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415467911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3415467911
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1865096260
Short name T221
Test name
Test status
Simulation time 14045128440 ps
CPU time 32.82 seconds
Started Jul 01 05:27:02 PM PDT 24
Finished Jul 01 05:27:36 PM PDT 24
Peak memory 248528 kb
Host smart-7a76fa6f-7daa-484e-b21e-76a99d37a8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865096260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1865096260
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2354240769
Short name T330
Test name
Test status
Simulation time 16291679 ps
CPU time 0.83 seconds
Started Jul 01 05:27:08 PM PDT 24
Finished Jul 01 05:27:11 PM PDT 24
Peak memory 205512 kb
Host smart-7f364b20-b8a2-4b5c-8a8e-dafc40c8c0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354240769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2354240769
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.250984824
Short name T111
Test name
Test status
Simulation time 1033626077 ps
CPU time 5.5 seconds
Started Jul 01 05:27:05 PM PDT 24
Finished Jul 01 05:27:11 PM PDT 24
Peak memory 232724 kb
Host smart-3225b063-7a15-412a-8be6-2c053e758c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250984824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.250984824
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1962191417
Short name T917
Test name
Test status
Simulation time 19872339 ps
CPU time 0.78 seconds
Started Jul 01 05:27:08 PM PDT 24
Finished Jul 01 05:27:11 PM PDT 24
Peak memory 206628 kb
Host smart-155444f2-0bae-4a44-976b-ff7dda5e20b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962191417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1962191417
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1031225520
Short name T410
Test name
Test status
Simulation time 10178233166 ps
CPU time 30.62 seconds
Started Jul 01 05:27:06 PM PDT 24
Finished Jul 01 05:27:38 PM PDT 24
Peak memory 250332 kb
Host smart-6d1a9aef-8205-4f35-b71e-2873026b2760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031225520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1031225520
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4267767242
Short name T790
Test name
Test status
Simulation time 46565851890 ps
CPU time 443.46 seconds
Started Jul 01 05:27:10 PM PDT 24
Finished Jul 01 05:34:35 PM PDT 24
Peak memory 257596 kb
Host smart-fd4f60ab-7421-4c2b-b242-7e455b475079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267767242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4267767242
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2496282413
Short name T794
Test name
Test status
Simulation time 5579204475 ps
CPU time 68.86 seconds
Started Jul 01 05:27:10 PM PDT 24
Finished Jul 01 05:28:20 PM PDT 24
Peak memory 252880 kb
Host smart-19b30f40-4806-434e-bab3-d71a206d7e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496282413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2496282413
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3288335956
Short name T665
Test name
Test status
Simulation time 49951487565 ps
CPU time 56.47 seconds
Started Jul 01 05:27:08 PM PDT 24
Finished Jul 01 05:28:06 PM PDT 24
Peak memory 255596 kb
Host smart-5aba5331-d9bc-41ec-94ee-19dd07ab2eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288335956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3288335956
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3947828000
Short name T546
Test name
Test status
Simulation time 6389294814 ps
CPU time 21.28 seconds
Started Jul 01 05:27:10 PM PDT 24
Finished Jul 01 05:27:33 PM PDT 24
Peak memory 224740 kb
Host smart-c8fc5c18-2781-4afd-b569-bd081c35523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947828000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3947828000
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1178827743
Short name T495
Test name
Test status
Simulation time 949394213 ps
CPU time 6 seconds
Started Jul 01 05:27:08 PM PDT 24
Finished Jul 01 05:27:16 PM PDT 24
Peak memory 224568 kb
Host smart-6b0970fd-550b-441e-95a2-159fe4b822ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178827743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1178827743
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2723948901
Short name T748
Test name
Test status
Simulation time 17363764348 ps
CPU time 14.08 seconds
Started Jul 01 05:27:07 PM PDT 24
Finished Jul 01 05:27:22 PM PDT 24
Peak memory 232924 kb
Host smart-2ed21193-c524-4e3b-bf10-8a53f66e9c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723948901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2723948901
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.702155092
Short name T622
Test name
Test status
Simulation time 5904477821 ps
CPU time 10.68 seconds
Started Jul 01 05:27:07 PM PDT 24
Finished Jul 01 05:27:19 PM PDT 24
Peak memory 232784 kb
Host smart-935e4ffd-b726-4245-8cde-8b6b49669ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702155092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.702155092
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1950867930
Short name T676
Test name
Test status
Simulation time 365094782 ps
CPU time 4.05 seconds
Started Jul 01 05:27:06 PM PDT 24
Finished Jul 01 05:27:11 PM PDT 24
Peak memory 220320 kb
Host smart-8974ad51-f34c-44bf-a6d4-1abd78c6c42b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1950867930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1950867930
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.475730190
Short name T272
Test name
Test status
Simulation time 274991159023 ps
CPU time 621.97 seconds
Started Jul 01 05:27:06 PM PDT 24
Finished Jul 01 05:37:29 PM PDT 24
Peak memory 265556 kb
Host smart-64200bd4-77de-4b5d-8387-106d875e1dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475730190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.475730190
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1310261860
Short name T393
Test name
Test status
Simulation time 4072359428 ps
CPU time 17.67 seconds
Started Jul 01 05:27:08 PM PDT 24
Finished Jul 01 05:27:27 PM PDT 24
Peak memory 216656 kb
Host smart-fe6426e2-dee5-475e-9427-95c4621de43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310261860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1310261860
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1754319932
Short name T755
Test name
Test status
Simulation time 1128781897 ps
CPU time 6.8 seconds
Started Jul 01 05:27:10 PM PDT 24
Finished Jul 01 05:27:18 PM PDT 24
Peak memory 216268 kb
Host smart-3dfc4536-6a0e-48cc-921e-8554a2241866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754319932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1754319932
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.42546412
Short name T349
Test name
Test status
Simulation time 127434304 ps
CPU time 2.04 seconds
Started Jul 01 05:27:08 PM PDT 24
Finished Jul 01 05:27:12 PM PDT 24
Peak memory 216320 kb
Host smart-77036535-715f-4c4b-81c4-2284342f0216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42546412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.42546412
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3991679160
Short name T557
Test name
Test status
Simulation time 21017067 ps
CPU time 0.79 seconds
Started Jul 01 05:27:10 PM PDT 24
Finished Jul 01 05:27:12 PM PDT 24
Peak memory 206000 kb
Host smart-dedb2740-8b83-4bc8-a943-94e42114b808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991679160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3991679160
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3496340370
Short name T423
Test name
Test status
Simulation time 3224911236 ps
CPU time 4.91 seconds
Started Jul 01 05:27:08 PM PDT 24
Finished Jul 01 05:27:14 PM PDT 24
Peak memory 224624 kb
Host smart-e783f962-d19f-4b14-8958-a3af5ac937ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496340370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3496340370
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1560832955
Short name T906
Test name
Test status
Simulation time 43909823 ps
CPU time 0.74 seconds
Started Jul 01 05:27:12 PM PDT 24
Finished Jul 01 05:27:16 PM PDT 24
Peak memory 205088 kb
Host smart-8aff2bf6-03b6-43d8-9027-bec9b487ccb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560832955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1560832955
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2834575970
Short name T820
Test name
Test status
Simulation time 119473672 ps
CPU time 4.59 seconds
Started Jul 01 05:27:13 PM PDT 24
Finished Jul 01 05:27:22 PM PDT 24
Peak memory 232652 kb
Host smart-3ac6a641-9b0b-4938-9d8e-3038620e5cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834575970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2834575970
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3368957397
Short name T889
Test name
Test status
Simulation time 46291220 ps
CPU time 0.79 seconds
Started Jul 01 05:27:12 PM PDT 24
Finished Jul 01 05:27:15 PM PDT 24
Peak memory 206708 kb
Host smart-af27df0e-4aff-4fcb-94e0-f2aac413e38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368957397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3368957397
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2853841412
Short name T948
Test name
Test status
Simulation time 65260517080 ps
CPU time 138.44 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:29:36 PM PDT 24
Peak memory 249676 kb
Host smart-febd8e6a-38c4-45bb-89d8-6f60fd137cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853841412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2853841412
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1265383605
Short name T916
Test name
Test status
Simulation time 143681475974 ps
CPU time 254 seconds
Started Jul 01 05:27:17 PM PDT 24
Finished Jul 01 05:31:34 PM PDT 24
Peak memory 251484 kb
Host smart-5ffa00be-4b2d-4e26-bf04-044845046a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265383605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1265383605
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3532622705
Short name T267
Test name
Test status
Simulation time 18767483745 ps
CPU time 125.89 seconds
Started Jul 01 05:27:13 PM PDT 24
Finished Jul 01 05:29:21 PM PDT 24
Peak memory 273276 kb
Host smart-67b5a0e2-2827-4e9a-a1a3-9bf5c8006bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532622705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3532622705
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2918250361
Short name T792
Test name
Test status
Simulation time 331582702 ps
CPU time 6.54 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:27:25 PM PDT 24
Peak memory 224560 kb
Host smart-3d738040-b1d8-41a5-b37b-bca67f56e227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918250361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2918250361
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.402633883
Short name T763
Test name
Test status
Simulation time 5834973286 ps
CPU time 27.96 seconds
Started Jul 01 05:27:13 PM PDT 24
Finished Jul 01 05:27:45 PM PDT 24
Peak memory 249216 kb
Host smart-81e6ab80-c939-43a3-9870-b0b5381520b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402633883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.402633883
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2595979289
Short name T433
Test name
Test status
Simulation time 3699531396 ps
CPU time 10.33 seconds
Started Jul 01 05:27:17 PM PDT 24
Finished Jul 01 05:27:31 PM PDT 24
Peak memory 224636 kb
Host smart-902e5959-c675-41ff-9770-03d72300e3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595979289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2595979289
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3392636563
Short name T964
Test name
Test status
Simulation time 9801533403 ps
CPU time 33.94 seconds
Started Jul 01 05:27:13 PM PDT 24
Finished Jul 01 05:27:51 PM PDT 24
Peak memory 224656 kb
Host smart-f431c5bf-237b-4497-8af6-c11e51186965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392636563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3392636563
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2291070644
Short name T411
Test name
Test status
Simulation time 125280110 ps
CPU time 2.47 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:27:20 PM PDT 24
Peak memory 232320 kb
Host smart-0ab5f1af-631d-4553-acba-9055a9f39b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291070644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2291070644
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3383738914
Short name T670
Test name
Test status
Simulation time 18939821536 ps
CPU time 12.3 seconds
Started Jul 01 05:27:09 PM PDT 24
Finished Jul 01 05:27:22 PM PDT 24
Peak memory 224616 kb
Host smart-6af721b7-4294-4a2b-bda0-cefa26908b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383738914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3383738914
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1391011131
Short name T613
Test name
Test status
Simulation time 1196340419 ps
CPU time 8.15 seconds
Started Jul 01 05:27:13 PM PDT 24
Finished Jul 01 05:27:24 PM PDT 24
Peak memory 219392 kb
Host smart-6cb1f052-5f83-4376-92eb-35494dea5b85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1391011131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1391011131
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3270177579
Short name T374
Test name
Test status
Simulation time 13280683057 ps
CPU time 53.97 seconds
Started Jul 01 05:27:15 PM PDT 24
Finished Jul 01 05:28:13 PM PDT 24
Peak memory 241048 kb
Host smart-1b870733-e9e9-432c-94a7-7e3cada1b564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270177579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3270177579
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3405810185
Short name T439
Test name
Test status
Simulation time 1244275645 ps
CPU time 2.93 seconds
Started Jul 01 05:27:06 PM PDT 24
Finished Jul 01 05:27:10 PM PDT 24
Peak memory 217364 kb
Host smart-b3ee5cbe-62d9-458f-951a-1c7451a67158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405810185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3405810185
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.828594843
Short name T679
Test name
Test status
Simulation time 3497172196 ps
CPU time 5.72 seconds
Started Jul 01 05:27:12 PM PDT 24
Finished Jul 01 05:27:19 PM PDT 24
Peak memory 216460 kb
Host smart-ed27d2e8-3b0d-415c-9e87-1fa38bb7d38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828594843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.828594843
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.849138894
Short name T677
Test name
Test status
Simulation time 99656914 ps
CPU time 2.48 seconds
Started Jul 01 05:27:12 PM PDT 24
Finished Jul 01 05:27:16 PM PDT 24
Peak memory 216344 kb
Host smart-8fbf1a84-8201-4dd0-b868-d170b5fed4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849138894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.849138894
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4093046271
Short name T327
Test name
Test status
Simulation time 38414818 ps
CPU time 0.89 seconds
Started Jul 01 05:27:08 PM PDT 24
Finished Jul 01 05:27:10 PM PDT 24
Peak memory 206268 kb
Host smart-dfcf58df-741e-4bac-871d-166621d08802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093046271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4093046271
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3354259346
Short name T876
Test name
Test status
Simulation time 5344237525 ps
CPU time 9.61 seconds
Started Jul 01 05:27:13 PM PDT 24
Finished Jul 01 05:27:27 PM PDT 24
Peak memory 232840 kb
Host smart-20bf8845-5720-4cb8-929c-a45d0c779434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354259346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3354259346
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2666969814
Short name T368
Test name
Test status
Simulation time 24688756 ps
CPU time 0.73 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:25 PM PDT 24
Peak memory 205856 kb
Host smart-c79bb748-20c0-47af-8e52-c948650f9f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666969814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2666969814
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3189482061
Short name T615
Test name
Test status
Simulation time 393601000 ps
CPU time 3.97 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:27:23 PM PDT 24
Peak memory 232688 kb
Host smart-cbf077df-8bd1-4331-8443-be1c6d89337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189482061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3189482061
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2852788165
Short name T460
Test name
Test status
Simulation time 15837875 ps
CPU time 0.79 seconds
Started Jul 01 05:27:17 PM PDT 24
Finished Jul 01 05:27:20 PM PDT 24
Peak memory 206616 kb
Host smart-c8dfc508-844d-4c93-90fd-7eaa067438a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852788165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2852788165
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.4168968579
Short name T282
Test name
Test status
Simulation time 23062099193 ps
CPU time 80.45 seconds
Started Jul 01 05:27:12 PM PDT 24
Finished Jul 01 05:28:36 PM PDT 24
Peak memory 255872 kb
Host smart-9a19d9d7-39a5-4693-a442-2171e55adfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168968579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4168968579
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2702513277
Short name T983
Test name
Test status
Simulation time 1006108909 ps
CPU time 5.01 seconds
Started Jul 01 05:27:13 PM PDT 24
Finished Jul 01 05:27:20 PM PDT 24
Peak memory 217420 kb
Host smart-bbd17959-5dcc-4dec-a71e-1c481c5c99d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702513277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2702513277
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1033153031
Short name T498
Test name
Test status
Simulation time 5457679437 ps
CPU time 114.45 seconds
Started Jul 01 05:27:13 PM PDT 24
Finished Jul 01 05:29:11 PM PDT 24
Peak memory 260052 kb
Host smart-a9d501ff-b7c9-41a0-a04a-d0746de7d9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033153031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1033153031
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3064967492
Short name T135
Test name
Test status
Simulation time 1317247110 ps
CPU time 8.17 seconds
Started Jul 01 05:27:12 PM PDT 24
Finished Jul 01 05:27:23 PM PDT 24
Peak memory 240880 kb
Host smart-18f85f16-ce88-4192-a41f-f97587d4268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064967492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3064967492
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3752470863
Short name T650
Test name
Test status
Simulation time 2437658173 ps
CPU time 56.19 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:28:14 PM PDT 24
Peak memory 249228 kb
Host smart-94116f43-8b8e-4be9-ac67-edf8b7bdb42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752470863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3752470863
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3955003930
Short name T205
Test name
Test status
Simulation time 5542308599 ps
CPU time 11.9 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:27:30 PM PDT 24
Peak memory 232936 kb
Host smart-1eede8aa-216d-467b-956d-2192cb41eedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955003930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3955003930
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1425216523
Short name T957
Test name
Test status
Simulation time 3129139246 ps
CPU time 43.41 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:28:02 PM PDT 24
Peak memory 238108 kb
Host smart-9d72660f-917f-4d30-8988-9a0c60325a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425216523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1425216523
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.845521193
Short name T238
Test name
Test status
Simulation time 93881294 ps
CPU time 2.78 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:27:21 PM PDT 24
Peak memory 232772 kb
Host smart-e26921e5-c10d-4cdd-8019-abad8cb2f48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845521193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.845521193
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3153639151
Short name T760
Test name
Test status
Simulation time 251556790 ps
CPU time 4.84 seconds
Started Jul 01 05:27:13 PM PDT 24
Finished Jul 01 05:27:20 PM PDT 24
Peak memory 232668 kb
Host smart-8cabe76b-4ba4-448d-9074-76adf0f7892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153639151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3153639151
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2961416007
Short name T690
Test name
Test status
Simulation time 1420019564 ps
CPU time 9.41 seconds
Started Jul 01 05:27:17 PM PDT 24
Finished Jul 01 05:27:30 PM PDT 24
Peak memory 220092 kb
Host smart-ed054ff5-f22a-4eae-bf09-6d219cd575c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2961416007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2961416007
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4174079620
Short name T671
Test name
Test status
Simulation time 113074011 ps
CPU time 1.01 seconds
Started Jul 01 05:27:20 PM PDT 24
Finished Jul 01 05:27:23 PM PDT 24
Peak memory 207072 kb
Host smart-f7777d35-3e64-4473-9bbe-a1eac6022c00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174079620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4174079620
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1975157144
Short name T518
Test name
Test status
Simulation time 12212271419 ps
CPU time 16.37 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:27:34 PM PDT 24
Peak memory 216556 kb
Host smart-193bb6a2-d00f-49d3-ac76-b40d621e4ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975157144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1975157144
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2141088654
Short name T302
Test name
Test status
Simulation time 1018597060 ps
CPU time 3.3 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:27:21 PM PDT 24
Peak memory 216284 kb
Host smart-32c15749-9d66-4ee9-b068-871478d728ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141088654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2141088654
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1133532957
Short name T798
Test name
Test status
Simulation time 2189723438 ps
CPU time 3.12 seconds
Started Jul 01 05:27:14 PM PDT 24
Finished Jul 01 05:27:21 PM PDT 24
Peak memory 216336 kb
Host smart-81ab5cee-77f4-4d97-8fd9-f14bacefe8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133532957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1133532957
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1635227050
Short name T1014
Test name
Test status
Simulation time 25593556 ps
CPU time 0.7 seconds
Started Jul 01 05:27:13 PM PDT 24
Finished Jul 01 05:27:17 PM PDT 24
Peak memory 205748 kb
Host smart-da837ff7-ba87-4388-b411-7270e543ed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635227050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1635227050
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1843258127
Short name T479
Test name
Test status
Simulation time 492507204 ps
CPU time 2.93 seconds
Started Jul 01 05:27:12 PM PDT 24
Finished Jul 01 05:27:18 PM PDT 24
Peak memory 224484 kb
Host smart-18b9e140-61ac-455e-abaa-5099f8ac60c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843258127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1843258127
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.707811515
Short name T450
Test name
Test status
Simulation time 13200825 ps
CPU time 0.7 seconds
Started Jul 01 05:27:20 PM PDT 24
Finished Jul 01 05:27:23 PM PDT 24
Peak memory 204996 kb
Host smart-9cc6dc47-be5a-4d85-80b1-4e439b56c8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707811515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.707811515
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.373579541
Short name T701
Test name
Test status
Simulation time 888805707 ps
CPU time 11.72 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:35 PM PDT 24
Peak memory 232688 kb
Host smart-262ab047-6870-479d-a245-3ae06d4d84fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373579541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.373579541
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2147680305
Short name T528
Test name
Test status
Simulation time 23816057 ps
CPU time 0.79 seconds
Started Jul 01 05:27:22 PM PDT 24
Finished Jul 01 05:27:26 PM PDT 24
Peak memory 206980 kb
Host smart-dae52392-029c-45f3-87a8-0a21f0210a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147680305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2147680305
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4221025077
Short name T204
Test name
Test status
Simulation time 263862075661 ps
CPU time 319.95 seconds
Started Jul 01 05:27:20 PM PDT 24
Finished Jul 01 05:32:43 PM PDT 24
Peak memory 254788 kb
Host smart-241d5988-2954-439d-bcb3-b8f171e8f591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221025077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4221025077
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2047234914
Short name T932
Test name
Test status
Simulation time 37143350503 ps
CPU time 383.17 seconds
Started Jul 01 05:27:20 PM PDT 24
Finished Jul 01 05:33:45 PM PDT 24
Peak memory 262552 kb
Host smart-14eb19e5-6b23-4082-81ab-e06cdaf0d871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047234914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2047234914
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4261468051
Short name T844
Test name
Test status
Simulation time 152246952 ps
CPU time 5.9 seconds
Started Jul 01 05:27:22 PM PDT 24
Finished Jul 01 05:27:31 PM PDT 24
Peak memory 224556 kb
Host smart-1a2c5114-ca34-41cc-9764-bef8c2f7b898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261468051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4261468051
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2555177792
Short name T827
Test name
Test status
Simulation time 80060681 ps
CPU time 3.84 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:28 PM PDT 24
Peak memory 224508 kb
Host smart-328f0882-d1dd-4b08-a465-7635c641b959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555177792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2555177792
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2075812051
Short name T412
Test name
Test status
Simulation time 2067562832 ps
CPU time 7.3 seconds
Started Jul 01 05:27:20 PM PDT 24
Finished Jul 01 05:27:30 PM PDT 24
Peak memory 232728 kb
Host smart-706a6d8d-62bf-4006-ad42-1577117cc46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075812051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2075812051
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1152838814
Short name T759
Test name
Test status
Simulation time 4301787123 ps
CPU time 6.71 seconds
Started Jul 01 05:27:22 PM PDT 24
Finished Jul 01 05:27:32 PM PDT 24
Peak memory 224568 kb
Host smart-5e9d9f44-6b8a-490e-98b2-bf18f75b3930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152838814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1152838814
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.320784097
Short name T249
Test name
Test status
Simulation time 6551797504 ps
CPU time 17.96 seconds
Started Jul 01 05:27:20 PM PDT 24
Finished Jul 01 05:27:40 PM PDT 24
Peak memory 232864 kb
Host smart-421b389b-7440-4271-afcd-3d1f77e0be21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320784097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.320784097
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.560372125
Short name T740
Test name
Test status
Simulation time 4440548162 ps
CPU time 14.85 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:38 PM PDT 24
Peak memory 219384 kb
Host smart-7394bacf-f438-4316-98e8-244263b4e3fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=560372125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.560372125
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2514592988
Short name T703
Test name
Test status
Simulation time 4433755754 ps
CPU time 59.15 seconds
Started Jul 01 05:27:20 PM PDT 24
Finished Jul 01 05:28:22 PM PDT 24
Peak memory 241144 kb
Host smart-c37437b6-9eaf-4ac6-818a-c7762de49c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514592988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2514592988
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2230992453
Short name T772
Test name
Test status
Simulation time 1432285357 ps
CPU time 6.5 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:30 PM PDT 24
Peak memory 219352 kb
Host smart-98ee72a6-bc0c-400a-81c2-c6cb6c06c58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230992453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2230992453
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.4143930708
Short name T870
Test name
Test status
Simulation time 6351325316 ps
CPU time 5.58 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:29 PM PDT 24
Peak memory 217696 kb
Host smart-15c3baaa-4c9d-407a-bf3d-89d125897fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143930708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.4143930708
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1510289524
Short name T705
Test name
Test status
Simulation time 197683980 ps
CPU time 1.31 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:25 PM PDT 24
Peak memory 216264 kb
Host smart-773779be-7ef6-4401-a0ab-c6622f11c411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510289524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1510289524
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.791568414
Short name T605
Test name
Test status
Simulation time 343255647 ps
CPU time 0.85 seconds
Started Jul 01 05:27:20 PM PDT 24
Finished Jul 01 05:27:24 PM PDT 24
Peak memory 206008 kb
Host smart-5823987d-ec38-4af5-8e15-b241da4855a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791568414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.791568414
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.646716702
Short name T157
Test name
Test status
Simulation time 4715237431 ps
CPU time 11.05 seconds
Started Jul 01 05:27:23 PM PDT 24
Finished Jul 01 05:27:37 PM PDT 24
Peak memory 228864 kb
Host smart-ebc640cc-55a5-44ef-91bd-28f7f2c85fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646716702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.646716702
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1367438296
Short name T604
Test name
Test status
Simulation time 30736656 ps
CPU time 0.7 seconds
Started Jul 01 05:27:30 PM PDT 24
Finished Jul 01 05:27:33 PM PDT 24
Peak memory 205072 kb
Host smart-8c5af4e9-e750-4e07-9192-33543ea72225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367438296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1367438296
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3204075318
Short name T997
Test name
Test status
Simulation time 33345475 ps
CPU time 2.58 seconds
Started Jul 01 05:27:30 PM PDT 24
Finished Jul 01 05:27:34 PM PDT 24
Peak memory 232708 kb
Host smart-b4f8bdb1-f738-4bdb-93d0-3b3edc7c9dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204075318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3204075318
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.323027116
Short name T325
Test name
Test status
Simulation time 15331297 ps
CPU time 0.75 seconds
Started Jul 01 05:27:20 PM PDT 24
Finished Jul 01 05:27:24 PM PDT 24
Peak memory 205672 kb
Host smart-c4b9923e-ebf0-4263-86fd-a38d89fa3a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323027116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.323027116
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3230218832
Short name T289
Test name
Test status
Simulation time 787707726 ps
CPU time 8.79 seconds
Started Jul 01 05:27:25 PM PDT 24
Finished Jul 01 05:27:36 PM PDT 24
Peak memory 232624 kb
Host smart-af7dcddf-0a14-480e-974f-d73844713a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230218832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3230218832
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4255636347
Short name T306
Test name
Test status
Simulation time 188102302299 ps
CPU time 394.37 seconds
Started Jul 01 05:27:29 PM PDT 24
Finished Jul 01 05:34:06 PM PDT 24
Peak memory 252864 kb
Host smart-3f5f491a-cce0-4902-a355-090285bb3772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255636347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4255636347
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2522047811
Short name T974
Test name
Test status
Simulation time 15458613135 ps
CPU time 51.21 seconds
Started Jul 01 05:27:28 PM PDT 24
Finished Jul 01 05:28:22 PM PDT 24
Peak memory 249276 kb
Host smart-1406e7cf-b064-449a-bbe5-48f57e5c5de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522047811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2522047811
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2507842952
Short name T573
Test name
Test status
Simulation time 14581825044 ps
CPU time 96.12 seconds
Started Jul 01 05:27:27 PM PDT 24
Finished Jul 01 05:29:06 PM PDT 24
Peak memory 265528 kb
Host smart-3bc6ab25-8189-4cce-81cc-ca19a2b9682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507842952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2507842952
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.382152965
Short name T787
Test name
Test status
Simulation time 1379335315 ps
CPU time 2.25 seconds
Started Jul 01 05:27:24 PM PDT 24
Finished Jul 01 05:27:28 PM PDT 24
Peak memory 224440 kb
Host smart-e12bb054-d3eb-4db2-9ede-efbd83c0f4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382152965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.382152965
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1534739255
Short name T843
Test name
Test status
Simulation time 8972991418 ps
CPU time 46.86 seconds
Started Jul 01 05:27:29 PM PDT 24
Finished Jul 01 05:28:18 PM PDT 24
Peak memory 232748 kb
Host smart-4ae2e61e-99ef-4f15-bba4-76f322466d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534739255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1534739255
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.308665061
Short name T618
Test name
Test status
Simulation time 4537586839 ps
CPU time 11.95 seconds
Started Jul 01 05:27:24 PM PDT 24
Finished Jul 01 05:27:38 PM PDT 24
Peak memory 232852 kb
Host smart-6878225c-6fe1-49e6-ba4d-46f1085dc0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308665061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.308665061
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3258950851
Short name T1002
Test name
Test status
Simulation time 8105198857 ps
CPU time 6.71 seconds
Started Jul 01 05:27:24 PM PDT 24
Finished Jul 01 05:27:33 PM PDT 24
Peak memory 232852 kb
Host smart-cd4ce5cb-9261-4735-bb2f-54756d422053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258950851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3258950851
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.359285502
Short name T457
Test name
Test status
Simulation time 5098832696 ps
CPU time 7.59 seconds
Started Jul 01 05:27:25 PM PDT 24
Finished Jul 01 05:27:35 PM PDT 24
Peak memory 222684 kb
Host smart-5bbca0fe-1a39-4501-bde2-5929695637b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=359285502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.359285502
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3219654492
Short name T32
Test name
Test status
Simulation time 67254551 ps
CPU time 0.98 seconds
Started Jul 01 05:27:27 PM PDT 24
Finished Jul 01 05:27:30 PM PDT 24
Peak memory 207744 kb
Host smart-119ece8f-33df-4759-99a1-462c0d1f3b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219654492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3219654492
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3675126686
Short name T308
Test name
Test status
Simulation time 1856817019 ps
CPU time 25.52 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:49 PM PDT 24
Peak memory 216300 kb
Host smart-4cfa53ee-7460-4629-a8e4-fed350745443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675126686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3675126686
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1470949822
Short name T716
Test name
Test status
Simulation time 2004201391 ps
CPU time 10.18 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:34 PM PDT 24
Peak memory 216220 kb
Host smart-751ad373-17ed-486e-bbbc-2f8443d352aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470949822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1470949822
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3325762474
Short name T643
Test name
Test status
Simulation time 74945918 ps
CPU time 2.33 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:27 PM PDT 24
Peak memory 216216 kb
Host smart-2a12c8e5-ec10-42f4-a27c-d539e9326569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325762474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3325762474
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2636463349
Short name T693
Test name
Test status
Simulation time 56433412 ps
CPU time 0.82 seconds
Started Jul 01 05:27:21 PM PDT 24
Finished Jul 01 05:27:25 PM PDT 24
Peak memory 205968 kb
Host smart-da335ea7-2799-45cb-b369-06b301e0672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636463349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2636463349
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1011985881
Short name T998
Test name
Test status
Simulation time 6882990125 ps
CPU time 7.98 seconds
Started Jul 01 05:27:27 PM PDT 24
Finished Jul 01 05:27:38 PM PDT 24
Peak memory 232788 kb
Host smart-3b73e672-7296-48fb-a4f8-2a748b82bf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011985881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1011985881
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4138657650
Short name T338
Test name
Test status
Simulation time 39891137 ps
CPU time 0.7 seconds
Started Jul 01 05:27:28 PM PDT 24
Finished Jul 01 05:27:31 PM PDT 24
Peak memory 205668 kb
Host smart-6e29868a-4735-49da-a1fa-8315a948c428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138657650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4138657650
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.732179738
Short name T606
Test name
Test status
Simulation time 85529032 ps
CPU time 2.93 seconds
Started Jul 01 05:27:26 PM PDT 24
Finished Jul 01 05:27:31 PM PDT 24
Peak memory 232768 kb
Host smart-e1b90a96-b8bd-40ae-a95d-5a156f560801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732179738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.732179738
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.236625570
Short name T395
Test name
Test status
Simulation time 69310409 ps
CPU time 0.81 seconds
Started Jul 01 05:27:29 PM PDT 24
Finished Jul 01 05:27:32 PM PDT 24
Peak memory 206692 kb
Host smart-bd2dc4b5-3fc8-44ed-8cbb-46f9a0281986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236625570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.236625570
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2917033380
Short name T731
Test name
Test status
Simulation time 77652512991 ps
CPU time 537.4 seconds
Started Jul 01 05:27:26 PM PDT 24
Finished Jul 01 05:36:25 PM PDT 24
Peak memory 267952 kb
Host smart-035bebef-9137-4fc7-8c6a-5f20f6b3cd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917033380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2917033380
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3887851438
Short name T126
Test name
Test status
Simulation time 139122695872 ps
CPU time 292.27 seconds
Started Jul 01 05:27:27 PM PDT 24
Finished Jul 01 05:32:22 PM PDT 24
Peak memory 265632 kb
Host smart-46390fba-fd8c-42cc-bad2-fac44e525b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887851438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3887851438
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2594191936
Short name T699
Test name
Test status
Simulation time 4861239191 ps
CPU time 7.7 seconds
Started Jul 01 05:27:26 PM PDT 24
Finished Jul 01 05:27:36 PM PDT 24
Peak memory 217716 kb
Host smart-d77c5a95-a353-4c0a-9763-971259e11008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594191936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2594191936
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1555082833
Short name T417
Test name
Test status
Simulation time 3536335180 ps
CPU time 8.78 seconds
Started Jul 01 05:27:27 PM PDT 24
Finished Jul 01 05:27:38 PM PDT 24
Peak memory 232860 kb
Host smart-00fd4118-0fe3-4bfc-975f-1b4ceeadced0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555082833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1555082833
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2795224263
Short name T277
Test name
Test status
Simulation time 12843616081 ps
CPU time 87.98 seconds
Started Jul 01 05:27:26 PM PDT 24
Finished Jul 01 05:28:57 PM PDT 24
Peak memory 264764 kb
Host smart-6d1a2148-acd1-4503-9e80-c21358b461e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795224263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2795224263
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.863561570
Short name T23
Test name
Test status
Simulation time 2574321243 ps
CPU time 17.76 seconds
Started Jul 01 05:27:27 PM PDT 24
Finished Jul 01 05:27:47 PM PDT 24
Peak memory 224580 kb
Host smart-c8980083-f427-4cbb-b298-61bfc5491d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863561570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.863561570
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3894738345
Short name T501
Test name
Test status
Simulation time 192333781 ps
CPU time 5.41 seconds
Started Jul 01 05:27:27 PM PDT 24
Finished Jul 01 05:27:35 PM PDT 24
Peak memory 232608 kb
Host smart-35bca16b-1991-4d0c-9578-4a96f1611382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894738345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3894738345
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3272828370
Short name T373
Test name
Test status
Simulation time 16929678873 ps
CPU time 16.11 seconds
Started Jul 01 05:27:29 PM PDT 24
Finished Jul 01 05:27:48 PM PDT 24
Peak memory 240736 kb
Host smart-76d05783-c256-4596-b41b-e818a9509b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272828370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3272828370
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2803675442
Short name T478
Test name
Test status
Simulation time 2111026713 ps
CPU time 5.61 seconds
Started Jul 01 05:27:25 PM PDT 24
Finished Jul 01 05:27:33 PM PDT 24
Peak memory 232692 kb
Host smart-13833d15-0984-4502-abfd-a3482f426857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803675442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2803675442
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3256282081
Short name T784
Test name
Test status
Simulation time 1434090516 ps
CPU time 9.18 seconds
Started Jul 01 05:27:26 PM PDT 24
Finished Jul 01 05:27:37 PM PDT 24
Peak memory 222828 kb
Host smart-7a6830c2-c4d8-4d97-8e17-1da36e050913
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3256282081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3256282081
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3211104940
Short name T384
Test name
Test status
Simulation time 1251395940 ps
CPU time 15.09 seconds
Started Jul 01 05:27:25 PM PDT 24
Finished Jul 01 05:27:42 PM PDT 24
Peak memory 216292 kb
Host smart-ec6b4b03-39e9-4318-911f-f38ede24cb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211104940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3211104940
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2853230557
Short name T894
Test name
Test status
Simulation time 320593995 ps
CPU time 3.24 seconds
Started Jul 01 05:27:28 PM PDT 24
Finished Jul 01 05:27:34 PM PDT 24
Peak memory 216212 kb
Host smart-7fa7c685-f444-4bd9-a9f0-ddcb3301b1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853230557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2853230557
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.914811865
Short name T754
Test name
Test status
Simulation time 213338104 ps
CPU time 1.51 seconds
Started Jul 01 05:27:26 PM PDT 24
Finished Jul 01 05:27:30 PM PDT 24
Peak memory 216216 kb
Host smart-b12d4d30-d92c-4dcd-8365-7992ca92251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914811865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.914811865
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2345597185
Short name T328
Test name
Test status
Simulation time 60868573 ps
CPU time 0.96 seconds
Started Jul 01 05:27:29 PM PDT 24
Finished Jul 01 05:27:32 PM PDT 24
Peak memory 207020 kb
Host smart-eb7ce7b8-7e14-4655-bd08-fc61033679ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345597185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2345597185
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3807322672
Short name T483
Test name
Test status
Simulation time 5047911695 ps
CPU time 21.93 seconds
Started Jul 01 05:27:26 PM PDT 24
Finished Jul 01 05:27:50 PM PDT 24
Peak memory 238592 kb
Host smart-c0aea67e-479b-4e54-a62d-361b50237792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807322672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3807322672
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2987155960
Short name T700
Test name
Test status
Simulation time 14049761 ps
CPU time 0.73 seconds
Started Jul 01 05:27:31 PM PDT 24
Finished Jul 01 05:27:34 PM PDT 24
Peak memory 205888 kb
Host smart-b8489a59-e656-41c0-ace4-121b2213b379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987155960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2987155960
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1131386690
Short name T403
Test name
Test status
Simulation time 1570479408 ps
CPU time 8.99 seconds
Started Jul 01 05:27:32 PM PDT 24
Finished Jul 01 05:27:44 PM PDT 24
Peak memory 232656 kb
Host smart-0851aab3-0187-4b3b-81e6-f8ad5aba4295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131386690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1131386690
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2587361025
Short name T958
Test name
Test status
Simulation time 13732954 ps
CPU time 0.78 seconds
Started Jul 01 05:27:31 PM PDT 24
Finished Jul 01 05:27:34 PM PDT 24
Peak memory 206608 kb
Host smart-40abf69b-9c6d-4e08-8a86-62da9fd2b67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587361025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2587361025
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4028992758
Short name T279
Test name
Test status
Simulation time 25803061913 ps
CPU time 36.78 seconds
Started Jul 01 05:27:34 PM PDT 24
Finished Jul 01 05:28:14 PM PDT 24
Peak memory 234452 kb
Host smart-ef9fe020-6c7f-48d6-9d88-7769ff7dfe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028992758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4028992758
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3358052021
Short name T630
Test name
Test status
Simulation time 31270249211 ps
CPU time 222.45 seconds
Started Jul 01 05:27:32 PM PDT 24
Finished Jul 01 05:31:18 PM PDT 24
Peak memory 249356 kb
Host smart-1439bc09-b3ec-4a06-b369-494eaef87745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358052021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3358052021
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.747869000
Short name T946
Test name
Test status
Simulation time 19916815066 ps
CPU time 93.59 seconds
Started Jul 01 05:27:33 PM PDT 24
Finished Jul 01 05:29:10 PM PDT 24
Peak memory 266340 kb
Host smart-ba9a5b55-e0e4-4a91-811f-5c40ba8774ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747869000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.747869000
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.692774541
Short name T726
Test name
Test status
Simulation time 160297915 ps
CPU time 5.6 seconds
Started Jul 01 05:27:35 PM PDT 24
Finished Jul 01 05:27:43 PM PDT 24
Peak memory 239876 kb
Host smart-daff44d1-fdc0-4fa3-878d-e3343b5fabbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692774541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.692774541
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1800712269
Short name T982
Test name
Test status
Simulation time 48762270901 ps
CPU time 118.65 seconds
Started Jul 01 05:27:32 PM PDT 24
Finished Jul 01 05:29:34 PM PDT 24
Peak memory 257384 kb
Host smart-3b526a4d-b9ac-4e5d-b7f2-df9e1f112d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800712269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1800712269
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1033332034
Short name T236
Test name
Test status
Simulation time 3199570267 ps
CPU time 9.66 seconds
Started Jul 01 05:27:32 PM PDT 24
Finished Jul 01 05:27:45 PM PDT 24
Peak memory 232776 kb
Host smart-48a82bef-91f8-45c3-b921-1f0a43568ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033332034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1033332034
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4058762315
Short name T734
Test name
Test status
Simulation time 2072765797 ps
CPU time 10.85 seconds
Started Jul 01 05:27:33 PM PDT 24
Finished Jul 01 05:27:47 PM PDT 24
Peak memory 232776 kb
Host smart-ce171a65-1d57-4a58-8dfa-0e4675aef0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058762315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4058762315
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3296014977
Short name T7
Test name
Test status
Simulation time 1663154064 ps
CPU time 4.04 seconds
Started Jul 01 05:27:33 PM PDT 24
Finished Jul 01 05:27:41 PM PDT 24
Peak memory 224520 kb
Host smart-e9ee2367-7a20-4d7b-8cd7-fd838d42d4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296014977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3296014977
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1221703509
Short name T194
Test name
Test status
Simulation time 895547497 ps
CPU time 4 seconds
Started Jul 01 05:27:31 PM PDT 24
Finished Jul 01 05:27:39 PM PDT 24
Peak memory 232692 kb
Host smart-a38363cf-7363-4e0a-a667-d1fbce6c44b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221703509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1221703509
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1347234523
Short name T595
Test name
Test status
Simulation time 562671174 ps
CPU time 5.24 seconds
Started Jul 01 05:27:33 PM PDT 24
Finished Jul 01 05:27:42 PM PDT 24
Peak memory 222100 kb
Host smart-821448e7-8a28-4f62-aeee-7b64403ceb3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1347234523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1347234523
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.267980784
Short name T720
Test name
Test status
Simulation time 2080977935 ps
CPU time 4.13 seconds
Started Jul 01 05:27:33 PM PDT 24
Finished Jul 01 05:27:41 PM PDT 24
Peak memory 217844 kb
Host smart-80e30c01-428f-4d13-ad6d-ff06ac0dda9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267980784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.267980784
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.5221690
Short name T532
Test name
Test status
Simulation time 4520870587 ps
CPU time 23.78 seconds
Started Jul 01 05:27:33 PM PDT 24
Finished Jul 01 05:28:00 PM PDT 24
Peak memory 216432 kb
Host smart-70a344b0-9ae9-46f3-8194-c0c5d10b211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5221690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.5221690
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.560250952
Short name T753
Test name
Test status
Simulation time 3085801341 ps
CPU time 7.98 seconds
Started Jul 01 05:27:33 PM PDT 24
Finished Jul 01 05:27:44 PM PDT 24
Peak memory 216320 kb
Host smart-c7b1d09a-8d30-490e-984c-bb410dc3195e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560250952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.560250952
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.89506059
Short name T399
Test name
Test status
Simulation time 1246763836 ps
CPU time 3.88 seconds
Started Jul 01 05:27:32 PM PDT 24
Finished Jul 01 05:27:39 PM PDT 24
Peak memory 216256 kb
Host smart-1cf22427-6fa9-4079-9f1a-8ca2442d728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89506059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.89506059
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1396271134
Short name T951
Test name
Test status
Simulation time 42686861 ps
CPU time 0.79 seconds
Started Jul 01 05:27:34 PM PDT 24
Finished Jul 01 05:27:38 PM PDT 24
Peak memory 206008 kb
Host smart-6af08a30-66f7-4e03-b32d-1fd8268389ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396271134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1396271134
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1051910391
Short name T681
Test name
Test status
Simulation time 5774161734 ps
CPU time 4.9 seconds
Started Jul 01 05:27:31 PM PDT 24
Finished Jul 01 05:27:39 PM PDT 24
Peak memory 224648 kb
Host smart-1b3f3288-5a6e-4da9-81f1-1a7a94c44157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051910391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1051910391
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1788078318
Short name T326
Test name
Test status
Simulation time 46389974 ps
CPU time 0.75 seconds
Started Jul 01 05:27:37 PM PDT 24
Finished Jul 01 05:27:40 PM PDT 24
Peak memory 205008 kb
Host smart-67b853bb-de6d-485e-8d78-599ddc237bfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788078318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1788078318
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.883868312
Short name T348
Test name
Test status
Simulation time 155216264 ps
CPU time 3.91 seconds
Started Jul 01 05:27:39 PM PDT 24
Finished Jul 01 05:27:45 PM PDT 24
Peak memory 232600 kb
Host smart-2983d3f9-8668-490b-aef2-914a21d79152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883868312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.883868312
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3446879876
Short name T976
Test name
Test status
Simulation time 101698346 ps
CPU time 0.76 seconds
Started Jul 01 05:27:35 PM PDT 24
Finished Jul 01 05:27:38 PM PDT 24
Peak memory 206608 kb
Host smart-6df9f2db-ce0f-40e2-a91f-28c162e13ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446879876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3446879876
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3355795105
Short name T888
Test name
Test status
Simulation time 4415496955 ps
CPU time 33.2 seconds
Started Jul 01 05:27:38 PM PDT 24
Finished Jul 01 05:28:13 PM PDT 24
Peak memory 236712 kb
Host smart-34243471-1a7f-455d-82b0-d269f83f5517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355795105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3355795105
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.705486588
Short name T43
Test name
Test status
Simulation time 36266418371 ps
CPU time 323.01 seconds
Started Jul 01 05:27:39 PM PDT 24
Finished Jul 01 05:33:04 PM PDT 24
Peak memory 272784 kb
Host smart-60a0d804-9d6a-4b95-be61-581c8d9c44ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705486588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.705486588
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1479513300
Short name T744
Test name
Test status
Simulation time 9310364465 ps
CPU time 91.67 seconds
Started Jul 01 05:27:39 PM PDT 24
Finished Jul 01 05:29:13 PM PDT 24
Peak memory 257404 kb
Host smart-c7c03d17-4c56-40b9-8542-58c8264a938f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479513300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1479513300
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4242719893
Short name T572
Test name
Test status
Simulation time 5123784516 ps
CPU time 18.45 seconds
Started Jul 01 05:27:40 PM PDT 24
Finished Jul 01 05:28:01 PM PDT 24
Peak memory 232856 kb
Host smart-c333cffd-f401-41fc-9cf1-837cd37223c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242719893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4242719893
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1534844584
Short name T978
Test name
Test status
Simulation time 4654616967 ps
CPU time 48.89 seconds
Started Jul 01 05:27:40 PM PDT 24
Finished Jul 01 05:28:31 PM PDT 24
Peak memory 255476 kb
Host smart-c128dabb-af36-42b8-8daa-1abb8cc5b796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534844584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1534844584
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3871665236
Short name T210
Test name
Test status
Simulation time 501970498 ps
CPU time 8.05 seconds
Started Jul 01 05:27:39 PM PDT 24
Finished Jul 01 05:27:49 PM PDT 24
Peak memory 224488 kb
Host smart-8c7f8825-41b6-4cad-bc19-c61db15e85c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871665236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3871665236
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.276753127
Short name T85
Test name
Test status
Simulation time 4801148890 ps
CPU time 16.96 seconds
Started Jul 01 05:27:40 PM PDT 24
Finished Jul 01 05:27:59 PM PDT 24
Peak memory 219004 kb
Host smart-ed0a13f7-87f8-4ceb-a315-724245f6b877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276753127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.276753127
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4226135428
Short name T1015
Test name
Test status
Simulation time 6829108209 ps
CPU time 8.85 seconds
Started Jul 01 05:27:41 PM PDT 24
Finished Jul 01 05:27:52 PM PDT 24
Peak memory 232832 kb
Host smart-3898e1d1-96a4-4c52-bd54-2171bd88837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226135428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4226135428
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4249310355
Short name T401
Test name
Test status
Simulation time 764974979 ps
CPU time 4.78 seconds
Started Jul 01 05:27:38 PM PDT 24
Finished Jul 01 05:27:45 PM PDT 24
Peak memory 232688 kb
Host smart-c48e0abe-5e93-4bf5-8547-6b888c43b543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249310355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4249310355
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3365606314
Short name T360
Test name
Test status
Simulation time 156616575 ps
CPU time 3.32 seconds
Started Jul 01 05:27:38 PM PDT 24
Finished Jul 01 05:27:43 PM PDT 24
Peak memory 220332 kb
Host smart-8c99e732-e585-4c83-a1b6-2fd813c957cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3365606314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3365606314
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.803412532
Short name T810
Test name
Test status
Simulation time 21658214361 ps
CPU time 126.75 seconds
Started Jul 01 05:27:39 PM PDT 24
Finished Jul 01 05:29:48 PM PDT 24
Peak memory 249492 kb
Host smart-12de24a4-ae1c-4e65-bff3-b2fe1660adf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803412532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.803412532
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3337438668
Short name T81
Test name
Test status
Simulation time 984117474 ps
CPU time 15.49 seconds
Started Jul 01 05:27:34 PM PDT 24
Finished Jul 01 05:27:53 PM PDT 24
Peak memory 216548 kb
Host smart-411ec53b-d77e-42a7-8417-087d208fa2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337438668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3337438668
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.920933163
Short name T346
Test name
Test status
Simulation time 1198033767 ps
CPU time 3.86 seconds
Started Jul 01 05:27:34 PM PDT 24
Finished Jul 01 05:27:41 PM PDT 24
Peak memory 216076 kb
Host smart-e797ad82-af89-4517-8a38-adfeae3784d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920933163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.920933163
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4032081561
Short name T777
Test name
Test status
Simulation time 88808902 ps
CPU time 1.15 seconds
Started Jul 01 05:27:33 PM PDT 24
Finished Jul 01 05:27:38 PM PDT 24
Peak memory 216200 kb
Host smart-76d782a7-c406-4ab9-b177-d4b498892877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032081561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4032081561
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1976758244
Short name T331
Test name
Test status
Simulation time 31545782 ps
CPU time 0.87 seconds
Started Jul 01 05:27:34 PM PDT 24
Finished Jul 01 05:27:38 PM PDT 24
Peak memory 207044 kb
Host smart-2c7fc067-a680-4499-b246-419cfa3b6adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976758244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1976758244
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.898238606
Short name T226
Test name
Test status
Simulation time 1462698575 ps
CPU time 8.93 seconds
Started Jul 01 05:27:37 PM PDT 24
Finished Jul 01 05:27:49 PM PDT 24
Peak memory 240888 kb
Host smart-aa065407-b01c-4630-a2c7-8abd0ae2915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898238606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.898238606
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3140509923
Short name T799
Test name
Test status
Simulation time 14997630 ps
CPU time 0.79 seconds
Started Jul 01 05:24:16 PM PDT 24
Finished Jul 01 05:24:19 PM PDT 24
Peak memory 205616 kb
Host smart-8addb04b-f39b-4c03-9de0-c71d901e4588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140509923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
140509923
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3810270020
Short name T407
Test name
Test status
Simulation time 765057813 ps
CPU time 3.21 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:15 PM PDT 24
Peak memory 224496 kb
Host smart-2289272d-1852-4270-bccf-098177c97e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810270020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3810270020
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1030235903
Short name T961
Test name
Test status
Simulation time 22366166 ps
CPU time 0.84 seconds
Started Jul 01 05:24:12 PM PDT 24
Finished Jul 01 05:24:15 PM PDT 24
Peak memory 206668 kb
Host smart-4f860db1-064e-4448-9cf9-a555c6bae982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030235903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1030235903
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3880191071
Short name T996
Test name
Test status
Simulation time 80014226061 ps
CPU time 194.97 seconds
Started Jul 01 05:24:27 PM PDT 24
Finished Jul 01 05:27:44 PM PDT 24
Peak memory 264704 kb
Host smart-d947956b-81f0-4cde-8f25-a3a1d39394bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880191071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3880191071
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.379373501
Short name T180
Test name
Test status
Simulation time 6629560199 ps
CPU time 108.52 seconds
Started Jul 01 05:24:15 PM PDT 24
Finished Jul 01 05:26:05 PM PDT 24
Peak memory 256856 kb
Host smart-3101c9cc-4621-4e93-8794-4cf4305c62ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379373501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.379373501
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1874235024
Short name T189
Test name
Test status
Simulation time 14581809185 ps
CPU time 45.09 seconds
Started Jul 01 05:24:16 PM PDT 24
Finished Jul 01 05:25:03 PM PDT 24
Peak memory 240932 kb
Host smart-e5dbf4c3-6277-4786-8157-119c6e3df4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874235024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1874235024
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3939673786
Short name T536
Test name
Test status
Simulation time 175322939 ps
CPU time 3.36 seconds
Started Jul 01 05:24:13 PM PDT 24
Finished Jul 01 05:24:18 PM PDT 24
Peak memory 240916 kb
Host smart-2bf3a900-eebe-42d7-94a1-2c2deb418089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939673786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3939673786
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2415691833
Short name T999
Test name
Test status
Simulation time 29502576061 ps
CPU time 136.4 seconds
Started Jul 01 05:24:15 PM PDT 24
Finished Jul 01 05:26:34 PM PDT 24
Peak memory 249216 kb
Host smart-ca7ea2a8-30e3-4ba7-bf85-1c5444155a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415691833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2415691833
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.264654671
Short name T835
Test name
Test status
Simulation time 136714894 ps
CPU time 5.51 seconds
Started Jul 01 05:24:09 PM PDT 24
Finished Jul 01 05:24:16 PM PDT 24
Peak memory 232724 kb
Host smart-8e840ed5-4bdf-4b61-ade5-7ff15b01ccb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264654671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.264654671
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1420524890
Short name T988
Test name
Test status
Simulation time 1992757217 ps
CPU time 27.1 seconds
Started Jul 01 05:24:24 PM PDT 24
Finished Jul 01 05:24:53 PM PDT 24
Peak memory 236632 kb
Host smart-8879315f-1066-40a7-b3cc-74e0922bd5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420524890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1420524890
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.990262262
Short name T841
Test name
Test status
Simulation time 5492291155 ps
CPU time 20.1 seconds
Started Jul 01 05:24:11 PM PDT 24
Finished Jul 01 05:24:34 PM PDT 24
Peak memory 248936 kb
Host smart-016c9b30-316f-43e1-8a09-ca54346fa876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990262262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
990262262
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.862369799
Short name T217
Test name
Test status
Simulation time 1433597505 ps
CPU time 6.98 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:19 PM PDT 24
Peak memory 224472 kb
Host smart-e0e6b632-f53b-4f54-9d26-e71b69fcce87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862369799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.862369799
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.777805831
Short name T973
Test name
Test status
Simulation time 3969175565 ps
CPU time 11.18 seconds
Started Jul 01 05:24:16 PM PDT 24
Finished Jul 01 05:24:29 PM PDT 24
Peak memory 221796 kb
Host smart-48a2864d-4b4f-414b-8082-51bb8e4b79ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=777805831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.777805831
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1405212864
Short name T147
Test name
Test status
Simulation time 25601103832 ps
CPU time 181.31 seconds
Started Jul 01 05:24:15 PM PDT 24
Finished Jul 01 05:27:18 PM PDT 24
Peak memory 241272 kb
Host smart-fa166ee6-b03e-4c3b-8974-3cd446329186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405212864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1405212864
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2875845388
Short name T486
Test name
Test status
Simulation time 10585975889 ps
CPU time 19.89 seconds
Started Jul 01 05:24:09 PM PDT 24
Finished Jul 01 05:24:30 PM PDT 24
Peak memory 216424 kb
Host smart-5d792230-018e-4cb8-82e9-26d1e274af75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875845388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2875845388
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.382425573
Short name T796
Test name
Test status
Simulation time 2006111533 ps
CPU time 7.43 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:19 PM PDT 24
Peak memory 216268 kb
Host smart-3c418e28-f1a7-46eb-9cc2-12f2f4a48566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382425573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.382425573
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1675788913
Short name T927
Test name
Test status
Simulation time 267778379 ps
CPU time 2.52 seconds
Started Jul 01 05:24:09 PM PDT 24
Finished Jul 01 05:24:13 PM PDT 24
Peak memory 216260 kb
Host smart-907f3cae-0abe-4258-b2b7-f03f9f3d5cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675788913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1675788913
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.525325203
Short name T757
Test name
Test status
Simulation time 77905880 ps
CPU time 0.8 seconds
Started Jul 01 05:24:10 PM PDT 24
Finished Jul 01 05:24:14 PM PDT 24
Peak memory 206000 kb
Host smart-d57f5e2a-9016-4909-9029-8c87e8684141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525325203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.525325203
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.834171499
Short name T262
Test name
Test status
Simulation time 8607381211 ps
CPU time 25.79 seconds
Started Jul 01 05:24:08 PM PDT 24
Finished Jul 01 05:24:35 PM PDT 24
Peak memory 232772 kb
Host smart-bb9f1338-1789-4d92-b16e-aa13ffd17b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834171499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.834171499
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.21641541
Short name T584
Test name
Test status
Simulation time 19868306 ps
CPU time 0.71 seconds
Started Jul 01 05:24:16 PM PDT 24
Finished Jul 01 05:24:19 PM PDT 24
Peak memory 205472 kb
Host smart-2bd3d8d7-a4e9-40b5-8f4d-c1df7e521159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21641541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.21641541
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.218812741
Short name T402
Test name
Test status
Simulation time 1497378273 ps
CPU time 5.8 seconds
Started Jul 01 05:24:16 PM PDT 24
Finished Jul 01 05:24:24 PM PDT 24
Peak memory 232712 kb
Host smart-d0adf059-9301-475e-80c3-35b5bb36d1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218812741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.218812741
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3856022331
Short name T359
Test name
Test status
Simulation time 14393859 ps
CPU time 0.75 seconds
Started Jul 01 05:24:26 PM PDT 24
Finished Jul 01 05:24:30 PM PDT 24
Peak memory 205580 kb
Host smart-fa817509-d961-4e1a-b7cf-b5c36c9f3ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856022331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3856022331
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3544753096
Short name T709
Test name
Test status
Simulation time 15602294629 ps
CPU time 61.56 seconds
Started Jul 01 05:24:26 PM PDT 24
Finished Jul 01 05:25:30 PM PDT 24
Peak memory 249212 kb
Host smart-5a312c4b-f348-4f54-bd1d-d5cbc91f2086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544753096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3544753096
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2088296993
Short name T35
Test name
Test status
Simulation time 1908244963 ps
CPU time 54.52 seconds
Started Jul 01 05:24:15 PM PDT 24
Finished Jul 01 05:25:11 PM PDT 24
Peak memory 256648 kb
Host smart-ddff4ce3-8652-4eaf-9775-a63c5a0e8891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088296993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2088296993
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1340680907
Short name T26
Test name
Test status
Simulation time 40270351984 ps
CPU time 110.17 seconds
Started Jul 01 05:24:15 PM PDT 24
Finished Jul 01 05:26:07 PM PDT 24
Peak memory 249276 kb
Host smart-b07f4aa0-143e-4d12-9ff6-71898f5ef32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340680907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1340680907
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3737425967
Short name T343
Test name
Test status
Simulation time 5526239373 ps
CPU time 9.18 seconds
Started Jul 01 05:24:15 PM PDT 24
Finished Jul 01 05:24:26 PM PDT 24
Peak memory 236740 kb
Host smart-b548510b-5b68-4d2b-8068-76710d8ba7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737425967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3737425967
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3642655915
Short name T244
Test name
Test status
Simulation time 9210451296 ps
CPU time 120.57 seconds
Started Jul 01 05:24:15 PM PDT 24
Finished Jul 01 05:26:18 PM PDT 24
Peak memory 253980 kb
Host smart-6d6224f2-036f-485c-aa30-4522cf348dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642655915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3642655915
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1439646037
Short name T811
Test name
Test status
Simulation time 56374771 ps
CPU time 2.38 seconds
Started Jul 01 05:24:27 PM PDT 24
Finished Jul 01 05:24:32 PM PDT 24
Peak memory 232336 kb
Host smart-d5d8b0b9-5ec7-4d60-84c2-058046fa1eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439646037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1439646037
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1371676270
Short name T607
Test name
Test status
Simulation time 1476043407 ps
CPU time 13.54 seconds
Started Jul 01 05:24:19 PM PDT 24
Finished Jul 01 05:24:34 PM PDT 24
Peak memory 232652 kb
Host smart-b33290eb-dfa6-4dd4-b4e1-1bbe484e7817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371676270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1371676270
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2477146414
Short name T826
Test name
Test status
Simulation time 31806113 ps
CPU time 2.43 seconds
Started Jul 01 05:24:16 PM PDT 24
Finished Jul 01 05:24:21 PM PDT 24
Peak memory 232300 kb
Host smart-c7b7f7d3-247c-4474-a60a-2523f72067d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477146414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2477146414
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2338889612
Short name T227
Test name
Test status
Simulation time 3560904645 ps
CPU time 11.68 seconds
Started Jul 01 05:24:17 PM PDT 24
Finished Jul 01 05:24:31 PM PDT 24
Peak memory 240928 kb
Host smart-ebf790af-3ebf-41f2-9bc5-4cbe760757c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338889612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2338889612
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3575367079
Short name T484
Test name
Test status
Simulation time 880919703 ps
CPU time 8.64 seconds
Started Jul 01 05:24:18 PM PDT 24
Finished Jul 01 05:24:28 PM PDT 24
Peak memory 220644 kb
Host smart-0dc409a4-246d-47f8-8e4d-c6a842798058
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3575367079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3575367079
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1756804875
Short name T966
Test name
Test status
Simulation time 15786040423 ps
CPU time 162.13 seconds
Started Jul 01 05:24:16 PM PDT 24
Finished Jul 01 05:27:00 PM PDT 24
Peak memory 241104 kb
Host smart-e8fb4e13-d29e-4487-a736-5c06d08f6269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756804875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1756804875
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4255686356
Short name T668
Test name
Test status
Simulation time 39911761166 ps
CPU time 44.21 seconds
Started Jul 01 05:24:15 PM PDT 24
Finished Jul 01 05:25:01 PM PDT 24
Peak memory 216560 kb
Host smart-7e13ba11-c51c-492c-a8b8-550992fd0a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255686356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4255686356
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2906814155
Short name T323
Test name
Test status
Simulation time 7756919394 ps
CPU time 17.77 seconds
Started Jul 01 05:24:16 PM PDT 24
Finished Jul 01 05:24:36 PM PDT 24
Peak memory 216384 kb
Host smart-c4be74d3-fb61-4d42-ac5b-9d93944c3505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906814155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2906814155
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.155833053
Short name T823
Test name
Test status
Simulation time 566681591 ps
CPU time 2.45 seconds
Started Jul 01 05:24:18 PM PDT 24
Finished Jul 01 05:24:22 PM PDT 24
Peak memory 216312 kb
Host smart-57ee54f1-3b2e-479c-93ed-2d48ba479165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155833053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.155833053
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2902561766
Short name T448
Test name
Test status
Simulation time 126239364 ps
CPU time 0.83 seconds
Started Jul 01 05:24:18 PM PDT 24
Finished Jul 01 05:24:20 PM PDT 24
Peak memory 206008 kb
Host smart-d88704e7-be68-4d4f-98ed-e50efab45f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902561766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2902561766
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.44767850
Short name T900
Test name
Test status
Simulation time 400188922 ps
CPU time 3.59 seconds
Started Jul 01 05:24:15 PM PDT 24
Finished Jul 01 05:24:21 PM PDT 24
Peak memory 224448 kb
Host smart-53d8e061-6922-449b-b996-8cc8a6c1ac1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44767850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.44767850
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2171648158
Short name T381
Test name
Test status
Simulation time 28446443 ps
CPU time 0.71 seconds
Started Jul 01 05:24:25 PM PDT 24
Finished Jul 01 05:24:27 PM PDT 24
Peak memory 205544 kb
Host smart-643490d2-9fe1-4593-8031-2de99511c07f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171648158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
171648158
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.820479987
Short name T452
Test name
Test status
Simulation time 1438251026 ps
CPU time 7.36 seconds
Started Jul 01 05:24:27 PM PDT 24
Finished Jul 01 05:24:37 PM PDT 24
Peak memory 232780 kb
Host smart-c981db98-4742-4fd8-8cfe-61eabfd10cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820479987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.820479987
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.70679005
Short name T970
Test name
Test status
Simulation time 53956380 ps
CPU time 0.8 seconds
Started Jul 01 05:24:27 PM PDT 24
Finished Jul 01 05:24:30 PM PDT 24
Peak memory 206612 kb
Host smart-a0af96ea-8525-46d9-854b-593c0dd4e334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70679005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.70679005
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2192558810
Short name T742
Test name
Test status
Simulation time 53732139 ps
CPU time 0.86 seconds
Started Jul 01 05:24:25 PM PDT 24
Finished Jul 01 05:24:28 PM PDT 24
Peak memory 215896 kb
Host smart-9f37a5be-4f94-4943-9483-0096e503431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192558810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2192558810
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1499319151
Short name T1009
Test name
Test status
Simulation time 81164135031 ps
CPU time 387.32 seconds
Started Jul 01 05:24:27 PM PDT 24
Finished Jul 01 05:30:57 PM PDT 24
Peak memory 257436 kb
Host smart-5590361d-5e05-45f5-b33c-1a8ee5bacedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499319151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1499319151
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1175773492
Short name T797
Test name
Test status
Simulation time 5218509194 ps
CPU time 28.87 seconds
Started Jul 01 05:24:28 PM PDT 24
Finished Jul 01 05:24:59 PM PDT 24
Peak memory 249168 kb
Host smart-0bd41330-4701-4eb0-b289-704fbafd290d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175773492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1175773492
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4187884762
Short name T13
Test name
Test status
Simulation time 2925848846 ps
CPU time 31.38 seconds
Started Jul 01 05:24:27 PM PDT 24
Finished Jul 01 05:25:01 PM PDT 24
Peak memory 249348 kb
Host smart-5b517374-d073-4421-857e-97ae34089830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187884762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4187884762
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3011680619
Short name T188
Test name
Test status
Simulation time 3700318512 ps
CPU time 31.26 seconds
Started Jul 01 05:24:25 PM PDT 24
Finished Jul 01 05:24:58 PM PDT 24
Peak memory 232836 kb
Host smart-6907ebcc-04a4-494f-bdd8-6f5fba5987ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011680619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3011680619
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3709119310
Short name T383
Test name
Test status
Simulation time 1203581296 ps
CPU time 10.47 seconds
Started Jul 01 05:24:26 PM PDT 24
Finished Jul 01 05:24:39 PM PDT 24
Peak memory 232708 kb
Host smart-25f11fe6-99f8-4f52-8635-9c0499b7c994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709119310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3709119310
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.640171682
Short name T551
Test name
Test status
Simulation time 2930256326 ps
CPU time 10.89 seconds
Started Jul 01 05:24:27 PM PDT 24
Finished Jul 01 05:24:40 PM PDT 24
Peak memory 232828 kb
Host smart-039d2064-3f35-4831-982f-04abebeee79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640171682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
640171682
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.550217053
Short name T28
Test name
Test status
Simulation time 25317486370 ps
CPU time 23.54 seconds
Started Jul 01 05:24:27 PM PDT 24
Finished Jul 01 05:24:53 PM PDT 24
Peak memory 232796 kb
Host smart-d324a5c2-1262-445b-9b67-89b39f7de08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550217053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.550217053
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.428585065
Short name T1018
Test name
Test status
Simulation time 1358580281 ps
CPU time 5.03 seconds
Started Jul 01 05:24:24 PM PDT 24
Finished Jul 01 05:24:31 PM PDT 24
Peak memory 219300 kb
Host smart-ed410b5d-700b-4811-8bf5-d8ab729954af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=428585065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.428585065
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3134189859
Short name T19
Test name
Test status
Simulation time 7599554733 ps
CPU time 12.55 seconds
Started Jul 01 05:24:26 PM PDT 24
Finished Jul 01 05:24:40 PM PDT 24
Peak memory 224660 kb
Host smart-54b0b581-ee72-4a32-8dd8-956bc61ed08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134189859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3134189859
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2019019910
Short name T589
Test name
Test status
Simulation time 4863975171 ps
CPU time 11.31 seconds
Started Jul 01 05:24:26 PM PDT 24
Finished Jul 01 05:24:40 PM PDT 24
Peak memory 216704 kb
Host smart-5336f8ef-b5e3-4483-9abc-52acd08a77bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019019910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2019019910
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.480809171
Short name T392
Test name
Test status
Simulation time 582059088 ps
CPU time 2.42 seconds
Started Jul 01 05:24:18 PM PDT 24
Finished Jul 01 05:24:22 PM PDT 24
Peak memory 216120 kb
Host smart-16e314df-04be-4f73-bb35-7476dcff7ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480809171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.480809171
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.295987431
Short name T463
Test name
Test status
Simulation time 80564235 ps
CPU time 1.7 seconds
Started Jul 01 05:24:15 PM PDT 24
Finished Jul 01 05:24:18 PM PDT 24
Peak memory 216260 kb
Host smart-7c10ef69-5c2a-4c76-8789-98dd41039b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295987431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.295987431
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2046171134
Short name T428
Test name
Test status
Simulation time 27327889 ps
CPU time 0.78 seconds
Started Jul 01 05:24:16 PM PDT 24
Finished Jul 01 05:24:19 PM PDT 24
Peak memory 205996 kb
Host smart-7ae11230-433c-4844-85c3-e0b0fddd29ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046171134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2046171134
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1755886368
Short name T776
Test name
Test status
Simulation time 245596533 ps
CPU time 2.57 seconds
Started Jul 01 05:24:26 PM PDT 24
Finished Jul 01 05:24:31 PM PDT 24
Peak memory 224520 kb
Host smart-34eb782d-5473-4fa2-a55a-2a093cf2ee04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755886368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1755886368
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3139457643
Short name T386
Test name
Test status
Simulation time 54009251 ps
CPU time 0.73 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:24:35 PM PDT 24
Peak memory 205608 kb
Host smart-59515f9a-0076-4b0e-b9d9-1dae6a9b31ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139457643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
139457643
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.355324067
Short name T579
Test name
Test status
Simulation time 127755306 ps
CPU time 2.48 seconds
Started Jul 01 05:24:33 PM PDT 24
Finished Jul 01 05:24:38 PM PDT 24
Peak memory 232708 kb
Host smart-1c3ead55-7c88-42f3-b02a-e7111079a8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355324067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.355324067
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2469479887
Short name T940
Test name
Test status
Simulation time 32804709 ps
CPU time 0.78 seconds
Started Jul 01 05:24:25 PM PDT 24
Finished Jul 01 05:24:27 PM PDT 24
Peak memory 206612 kb
Host smart-d9bca5c3-4227-4731-bd42-582a30fde313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469479887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2469479887
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2508098825
Short name T202
Test name
Test status
Simulation time 3054590823 ps
CPU time 72.5 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:25:47 PM PDT 24
Peak memory 267212 kb
Host smart-316c74e3-0bea-4cd9-a0dd-acf356bee268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508098825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2508098825
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3316945424
Short name T598
Test name
Test status
Simulation time 27933696911 ps
CPU time 75.97 seconds
Started Jul 01 05:24:33 PM PDT 24
Finished Jul 01 05:25:52 PM PDT 24
Peak memory 241080 kb
Host smart-d5d9e605-12f6-4928-ba80-8707ea3e0e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316945424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3316945424
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3304587862
Short name T488
Test name
Test status
Simulation time 5860494952 ps
CPU time 46.65 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:25:20 PM PDT 24
Peak memory 249292 kb
Host smart-0bc5ed01-cc66-489d-b88e-e4403ea8c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304587862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3304587862
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.483888986
Short name T803
Test name
Test status
Simulation time 1117738803 ps
CPU time 2.85 seconds
Started Jul 01 05:24:36 PM PDT 24
Finished Jul 01 05:24:42 PM PDT 24
Peak memory 224428 kb
Host smart-07271a8b-8120-4611-b240-086142a65e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483888986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.483888986
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1786486051
Short name T489
Test name
Test status
Simulation time 11429736470 ps
CPU time 57.52 seconds
Started Jul 01 05:24:34 PM PDT 24
Finished Jul 01 05:25:35 PM PDT 24
Peak memory 250416 kb
Host smart-3b3b965e-b545-45f1-8d95-6f186013d3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786486051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1786486051
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.821963575
Short name T727
Test name
Test status
Simulation time 2699371894 ps
CPU time 31.86 seconds
Started Jul 01 05:24:25 PM PDT 24
Finished Jul 01 05:24:58 PM PDT 24
Peak memory 224620 kb
Host smart-12b558e1-a66d-4e05-9166-35b47981224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821963575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.821963575
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2451781534
Short name T707
Test name
Test status
Simulation time 720749335 ps
CPU time 11.56 seconds
Started Jul 01 05:24:34 PM PDT 24
Finished Jul 01 05:24:48 PM PDT 24
Peak memory 224548 kb
Host smart-02186129-4b8d-41c6-8ea5-8e523b1ac4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451781534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2451781534
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3675493241
Short name T758
Test name
Test status
Simulation time 294761643 ps
CPU time 5.03 seconds
Started Jul 01 05:24:23 PM PDT 24
Finished Jul 01 05:24:29 PM PDT 24
Peak memory 232636 kb
Host smart-e9f98128-d1e8-4620-bd70-77ceea5b6f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675493241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3675493241
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2845393601
Short name T345
Test name
Test status
Simulation time 18238544378 ps
CPU time 15.58 seconds
Started Jul 01 05:24:28 PM PDT 24
Finished Jul 01 05:24:45 PM PDT 24
Peak memory 224652 kb
Host smart-49e4d482-4c6f-4076-8a52-d1692b62e728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845393601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2845393601
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3340112808
Short name T492
Test name
Test status
Simulation time 644837720 ps
CPU time 10.4 seconds
Started Jul 01 05:24:33 PM PDT 24
Finished Jul 01 05:24:45 PM PDT 24
Peak memory 219280 kb
Host smart-974bcc7f-f623-45be-ad00-bb46f9983443
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3340112808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3340112808
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1828808086
Short name T977
Test name
Test status
Simulation time 212056977305 ps
CPU time 280.2 seconds
Started Jul 01 05:24:34 PM PDT 24
Finished Jul 01 05:29:16 PM PDT 24
Peak memory 257020 kb
Host smart-a4aa4695-b00a-497c-bbda-f49598f0b8f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828808086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1828808086
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2712141137
Short name T30
Test name
Test status
Simulation time 9577710111 ps
CPU time 26.56 seconds
Started Jul 01 05:24:28 PM PDT 24
Finished Jul 01 05:24:56 PM PDT 24
Peak memory 216332 kb
Host smart-480ba53d-c874-42bf-8b55-0794ac425068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712141137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2712141137
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2933396186
Short name T319
Test name
Test status
Simulation time 1289417172 ps
CPU time 8.26 seconds
Started Jul 01 05:24:26 PM PDT 24
Finished Jul 01 05:24:36 PM PDT 24
Peak memory 216316 kb
Host smart-78074f1c-64d2-4ae2-9dc2-de8946676f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933396186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2933396186
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2601743779
Short name T580
Test name
Test status
Simulation time 636824804 ps
CPU time 3.78 seconds
Started Jul 01 05:24:25 PM PDT 24
Finished Jul 01 05:24:30 PM PDT 24
Peak memory 216264 kb
Host smart-1dfbc366-23d4-410a-910a-dc230c07e317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601743779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2601743779
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3705075071
Short name T928
Test name
Test status
Simulation time 52331570 ps
CPU time 0.76 seconds
Started Jul 01 05:24:25 PM PDT 24
Finished Jul 01 05:24:27 PM PDT 24
Peak memory 206112 kb
Host smart-8ae7a13e-141e-4d48-bbca-9e5e88974516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705075071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3705075071
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1849271071
Short name T235
Test name
Test status
Simulation time 14240246031 ps
CPU time 16.69 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:24:52 PM PDT 24
Peak memory 232732 kb
Host smart-3b4aa07b-7152-4da0-ad71-0ae7c8980979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849271071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1849271071
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3926579606
Short name T959
Test name
Test status
Simulation time 13631807 ps
CPU time 0.71 seconds
Started Jul 01 05:24:42 PM PDT 24
Finished Jul 01 05:24:47 PM PDT 24
Peak memory 205892 kb
Host smart-1b6e6326-f400-4ec1-871d-9490dbcb1591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926579606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
926579606
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3637489654
Short name T830
Test name
Test status
Simulation time 368627425 ps
CPU time 3.33 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:24:37 PM PDT 24
Peak memory 224672 kb
Host smart-80665a5e-c469-4cf7-b80a-7d62b6fbe525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637489654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3637489654
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1033142746
Short name T805
Test name
Test status
Simulation time 279464665 ps
CPU time 0.79 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:24:34 PM PDT 24
Peak memory 206620 kb
Host smart-9e43c1cb-adf8-4079-af03-5c3fb99d68e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033142746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1033142746
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2465025782
Short name T881
Test name
Test status
Simulation time 4236639626 ps
CPU time 11.01 seconds
Started Jul 01 05:24:36 PM PDT 24
Finished Jul 01 05:24:50 PM PDT 24
Peak memory 234456 kb
Host smart-a0ab54f6-4c5b-4001-9c66-52f4c8f595b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465025782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2465025782
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.140954266
Short name T925
Test name
Test status
Simulation time 18783934447 ps
CPU time 175.81 seconds
Started Jul 01 05:24:34 PM PDT 24
Finished Jul 01 05:27:33 PM PDT 24
Peak memory 254828 kb
Host smart-0c36df96-1b03-4cfc-bc3d-dd5661f745c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140954266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.140954266
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.322147328
Short name T193
Test name
Test status
Simulation time 6246737758 ps
CPU time 46.96 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:25:21 PM PDT 24
Peak memory 249728 kb
Host smart-6d2b2833-cac4-4d11-aeb7-50912dfd803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322147328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
322147328
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2139408624
Short name T357
Test name
Test status
Simulation time 12011807590 ps
CPU time 42.86 seconds
Started Jul 01 05:24:33 PM PDT 24
Finished Jul 01 05:25:19 PM PDT 24
Peak memory 240984 kb
Host smart-141a7c62-1fb5-47d0-9332-c11c5ce42341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139408624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2139408624
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.540340104
Short name T577
Test name
Test status
Simulation time 128591277482 ps
CPU time 227.55 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:28:23 PM PDT 24
Peak memory 257360 kb
Host smart-f1dbe14b-8da3-4bfb-b87d-881f51107b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540340104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
540340104
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.649645025
Short name T994
Test name
Test status
Simulation time 2044775040 ps
CPU time 3.85 seconds
Started Jul 01 05:24:34 PM PDT 24
Finished Jul 01 05:24:41 PM PDT 24
Peak memory 232792 kb
Host smart-4fe0f7f6-1dec-4705-9f63-1ef708e70178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649645025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.649645025
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.917912983
Short name T192
Test name
Test status
Simulation time 7382272326 ps
CPU time 47.08 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:25:22 PM PDT 24
Peak memory 232844 kb
Host smart-509da80d-900f-47b3-aa5b-e1ee8da13551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917912983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.917912983
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.889119206
Short name T768
Test name
Test status
Simulation time 457001971 ps
CPU time 6.09 seconds
Started Jul 01 05:24:33 PM PDT 24
Finished Jul 01 05:24:41 PM PDT 24
Peak memory 232704 kb
Host smart-fec90c4c-2663-44d9-8068-bdaa5903b126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889119206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
889119206
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.253004423
Short name T366
Test name
Test status
Simulation time 525593521 ps
CPU time 6.94 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:24:42 PM PDT 24
Peak memory 232712 kb
Host smart-a2d8a3de-b94c-4bcd-8cea-c0095b0fd5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253004423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.253004423
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3092453279
Short name T886
Test name
Test status
Simulation time 321513475 ps
CPU time 5.58 seconds
Started Jul 01 05:24:35 PM PDT 24
Finished Jul 01 05:24:43 PM PDT 24
Peak memory 220288 kb
Host smart-79e0baff-876c-49d1-877d-4aaa8b70f781
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3092453279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3092453279
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3295308394
Short name T150
Test name
Test status
Simulation time 13687548903 ps
CPU time 106.56 seconds
Started Jul 01 05:24:36 PM PDT 24
Finished Jul 01 05:26:25 PM PDT 24
Peak memory 224584 kb
Host smart-52399ea4-ed5a-4f39-b26a-9ef348a4d947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295308394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3295308394
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1478314293
Short name T385
Test name
Test status
Simulation time 1452423490 ps
CPU time 8.3 seconds
Started Jul 01 05:24:33 PM PDT 24
Finished Jul 01 05:24:44 PM PDT 24
Peak memory 216560 kb
Host smart-83e3add5-4cef-4e54-92b7-b3745da484fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478314293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1478314293
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.334153863
Short name T440
Test name
Test status
Simulation time 211942422 ps
CPU time 1.02 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:24:35 PM PDT 24
Peak memory 206884 kb
Host smart-51bf1a9c-6d33-48a3-90f9-0c6019fe7e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334153863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.334153863
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2910452525
Short name T735
Test name
Test status
Simulation time 138562731 ps
CPU time 1.1 seconds
Started Jul 01 05:24:35 PM PDT 24
Finished Jul 01 05:24:39 PM PDT 24
Peak memory 207048 kb
Host smart-37b00742-cb8d-4891-ba35-955d87f81ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910452525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2910452525
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3613636916
Short name T324
Test name
Test status
Simulation time 87806552 ps
CPU time 0.87 seconds
Started Jul 01 05:24:32 PM PDT 24
Finished Jul 01 05:24:36 PM PDT 24
Peak memory 206052 kb
Host smart-80cc23cc-25cb-410a-bbf7-c577b8a2b8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613636916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3613636916
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4010340436
Short name T556
Test name
Test status
Simulation time 1332391395 ps
CPU time 6.17 seconds
Started Jul 01 05:24:35 PM PDT 24
Finished Jul 01 05:24:44 PM PDT 24
Peak memory 224420 kb
Host smart-0432e74c-9fba-4dae-bae7-2ff324821134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010340436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4010340436
Directory /workspace/9.spi_device_upload/latest
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