Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2604097	1			T1	2		T2	5		T3	1717
all_values[1]	2604097	1			T1	2		T2	5		T3	1717
all_values[2]	2604097	1			T1	2		T2	5		T3	1717
all_values[3]	2604097	1			T1	2		T2	5		T3	1717
all_values[4]	2604097	1			T1	2		T2	5		T3	1717
all_values[5]	2604097	1			T1	2		T2	5		T3	1717
all_values[6]	2604097	1			T1	2		T2	5		T3	1717
all_values[7]	2604097	1			T1	2		T2	5		T3	1717

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20327287

1

T1

16

T2

40

T3

13736

auto[1]

505489

1

T12

59

T14

30

T16

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20804083

1

T1

16

T2

40

T3

13654

auto[1]

28693

1

T3

82

T12

40

T14

32

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2454750	1			T1	2		T2	5		T3	1664
all_values[0]	auto[0]	auto[1]	12989	1			T3	53		T12	3		T14	2
all_values[0]	auto[1]	auto[0]	135327	1			T12	3		T16	4		T17	6
all_values[0]	auto[1]	auto[1]	1031	1			T12	2		T14	3		T16	1
all_values[1]	auto[0]	auto[0]	2532711	1			T1	2		T2	5		T3	1690
all_values[1]	auto[0]	auto[1]	8597	1			T3	27		T12	1		T14	2
all_values[1]	auto[1]	auto[0]	62068	1			T12	7		T14	2		T17	1
all_values[1]	auto[1]	auto[1]	721	1			T12	4		T16	1		T17	4
all_values[2]	auto[0]	auto[0]	2561775	1			T1	2		T2	5		T3	1715
all_values[2]	auto[0]	auto[1]	3230	1			T3	2		T12	5		T14	5
all_values[2]	auto[1]	auto[0]	38855	1			T12	5		T16	1		T17	1
all_values[2]	auto[1]	auto[1]	237	1			T12	1		T14	2		T16	5
all_values[3]	auto[0]	auto[0]	2568109	1			T1	2		T2	5		T3	1717
all_values[3]	auto[0]	auto[1]	162	1			T12	2		T14	5		T18	2
all_values[3]	auto[1]	auto[0]	35624	1			T12	7		T16	5		T17	5
all_values[3]	auto[1]	auto[1]	202	1			T12	1		T14	1		T17	2
all_values[4]	auto[0]	auto[0]	2590699	1			T1	2		T2	5		T3	1717
all_values[4]	auto[0]	auto[1]	198	1			T12	3		T16	2		T17	1
all_values[4]	auto[1]	auto[0]	13002	1			T12	5		T14	5		T16	2
all_values[4]	auto[1]	auto[1]	198	1			T12	5		T14	2		T16	1
all_values[5]	auto[0]	auto[0]	2493495	1			T1	2		T2	5		T3	1717
all_values[5]	auto[0]	auto[1]	173	1			T12	1		T14	2		T16	2
all_values[5]	auto[1]	auto[0]	110247	1			T12	5		T14	4		T16	3
all_values[5]	auto[1]	auto[1]	182	1			T12	3		T14	2		T16	1
all_values[6]	auto[0]	auto[0]	2590135	1			T1	2		T2	5		T3	1717
all_values[6]	auto[0]	auto[1]	178	1			T12	4		T14	1		T17	1
all_values[6]	auto[1]	auto[0]	13579	1			T12	7		T14	2		T16	3
all_values[6]	auto[1]	auto[1]	205	1			T12	2		T14	1		T16	1
all_values[7]	auto[0]	auto[0]	2509874	1			T1	2		T2	5		T3	1717
all_values[7]	auto[0]	auto[1]	212	1			T12	3		T14	1		T16	5
all_values[7]	auto[1]	auto[0]	93833	1			T12	2		T14	3		T16	1
all_values[7]	auto[1]	auto[1]	178	1			T14	3		T16	1		T18	5