Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34308	1			T3	224		T5	184		T13	2
auto[SpiFlashAddrCfg]	7896	1			T1	1		T3	15		T5	29
auto[SpiFlashAddr3b]	9204	1			T2	5		T3	33		T5	41
auto[SpiFlashAddr4b]	7718	1			T1	1		T3	15		T5	32

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33394

1

T1

2

T2

5

T3

139

auto[1]

25732

1

T3

148

T5

75

T14

201

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31918

1

T1

2

T3

127

T5

98

auto[1]

27208

1

T2

5

T3

160

T5

188

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39185	1			T2	2		T3	234		T5	210
values[1]	1110	1			T3	7		T5	4		T14	1
values[2]	1520	1			T3	3		T5	4		T14	5
values[3]	1474	1			T3	1		T5	2		T14	2
values[4]	1570	1			T3	1		T5	5		T14	6
values[5]	1501	1			T2	3		T3	5		T5	6
values[6]	1492	1			T3	6		T5	9		T14	6
values[7]	1392	1			T3	5		T5	4		T6	4
values[8]	9882	1			T1	2		T3	25		T5	42

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29965

1

T3

287

T5

286

T6

14

auto[1]

29161

1

T1

2

T2

5

T7

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55721

1

T1

2

T2

5

T3

276

write

3405

1

T3

11

T5

12

T14

25

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19766

1

T1

1

T2

3

T3

54

valids[0x1]

39360

1

T1

1

T2

2

T3

233

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1614	1			T3	5		T5	8		T13	2
internal_process_ops[0x5a]	1541	1			T3	4		T5	3		T14	9
internal_process_ops[0x05]	19716	1			T3	173		T5	130		T14	232
internal_process_ops[0x35]	1633	1			T3	3		T5	6		T14	4
internal_process_ops[0x15]	1614	1			T3	5		T5	8		T14	11
internal_process_ops[0x03]	1089	1			T1	1		T2	2		T3	4
internal_process_ops[0x0b]	1067	1			T3	3		T5	8		T6	2
internal_process_ops[0x3b]	1132	1			T3	1		T5	2		T7	1
internal_process_ops[0x6b]	1073	1			T3	4		T5	6		T14	1
internal_process_ops[0xbb]	1061	1			T2	3		T5	4		T7	1
internal_process_ops[0xeb]	1039	1			T1	1		T3	5		T5	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57420

1

T1

2

T2

5

T3

280

auto[1]

1706

1

T3

7

T5

8

T14

15

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56683

1

T1

2

T2

5

T3

275

auto[1]

2443

1

T3

12

T5

10

T14

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10094

1

T3

110

T5

161

T13

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5666

1

T3

110

T5

20

T39

11

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2115

1

T3

4

T5

12

T8

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1801

1

T3

7

T5

15

T39

20

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2477

1

T3

15

T5

14

T6

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2265

1

T3

15

T5

20

T39

17

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2075

1

T3

6

T5

18

T6

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1832

1

T3

9

T5

14

T39

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

119

1

T39

1

T156

2

T41

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

119

1

T3

2

T42

2

T18

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

89

1

T3

1

T18

1

T43

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

119

1

T3

1

T5

3

T39

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

107

1

T3

1

T5

1

T42

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

110

1

T3

1

T5

1

T39

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

90

1

T18

6

T43

3

T45

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

94

1

T3

2

T39

1

T45

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

99

1

T5

3

T18

2

T59

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

101

1

T5

1

T42

1

T18

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

116

1

T3

2

T42

2

T18

5

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

70

1

T3

1

T5

3

T46

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T39

1

T42

1

T157

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

91

1

T39

2

T43

2

T45

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

98

1

T43

1

T45

1

T40

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T39

1

T40

3

T41

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9998

1

T14

157

T38

216

T31

316

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7639

1

T14

135

T38

56

T31

106

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1580

1

T1

1

T7

2

T14

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1556

1

T14

14

T38

18

T31

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1807

1

T2

5

T14

20

T38

13

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1825

1

T14

25

T38

18

T31

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1541

1

T1

1

T7

4

T14

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1450

1

T14

12

T38

15

T31

20

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

92

1

T14

2

T38

1

T31

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

129

1

T14

3

T38

6

T31

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

137

1

T14

1

T31

3

T16

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

107

1

T14

1

T31

1

T16

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

99

1

T31

3

T17

4

T48

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

115

1

T14

2

T38

3

T31

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

115

1

T14

1

T38

1

T31

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

114

1

T14

4

T31

1

T33

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

93

1

T14

1

T31

2

T16

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

111

1

T31

4

T48

6

T95

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

125

1

T14

1

T38

3

T31

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

115

1

T31

1

T16

7

T17

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

94

1

T38

4

T16

2

T95

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

110

1

T14

2

T31

3

T16

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

108

1

T14

4

T38

2

T31

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

101

1

T14

3

T38

2

T31

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4027	1			T3	27		T5	30		T26	8
auto[0]	values[0]	valids[0x1]	14731	1			T3	207		T5	180		T6	4
auto[0]	values[1]	valids[0x1]	592	1			T3	7		T5	4		T39	2
auto[0]	values[2]	valids[0x0]	522	1			T5	2		T39	2		T42	3
auto[0]	values[2]	valids[0x1]	338	1			T3	3		T5	2		T39	3
auto[0]	values[3]	valids[0x0]	489	1			T39	15		T42	2		T43	6
auto[0]	values[3]	valids[0x1]	330	1			T3	1		T5	2		T44	2
auto[0]	values[4]	valids[0x0]	565	1			T5	3		T44	2		T39	5
auto[0]	values[4]	valids[0x1]	334	1			T3	1		T5	2		T42	4
auto[0]	values[5]	valids[0x0]	560	1			T3	3		T5	5		T158	2
auto[0]	values[5]	valids[0x1]	265	1			T3	2		T5	1		T39	3
auto[0]	values[6]	valids[0x0]	492	1			T3	4		T5	5		T39	2
auto[0]	values[6]	valids[0x1]	307	1			T3	2		T5	4		T158	2
auto[0]	values[7]	valids[0x0]	493	1			T3	5		T5	3		T6	4
auto[0]	values[7]	valids[0x1]	266	1			T5	1		T39	2		T54	4
auto[0]	values[8]	valids[0x0]	3561	1			T3	15		T5	28		T6	4
auto[0]	values[8]	valids[0x1]	2093	1			T3	10		T5	14		T6	2
auto[1]	values[0]	valids[0x0]	4190	1			T14	37		T38	44		T31	59
auto[1]	values[0]	valids[0x1]	16237	1			T2	2		T7	4		T14	300
auto[1]	values[1]	valids[0x1]	518	1			T14	1		T38	3		T31	9
auto[1]	values[2]	valids[0x0]	389	1			T38	7		T31	5		T16	10
auto[1]	values[2]	valids[0x1]	271	1			T14	5		T31	2		T16	4
auto[1]	values[3]	valids[0x0]	402	1			T38	3		T31	3		T16	6
auto[1]	values[3]	valids[0x1]	253	1			T14	2		T38	1		T31	5
auto[1]	values[4]	valids[0x0]	411	1			T38	8		T31	3		T16	3
auto[1]	values[4]	valids[0x1]	260	1			T14	6		T38	2		T31	3
auto[1]	values[5]	valids[0x0]	400	1			T2	3		T7	1		T14	4
auto[1]	values[5]	valids[0x1]	276	1			T14	1		T38	5		T31	5
auto[1]	values[6]	valids[0x0]	415	1			T14	4		T29	1		T38	5
auto[1]	values[6]	valids[0x1]	278	1			T14	2		T38	2		T31	5
auto[1]	values[7]	valids[0x0]	377	1			T14	2		T38	2		T31	4
auto[1]	values[7]	valids[0x1]	256	1			T14	2		T31	2		T16	5
auto[1]	values[8]	valids[0x0]	2473	1			T1	1		T7	1		T14	25
auto[1]	values[8]	valids[0x1]	1755	1			T1	1		T14	16		T38	20