Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3331643

1

T1

5925

T2

135

T3

9078

auto[1]

30597

1

T3

167

T5

126

T14

227

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

936164

1

T1

5925

T2

135

T3

44

auto[1]

2426076

1

T3

9201

T5

7727

T14

6467

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	611186	1			T1	841		T2	15		T3	8
auto[524288:1048575]	403115	1			T1	4480		T3	2478		T5	5556
auto[1048576:1572863]	340546	1			T3	1854		T7	166		T14	37
auto[1572864:2097151]	401797	1			T2	7		T3	4262		T7	383
auto[2097152:2621439]	445966	1			T2	56		T3	522		T5	856
auto[2621440:3145727]	386348	1			T3	77		T5	5		T14	1532
auto[3145728:3670015]	373085	1			T1	399		T2	39		T3	27
auto[3670016:4194303]	400197	1			T1	205		T2	18		T3	17

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2461493

1

T1

8

T2

21

T3

9240

auto[1]

900747

1

T1

5917

T2

114

T3

5

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2961996

1

T1

5925

T2

135

T3

7343

auto[1]

400244

1

T3

1902

T5

1039

T14

3633

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	197713	1			T1	841		T2	15		T3	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	368160	1			T3	5		T5	257		T15	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	91003	1			T1	4480		T3	1		T5	15
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	246763	1			T3	2477		T5	5214		T14	257
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	59331	1			T3	2		T7	166		T14	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	223243	1			T3	1851		T14	1		T38	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	101365	1			T2	7		T3	5		T7	383
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	247733	1			T3	2330		T14	526		T38	1399
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	137860	1			T2	56		T3	4		T5	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	253551	1			T3	513		T5	852		T14	256
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	108403	1			T3	3		T5	5		T14	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	217658	1			T3	2		T14	1170		T15	2198
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	102515	1			T1	399		T2	39		T3	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	225567	1			T3	6		T5	1		T15	2188
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	125275	1			T1	205		T2	18		T3	3
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	229452	1			T3	1		T5	261		T14	513
auto[0]	auto[1]	auto[0:524287]	auto[0]	705	1			T14	3		T31	2		T16	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	39222	1			T14	260		T31	1		T16	516
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	640	1			T5	5		T14	3		T26	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	59680	1			T5	258		T14	2498		T34	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2013	1			T3	1		T26	4		T38	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	53546	1			T38	256		T31	513		T16	389
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	561	1			T3	2		T14	1		T16	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	49603	1			T3	1860		T14	512		T16	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	955	1			T26	6		T38	1		T31	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	49780	1			T38	256		T31	1961		T16	308
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2876	1			T3	2		T14	11		T31	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53772	1			T3	1		T14	259		T38	1855
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	431	1			T5	2		T14	5		T38	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	40013	1			T5	768		T14	2		T38	953
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	511	1			T17	1		T33	1		T34	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	41743	1			T33	512		T34	670		T18	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	594	1			T5	1		T38	4		T39	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	4335	1			T5	12		T38	39		T34	5
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	465	1			T5	4		T14	1		T38	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4025	1			T5	54		T38	50		T31	14
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	369	1			T14	1		T38	2		T31	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1548	1			T14	30		T38	48		T31	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	367	1			T3	3		T14	3		T16	11
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1860	1			T3	46		T14	63		T16	11
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	384	1			T3	1		T38	1		T31	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2858	1			T3	4		T38	12		T31	120
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	346	1			T3	2		T14	2		T38	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2683	1			T3	47		T14	41		T38	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	458	1			T3	3		T5	1		T38	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3684	1			T3	12		T5	5		T38	21
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	378	1			T3	1		T5	3		T14	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2050	1			T3	12		T5	40		T14	6
auto[1]	auto[1]	auto[0:524287]	auto[0]	79	1			T14	1		T31	1		T48	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	378	1			T14	21		T48	4		T40	59
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	79	1			T5	1		T42	3		T34	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	460	1			T5	5		T34	9		T185	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	89	1			T31	1		T16	1		T33	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	407	1			T31	4		T16	1		T34	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	70	1			T3	1		T16	1		T41	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	238	1			T3	15		T16	1		T41	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	85	1			T31	1		T16	1		T45	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	493	1			T31	5		T16	1		T45	8
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	84	1			T3	1		T14	3		T16	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	526	1			T3	19		T14	42		T16	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	57	1			T14	2		T16	1		T221	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	360	1			T14	10		T16	22		T221	21
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	103	1			T43	1		T95	2		T40	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	685	1			T43	3		T40	22		T178	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2039948	1			T1	8		T2	21		T3	7210
auto[0]	auto[0]	auto[1]	895644	1			T1	5917		T2	114		T3	2
auto[0]	auto[1]	auto[0]	391664	1			T3	1864		T5	1032		T14	3552
auto[0]	auto[1]	auto[1]	4387	1			T3	2		T5	1		T14	2
auto[1]	auto[0]	auto[0]	25798	1			T3	130		T5	112		T14	146
auto[1]	auto[0]	auto[1]	606	1			T3	1		T5	8		T14	2
auto[1]	auto[1]	auto[0]	4083	1			T3	36		T5	5		T14	77
auto[1]	auto[1]	auto[1]	110	1			T5	1		T14	2		T31	2