Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2604097	1			T1	2		T2	5		T3	1717
all_pins[1]	2604097	1			T1	2		T2	5		T3	1717
all_pins[2]	2604097	1			T1	2		T2	5		T3	1717
all_pins[3]	2604097	1			T1	2		T2	5		T3	1717
all_pins[4]	2604097	1			T1	2		T2	5		T3	1717
all_pins[5]	2604097	1			T1	2		T2	5		T3	1717
all_pins[6]	2604097	1			T1	2		T2	5		T3	1717
all_pins[7]	2604097	1			T1	2		T2	5		T3	1717

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20814622	1			T1	16		T2	40		T3	13736
values[0x1]	18154	1			T12	18		T14	14		T16	11
transitions[0x0=>0x1]	17116	1			T12	15		T14	11		T16	11
transitions[0x1=>0x0]	17123	1			T12	15		T14	11		T16	11

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2602986	1			T1	2		T2	5		T3	1717
all_pins[0]	values[0x1]	1111	1			T12	2		T14	3		T16	1
all_pins[0]	transitions[0x0=>0x1]	624	1			T12	1		T14	3		T16	1
all_pins[0]	transitions[0x1=>0x0]	283	1			T12	3		T16	1		T17	3
all_pins[1]	values[0x0]	2603327	1			T1	2		T2	5		T3	1717
all_pins[1]	values[0x1]	770	1			T12	4		T16	1		T17	4
all_pins[1]	transitions[0x0=>0x1]	707	1			T12	4		T16	1		T17	3
all_pins[1]	transitions[0x1=>0x0]	180	1			T12	1		T14	2		T16	5
all_pins[2]	values[0x0]	2603854	1			T1	2		T2	5		T3	1717
all_pins[2]	values[0x1]	243	1			T12	1		T14	2		T16	5
all_pins[2]	transitions[0x0=>0x1]	196	1			T12	1		T14	2		T16	5
all_pins[2]	transitions[0x1=>0x0]	155	1			T12	1		T14	1		T17	2
all_pins[3]	values[0x0]	2603895	1			T1	2		T2	5		T3	1717
all_pins[3]	values[0x1]	202	1			T12	1		T14	1		T17	2
all_pins[3]	transitions[0x0=>0x1]	147	1			T12	1		T17	2		T18	1
all_pins[3]	transitions[0x1=>0x0]	143	1			T12	5		T14	1		T16	1
all_pins[4]	values[0x0]	2603899	1			T1	2		T2	5		T3	1717
all_pins[4]	values[0x1]	198	1			T12	5		T14	2		T16	1
all_pins[4]	transitions[0x0=>0x1]	145	1			T12	3		T14	2		T16	1
all_pins[4]	transitions[0x1=>0x0]	1924	1			T12	1		T14	2		T16	1
all_pins[5]	values[0x0]	2602120	1			T1	2		T2	5		T3	1717
all_pins[5]	values[0x1]	1977	1			T12	3		T14	2		T16	1
all_pins[5]	transitions[0x0=>0x1]	1746	1			T12	3		T14	2		T16	1
all_pins[5]	transitions[0x1=>0x0]	13244	1			T12	2		T14	1		T16	1
all_pins[6]	values[0x0]	2590622	1			T1	2		T2	5		T3	1717
all_pins[6]	values[0x1]	13475	1			T12	2		T14	1		T16	1
all_pins[6]	transitions[0x0=>0x1]	13433	1			T12	2		T16	1		T18	2
all_pins[6]	transitions[0x1=>0x0]	136	1			T14	2		T16	1		T18	3
all_pins[7]	values[0x0]	2603919	1			T1	2		T2	5		T3	1717
all_pins[7]	values[0x1]	178	1			T14	3		T16	1		T18	5
all_pins[7]	transitions[0x0=>0x1]	118	1			T14	2		T16	1		T18	2
all_pins[7]	transitions[0x1=>0x0]	1058	1			T12	2		T14	2		T16	1