Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17625

1

T3

139

T5

211

T6

14

auto[1]

12340

1

T3

148

T5

75

T39

62

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3918	1			T5	26		T6	14		T18	49
values[1]	4141	1			T3	71		T5	81		T13	2
values[2]	3711	1			T3	20		T39	60		T42	20
values[3]	3684	1			T5	69		T8	4		T44	18
values[4]	3453	1			T5	30		T15	6		T26	8
values[5]	3583	1			T5	20		T39	20		T42	20
values[6]	3819	1			T3	27		T18	40		T43	50
values[7]	3656	1			T3	169		T5	60		T158	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3982	1			T3	116		T158	4		T39	20
values[1]	3473	1			T5	20		T13	2		T39	20
values[2]	3875	1			T3	20		T5	69		T6	14
values[3]	3188	1			T5	30		T26	8		T54	18
values[4]	3869	1			T3	98		T8	4		T222	2
values[5]	3665	1			T5	46		T44	18		T39	20
values[6]	4219	1			T3	20		T5	101		T39	40
values[7]	3694	1			T3	33		T5	20		T15	6

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	287	1			T223	12		T180	11		T174	12
auto[0]	values[0]	values[1]	283	1			T18	19		T224	2		T45	19
auto[0]	values[0]	values[2]	285	1			T6	14		T218	16		T180	13
auto[0]	values[0]	values[3]	207	1			T41	10		T177	13		T193	14
auto[0]	values[0]	values[4]	277	1			T45	14		T19	10		T188	14
auto[0]	values[0]	values[5]	247	1			T5	20		T43	12		T45	10
auto[0]	values[0]	values[6]	390	1			T18	19		T157	37		T40	16
auto[0]	values[0]	values[7]	219	1			T40	9		T41	11		T19	9
auto[0]	values[1]	values[0]	261	1			T19	13		T225	2		T192	15
auto[0]	values[1]	values[1]	332	1			T13	2		T18	12		T45	25
auto[0]	values[1]	values[2]	223	1			T19	13		T180	13		T168	9
auto[0]	values[1]	values[3]	296	1			T226	4		T135	69		T227	4
auto[0]	values[1]	values[4]	272	1			T3	64		T156	12		T40	9
auto[0]	values[1]	values[5]	238	1			T59	14		T228	2		T170	10
auto[0]	values[1]	values[6]	505	1			T5	74		T39	10		T42	11
auto[0]	values[1]	values[7]	232	1			T229	6		T218	11		T176	14
auto[0]	values[2]	values[0]	198	1			T39	12		T42	16		T193	12
auto[0]	values[2]	values[1]	191	1			T18	12		T45	14		T197	16
auto[0]	values[2]	values[2]	218	1			T3	12		T19	9		T197	36
auto[0]	values[2]	values[3]	353	1			T230	6		T196	12		T195	11
auto[0]	values[2]	values[4]	256	1			T40	9		T41	11		T171	20
auto[0]	values[2]	values[5]	448	1			T39	9		T19	53		T204	26
auto[0]	values[2]	values[6]	269	1			T39	10		T18	23		T218	24
auto[0]	values[2]	values[7]	276	1			T18	13		T45	33		T191	13
auto[0]	values[3]	values[0]	239	1			T191	7		T192	10		T189	41
auto[0]	values[3]	values[1]	501	1			T18	16		T43	9		T40	54
auto[0]	values[3]	values[2]	260	1			T5	58		T176	12		T180	12
auto[0]	values[3]	values[3]	137	1			T19	15		T231	4		T192	8
auto[0]	values[3]	values[4]	144	1			T8	4		T222	2		T42	9
auto[0]	values[3]	values[5]	216	1			T44	18		T179	6		T216	14
auto[0]	values[3]	values[6]	278	1			T20	10		T23	13		T218	12
auto[0]	values[3]	values[7]	264	1			T40	12		T176	47		T177	16
auto[0]	values[4]	values[0]	341	1			T42	11		T41	10		T19	4
auto[0]	values[4]	values[1]	104	1			T196	12		T232	6		T233	11
auto[0]	values[4]	values[2]	369	1			T188	12		T23	12		T180	17
auto[0]	values[4]	values[3]	252	1			T5	11		T26	8		T218	9
auto[0]	values[4]	values[4]	234	1			T18	8		T197	15		T234	16
auto[0]	values[4]	values[5]	294	1			T41	20		T191	40		T193	13
auto[0]	values[4]	values[6]	224	1			T43	7		T235	15		T150	11
auto[0]	values[4]	values[7]	190	1			T15	6		T42	12		T176	9
auto[0]	values[5]	values[0]	273	1			T236	104		T180	7		T237	8
auto[0]	values[5]	values[1]	270	1			T41	9		T214	20		T238	2
auto[0]	values[5]	values[2]	235	1			T191	11		T180	21		T239	12
auto[0]	values[5]	values[3]	348	1			T18	7		T40	11		T193	17
auto[0]	values[5]	values[4]	389	1			T97	8		T213	13		T240	2
auto[0]	values[5]	values[5]	215	1			T5	12		T241	4		T176	14
auto[0]	values[5]	values[6]	265	1			T57	10		T40	36		T19	15
auto[0]	values[5]	values[7]	228	1			T39	9		T42	14		T176	11
auto[0]	values[6]	values[0]	234	1			T43	35		T45	7		T176	9
auto[0]	values[6]	values[1]	280	1			T242	2		T176	11		T180	14
auto[0]	values[6]	values[2]	283	1			T176	42		T168	14		T243	20
auto[0]	values[6]	values[3]	195	1			T191	17		T180	15		T244	4
auto[0]	values[6]	values[4]	368	1			T3	18		T45	27		T40	13
auto[0]	values[6]	values[5]	399	1			T40	9		T41	9		T20	15
auto[0]	values[6]	values[6]	432	1			T18	16		T45	37		T20	11
auto[0]	values[6]	values[7]	220	1			T18	8		T41	32		T217	15
auto[0]	values[7]	values[0]	390	1			T3	14		T158	4		T245	2
auto[0]	values[7]	values[1]	239	1			T5	12		T39	8		T19	23
auto[0]	values[7]	values[2]	356	1			T18	9		T188	24		T246	4
auto[0]	values[7]	values[3]	132	1			T19	14		T197	13		T189	14
auto[0]	values[7]	values[4]	222	1			T42	12		T168	10		T135	15
auto[0]	values[7]	values[5]	259	1			T43	8		T177	11		T135	9
auto[0]	values[7]	values[6]	258	1			T3	10		T5	14		T18	14
auto[0]	values[7]	values[7]	325	1			T3	21		T5	10		T41	7
auto[1]	values[0]	values[0]	345	1			T180	14		T174	15		T247	35
auto[1]	values[0]	values[1]	122	1			T18	4		T45	10		T19	9
auto[1]	values[0]	values[2]	304	1			T218	11		T180	7		T192	22
auto[1]	values[0]	values[3]	169	1			T41	15		T177	18		T193	6
auto[1]	values[0]	values[4]	196	1			T45	6		T19	10		T188	6
auto[1]	values[0]	values[5]	174	1			T5	6		T43	8		T45	10
auto[1]	values[0]	values[6]	170	1			T18	7		T40	32		T20	5
auto[1]	values[0]	values[7]	243	1			T40	47		T41	9		T19	15
auto[1]	values[1]	values[0]	130	1			T19	7		T248	18		T192	5
auto[1]	values[1]	values[1]	248	1			T18	10		T45	7		T197	8
auto[1]	values[1]	values[2]	252	1			T19	7		T180	9		T168	11
auto[1]	values[1]	values[3]	201	1			T135	5		T189	10		T182	8
auto[1]	values[1]	values[4]	376	1			T3	7		T46	10		T47	10
auto[1]	values[1]	values[5]	132	1			T184	18		T170	10		T233	7
auto[1]	values[1]	values[6]	231	1			T5	7		T39	10		T42	9
auto[1]	values[1]	values[7]	212	1			T218	9		T176	6		T168	15
auto[1]	values[2]	values[0]	162	1			T39	8		T42	4		T193	9
auto[1]	values[2]	values[1]	198	1			T18	14		T45	18		T197	24
auto[1]	values[2]	values[2]	182	1			T3	8		T19	11		T197	11
auto[1]	values[2]	values[3]	86	1			T54	18		T196	8		T195	9
auto[1]	values[2]	values[4]	178	1			T40	11		T41	11		T171	8
auto[1]	values[2]	values[5]	217	1			T39	11		T19	8		T218	39
auto[1]	values[2]	values[6]	199	1			T39	10		T18	8		T218	9
auto[1]	values[2]	values[7]	280	1			T18	7		T45	16		T191	11
auto[1]	values[3]	values[0]	191	1			T191	54		T192	10		T189	22
auto[1]	values[3]	values[1]	167	1			T18	4		T43	11		T40	6
auto[1]	values[3]	values[2]	257	1			T5	11		T176	8		T180	19
auto[1]	values[3]	values[3]	246	1			T19	5		T192	30		T193	8
auto[1]	values[3]	values[4]	164	1			T42	11		T43	13		T40	16
auto[1]	values[3]	values[5]	140	1			T237	25		T249	10		T250	9
auto[1]	values[3]	values[6]	252	1			T20	12		T210	16		T23	8
auto[1]	values[3]	values[7]	228	1			T40	63		T176	10		T177	5
auto[1]	values[4]	values[0]	310	1			T42	9		T41	10		T19	16
auto[1]	values[4]	values[1]	60	1			T196	8		T233	9		T251	2
auto[1]	values[4]	values[2]	202	1			T188	19		T23	8		T180	8
auto[1]	values[4]	values[3]	151	1			T5	19		T218	11		T196	2
auto[1]	values[4]	values[4]	164	1			T18	16		T197	5		T191	16
auto[1]	values[4]	values[5]	170	1			T41	6		T191	1		T193	10
auto[1]	values[4]	values[6]	222	1			T43	19		T235	10		T150	54
auto[1]	values[4]	values[7]	166	1			T42	8		T176	26		T195	9
auto[1]	values[5]	values[0]	172	1			T180	37		T237	33		T152	4
auto[1]	values[5]	values[1]	109	1			T41	14		T174	7		T237	11
auto[1]	values[5]	values[2]	168	1			T191	9		T180	6		T189	7
auto[1]	values[5]	values[3]	161	1			T18	15		T40	9		T193	7
auto[1]	values[5]	values[4]	202	1			T213	7		T235	86		T135	7
auto[1]	values[5]	values[5]	143	1			T5	8		T176	6		T193	15
auto[1]	values[5]	values[6]	177	1			T40	8		T19	5		T20	6
auto[1]	values[5]	values[7]	228	1			T39	11		T42	6		T176	9
auto[1]	values[6]	values[0]	196	1			T43	15		T45	41		T176	19
auto[1]	values[6]	values[1]	174	1			T176	9		T180	6		T217	6
auto[1]	values[6]	values[2]	93	1			T176	11		T168	6		T237	8
auto[1]	values[6]	values[3]	135	1			T191	6		T180	5		T202	10
auto[1]	values[6]	values[4]	246	1			T3	9		T45	9		T40	7
auto[1]	values[6]	values[5]	218	1			T40	49		T41	11		T20	7
auto[1]	values[6]	values[6]	195	1			T18	4		T45	5		T20	10
auto[1]	values[6]	values[7]	151	1			T18	12		T41	17		T217	11
auto[1]	values[7]	values[0]	253	1			T3	102		T40	2		T188	7
auto[1]	values[7]	values[1]	195	1			T5	8		T39	12		T19	17
auto[1]	values[7]	values[2]	188	1			T18	11		T188	8		T168	11
auto[1]	values[7]	values[3]	119	1			T19	6		T197	7		T189	8
auto[1]	values[7]	values[4]	181	1			T42	8		T168	10		T135	5
auto[1]	values[7]	values[5]	155	1			T43	12		T177	12		T135	11
auto[1]	values[7]	values[6]	152	1			T3	10		T5	6		T18	6
auto[1]	values[7]	values[7]	232	1			T3	12		T5	10		T41	14