Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	419	1			T5	2		T39	3		T42	2
auto[ReadAddrCrossIntoMailbox]	288	1			T5	1		T39	3		T42	1
auto[ReadAddrCrossOutOfMailbox]	294	1			T3	1		T5	2		T39	3
auto[ReadAddrCrossAllMailbox]	190	1			T5	2		T39	2		T42	2
auto[ReadAddrOutsideMailbox]	3649	1			T3	16		T5	27		T6	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2468

1

T3

5

T5

16

T6

1

auto[1]

2372

1

T3

12

T5

18

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	831	1			T3	4		T5	9		T44	2
read_ops[0x0b]	778	1			T3	3		T5	8		T6	2
read_ops[0x3b]	862	1			T3	1		T5	2		T8	2
read_ops[0x6b]	813	1			T3	4		T5	6		T39	4
read_ops[0xbb]	787	1			T5	4		T44	2		T39	5
read_ops[0xeb]	769	1			T3	5		T5	5		T39	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T39	1		T42	1		T18	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T39	1		T43	1		T40	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T39	1		T18	2		T43	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T18	1		T197	1		T218	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T45	1		T41	1		T168	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T39	1		T42	1		T43	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T5	1		T42	1		T18	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T18	1		T40	1		T171	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T3	2		T5	4		T44	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T3	2		T5	4		T44	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T18	3		T57	2		T45	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T42	1		T57	2		T204	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T18	1		T188	1		T171	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T42	1		T18	2		T40	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T18	2		T45	1		T193	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T5	1		T218	1		T168	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T18	1		T20	1		T168	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T5	1		T39	1		T188	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	289	1			T5	3		T6	1		T44	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T3	3		T5	3		T6	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T156	1		T234	2		T218	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T156	1		T41	1		T234	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T188	1		T171	1		T217	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T41	1		T21	1		T168	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T39	2		T40	1		T188	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T189	1		T233	1		T253	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T23	1		T189	1		T152	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T18	1		T218	1		T168	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	331	1			T5	2		T8	1		T158	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	345	1			T3	1		T8	1		T158	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T18	1		T57	1		T43	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T5	1		T57	1		T234	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T40	1		T20	1		T176	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T5	1		T19	1		T218	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T18	1		T45	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T18	1		T23	2		T218	3
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T190	2		T254	1		T206	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T43	1		T45	1		T218	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T3	1		T5	2		T39	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T3	3		T5	2		T39	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T18	1		T45	1		T40	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T39	1		T40	1		T171	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T18	1		T45	1		T197	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T18	1		T188	1		T218	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T41	1		T196	1		T135	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T45	3		T176	1		T135	3
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T42	1		T171	1		T227	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T23	1		T227	2		T152	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	316	1			T44	1		T39	1		T179	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T5	4		T44	1		T39	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T45	1		T19	1		T234	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T5	1		T234	1		T90	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T41	1		T150	1		T189	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T39	2		T176	1		T168	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T3	1		T5	1		T40	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T40	1		T177	1		T168	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T39	1		T19	1		T180	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T41	1		T23	1		T207	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T3	1		T5	3		T39	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T3	3		T42	2		T18	4