Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3621	1			T3	27		T5	20		T39	20
values[1]	3459	1			T5	89		T39	20		T179	6
values[2]	4019	1			T5	56		T39	20		T222	2
values[3]	4303	1			T3	136		T5	20		T42	20
values[4]	3195	1			T3	20		T5	20		T8	4
values[5]	3318	1			T6	14		T18	69		T157	37
values[6]	3762	1			T5	81		T13	2		T15	6
values[7]	4288	1			T3	104		T158	4		T39	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3440	1			T39	40		T42	20		T97	8
values[1]	3375	1			T5	46		T13	2		T26	8
values[2]	4433	1			T3	163		T44	18		T42	20
values[3]	3622	1			T39	20		T42	40		T18	57
values[4]	3587	1			T3	33		T5	70		T6	14
values[5]	3628	1			T3	71		T5	81		T158	4
values[6]	4245	1			T3	20		T5	69		T42	20
values[7]	3635	1			T5	20		T8	4		T15	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29161

1

T3

280

T5

278

T6

14

auto[1]

804

1

T3

7

T5

8

T39

9

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	446	1			T97	8		T191	59		T196	20
auto[0]	values[0]	values[1]	390	1			T45	29		T20	20		T188	22
auto[0]	values[0]	values[2]	484	1			T3	26		T89	14		T41	20
auto[0]	values[0]	values[3]	665	1			T40	129		T23	20		T193	20
auto[0]	values[0]	values[4]	308	1			T39	19		T45	20		T191	20
auto[0]	values[0]	values[5]	458	1			T40	71		T19	20		T193	22
auto[0]	values[0]	values[6]	274	1			T18	20		T57	10		T43	20
auto[0]	values[0]	values[7]	502	1			T5	20		T40	56		T152	20
auto[0]	values[1]	values[0]	371	1			T245	2		T176	20		T193	23
auto[0]	values[1]	values[1]	220	1			T43	40		T171	18		T218	20
auto[0]	values[1]	values[2]	732	1			T45	20		T41	19		T180	31
auto[0]	values[1]	values[3]	348	1			T189	27		T255	22		T152	18
auto[0]	values[1]	values[4]	391	1			T5	20		T42	20		T40	47
auto[0]	values[1]	values[5]	438	1			T39	17		T18	20		T40	44
auto[0]	values[1]	values[6]	501	1			T5	68		T45	46		T19	19
auto[0]	values[1]	values[7]	353	1			T179	6		T197	47		T168	18
auto[0]	values[2]	values[0]	510	1			T39	18		T45	30		T40	78
auto[0]	values[2]	values[1]	547	1			T5	25		T41	21		T20	20
auto[0]	values[2]	values[2]	458	1			T42	19		T184	14		T176	19
auto[0]	values[2]	values[3]	504	1			T18	25		T19	61		T176	53
auto[0]	values[2]	values[4]	438	1			T5	26		T54	18		T18	22
auto[0]	values[2]	values[5]	300	1			T222	2		T43	28		T20	20
auto[0]	values[2]	values[6]	653	1			T43	27		T19	40		T197	20
auto[0]	values[2]	values[7]	503	1			T45	42		T135	44		T256	4
auto[0]	values[3]	values[0]	435	1			T41	19		T257	16		T176	19
auto[0]	values[3]	values[1]	488	1			T5	20		T18	20		T40	59
auto[0]	values[3]	values[2]	696	1			T3	112		T18	20		T41	23
auto[0]	values[3]	values[3]	549	1			T42	20		T18	31		T191	41
auto[0]	values[3]	values[4]	378	1			T18	20		T156	12		T191	20
auto[0]	values[3]	values[5]	428	1			T43	20		T41	20		T234	16
auto[0]	values[3]	values[6]	600	1			T3	19		T168	36		T235	97
auto[0]	values[3]	values[7]	620	1			T43	18		T188	20		T171	27
auto[0]	values[4]	values[0]	347	1			T39	19		T47	8		T40	24
auto[0]	values[4]	values[1]	396	1			T26	8		T18	19		T41	23
auto[0]	values[4]	values[2]	461	1			T3	19		T44	18		T43	26
auto[0]	values[4]	values[3]	469	1			T39	20		T224	2		T45	31
auto[0]	values[4]	values[4]	454	1			T5	20		T258	6		T191	22
auto[0]	values[4]	values[5]	303	1			T18	25		T59	14		T223	12
auto[0]	values[4]	values[6]	471	1			T41	22		T197	18		T235	19
auto[0]	values[4]	values[7]	212	1			T8	4		T19	20		T21	39
auto[0]	values[5]	values[0]	511	1			T188	20		T176	57		T180	20
auto[0]	values[5]	values[1]	274	1			T188	31		T189	43		T76	8
auto[0]	values[5]	values[2]	396	1			T157	37		T19	18		T191	20
auto[0]	values[5]	values[3]	288	1			T46	8		T188	20		T168	19
auto[0]	values[5]	values[4]	427	1			T6	14		T18	22		T41	20
auto[0]	values[5]	values[5]	304	1			T18	24		T238	2		T239	12
auto[0]	values[5]	values[6]	454	1			T18	23		T19	40		T252	10
auto[0]	values[5]	values[7]	562	1			T40	81		T19	22		T218	26
auto[0]	values[6]	values[0]	439	1			T42	20		T197	38		T188	31
auto[0]	values[6]	values[1]	496	1			T13	2		T45	28		T176	20
auto[0]	values[6]	values[2]	427	1			T235	151		T217	20		T154	20
auto[0]	values[6]	values[3]	334	1			T259	6		T214	20		T196	20
auto[0]	values[6]	values[4]	395	1			T41	44		T210	16		T248	14
auto[0]	values[6]	values[5]	670	1			T5	79		T201	18		T192	33
auto[0]	values[6]	values[6]	545	1			T260	4		T180	21		T135	19
auto[0]	values[6]	values[7]	368	1			T15	6		T20	21		T176	34
auto[0]	values[7]	values[0]	291	1			T261	8		T235	20		T262	21
auto[0]	values[7]	values[1]	470	1			T40	20		T171	20		T213	16
auto[0]	values[7]	values[2]	660	1			T45	32		T191	20		T235	25
auto[0]	values[7]	values[3]	366	1			T42	20		T23	19		T218	41
auto[0]	values[7]	values[4]	682	1			T3	33		T39	18		T42	20
auto[0]	values[7]	values[5]	627	1			T3	71		T158	4		T218	91
auto[0]	values[7]	values[6]	650	1			T42	18		T40	77		T41	21
auto[0]	values[7]	values[7]	424	1			T171	30		T218	48		T135	18
auto[1]	values[0]	values[0]	12	1			T191	2		T152	1		T154	1
auto[1]	values[0]	values[1]	11	1			T20	2		T193	1		T152	2
auto[1]	values[0]	values[2]	10	1			T3	1		T20	1		T263	4
auto[1]	values[0]	values[3]	26	1			T23	1		T193	1		T135	3
auto[1]	values[0]	values[4]	5	1			T39	1		T264	1		T265	2
auto[1]	values[0]	values[5]	11	1			T40	4		T233	3		T50	3
auto[1]	values[0]	values[6]	6	1			T233	1		T266	2		T200	1
auto[1]	values[0]	values[7]	13	1			T152	3		T253	2		T267	1
auto[1]	values[1]	values[0]	12	1			T193	2		T189	1		T195	1
auto[1]	values[1]	values[1]	13	1			T43	2		T171	2		T195	2
auto[1]	values[1]	values[2]	12	1			T41	1		T152	2		T247	3
auto[1]	values[1]	values[3]	7	1			T152	2		T253	1		T268	2
auto[1]	values[1]	values[4]	20	1			T40	1		T197	1		T177	1
auto[1]	values[1]	values[5]	17	1			T39	3		T218	1		T217	1
auto[1]	values[1]	values[6]	13	1			T5	1		T45	2		T19	1
auto[1]	values[1]	values[7]	11	1			T168	2		T262	1		T189	2
auto[1]	values[2]	values[0]	16	1			T39	2		T45	6		T206	2
auto[1]	values[2]	values[1]	13	1			T5	1		T41	2		T176	1
auto[1]	values[2]	values[2]	22	1			T42	1		T184	4		T176	1
auto[1]	values[2]	values[3]	9	1			T18	1		T180	1		T247	1
auto[1]	values[2]	values[4]	12	1			T5	4		T217	1		T50	1
auto[1]	values[2]	values[5]	7	1			T217	1		T152	1		T269	2
auto[1]	values[2]	values[6]	15	1			T43	1		T189	1		T233	3
auto[1]	values[2]	values[7]	12	1			T135	2		T270	3		T269	2
auto[1]	values[3]	values[0]	16	1			T41	1		T176	1		T189	1
auto[1]	values[3]	values[1]	7	1			T150	2		T182	1		T271	2
auto[1]	values[3]	values[2]	15	1			T3	4		T41	1		T272	2
auto[1]	values[3]	values[3]	18	1			T193	1		T253	1		T273	1
auto[1]	values[3]	values[4]	13	1			T168	3		T237	2		T274	3
auto[1]	values[3]	values[5]	4	1			T182	1		T275	1		T276	2
auto[1]	values[3]	values[6]	24	1			T3	1		T168	4		T235	2
auto[1]	values[3]	values[7]	12	1			T43	2		T217	2		T206	1
auto[1]	values[4]	values[0]	12	1			T39	1		T47	2		T237	1
auto[1]	values[4]	values[1]	13	1			T18	1		T41	2		T188	3
auto[1]	values[4]	values[2]	12	1			T3	1		T180	2		T196	1
auto[1]	values[4]	values[3]	7	1			T45	1		T237	1		T275	3
auto[1]	values[4]	values[4]	11	1			T191	2		T192	4		T271	2
auto[1]	values[4]	values[5]	18	1			T18	1		T218	1		T177	1
auto[1]	values[4]	values[6]	5	1			T197	2		T235	1		T189	1
auto[1]	values[4]	values[7]	4	1			T21	1		T135	1		T233	1
auto[1]	values[5]	values[0]	6	1			T199	4		T277	1		T278	1
auto[1]	values[5]	values[1]	6	1			T188	1		T279	1		T280	2
auto[1]	values[5]	values[2]	25	1			T19	2		T180	3		T202	1
auto[1]	values[5]	values[3]	16	1			T46	2		T168	1		T269	1
auto[1]	values[5]	values[4]	8	1			T20	1		T275	2		T281	2
auto[1]	values[5]	values[5]	11	1			T206	1		T273	2		T282	4
auto[1]	values[5]	values[6]	10	1			T180	3		T170	2		T206	2
auto[1]	values[5]	values[7]	20	1			T40	1		T19	2		T218	1
auto[1]	values[6]	values[0]	5	1			T197	2		T264	3		-	-
auto[1]	values[6]	values[1]	19	1			T45	1		T49	1		T283	1
auto[1]	values[6]	values[2]	16	1			T235	2		T206	3		T284	2
auto[1]	values[6]	values[3]	8	1			T247	1		T281	2		T209	3
auto[1]	values[6]	values[4]	12	1			T41	2		T248	4		T249	2
auto[1]	values[6]	values[5]	8	1			T5	2		T250	2		T276	1
auto[1]	values[6]	values[6]	12	1			T180	1		T135	1		T190	2
auto[1]	values[6]	values[7]	8	1			T176	1		T150	2		T49	1
auto[1]	values[7]	values[0]	11	1			T237	3		T152	1		T182	1
auto[1]	values[7]	values[1]	12	1			T213	4		T177	1		T168	2
auto[1]	values[7]	values[2]	7	1			T174	1		T190	1		T182	1
auto[1]	values[7]	values[3]	8	1			T23	1		T249	1		T267	2
auto[1]	values[7]	values[4]	33	1			T39	2		T41	1		T235	4
auto[1]	values[7]	values[5]	24	1			T150	2		T237	5		T253	3
auto[1]	values[7]	values[6]	12	1			T42	2		T40	3		T193	2
auto[1]	values[7]	values[7]	11	1			T135	2		T237	1		T195	1