Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	805	1			T12	11		T14	7		T16	7
all_values[1]	805	1			T12	11		T14	7		T16	7
all_values[2]	805	1			T12	11		T14	7		T16	7
all_values[3]	805	1			T12	11		T14	7		T16	7
all_values[4]	805	1			T12	11		T14	7		T16	7
all_values[5]	805	1			T12	11		T14	7		T16	7
all_values[6]	805	1			T12	11		T14	7		T16	7
all_values[7]	805	1			T12	11		T14	7		T16	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3367

1

T12

42

T14

34

T16

29

auto[1]

3073

1

T12

46

T14

22

T16

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2583

1

T12

35

T14

22

T16

22

auto[1]

3857

1

T12

53

T14

34

T16

34

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3654

1

T12

50

T14

33

T16

33

auto[1]

2786

1

T12

38

T14

23

T16

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	158	1			T12	2		T14	2		T16	2
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T12	1		T18	1		T19	3
all_values[0]	auto[0]	auto[1]	auto[0]	145	1			T12	3		T16	2		T17	3
all_values[0]	auto[0]	auto[1]	auto[1]	77	1			T14	1		T16	1		T17	1
all_values[0]	auto[1]	auto[0]	auto[1]	183	1			T12	3		T14	2		T16	1
all_values[0]	auto[1]	auto[1]	auto[1]	168	1			T12	2		T14	2		T16	1
all_values[1]	auto[0]	auto[0]	auto[0]	173	1			T12	1		T14	3		T18	2
all_values[1]	auto[0]	auto[0]	auto[1]	87	1			T12	2		T14	1		T16	1
all_values[1]	auto[0]	auto[1]	auto[0]	143	1			T12	2		T14	1		T18	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T12	1		T16	1		T17	1
all_values[1]	auto[1]	auto[0]	auto[1]	160	1			T12	1		T14	1		T16	5
all_values[1]	auto[1]	auto[1]	auto[1]	162	1			T12	4		T14	1		T17	4
all_values[2]	auto[0]	auto[0]	auto[0]	167	1			T18	2		T19	3		T20	4
all_values[2]	auto[0]	auto[0]	auto[1]	78	1			T12	2		T14	1		T16	1
all_values[2]	auto[0]	auto[1]	auto[0]	136	1			T12	4		T17	1		T18	1
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T14	2		T16	2		T17	1
all_values[2]	auto[1]	auto[0]	auto[1]	185	1			T12	4		T14	3		T16	1
all_values[2]	auto[1]	auto[1]	auto[1]	169	1			T12	1		T14	1		T16	3
all_values[3]	auto[0]	auto[0]	auto[0]	148	1			T12	3		T16	3		T17	2
all_values[3]	auto[0]	auto[0]	auto[1]	62	1			T12	1		T14	3		T18	2
all_values[3]	auto[0]	auto[1]	auto[0]	166	1			T12	2		T16	3		T17	2
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T14	1		T17	1		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	173	1			T12	2		T14	3		T18	3
all_values[3]	auto[1]	auto[1]	auto[1]	171	1			T12	3		T16	1		T17	2
all_values[4]	auto[0]	auto[0]	auto[0]	155	1			T12	1		T14	1		T17	1
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T16	1		T18	3		T19	1
all_values[4]	auto[0]	auto[1]	auto[0]	134	1			T12	1		T14	4		T16	2
all_values[4]	auto[0]	auto[1]	auto[1]	82	1			T12	5		T16	1		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	202	1			T12	3		T14	2		T16	2
all_values[4]	auto[1]	auto[1]	auto[1]	158	1			T12	1		T16	1		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	231	1			T12	3		T14	2		T16	2
all_values[5]	auto[0]	auto[1]	auto[0]	219	1			T12	4		T14	1		T16	2
all_values[5]	auto[1]	auto[0]	auto[1]	191	1			T12	2		T14	3		T16	3
all_values[5]	auto[1]	auto[1]	auto[1]	164	1			T12	2		T14	1		T17	1
all_values[6]	auto[0]	auto[0]	auto[0]	178	1			T14	2		T16	2		T17	3
all_values[6]	auto[0]	auto[0]	auto[1]	75	1			T12	2		T18	1		T19	2
all_values[6]	auto[0]	auto[1]	auto[0]	136	1			T12	3		T14	3		T16	3
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T18	2		T19	2		T20	1
all_values[6]	auto[1]	auto[0]	auto[1]	185	1			T12	1		T14	1		T17	2
all_values[6]	auto[1]	auto[1]	auto[1]	152	1			T12	5		T14	1		T16	2
all_values[7]	auto[0]	auto[0]	auto[0]	153	1			T12	4		T14	2		T16	1
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T12	1		T16	3		T17	1
all_values[7]	auto[0]	auto[1]	auto[0]	141	1			T12	2		T14	1		T17	2
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T14	2		T18	5		T19	1
all_values[7]	auto[1]	auto[0]	auto[1]	196	1			T12	3		T14	2		T16	1
all_values[7]	auto[1]	auto[1]	auto[1]	167	1			T12	1		T16	2		T19	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal