Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1711

1

T3

2

T14

1

T27

1

auto[1]

1758

1

T3

1

T27

1

T30

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1906

1

T3

1

T14

1

T31

3

auto[1]

1563

1

T3

2

T27

2

T30

14

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2737

1

T3

3

T14

1

T27

2

auto[1]

732

1

T31

3

T16

11

T17

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	711	1			T30	4		T31	1		T16	6
valid[1]	698	1			T30	2		T31	1		T16	5
valid[2]	703	1			T3	1		T14	1		T27	1
valid[3]	678	1			T3	1		T27	1		T30	3
valid[4]	679	1			T3	1		T30	3		T16	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	120	1			T16	1		T34	1		T85	1
auto[0]	auto[0]	valid[0]	auto[1]	163	1			T30	1		T16	1		T43	1
auto[0]	auto[0]	valid[1]	auto[0]	129	1			T16	3		T17	1		T34	2
auto[0]	auto[0]	valid[1]	auto[1]	160	1			T86	2		T305	1		T306	1
auto[0]	auto[0]	valid[2]	auto[0]	116	1			T14	1		T16	1		T33	1
auto[0]	auto[0]	valid[2]	auto[1]	141	1			T30	1		T86	2		T87	1
auto[0]	auto[0]	valid[3]	auto[0]	112	1			T18	2		T85	1		T43	1
auto[0]	auto[0]	valid[3]	auto[1]	146	1			T3	1		T27	1		T30	2
auto[0]	auto[0]	valid[4]	auto[0]	112	1			T3	1		T16	1		T34	1
auto[0]	auto[0]	valid[4]	auto[1]	143	1			T43	1		T88	1		T305	2
auto[0]	auto[1]	valid[0]	auto[0]	115	1			T16	1		T34	1		T18	3
auto[0]	auto[1]	valid[0]	auto[1]	171	1			T30	3		T31	1		T86	1
auto[0]	auto[1]	valid[1]	auto[0]	112	1			T34	1		T18	1		T298	2
auto[0]	auto[1]	valid[1]	auto[1]	145	1			T30	2		T31	1		T86	1
auto[0]	auto[1]	valid[2]	auto[0]	133	1			T16	4		T17	1		T18	3
auto[0]	auto[1]	valid[2]	auto[1]	173	1			T3	1		T27	1		T30	1
auto[0]	auto[1]	valid[3]	auto[0]	119	1			T16	2		T33	1		T34	1
auto[0]	auto[1]	valid[3]	auto[1]	153	1			T30	1		T86	1		T305	2
auto[0]	auto[1]	valid[4]	auto[0]	106	1			T16	2		T18	1		T43	1
auto[0]	auto[1]	valid[4]	auto[1]	168	1			T30	3		T86	1		T88	1
auto[1]	auto[0]	valid[0]	auto[0]	70	1			T16	1		T34	1		T43	1
auto[1]	auto[0]	valid[1]	auto[0]	81	1			T16	1		T17	1		T34	1
auto[1]	auto[0]	valid[2]	auto[0]	74	1			T16	2		T88	1		T188	3
auto[1]	auto[0]	valid[3]	auto[0]	73	1			T31	1		T16	3		T18	2
auto[1]	auto[0]	valid[4]	auto[0]	71	1			T34	2		T185	1		T21	2
auto[1]	auto[1]	valid[0]	auto[0]	72	1			T16	2		T18	1		T298	1
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T16	1		T33	1		T34	1
auto[1]	auto[1]	valid[2]	auto[0]	66	1			T18	1		T19	1		T79	1
auto[1]	auto[1]	valid[3]	auto[0]	75	1			T31	2		T34	1		T41	1
auto[1]	auto[1]	valid[4]	auto[0]	79	1			T16	1		T34	2		T185	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal