Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47724

1

T3

64

T4

3

T14

27

auto[1]

16364

1

T3

18

T27

2

T30

162

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46667

1

T3

51

T4

1

T14

21

auto[1]

17421

1

T3

31

T4

2

T14

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32966	1			T3	42		T4	3		T14	8
others[1]	5384	1			T3	5		T14	3		T30	9
others[2]	5294	1			T3	7		T30	11		T31	12
others[3]	6214	1			T3	9		T14	5		T30	16
interest[1]	3599	1			T3	9		T14	4		T30	9
interest[4]	21493	1			T3	21		T4	2		T14	8
interest[64]	10631	1			T3	10		T14	7		T30	32

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15438	1			T3	14		T4	1		T14	8
auto[0]	auto[0]	others[1]	2605	1			T3	2		T14	2		T31	7
auto[0]	auto[0]	others[2]	2559	1			T3	3		T31	5		T16	29
auto[0]	auto[0]	others[3]	2897	1			T3	5		T14	5		T31	8
auto[0]	auto[0]	interest[1]	1783	1			T3	4		T14	1		T31	8
auto[0]	auto[0]	interest[4]	10155	1			T3	7		T4	1		T14	8
auto[0]	auto[0]	interest[64]	5021	1			T3	5		T14	5		T31	9
auto[0]	auto[1]	others[0]	8569	1			T3	12		T27	2		T30	85
auto[0]	auto[1]	others[1]	1325	1			T3	1		T30	9		T31	1
auto[0]	auto[1]	others[2]	1303	1			T3	1		T30	11		T31	4
auto[0]	auto[1]	others[3]	1546	1			T3	1		T30	16		T31	5
auto[0]	auto[1]	interest[1]	911	1			T3	2		T30	9		T31	1
auto[0]	auto[1]	interest[4]	5622	1			T3	6		T27	2		T30	61
auto[0]	auto[1]	interest[64]	2710	1			T3	1		T30	32		T31	2
auto[1]	auto[0]	others[0]	8959	1			T3	16		T4	2		T31	15
auto[1]	auto[0]	others[1]	1454	1			T3	2		T14	1		T31	3
auto[1]	auto[0]	others[2]	1432	1			T3	3		T31	3		T16	27
auto[1]	auto[0]	others[3]	1771	1			T3	3		T31	3		T16	20
auto[1]	auto[0]	interest[1]	905	1			T3	3		T14	3		T31	2
auto[1]	auto[0]	interest[4]	5716	1			T3	8		T4	1		T31	10
auto[1]	auto[0]	interest[64]	2900	1			T3	4		T14	2		T31	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal