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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.21 95.45 99.26


Total test records in report: 1129
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T148 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.328720405 Jul 02 07:52:36 AM PDT 24 Jul 02 07:52:51 AM PDT 24 96027121 ps
T1029 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3377308857 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:40 AM PDT 24 121093031 ps
T1030 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2964672241 Jul 02 07:52:37 AM PDT 24 Jul 02 07:52:49 AM PDT 24 15030216 ps
T128 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1253162084 Jul 02 07:52:26 AM PDT 24 Jul 02 07:52:38 AM PDT 24 146150262 ps
T149 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4099591314 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:38 AM PDT 24 119695834 ps
T1031 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3788950254 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:34 AM PDT 24 25234645 ps
T113 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4075597683 Jul 02 07:52:12 AM PDT 24 Jul 02 07:52:15 AM PDT 24 50829810 ps
T1032 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2774749380 Jul 02 07:52:21 AM PDT 24 Jul 02 07:52:35 AM PDT 24 4034903149 ps
T82 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1451250368 Jul 02 07:52:21 AM PDT 24 Jul 02 07:52:24 AM PDT 24 326871482 ps
T1033 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.890940075 Jul 02 07:52:36 AM PDT 24 Jul 02 07:52:52 AM PDT 24 51368859 ps
T105 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.436470678 Jul 02 07:52:32 AM PDT 24 Jul 02 07:52:47 AM PDT 24 223781420 ps
T1034 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1806240358 Jul 02 07:52:43 AM PDT 24 Jul 02 07:52:54 AM PDT 24 17651988 ps
T109 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3019969678 Jul 02 07:52:28 AM PDT 24 Jul 02 07:52:45 AM PDT 24 270219704 ps
T1035 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.281497954 Jul 02 07:52:31 AM PDT 24 Jul 02 07:52:45 AM PDT 24 51909068 ps
T159 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.757554142 Jul 02 07:52:31 AM PDT 24 Jul 02 07:52:59 AM PDT 24 686644133 ps
T1036 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1988867736 Jul 02 07:52:42 AM PDT 24 Jul 02 07:52:54 AM PDT 24 13096550 ps
T1037 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2079468617 Jul 02 07:52:39 AM PDT 24 Jul 02 07:52:51 AM PDT 24 35507768 ps
T1038 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3213946432 Jul 02 07:52:43 AM PDT 24 Jul 02 07:52:54 AM PDT 24 23730014 ps
T1039 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1367663000 Jul 02 07:52:33 AM PDT 24 Jul 02 07:52:48 AM PDT 24 82478864 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1260388360 Jul 02 07:52:23 AM PDT 24 Jul 02 07:52:31 AM PDT 24 12874274 ps
T112 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1671704000 Jul 02 07:52:31 AM PDT 24 Jul 02 07:52:47 AM PDT 24 172546570 ps
T1041 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1256076317 Jul 02 07:52:33 AM PDT 24 Jul 02 07:52:48 AM PDT 24 74277843 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.469578273 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:37 AM PDT 24 65616854 ps
T1043 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2476505765 Jul 02 07:52:39 AM PDT 24 Jul 02 07:52:52 AM PDT 24 13813254 ps
T1044 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3090467383 Jul 02 07:52:28 AM PDT 24 Jul 02 07:52:43 AM PDT 24 59793175 ps
T1045 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1291943365 Jul 02 07:52:32 AM PDT 24 Jul 02 07:52:46 AM PDT 24 18739191 ps
T106 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3074383132 Jul 02 07:52:29 AM PDT 24 Jul 02 07:52:46 AM PDT 24 284762505 ps
T1046 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3490004717 Jul 02 07:52:33 AM PDT 24 Jul 02 07:52:47 AM PDT 24 444719323 ps
T1047 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2188661738 Jul 02 07:52:39 AM PDT 24 Jul 02 07:52:54 AM PDT 24 84670688 ps
T1048 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4236952192 Jul 02 07:52:32 AM PDT 24 Jul 02 07:52:47 AM PDT 24 48112882 ps
T1049 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3979719040 Jul 02 07:52:36 AM PDT 24 Jul 02 07:52:53 AM PDT 24 431875076 ps
T1050 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1766501772 Jul 02 07:52:26 AM PDT 24 Jul 02 07:52:42 AM PDT 24 311859719 ps
T1051 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.766253340 Jul 02 07:52:31 AM PDT 24 Jul 02 07:52:44 AM PDT 24 38499791 ps
T129 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1628851441 Jul 02 07:52:36 AM PDT 24 Jul 02 07:52:51 AM PDT 24 81324514 ps
T1052 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.32878190 Jul 02 07:52:38 AM PDT 24 Jul 02 07:52:50 AM PDT 24 48532563 ps
T107 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1299284077 Jul 02 07:52:23 AM PDT 24 Jul 02 07:52:31 AM PDT 24 310101268 ps
T1053 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2679388835 Jul 02 07:52:39 AM PDT 24 Jul 02 07:52:51 AM PDT 24 13010161 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2711941321 Jul 02 07:52:22 AM PDT 24 Jul 02 07:52:26 AM PDT 24 22766957 ps
T1055 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.106504402 Jul 02 07:52:48 AM PDT 24 Jul 02 07:52:57 AM PDT 24 27348662 ps
T1056 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1505855719 Jul 02 07:52:21 AM PDT 24 Jul 02 07:52:23 AM PDT 24 35665450 ps
T108 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2213936947 Jul 02 07:52:35 AM PDT 24 Jul 02 07:52:52 AM PDT 24 418501805 ps
T1057 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1017320721 Jul 02 07:52:33 AM PDT 24 Jul 02 07:52:47 AM PDT 24 241200642 ps
T166 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3559594372 Jul 02 07:52:29 AM PDT 24 Jul 02 07:52:50 AM PDT 24 280480652 ps
T1058 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1297840758 Jul 02 07:52:22 AM PDT 24 Jul 02 07:52:35 AM PDT 24 400222922 ps
T1059 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1238916583 Jul 02 07:52:38 AM PDT 24 Jul 02 07:52:51 AM PDT 24 51863176 ps
T1060 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4034753772 Jul 02 07:52:34 AM PDT 24 Jul 02 07:52:50 AM PDT 24 100710615 ps
T160 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.240085894 Jul 02 07:52:29 AM PDT 24 Jul 02 07:52:55 AM PDT 24 207952598 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.863659398 Jul 02 07:52:13 AM PDT 24 Jul 02 07:52:16 AM PDT 24 15201287 ps
T1062 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3716335409 Jul 02 07:52:43 AM PDT 24 Jul 02 07:52:54 AM PDT 24 30351622 ps
T1063 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2357592491 Jul 02 07:52:41 AM PDT 24 Jul 02 07:52:52 AM PDT 24 43617945 ps
T83 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3508151778 Jul 02 07:52:31 AM PDT 24 Jul 02 07:52:45 AM PDT 24 194771744 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2349203233 Jul 02 07:52:23 AM PDT 24 Jul 02 07:52:37 AM PDT 24 391595670 ps
T1065 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2953992168 Jul 02 07:52:22 AM PDT 24 Jul 02 07:52:30 AM PDT 24 215537137 ps
T1066 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1845144961 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:33 AM PDT 24 171315229 ps
T1067 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3751013294 Jul 02 07:52:22 AM PDT 24 Jul 02 07:52:29 AM PDT 24 38514816 ps
T1068 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2876428066 Jul 02 07:52:39 AM PDT 24 Jul 02 07:52:51 AM PDT 24 27691610 ps
T1069 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3783258172 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:36 AM PDT 24 17429548 ps
T1070 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3599626507 Jul 02 07:52:30 AM PDT 24 Jul 02 07:52:49 AM PDT 24 376190782 ps
T111 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3351071393 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:36 AM PDT 24 344567401 ps
T1071 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.209046351 Jul 02 07:52:32 AM PDT 24 Jul 02 07:52:49 AM PDT 24 57183894 ps
T1072 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.218817123 Jul 02 07:52:33 AM PDT 24 Jul 02 07:52:48 AM PDT 24 26417974 ps
T130 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3413650888 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:37 AM PDT 24 196099920 ps
T114 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3553852 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:38 AM PDT 24 273971856 ps
T1073 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4024657844 Jul 02 07:52:41 AM PDT 24 Jul 02 07:52:53 AM PDT 24 11647460 ps
T1074 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3043574257 Jul 02 07:52:47 AM PDT 24 Jul 02 07:52:57 AM PDT 24 132329876 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2327682138 Jul 02 07:52:26 AM PDT 24 Jul 02 07:52:40 AM PDT 24 27468401 ps
T1076 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1637800082 Jul 02 07:52:36 AM PDT 24 Jul 02 07:52:50 AM PDT 24 55009196 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1533492973 Jul 02 07:52:30 AM PDT 24 Jul 02 07:52:45 AM PDT 24 153332724 ps
T1078 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1389743711 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:37 AM PDT 24 766412056 ps
T1079 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4147918264 Jul 02 07:52:14 AM PDT 24 Jul 02 07:52:19 AM PDT 24 161317525 ps
T1080 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.596535288 Jul 02 07:52:34 AM PDT 24 Jul 02 07:52:48 AM PDT 24 89409617 ps
T1081 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2768138660 Jul 02 07:52:34 AM PDT 24 Jul 02 07:52:48 AM PDT 24 14281197 ps
T1082 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1643570760 Jul 02 07:52:39 AM PDT 24 Jul 02 07:52:52 AM PDT 24 18170660 ps
T131 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1470453027 Jul 02 07:52:23 AM PDT 24 Jul 02 07:52:31 AM PDT 24 75198547 ps
T1083 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2976736727 Jul 02 07:52:43 AM PDT 24 Jul 02 07:52:54 AM PDT 24 35759817 ps
T163 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1757241028 Jul 02 07:52:35 AM PDT 24 Jul 02 07:53:06 AM PDT 24 828470388 ps
T1084 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2215782495 Jul 02 07:52:41 AM PDT 24 Jul 02 07:52:53 AM PDT 24 39535841 ps
T1085 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2531615966 Jul 02 07:52:31 AM PDT 24 Jul 02 07:52:47 AM PDT 24 143722369 ps
T1086 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4057381699 Jul 02 07:52:30 AM PDT 24 Jul 02 07:52:45 AM PDT 24 131041858 ps
T1087 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4074204992 Jul 02 07:52:23 AM PDT 24 Jul 02 07:52:33 AM PDT 24 193132317 ps
T1088 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1160405468 Jul 02 07:52:32 AM PDT 24 Jul 02 07:52:46 AM PDT 24 16567550 ps
T1089 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1720563730 Jul 02 07:52:33 AM PDT 24 Jul 02 07:52:54 AM PDT 24 1772090225 ps
T1090 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3199897315 Jul 02 07:52:37 AM PDT 24 Jul 02 07:52:52 AM PDT 24 595468482 ps
T164 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.558698564 Jul 02 07:52:26 AM PDT 24 Jul 02 07:52:51 AM PDT 24 2248655529 ps
T1091 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3596871682 Jul 02 07:52:30 AM PDT 24 Jul 02 07:52:46 AM PDT 24 217520662 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3270509710 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:44 AM PDT 24 1289559569 ps
T1093 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3109667626 Jul 02 07:52:30 AM PDT 24 Jul 02 07:52:50 AM PDT 24 981036118 ps
T1094 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.646150171 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:32 AM PDT 24 51949430 ps
T1095 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2263593630 Jul 02 07:52:40 AM PDT 24 Jul 02 07:52:52 AM PDT 24 109620088 ps
T1096 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3183829909 Jul 02 07:52:34 AM PDT 24 Jul 02 07:52:49 AM PDT 24 79755777 ps
T1097 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2745153638 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:34 AM PDT 24 46605993 ps
T1098 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1815304388 Jul 02 07:52:42 AM PDT 24 Jul 02 07:52:53 AM PDT 24 13812357 ps
T1099 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2024536224 Jul 02 07:52:38 AM PDT 24 Jul 02 07:52:50 AM PDT 24 44788865 ps
T1100 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3567088072 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:49 AM PDT 24 673086796 ps
T1101 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1575213795 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:38 AM PDT 24 28821195 ps
T165 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1506874781 Jul 02 07:52:35 AM PDT 24 Jul 02 07:53:03 AM PDT 24 603839084 ps
T1102 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1537186864 Jul 02 07:52:25 AM PDT 24 Jul 02 07:52:36 AM PDT 24 13482672 ps
T1103 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3675874494 Jul 02 07:52:15 AM PDT 24 Jul 02 07:52:27 AM PDT 24 190326271 ps
T1104 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2635373795 Jul 02 07:52:30 AM PDT 24 Jul 02 07:52:43 AM PDT 24 30847710 ps
T132 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.558522099 Jul 02 07:52:34 AM PDT 24 Jul 02 07:52:49 AM PDT 24 253847736 ps
T1105 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4252224871 Jul 02 07:52:32 AM PDT 24 Jul 02 07:52:46 AM PDT 24 175412993 ps
T1106 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2895166459 Jul 02 07:52:39 AM PDT 24 Jul 02 07:52:52 AM PDT 24 15873564 ps
T1107 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.80150792 Jul 02 07:52:26 AM PDT 24 Jul 02 07:52:39 AM PDT 24 57670816 ps
T84 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4096291930 Jul 02 07:52:33 AM PDT 24 Jul 02 07:52:47 AM PDT 24 42189092 ps
T161 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.547203482 Jul 02 07:52:34 AM PDT 24 Jul 02 07:52:53 AM PDT 24 220229867 ps
T133 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1370275117 Jul 02 07:52:26 AM PDT 24 Jul 02 07:52:39 AM PDT 24 68237085 ps
T1108 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2431597840 Jul 02 07:52:35 AM PDT 24 Jul 02 07:52:49 AM PDT 24 155744870 ps
T1109 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3185815914 Jul 02 07:52:33 AM PDT 24 Jul 02 07:52:48 AM PDT 24 30132149 ps
T1110 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3145824735 Jul 02 07:52:41 AM PDT 24 Jul 02 07:52:53 AM PDT 24 141461897 ps
T162 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2147386309 Jul 02 07:52:34 AM PDT 24 Jul 02 07:53:01 AM PDT 24 1096399217 ps
T1111 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2629371311 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:35 AM PDT 24 379106359 ps
T1112 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.276959409 Jul 02 07:52:36 AM PDT 24 Jul 02 07:52:49 AM PDT 24 16884119 ps
T1113 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.682475969 Jul 02 07:52:32 AM PDT 24 Jul 02 07:52:48 AM PDT 24 378007227 ps
T1114 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1555610828 Jul 02 07:52:26 AM PDT 24 Jul 02 07:52:37 AM PDT 24 71260146 ps
T1115 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1410628129 Jul 02 07:52:36 AM PDT 24 Jul 02 07:52:50 AM PDT 24 135914698 ps
T1116 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1259733948 Jul 02 07:52:39 AM PDT 24 Jul 02 07:52:52 AM PDT 24 25854875 ps
T1117 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4018528375 Jul 02 07:52:23 AM PDT 24 Jul 02 07:52:38 AM PDT 24 562221164 ps
T1118 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.807624831 Jul 02 07:52:40 AM PDT 24 Jul 02 07:52:52 AM PDT 24 14163284 ps
T1119 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.671428162 Jul 02 07:52:39 AM PDT 24 Jul 02 07:52:54 AM PDT 24 140181782 ps
T1120 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.549141186 Jul 02 07:52:34 AM PDT 24 Jul 02 07:52:50 AM PDT 24 306383350 ps
T1121 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3183137926 Jul 02 07:52:33 AM PDT 24 Jul 02 07:52:52 AM PDT 24 418232838 ps
T1122 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1220142677 Jul 02 07:52:29 AM PDT 24 Jul 02 07:52:43 AM PDT 24 14432218 ps
T1123 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1968450006 Jul 02 07:52:32 AM PDT 24 Jul 02 07:52:47 AM PDT 24 267415521 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3040947497 Jul 02 07:52:26 AM PDT 24 Jul 02 07:52:53 AM PDT 24 805938887 ps
T1125 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2326618130 Jul 02 07:52:23 AM PDT 24 Jul 02 07:52:53 AM PDT 24 814734936 ps
T1126 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.810412109 Jul 02 07:52:24 AM PDT 24 Jul 02 07:52:35 AM PDT 24 63760533 ps
T1127 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1211983942 Jul 02 07:52:52 AM PDT 24 Jul 02 07:52:58 AM PDT 24 34948714 ps
T1128 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3356242409 Jul 02 07:52:36 AM PDT 24 Jul 02 07:52:53 AM PDT 24 846215126 ps
T1129 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2976240369 Jul 02 07:52:28 AM PDT 24 Jul 02 07:52:42 AM PDT 24 51002086 ps

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1452987710
Short name T3
Test name
Test status
Simulation time 3056211690 ps
CPU time 56.88 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:55:21 AM PDT 24
Peak memory 254852 kb
Host smart-5b5fc4d5-604f-4c54-b38a-0705ad1152cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452987710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1452987710
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.707925596
Short name T16
Test name
Test status
Simulation time 58608485125 ps
CPU time 531.36 seconds
Started Jul 02 07:53:50 AM PDT 24
Finished Jul 02 08:02:45 AM PDT 24
Peak memory 273748 kb
Host smart-91602f12-8bd0-4c92-a9a0-cea879fdd845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707925596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.707925596
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1552247968
Short name T18
Test name
Test status
Simulation time 29340567146 ps
CPU time 352.16 seconds
Started Jul 02 07:53:39 AM PDT 24
Finished Jul 02 07:59:33 AM PDT 24
Peak memory 255984 kb
Host smart-6a35d514-096b-462f-8e11-21af7ad27013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552247968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1552247968
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2988324006
Short name T99
Test name
Test status
Simulation time 661025386 ps
CPU time 4.01 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:52:41 AM PDT 24
Peak memory 218084 kb
Host smart-f47cf313-f3ba-4e19-9dd2-308c89e5f6bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988324006 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2988324006
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1056547389
Short name T152
Test name
Test status
Simulation time 87100088873 ps
CPU time 989.66 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 08:10:53 AM PDT 24
Peak memory 298380 kb
Host smart-18941343-6033-4ae2-b3a9-3b5bf581fdc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056547389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1056547389
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2503282589
Short name T64
Test name
Test status
Simulation time 33916333 ps
CPU time 0.8 seconds
Started Jul 02 07:53:18 AM PDT 24
Finished Jul 02 07:53:20 AM PDT 24
Peak memory 215964 kb
Host smart-54a6de38-e5ea-4b29-806c-db346a97b900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503282589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2503282589
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2011643814
Short name T22
Test name
Test status
Simulation time 143218401782 ps
CPU time 138.7 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:57:09 AM PDT 24
Peak memory 249172 kb
Host smart-9cfa19a2-baf2-4961-9918-08fc4aa96ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011643814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2011643814
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1433680556
Short name T188
Test name
Test status
Simulation time 17976083846 ps
CPU time 93.96 seconds
Started Jul 02 07:55:36 AM PDT 24
Finished Jul 02 07:57:28 AM PDT 24
Peak memory 251308 kb
Host smart-f1de6f09-17af-4d0b-83e3-9f77caa6f3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433680556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1433680556
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3636422058
Short name T40
Test name
Test status
Simulation time 90880989648 ps
CPU time 227.94 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:59:03 AM PDT 24
Peak memory 269076 kb
Host smart-909ff604-65b5-42ee-ad49-c2309c4e4ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636422058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3636422058
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2453869246
Short name T2
Test name
Test status
Simulation time 123365081 ps
CPU time 4.71 seconds
Started Jul 02 07:53:52 AM PDT 24
Finished Jul 02 07:54:02 AM PDT 24
Peak memory 224388 kb
Host smart-aece6586-bac1-474d-bce5-6cf37c374d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453869246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2453869246
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2470438437
Short name T189
Test name
Test status
Simulation time 887015127508 ps
CPU time 1166.92 seconds
Started Jul 02 07:53:30 AM PDT 24
Finished Jul 02 08:12:59 AM PDT 24
Peak memory 282012 kb
Host smart-2931e94d-bbe1-4a17-b956-c4ddbc69f22d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470438437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2470438437
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3469813801
Short name T118
Test name
Test status
Simulation time 2900492555 ps
CPU time 16.85 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:42 AM PDT 24
Peak memory 215992 kb
Host smart-ab27cc8b-086e-43a1-9481-8a37261a408b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469813801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3469813801
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2253862329
Short name T329
Test name
Test status
Simulation time 49836098 ps
CPU time 0.71 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 205428 kb
Host smart-eb02e7ea-d0e6-40f5-befb-d508172a2513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253862329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
253862329
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2375628025
Short name T176
Test name
Test status
Simulation time 11150767572 ps
CPU time 146.33 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 260360 kb
Host smart-9f6bdcf7-1984-4008-96af-f3d4aa70de46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375628025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2375628025
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3719670035
Short name T41
Test name
Test status
Simulation time 225351422693 ps
CPU time 475.67 seconds
Started Jul 02 07:55:23 AM PDT 24
Finished Jul 02 08:03:36 AM PDT 24
Peak memory 265544 kb
Host smart-d673d1a6-39f5-48a9-a564-105b9ab0d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719670035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3719670035
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3860335784
Short name T233
Test name
Test status
Simulation time 47285790885 ps
CPU time 155.42 seconds
Started Jul 02 07:54:43 AM PDT 24
Finished Jul 02 07:57:20 AM PDT 24
Peak memory 270712 kb
Host smart-99322f1c-5ede-4e71-8199-5567e5e33a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860335784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3860335784
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1451250368
Short name T82
Test name
Test status
Simulation time 326871482 ps
CPU time 1.42 seconds
Started Jul 02 07:52:21 AM PDT 24
Finished Jul 02 07:52:24 AM PDT 24
Peak memory 207360 kb
Host smart-b32816ca-f77c-42fc-9f7e-0729ebed019e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451250368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1451250368
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1623948338
Short name T102
Test name
Test status
Simulation time 1174362666 ps
CPU time 3.18 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 216064 kb
Host smart-10136d78-095d-4355-b0ff-959bda757fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623948338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1623948338
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.395808500
Short name T34
Test name
Test status
Simulation time 26945047452 ps
CPU time 117.94 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 255060 kb
Host smart-fb235bb2-fa53-4396-8f26-2687237e2685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395808500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.395808500
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3080859408
Short name T23
Test name
Test status
Simulation time 3265602891 ps
CPU time 53.76 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:56:06 AM PDT 24
Peak memory 225168 kb
Host smart-45df3c32-94d6-481a-940f-27d0b2d19881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080859408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3080859408
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1165379023
Short name T180
Test name
Test status
Simulation time 42457840546 ps
CPU time 327.89 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:59:50 AM PDT 24
Peak memory 264652 kb
Host smart-407ac849-e0ce-4067-a001-f94408784563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165379023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1165379023
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.170055280
Short name T65
Test name
Test status
Simulation time 63333104 ps
CPU time 1.07 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:53:29 AM PDT 24
Peak memory 236348 kb
Host smart-b2738d21-8673-41fa-bae8-d64efbda579e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170055280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.170055280
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3589608583
Short name T39
Test name
Test status
Simulation time 26921860479 ps
CPU time 122.27 seconds
Started Jul 02 07:55:37 AM PDT 24
Finished Jul 02 07:57:58 AM PDT 24
Peak memory 251956 kb
Host smart-2fdec1eb-ed3d-4ce9-bc95-6793cc03c1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589608583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3589608583
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1322206354
Short name T206
Test name
Test status
Simulation time 55637975898 ps
CPU time 382.97 seconds
Started Jul 02 07:54:19 AM PDT 24
Finished Jul 02 08:00:52 AM PDT 24
Peak memory 268344 kb
Host smart-cc10bf5c-ad70-4ed5-8b91-98145da8649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322206354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1322206354
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3292082803
Short name T35
Test name
Test status
Simulation time 55933183288 ps
CPU time 146.92 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:58:11 AM PDT 24
Peak memory 251648 kb
Host smart-05eac03b-0d26-4cc9-8669-b8e6742f957d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292082803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3292082803
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1287709772
Short name T277
Test name
Test status
Simulation time 25305065537 ps
CPU time 373.35 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 08:00:25 AM PDT 24
Peak memory 281948 kb
Host smart-e0a2a70e-dd9a-49ae-9b17-93ef00dce411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287709772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1287709772
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1437733338
Short name T195
Test name
Test status
Simulation time 4015036668 ps
CPU time 91.47 seconds
Started Jul 02 07:53:42 AM PDT 24
Finished Jul 02 07:55:14 AM PDT 24
Peak memory 265468 kb
Host smart-7e45d72e-81c8-4781-8dd6-68055e2167b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437733338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1437733338
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1023236103
Short name T250
Test name
Test status
Simulation time 28444436389 ps
CPU time 129.36 seconds
Started Jul 02 07:54:03 AM PDT 24
Finished Jul 02 07:56:19 AM PDT 24
Peak memory 238412 kb
Host smart-b6baf9e2-a506-44ab-bddb-a70be9bac386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023236103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1023236103
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2844632600
Short name T271
Test name
Test status
Simulation time 17266738525 ps
CPU time 257.7 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:58:38 AM PDT 24
Peak memory 266280 kb
Host smart-734feaac-50b7-409d-b25b-74a4c0d1fe4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844632600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2844632600
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3351071393
Short name T111
Test name
Test status
Simulation time 344567401 ps
CPU time 4.01 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:36 AM PDT 24
Peak memory 215788 kb
Host smart-cdb11dc3-edbb-43ec-b561-191a82422ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351071393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
351071393
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1160176606
Short name T182
Test name
Test status
Simulation time 70363183426 ps
CPU time 219.46 seconds
Started Jul 02 07:55:29 AM PDT 24
Finished Jul 02 07:59:25 AM PDT 24
Peak memory 273376 kb
Host smart-057a8442-9ff5-4495-bc31-62bef7f736fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160176606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1160176606
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.132943887
Short name T135
Test name
Test status
Simulation time 11470480094 ps
CPU time 179.91 seconds
Started Jul 02 07:55:35 AM PDT 24
Finished Jul 02 07:58:53 AM PDT 24
Peak memory 272964 kb
Host smart-e0a158ec-942a-405b-bb28-3c2366e284c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132943887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.132943887
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.32344515
Short name T326
Test name
Test status
Simulation time 3180856435 ps
CPU time 3.11 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:26 AM PDT 24
Peak memory 216296 kb
Host smart-0c8d687e-539c-40a3-8dff-aeb0d2f31d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32344515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.32344515
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.774461985
Short name T289
Test name
Test status
Simulation time 238649726 ps
CPU time 11.69 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:55:56 AM PDT 24
Peak memory 232188 kb
Host smart-e7efa2ed-a6ee-4353-84ad-320e00f01b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774461985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.774461985
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2952753869
Short name T5
Test name
Test status
Simulation time 162786456697 ps
CPU time 253.29 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:59:24 AM PDT 24
Peak memory 253068 kb
Host smart-a54232aa-0485-4d85-9dfc-6b0b284dd167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952753869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2952753869
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2147386309
Short name T162
Test name
Test status
Simulation time 1096399217 ps
CPU time 14.92 seconds
Started Jul 02 07:52:34 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 215744 kb
Host smart-f5777412-3a61-4053-ae28-99458553a4c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147386309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2147386309
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.240085894
Short name T160
Test name
Test status
Simulation time 207952598 ps
CPU time 13 seconds
Started Jul 02 07:52:29 AM PDT 24
Finished Jul 02 07:52:55 AM PDT 24
Peak memory 215852 kb
Host smart-2325de8e-a8bd-4f06-a691-2494e0ed8997
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240085894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.240085894
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.711332008
Short name T168
Test name
Test status
Simulation time 137900921262 ps
CPU time 263.94 seconds
Started Jul 02 07:53:32 AM PDT 24
Finished Jul 02 07:57:57 AM PDT 24
Peak memory 265104 kb
Host smart-669c5588-c5ba-4893-b08e-37b5a8778b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711332008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
711332008
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3668044388
Short name T193
Test name
Test status
Simulation time 71606435186 ps
CPU time 569.18 seconds
Started Jul 02 07:55:40 AM PDT 24
Finished Jul 02 08:05:29 AM PDT 24
Peak memory 265572 kb
Host smart-ad7bb979-2b55-4168-91ce-607b4dc59dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668044388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3668044388
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1026592981
Short name T93
Test name
Test status
Simulation time 33106642829 ps
CPU time 212.25 seconds
Started Jul 02 07:53:19 AM PDT 24
Finished Jul 02 07:56:52 AM PDT 24
Peak memory 250176 kb
Host smart-07c9fd04-f7be-4dca-adac-c982b00099fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026592981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1026592981
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2326618130
Short name T1125
Test name
Test status
Simulation time 814734936 ps
CPU time 22.88 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 215668 kb
Host smart-cd1ef564-2921-4424-a8b7-11c60d30280f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326618130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2326618130
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1733575168
Short name T197
Test name
Test status
Simulation time 75011885604 ps
CPU time 301.04 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:58:27 AM PDT 24
Peak memory 250628 kb
Host smart-d6fd2794-9690-4556-9299-659fb0ed13ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733575168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1733575168
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2210583295
Short name T247
Test name
Test status
Simulation time 3417845593 ps
CPU time 64.31 seconds
Started Jul 02 07:54:19 AM PDT 24
Finished Jul 02 07:55:33 AM PDT 24
Peak memory 252968 kb
Host smart-6176a107-8030-4892-ab99-7a2e528f9ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210583295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2210583295
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2372676739
Short name T275
Test name
Test status
Simulation time 4710251984 ps
CPU time 100.31 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:56:00 AM PDT 24
Peak memory 256508 kb
Host smart-55ac8ce9-37bc-4689-a1c0-c0d488b6e69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372676739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2372676739
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1811742730
Short name T912
Test name
Test status
Simulation time 48266343958 ps
CPU time 121.07 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:56:19 AM PDT 24
Peak memory 254712 kb
Host smart-42e7e75c-aa89-43ef-8eaa-5c661cb9d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811742730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1811742730
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.665312699
Short name T307
Test name
Test status
Simulation time 1324303370 ps
CPU time 13.74 seconds
Started Jul 02 07:54:21 AM PDT 24
Finished Jul 02 07:54:44 AM PDT 24
Peak memory 218020 kb
Host smart-fde2e736-3a73-40d4-a56e-f4cd50598557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665312699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.665312699
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1588698760
Short name T286
Test name
Test status
Simulation time 1203926740 ps
CPU time 15.65 seconds
Started Jul 02 07:54:54 AM PDT 24
Finished Jul 02 07:55:15 AM PDT 24
Peak memory 232632 kb
Host smart-be739c71-2983-489b-a315-ec7bed8b744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588698760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1588698760
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3553852
Short name T114
Test name
Test status
Simulation time 273971856 ps
CPU time 4.69 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:38 AM PDT 24
Peak memory 216804 kb
Host smart-90886b1f-eeb4-40a0-b679-485da95ad5ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3553852
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3869462512
Short name T54
Test name
Test status
Simulation time 1964312481 ps
CPU time 6.7 seconds
Started Jul 02 07:53:17 AM PDT 24
Finished Jul 02 07:53:25 AM PDT 24
Peak memory 232568 kb
Host smart-097f9bb2-f9ba-4577-ac41-23265f995e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869462512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3869462512
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1475316601
Short name T94
Test name
Test status
Simulation time 43761954825 ps
CPU time 158.9 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:56:05 AM PDT 24
Peak memory 252544 kb
Host smart-c3ca45b6-357c-4983-958e-59f590a87436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475316601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1475316601
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3270509710
Short name T1092
Test name
Test status
Simulation time 1289559569 ps
CPU time 8.65 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:44 AM PDT 24
Peak memory 215584 kb
Host smart-265c63d0-4080-457f-b04c-01547200c094
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270509710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3270509710
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3675874494
Short name T1103
Test name
Test status
Simulation time 190326271 ps
CPU time 10.72 seconds
Started Jul 02 07:52:15 AM PDT 24
Finished Jul 02 07:52:27 AM PDT 24
Peak memory 207292 kb
Host smart-cb0b1d90-4861-4ec2-9385-0866c9216b51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675874494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3675874494
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4075597683
Short name T113
Test name
Test status
Simulation time 50829810 ps
CPU time 2.01 seconds
Started Jul 02 07:52:12 AM PDT 24
Finished Jul 02 07:52:15 AM PDT 24
Peak memory 216784 kb
Host smart-e122621a-8eb9-4284-8960-c222e7cff2c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075597683 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4075597683
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3751013294
Short name T1067
Test name
Test status
Simulation time 38514816 ps
CPU time 2.36 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:29 AM PDT 24
Peak memory 215576 kb
Host smart-85ebaab2-b5a2-44b3-97ff-6ef7f334a976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751013294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
751013294
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3783258172
Short name T1069
Test name
Test status
Simulation time 17429548 ps
CPU time 0.73 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:36 AM PDT 24
Peak memory 204456 kb
Host smart-3ba44a38-d2b8-4fa5-a99c-1012b8741f7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783258172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
783258172
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3624036036
Short name T122
Test name
Test status
Simulation time 47638578 ps
CPU time 1.77 seconds
Started Jul 02 07:52:15 AM PDT 24
Finished Jul 02 07:52:18 AM PDT 24
Peak memory 215684 kb
Host smart-25d1a763-a88d-4251-b9e3-95cec361790b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624036036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3624036036
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1260388360
Short name T1040
Test name
Test status
Simulation time 12874274 ps
CPU time 0.72 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 204296 kb
Host smart-3003e2fe-2c94-4189-96ba-bbcf15acddcf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260388360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1260388360
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1067290016
Short name T138
Test name
Test status
Simulation time 153094226 ps
CPU time 1.66 seconds
Started Jul 02 07:52:21 AM PDT 24
Finished Jul 02 07:52:24 AM PDT 24
Peak memory 215772 kb
Host smart-5f83ac29-3789-444e-99f0-a8a1824c1879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067290016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1067290016
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4018528375
Short name T1117
Test name
Test status
Simulation time 562221164 ps
CPU time 7.67 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:52:38 AM PDT 24
Peak memory 215724 kb
Host smart-df95245e-3773-4998-82fb-4b3ddfbe00bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018528375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4018528375
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3040947497
Short name T1124
Test name
Test status
Simulation time 805938887 ps
CPU time 14.72 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 215624 kb
Host smart-591d6beb-622b-4b5d-8320-b21e39781e49
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040947497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3040947497
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2774749380
Short name T1032
Test name
Test status
Simulation time 4034903149 ps
CPU time 13.23 seconds
Started Jul 02 07:52:21 AM PDT 24
Finished Jul 02 07:52:35 AM PDT 24
Peak memory 207548 kb
Host smart-98b95803-ab68-4106-8f68-feeb378eedc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774749380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2774749380
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2430853829
Short name T80
Test name
Test status
Simulation time 21351414 ps
CPU time 0.98 seconds
Started Jul 02 07:52:10 AM PDT 24
Finished Jul 02 07:52:12 AM PDT 24
Peak memory 207140 kb
Host smart-a81a2607-7a4e-4a28-9987-a9f100346be6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430853829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2430853829
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2745153638
Short name T1097
Test name
Test status
Simulation time 46605993 ps
CPU time 1.65 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:34 AM PDT 24
Peak memory 215860 kb
Host smart-914f9361-d754-41cd-ae1b-c37255906bdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745153638 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2745153638
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.118191814
Short name T125
Test name
Test status
Simulation time 140791490 ps
CPU time 2.08 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 207392 kb
Host smart-61c73619-84f8-4e4c-8eba-e70481864109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118191814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.118191814
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.863659398
Short name T1061
Test name
Test status
Simulation time 15201287 ps
CPU time 0.71 seconds
Started Jul 02 07:52:13 AM PDT 24
Finished Jul 02 07:52:16 AM PDT 24
Peak memory 204188 kb
Host smart-4bc4ad74-1b27-4c3e-9a2a-fc2661bf74ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863659398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.863659398
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3832931329
Short name T123
Test name
Test status
Simulation time 112360685 ps
CPU time 2.15 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:27 AM PDT 24
Peak memory 215684 kb
Host smart-89613e3e-94c6-4984-ad15-78bbf1cab481
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832931329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3832931329
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3788950254
Short name T1031
Test name
Test status
Simulation time 25234645 ps
CPU time 0.65 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:34 AM PDT 24
Peak memory 203968 kb
Host smart-5f28f242-f5dc-42c4-bc6f-6384412ff317
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788950254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3788950254
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.646150171
Short name T1094
Test name
Test status
Simulation time 51949430 ps
CPU time 1.62 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:32 AM PDT 24
Peak memory 207464 kb
Host smart-d789394c-77fd-4af6-a44c-56622bf463b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646150171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.646150171
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4147918264
Short name T1079
Test name
Test status
Simulation time 161317525 ps
CPU time 3.41 seconds
Started Jul 02 07:52:14 AM PDT 24
Finished Jul 02 07:52:19 AM PDT 24
Peak memory 215964 kb
Host smart-1d0cb402-c5c5-4c7b-8133-7333d4c0ceeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147918264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
147918264
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2188661738
Short name T1047
Test name
Test status
Simulation time 84670688 ps
CPU time 3.42 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:52:54 AM PDT 24
Peak memory 218724 kb
Host smart-1d4b1965-fe81-405a-bb65-54f6633e3a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188661738 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2188661738
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3185815914
Short name T1109
Test name
Test status
Simulation time 30132149 ps
CPU time 1.84 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 215516 kb
Host smart-d462c5f0-b261-4c43-85f1-5eae7acb8ee0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185815914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3185815914
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.766253340
Short name T1051
Test name
Test status
Simulation time 38499791 ps
CPU time 0.74 seconds
Started Jul 02 07:52:31 AM PDT 24
Finished Jul 02 07:52:44 AM PDT 24
Peak memory 204236 kb
Host smart-39ee1b6c-7d86-43ad-907f-c1c4833ba086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766253340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.766253340
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3397621840
Short name T142
Test name
Test status
Simulation time 227194832 ps
CPU time 1.68 seconds
Started Jul 02 07:52:34 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 207448 kb
Host smart-20c74288-d4b0-443e-8dbb-9439161cdb81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397621840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3397621840
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1533492973
Short name T1077
Test name
Test status
Simulation time 153332724 ps
CPU time 3.08 seconds
Started Jul 02 07:52:30 AM PDT 24
Finished Jul 02 07:52:45 AM PDT 24
Peak memory 216208 kb
Host smart-6dfff77d-eeb5-44c9-a436-4e6cfe4f9143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533492973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1533492973
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.757554142
Short name T159
Test name
Test status
Simulation time 686644133 ps
CPU time 15.3 seconds
Started Jul 02 07:52:31 AM PDT 24
Finished Jul 02 07:52:59 AM PDT 24
Peak memory 215812 kb
Host smart-1e02a6fd-6acd-4e62-8616-a95f29e02537
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757554142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.757554142
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2531615966
Short name T1085
Test name
Test status
Simulation time 143722369 ps
CPU time 3.49 seconds
Started Jul 02 07:52:31 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 217624 kb
Host smart-0009e6be-38d0-471a-b7a5-7f4617e495b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531615966 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2531615966
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1410628129
Short name T1115
Test name
Test status
Simulation time 135914698 ps
CPU time 1.23 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 207300 kb
Host smart-decf856f-4292-4a7e-9d18-2e2f42dfb409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410628129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1410628129
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4252224871
Short name T1105
Test name
Test status
Simulation time 175412993 ps
CPU time 0.71 seconds
Started Jul 02 07:52:32 AM PDT 24
Finished Jul 02 07:52:46 AM PDT 24
Peak memory 204248 kb
Host smart-02cc8b70-8666-426d-bfd3-00d9eb564927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252224871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4252224871
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3490004717
Short name T1046
Test name
Test status
Simulation time 444719323 ps
CPU time 1.7 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 215748 kb
Host smart-64e4cc12-d339-415d-9aa9-57b5c1fda76d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490004717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3490004717
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3560242283
Short name T104
Test name
Test status
Simulation time 187505784 ps
CPU time 2.67 seconds
Started Jul 02 07:52:28 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 215952 kb
Host smart-64e074cf-85f8-40fa-bc5f-c9f8a8fa2c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560242283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3560242283
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.671428162
Short name T1119
Test name
Test status
Simulation time 140181782 ps
CPU time 2.55 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:52:54 AM PDT 24
Peak memory 215688 kb
Host smart-83df751b-d371-4ba0-bee2-c6062bb452da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671428162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.671428162
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2768138660
Short name T1081
Test name
Test status
Simulation time 14281197 ps
CPU time 0.75 seconds
Started Jul 02 07:52:34 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 204240 kb
Host smart-ad8bb48d-8bf9-4239-8490-05bb70de69ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768138660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2768138660
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.563419744
Short name T1028
Test name
Test status
Simulation time 163148223 ps
CPU time 2.74 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 215628 kb
Host smart-8cb2ea2c-4537-470b-8d62-4b087f624ade
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563419744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.563419744
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.436470678
Short name T105
Test name
Test status
Simulation time 223781420 ps
CPU time 1.65 seconds
Started Jul 02 07:52:32 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 215980 kb
Host smart-f94ae891-7f40-42d3-a84e-1bd222fdd65e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436470678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.436470678
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3183137926
Short name T1121
Test name
Test status
Simulation time 418232838 ps
CPU time 7.3 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 215752 kb
Host smart-e0d478c7-f689-4212-ac13-f35a9a014f79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183137926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3183137926
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.328720405
Short name T148
Test name
Test status
Simulation time 96027121 ps
CPU time 2.49 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 216752 kb
Host smart-2ab7681a-25cb-4bca-b6d0-6792a3a8f03b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328720405 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.328720405
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.596535288
Short name T1080
Test name
Test status
Simulation time 89409617 ps
CPU time 1.32 seconds
Started Jul 02 07:52:34 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 207492 kb
Host smart-2cabd3f7-f44e-4652-9fb2-bc0c7b0ed44a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596535288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.596535288
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1160405468
Short name T1088
Test name
Test status
Simulation time 16567550 ps
CPU time 0.73 seconds
Started Jul 02 07:52:32 AM PDT 24
Finished Jul 02 07:52:46 AM PDT 24
Peak memory 204280 kb
Host smart-7dd542cc-38dd-4aca-9e35-d90f472fa512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160405468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1160405468
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4034753772
Short name T1060
Test name
Test status
Simulation time 100710615 ps
CPU time 2.82 seconds
Started Jul 02 07:52:34 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 215720 kb
Host smart-0f75ec1a-dd98-4726-804a-ffa07dc0ea3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034753772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4034753772
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3074383132
Short name T106
Test name
Test status
Simulation time 284762505 ps
CPU time 3.71 seconds
Started Jul 02 07:52:29 AM PDT 24
Finished Jul 02 07:52:46 AM PDT 24
Peak memory 215976 kb
Host smart-5b259a98-77a1-4be5-a8a5-8979373ef52e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074383132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3074383132
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.547203482
Short name T161
Test name
Test status
Simulation time 220229867 ps
CPU time 6.31 seconds
Started Jul 02 07:52:34 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 215556 kb
Host smart-41d7ed17-ae19-4dd2-824e-3a177a6c8d38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547203482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.547203482
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2724061736
Short name T119
Test name
Test status
Simulation time 2508768653 ps
CPU time 3.87 seconds
Started Jul 02 07:52:29 AM PDT 24
Finished Jul 02 07:52:46 AM PDT 24
Peak memory 218892 kb
Host smart-86779a79-94aa-4b35-ab93-47274341b8ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724061736 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2724061736
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1466706193
Short name T140
Test name
Test status
Simulation time 98345506 ps
CPU time 1.36 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 207400 kb
Host smart-c7455830-abca-41fd-aada-9c23860088e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466706193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1466706193
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1220142677
Short name T1122
Test name
Test status
Simulation time 14432218 ps
CPU time 0.75 seconds
Started Jul 02 07:52:29 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 204268 kb
Host smart-8de5cb0a-09b4-4088-ac7d-33390abb0e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220142677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1220142677
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3356242409
Short name T1128
Test name
Test status
Simulation time 846215126 ps
CPU time 4.29 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 215640 kb
Host smart-d2e2656a-ea70-4236-b541-e8f0f8026764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356242409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3356242409
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2744424511
Short name T101
Test name
Test status
Simulation time 64964076 ps
CPU time 2.12 seconds
Started Jul 02 07:52:35 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 215752 kb
Host smart-2b90048b-4dad-4232-aff7-60290562c611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744424511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2744424511
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2515548497
Short name T115
Test name
Test status
Simulation time 5819230268 ps
CPU time 20.07 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:53:11 AM PDT 24
Peak memory 215976 kb
Host smart-b9061c30-ea18-4505-bdba-3a2e539eef29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515548497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2515548497
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3979719040
Short name T1049
Test name
Test status
Simulation time 431875076 ps
CPU time 4.04 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 219180 kb
Host smart-824bee2a-93de-44dd-8b60-41ae12cd42e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979719040 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3979719040
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.715267447
Short name T127
Test name
Test status
Simulation time 19634146 ps
CPU time 1.22 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 215616 kb
Host smart-87b277e9-d368-4387-8f32-67ac7e5c8d18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715267447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.715267447
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1017320721
Short name T1057
Test name
Test status
Simulation time 241200642 ps
CPU time 0.71 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 204256 kb
Host smart-b8ad09fa-8f0f-4957-bc18-4d179648387f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017320721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1017320721
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.443879720
Short name T146
Test name
Test status
Simulation time 142477352 ps
CPU time 3.44 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 215588 kb
Host smart-28fac16e-33e2-428a-93ce-99de1aa3a6a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443879720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.443879720
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4057381699
Short name T1086
Test name
Test status
Simulation time 131041858 ps
CPU time 2.1 seconds
Started Jul 02 07:52:30 AM PDT 24
Finished Jul 02 07:52:45 AM PDT 24
Peak memory 215940 kb
Host smart-87693f10-ecb7-4d1d-8ce6-c71673e80ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057381699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4057381699
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1993836591
Short name T100
Test name
Test status
Simulation time 229172786 ps
CPU time 6.01 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 215752 kb
Host smart-8990cffd-4655-463b-a2f1-908d094f92dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993836591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1993836591
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.384640187
Short name T117
Test name
Test status
Simulation time 42181338 ps
CPU time 2.9 seconds
Started Jul 02 07:52:35 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 216924 kb
Host smart-3240db41-7c2b-46f4-a001-f6d6e8e9b3ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384640187 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.384640187
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.558522099
Short name T132
Test name
Test status
Simulation time 253847736 ps
CPU time 1.99 seconds
Started Jul 02 07:52:34 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 207480 kb
Host smart-9bc062d7-ae6c-4b76-a455-ca565a0af32c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558522099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.558522099
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.276959409
Short name T1112
Test name
Test status
Simulation time 16884119 ps
CPU time 0.75 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 204188 kb
Host smart-1af03017-7751-4ad2-bcd6-bcb0559adef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276959409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.276959409
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3199897315
Short name T1090
Test name
Test status
Simulation time 595468482 ps
CPU time 3.16 seconds
Started Jul 02 07:52:37 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 215676 kb
Host smart-65542c6b-5d2d-4765-b6a1-c6f247db453a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199897315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3199897315
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.692335419
Short name T110
Test name
Test status
Simulation time 66471937 ps
CPU time 1.87 seconds
Started Jul 02 07:52:35 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 216992 kb
Host smart-7666b954-d82d-4d7f-b9b4-8010de4893e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692335419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.692335419
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1757241028
Short name T163
Test name
Test status
Simulation time 828470388 ps
CPU time 18.85 seconds
Started Jul 02 07:52:35 AM PDT 24
Finished Jul 02 07:53:06 AM PDT 24
Peak memory 215628 kb
Host smart-55f3fcf6-8df7-4ef5-8b45-6dd92408a66e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757241028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1757241028
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.209046351
Short name T1071
Test name
Test status
Simulation time 57183894 ps
CPU time 3.66 seconds
Started Jul 02 07:52:32 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 217900 kb
Host smart-a3b8784c-5219-464c-a258-2c8d531a5248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209046351 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.209046351
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3168432313
Short name T126
Test name
Test status
Simulation time 359644722 ps
CPU time 2.6 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 215680 kb
Host smart-67dd5de3-32d9-4f2d-8894-1e8d86fbbdae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168432313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3168432313
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.32878190
Short name T1052
Test name
Test status
Simulation time 48532563 ps
CPU time 0.73 seconds
Started Jul 02 07:52:38 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 204604 kb
Host smart-8c8eaa65-d0da-4f1e-a34f-16f7d0e7f206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32878190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.32878190
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1828038907
Short name T141
Test name
Test status
Simulation time 160046116 ps
CPU time 2.54 seconds
Started Jul 02 07:52:37 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 215724 kb
Host smart-488cc782-3ae7-4f89-b673-8c1d87e25bfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828038907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1828038907
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1506874781
Short name T165
Test name
Test status
Simulation time 603839084 ps
CPU time 14.38 seconds
Started Jul 02 07:52:35 AM PDT 24
Finished Jul 02 07:53:03 AM PDT 24
Peak memory 215964 kb
Host smart-1fba26be-53d9-4981-a427-831a99398e74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506874781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1506874781
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.890940075
Short name T1033
Test name
Test status
Simulation time 51368859 ps
CPU time 3.43 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 218020 kb
Host smart-3b2bdd4f-cd61-4098-a4f5-9f7ce39b748a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890940075 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.890940075
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1628851441
Short name T129
Test name
Test status
Simulation time 81324514 ps
CPU time 2.66 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 215532 kb
Host smart-bb5bb894-7c1b-4801-9db5-0298eb867cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628851441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1628851441
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1291943365
Short name T1045
Test name
Test status
Simulation time 18739191 ps
CPU time 0.75 seconds
Started Jul 02 07:52:32 AM PDT 24
Finished Jul 02 07:52:46 AM PDT 24
Peak memory 204164 kb
Host smart-3f64edaf-d59d-4134-b3f3-7c743a2cbc16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291943365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1291943365
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1637800082
Short name T1076
Test name
Test status
Simulation time 55009196 ps
CPU time 1.81 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 207464 kb
Host smart-b7c52c9d-9a84-4e49-872e-ebc80a01eb0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637800082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1637800082
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2431597840
Short name T1108
Test name
Test status
Simulation time 155744870 ps
CPU time 1.57 seconds
Started Jul 02 07:52:35 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 216052 kb
Host smart-d2dd9dd6-4f6b-41ce-801c-c2827fbac349
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431597840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2431597840
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1720563730
Short name T1089
Test name
Test status
Simulation time 1772090225 ps
CPU time 8.07 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:54 AM PDT 24
Peak memory 215720 kb
Host smart-845ea1e3-1332-48cc-8d43-4c80e89499b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720563730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1720563730
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2382285372
Short name T98
Test name
Test status
Simulation time 58453496 ps
CPU time 3.48 seconds
Started Jul 02 07:52:37 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 218732 kb
Host smart-2ffecdfe-4999-4ae7-a5aa-8e30052f5500
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382285372 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2382285372
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1968450006
Short name T1123
Test name
Test status
Simulation time 267415521 ps
CPU time 1.91 seconds
Started Jul 02 07:52:32 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 207396 kb
Host smart-f9f5ded2-0fb0-4473-86ca-081f475de5c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968450006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1968450006
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.352142758
Short name T1018
Test name
Test status
Simulation time 15959732 ps
CPU time 0.71 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 204496 kb
Host smart-79158573-cbee-4465-932b-4562fc7f936f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352142758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.352142758
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4126236579
Short name T147
Test name
Test status
Simulation time 351947437 ps
CPU time 3.95 seconds
Started Jul 02 07:52:35 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 215740 kb
Host smart-0154d3e9-06e7-497f-8f06-8d72f73d2d08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126236579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4126236579
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2213936947
Short name T108
Test name
Test status
Simulation time 418501805 ps
CPU time 4.81 seconds
Started Jul 02 07:52:35 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 216920 kb
Host smart-4593df7f-d8f9-42af-8900-bdd89ae278fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213936947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2213936947
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2640156974
Short name T116
Test name
Test status
Simulation time 210093299 ps
CPU time 12.27 seconds
Started Jul 02 07:52:36 AM PDT 24
Finished Jul 02 07:53:01 AM PDT 24
Peak memory 222796 kb
Host smart-b0a45317-1f09-4819-b50e-348e62000388
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640156974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2640156974
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3377308857
Short name T1029
Test name
Test status
Simulation time 121093031 ps
CPU time 8.31 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:40 AM PDT 24
Peak memory 207604 kb
Host smart-1eb93055-8151-4ba5-8337-b23d74a0c4c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377308857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3377308857
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2183002183
Short name T121
Test name
Test status
Simulation time 5108375702 ps
CPU time 37.96 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:53:06 AM PDT 24
Peak memory 216836 kb
Host smart-962d17bc-7e6c-4e40-9f88-5e61f5609295
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183002183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2183002183
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.909975239
Short name T81
Test name
Test status
Simulation time 150493743 ps
CPU time 1.4 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:27 AM PDT 24
Peak memory 207492 kb
Host smart-0613e27c-de07-4767-a6f6-9149dd99f6f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909975239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.909975239
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2629371311
Short name T1111
Test name
Test status
Simulation time 379106359 ps
CPU time 2.59 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:35 AM PDT 24
Peak memory 217096 kb
Host smart-14ecd5fa-64b3-473e-939c-93a072abe084
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629371311 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2629371311
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1427489098
Short name T139
Test name
Test status
Simulation time 112789680 ps
CPU time 1.26 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:52:39 AM PDT 24
Peak memory 215556 kb
Host smart-a43bb4aa-18f1-473c-81cf-7dfbe32c1fa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427489098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
427489098
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2635373795
Short name T1104
Test name
Test status
Simulation time 30847710 ps
CPU time 0.74 seconds
Started Jul 02 07:52:30 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 204152 kb
Host smart-b756e0b2-720a-4b9e-8e46-6d2b0bb5d312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635373795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
635373795
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1960404177
Short name T124
Test name
Test status
Simulation time 89065000 ps
CPU time 1.81 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:26 AM PDT 24
Peak memory 215728 kb
Host smart-70c29c95-e331-45a8-8671-aadb5c8c0f53
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960404177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1960404177
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.469578273
Short name T1042
Test name
Test status
Simulation time 65616854 ps
CPU time 0.65 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:37 AM PDT 24
Peak memory 203948 kb
Host smart-65e79ed5-da3f-455c-869c-048092ce7771
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469578273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.469578273
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1389743711
Short name T1078
Test name
Test status
Simulation time 766412056 ps
CPU time 4.11 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:37 AM PDT 24
Peak memory 215672 kb
Host smart-c956f4b5-c849-40ce-928f-118bd425a4d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389743711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1389743711
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.558698564
Short name T164
Test name
Test status
Simulation time 2248655529 ps
CPU time 13.95 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 215656 kb
Host smart-216eb1bb-f638-40b4-9932-fc416d039214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558698564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.558698564
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4142358382
Short name T1023
Test name
Test status
Simulation time 34260453 ps
CPU time 0.76 seconds
Started Jul 02 07:52:35 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 204168 kb
Host smart-ba8515d8-1da8-4f2c-b09f-40f66c1507fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142358382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4142358382
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1197188056
Short name T1021
Test name
Test status
Simulation time 12143995 ps
CPU time 0.73 seconds
Started Jul 02 07:52:35 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 203924 kb
Host smart-0888826a-960e-41e9-a617-6ec9f7eae910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197188056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1197188056
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1643570760
Short name T1082
Test name
Test status
Simulation time 18170660 ps
CPU time 0.79 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 204200 kb
Host smart-05347424-7f66-4a43-9292-ce6ff3c9fa83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643570760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1643570760
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2976736727
Short name T1083
Test name
Test status
Simulation time 35759817 ps
CPU time 0.7 seconds
Started Jul 02 07:52:43 AM PDT 24
Finished Jul 02 07:52:54 AM PDT 24
Peak memory 204548 kb
Host smart-f89a2978-40bb-4f9f-9847-d5b8511e4703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976736727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2976736727
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1988867736
Short name T1036
Test name
Test status
Simulation time 13096550 ps
CPU time 0.74 seconds
Started Jul 02 07:52:42 AM PDT 24
Finished Jul 02 07:52:54 AM PDT 24
Peak memory 204468 kb
Host smart-64608aa2-bacd-48f5-8e47-a1a6d7f1ed14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988867736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1988867736
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2895166459
Short name T1106
Test name
Test status
Simulation time 15873564 ps
CPU time 0.72 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 204524 kb
Host smart-6376ddef-6aab-4d12-a001-b5f952c0b179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895166459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2895166459
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2476505765
Short name T1043
Test name
Test status
Simulation time 13813254 ps
CPU time 0.71 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 204240 kb
Host smart-754b4783-ef99-448e-852c-f18cf849b649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476505765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2476505765
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1815304388
Short name T1098
Test name
Test status
Simulation time 13812357 ps
CPU time 0.71 seconds
Started Jul 02 07:52:42 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 204584 kb
Host smart-a784ab28-6d98-4afd-b1fb-28338824ab8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815304388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1815304388
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2357592491
Short name T1063
Test name
Test status
Simulation time 43617945 ps
CPU time 0.68 seconds
Started Jul 02 07:52:41 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 204260 kb
Host smart-49c6068e-6e5d-434c-8c3b-d8c2eb820eae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357592491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2357592491
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1238916583
Short name T1059
Test name
Test status
Simulation time 51863176 ps
CPU time 0.75 seconds
Started Jul 02 07:52:38 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 204188 kb
Host smart-baea4ca6-44f6-4bf7-9484-b1ddaa719b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238916583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1238916583
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1297840758
Short name T1058
Test name
Test status
Simulation time 400222922 ps
CPU time 8.56 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:35 AM PDT 24
Peak memory 207496 kb
Host smart-5534bcae-5497-4007-8c97-cc233cd8f27d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297840758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1297840758
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3567088072
Short name T1100
Test name
Test status
Simulation time 673086796 ps
CPU time 12.45 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 207416 kb
Host smart-e435012a-4371-43b1-9da6-13197c56a3bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567088072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3567088072
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3508151778
Short name T83
Test name
Test status
Simulation time 194771744 ps
CPU time 1.34 seconds
Started Jul 02 07:52:31 AM PDT 24
Finished Jul 02 07:52:45 AM PDT 24
Peak memory 216476 kb
Host smart-99e12a08-99b8-43b1-8421-6cb9eb598bbe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508151778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3508151778
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2976240369
Short name T1129
Test name
Test status
Simulation time 51002086 ps
CPU time 1.68 seconds
Started Jul 02 07:52:28 AM PDT 24
Finished Jul 02 07:52:42 AM PDT 24
Peak memory 216756 kb
Host smart-10c27b7c-bb28-427d-87f1-8cc807b53491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976240369 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2976240369
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3413650888
Short name T130
Test name
Test status
Simulation time 196099920 ps
CPU time 1.5 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:37 AM PDT 24
Peak memory 215660 kb
Host smart-f9ed51b1-0307-41a5-b45c-ff80ec8d4102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413650888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
413650888
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1505855719
Short name T1056
Test name
Test status
Simulation time 35665450 ps
CPU time 0.78 seconds
Started Jul 02 07:52:21 AM PDT 24
Finished Jul 02 07:52:23 AM PDT 24
Peak memory 204192 kb
Host smart-b22cb3e5-bedc-4a46-83e8-ec23dc5dc611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505855719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
505855719
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1470453027
Short name T131
Test name
Test status
Simulation time 75198547 ps
CPU time 2.31 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 215576 kb
Host smart-2b9519b3-76c7-4d2f-b590-bb25f5c9c587
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470453027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1470453027
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3969427825
Short name T1016
Test name
Test status
Simulation time 12523909 ps
CPU time 0.67 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:46 AM PDT 24
Peak memory 204064 kb
Host smart-5546f23f-5169-42d4-9bf6-135065681a05
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969427825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3969427825
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3596871682
Short name T1091
Test name
Test status
Simulation time 217520662 ps
CPU time 2.77 seconds
Started Jul 02 07:52:30 AM PDT 24
Finished Jul 02 07:52:46 AM PDT 24
Peak memory 215568 kb
Host smart-61ab3324-8a5e-45a0-9707-3cbd705054dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596871682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3596871682
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3109667626
Short name T1093
Test name
Test status
Simulation time 981036118 ps
CPU time 2.56 seconds
Started Jul 02 07:52:30 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 216896 kb
Host smart-290608fa-e116-40f6-a0bc-108b83f69be5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109667626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
109667626
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4074204992
Short name T1087
Test name
Test status
Simulation time 193132317 ps
CPU time 5.78 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:52:33 AM PDT 24
Peak memory 215744 kb
Host smart-36296d9a-b3e3-444c-b53d-bafbe409e26a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074204992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4074204992
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2964672241
Short name T1030
Test name
Test status
Simulation time 15030216 ps
CPU time 0.75 seconds
Started Jul 02 07:52:37 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 204128 kb
Host smart-85164f61-2aed-4227-ac78-87df895d9341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964672241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2964672241
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3043574257
Short name T1074
Test name
Test status
Simulation time 132329876 ps
CPU time 0.7 seconds
Started Jul 02 07:52:47 AM PDT 24
Finished Jul 02 07:52:57 AM PDT 24
Peak memory 204472 kb
Host smart-de5cff6f-c497-43de-b70e-1eb5c18bc704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043574257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3043574257
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2024536224
Short name T1099
Test name
Test status
Simulation time 44788865 ps
CPU time 0.75 seconds
Started Jul 02 07:52:38 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 204248 kb
Host smart-7a601c0a-c0e4-40c3-9855-4a2d91071351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024536224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2024536224
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1806240358
Short name T1034
Test name
Test status
Simulation time 17651988 ps
CPU time 0.68 seconds
Started Jul 02 07:52:43 AM PDT 24
Finished Jul 02 07:52:54 AM PDT 24
Peak memory 204504 kb
Host smart-5ac5e87e-bd7c-4629-984d-d2b1b210440d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806240358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1806240358
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4024657844
Short name T1073
Test name
Test status
Simulation time 11647460 ps
CPU time 0.72 seconds
Started Jul 02 07:52:41 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 204248 kb
Host smart-7fe101d3-45a4-4b42-862b-29430e173678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024657844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4024657844
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3716335409
Short name T1062
Test name
Test status
Simulation time 30351622 ps
CPU time 0.72 seconds
Started Jul 02 07:52:43 AM PDT 24
Finished Jul 02 07:52:54 AM PDT 24
Peak memory 204192 kb
Host smart-e0c2dcb7-e7af-42e0-801c-79b449b49c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716335409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3716335409
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2079468617
Short name T1037
Test name
Test status
Simulation time 35507768 ps
CPU time 0.71 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 204572 kb
Host smart-745ec616-09f4-4ac5-a2b6-afccb0c95777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079468617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2079468617
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2679388835
Short name T1053
Test name
Test status
Simulation time 13010161 ps
CPU time 0.75 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 204228 kb
Host smart-94e86ffc-43a2-4193-b9de-0d41b2242c1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679388835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2679388835
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2263593630
Short name T1095
Test name
Test status
Simulation time 109620088 ps
CPU time 0.74 seconds
Started Jul 02 07:52:40 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 204472 kb
Host smart-725b2244-99ee-47cb-adcf-ec46e15d8de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263593630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2263593630
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1211983942
Short name T1127
Test name
Test status
Simulation time 34948714 ps
CPU time 0.71 seconds
Started Jul 02 07:52:52 AM PDT 24
Finished Jul 02 07:52:58 AM PDT 24
Peak memory 204156 kb
Host smart-c9a66ef2-f413-4601-b6d6-5d5e0a68e343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211983942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1211983942
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2349203233
Short name T1064
Test name
Test status
Simulation time 391595670 ps
CPU time 8.63 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:52:37 AM PDT 24
Peak memory 207428 kb
Host smart-8196d30d-4785-4f7c-a8b0-71aa2d97a4c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349203233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2349203233
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1165619307
Short name T1026
Test name
Test status
Simulation time 6944316500 ps
CPU time 38.12 seconds
Started Jul 02 07:52:27 AM PDT 24
Finished Jul 02 07:53:17 AM PDT 24
Peak memory 207752 kb
Host smart-849011c0-7732-4364-875f-d7676711e62c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165619307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1165619307
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4096291930
Short name T84
Test name
Test status
Simulation time 42189092 ps
CPU time 1.36 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 216668 kb
Host smart-eece484c-36cb-4bdb-90f5-05e0c4127629
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096291930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4096291930
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4236952192
Short name T1048
Test name
Test status
Simulation time 48112882 ps
CPU time 1.69 seconds
Started Jul 02 07:52:32 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 215644 kb
Host smart-99a72bb3-1666-4668-a299-2e3bcfaa9dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236952192 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4236952192
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4099591314
Short name T149
Test name
Test status
Simulation time 119695834 ps
CPU time 2.84 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:38 AM PDT 24
Peak memory 207348 kb
Host smart-0169f3bf-e8a7-4aba-90a3-34bf83fee769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099591314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
099591314
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1537186864
Short name T1102
Test name
Test status
Simulation time 13482672 ps
CPU time 0.72 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:36 AM PDT 24
Peak memory 204140 kb
Host smart-a2ead7d6-dc2f-47a5-97bf-59c4e09b8805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537186864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
537186864
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1370275117
Short name T133
Test name
Test status
Simulation time 68237085 ps
CPU time 1.19 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:52:39 AM PDT 24
Peak memory 215696 kb
Host smart-4879767f-7d72-4dee-9afd-fd3046448c9d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370275117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1370275117
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2711941321
Short name T1054
Test name
Test status
Simulation time 22766957 ps
CPU time 0.65 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:26 AM PDT 24
Peak memory 204288 kb
Host smart-cfdc9935-7519-4d81-bfdb-b9a8c80d8067
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711941321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2711941321
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2327682138
Short name T1075
Test name
Test status
Simulation time 27468401 ps
CPU time 1.6 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:52:40 AM PDT 24
Peak memory 215640 kb
Host smart-c3204d66-eda7-4891-bf0b-10091d120386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327682138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2327682138
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1299284077
Short name T107
Test name
Test status
Simulation time 310101268 ps
CPU time 3.59 seconds
Started Jul 02 07:52:23 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 216104 kb
Host smart-fdbc0e32-1788-4d9f-be6c-b38940f81831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299284077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
299284077
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3145824735
Short name T1110
Test name
Test status
Simulation time 141461897 ps
CPU time 0.72 seconds
Started Jul 02 07:52:41 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 204484 kb
Host smart-b3257704-6301-457f-b39e-a723b7e8ee31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145824735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3145824735
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.106504402
Short name T1055
Test name
Test status
Simulation time 27348662 ps
CPU time 0.68 seconds
Started Jul 02 07:52:48 AM PDT 24
Finished Jul 02 07:52:57 AM PDT 24
Peak memory 204140 kb
Host smart-258d8aa7-186c-465c-9617-ff916bc03ec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106504402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.106504402
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3213946432
Short name T1038
Test name
Test status
Simulation time 23730014 ps
CPU time 0.73 seconds
Started Jul 02 07:52:43 AM PDT 24
Finished Jul 02 07:52:54 AM PDT 24
Peak memory 204180 kb
Host smart-565ad921-463a-432a-b1c1-f3c054969b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213946432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3213946432
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2215782495
Short name T1084
Test name
Test status
Simulation time 39535841 ps
CPU time 0.69 seconds
Started Jul 02 07:52:41 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 204248 kb
Host smart-2f18f446-90c7-4987-8bb6-28003fb2a473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215782495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2215782495
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.807624831
Short name T1118
Test name
Test status
Simulation time 14163284 ps
CPU time 0.76 seconds
Started Jul 02 07:52:40 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 204520 kb
Host smart-29756115-de18-4884-9f64-bc53452460be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807624831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.807624831
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3156634032
Short name T1015
Test name
Test status
Simulation time 48576573 ps
CPU time 0.78 seconds
Started Jul 02 07:52:38 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 204504 kb
Host smart-fe992326-cec1-41bb-bf72-6b6c160b556e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156634032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3156634032
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2692714445
Short name T1027
Test name
Test status
Simulation time 68803390 ps
CPU time 0.8 seconds
Started Jul 02 07:52:40 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 204192 kb
Host smart-20d18901-3d98-49fa-a0ad-a19951c221d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692714445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2692714445
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1259733948
Short name T1116
Test name
Test status
Simulation time 25854875 ps
CPU time 0.78 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 204268 kb
Host smart-1ae22f56-d528-4d4a-8dcd-7e0737d50bf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259733948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1259733948
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3469586718
Short name T1019
Test name
Test status
Simulation time 44649639 ps
CPU time 0.78 seconds
Started Jul 02 07:52:44 AM PDT 24
Finished Jul 02 07:52:55 AM PDT 24
Peak memory 204484 kb
Host smart-a4154b82-2b12-4e88-b104-dde4db4677b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469586718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3469586718
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2876428066
Short name T1068
Test name
Test status
Simulation time 27691610 ps
CPU time 0.77 seconds
Started Jul 02 07:52:39 AM PDT 24
Finished Jul 02 07:52:51 AM PDT 24
Peak memory 204264 kb
Host smart-466416b2-943c-432f-af9b-c3ce8e9f6920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876428066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2876428066
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2953992168
Short name T1065
Test name
Test status
Simulation time 215537137 ps
CPU time 3.87 seconds
Started Jul 02 07:52:22 AM PDT 24
Finished Jul 02 07:52:30 AM PDT 24
Peak memory 217868 kb
Host smart-47fc8909-2bd9-4ef0-804f-554721a1e0b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953992168 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2953992168
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.210665441
Short name T120
Test name
Test status
Simulation time 98038042 ps
CPU time 1.36 seconds
Started Jul 02 07:52:31 AM PDT 24
Finished Jul 02 07:52:46 AM PDT 24
Peak memory 207520 kb
Host smart-1fc42151-38c7-4be9-9bbb-ec698ac4cb73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210665441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.210665441
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.868901257
Short name T1024
Test name
Test status
Simulation time 41514337 ps
CPU time 0.7 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:46 AM PDT 24
Peak memory 204264 kb
Host smart-73d531c4-3c23-46f4-b460-d01d4f7885f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868901257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.868901257
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3090467383
Short name T1044
Test name
Test status
Simulation time 59793175 ps
CPU time 1.72 seconds
Started Jul 02 07:52:28 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 215660 kb
Host smart-a20f5d5d-0c74-4e5e-8843-d80f24e70a38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090467383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3090467383
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1671704000
Short name T112
Test name
Test status
Simulation time 172546570 ps
CPU time 2.48 seconds
Started Jul 02 07:52:31 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 216148 kb
Host smart-60ac841d-d98f-46ea-9e45-5c5291997850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671704000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
671704000
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3418923181
Short name T63
Test name
Test status
Simulation time 3184636106 ps
CPU time 15.03 seconds
Started Jul 02 07:52:28 AM PDT 24
Finished Jul 02 07:52:56 AM PDT 24
Peak memory 223976 kb
Host smart-0072d809-68ee-4f61-8883-99fab694de39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418923181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3418923181
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1575213795
Short name T1101
Test name
Test status
Simulation time 28821195 ps
CPU time 1.72 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:38 AM PDT 24
Peak memory 216748 kb
Host smart-a9d8fbf9-eee6-4e6a-b26b-45df51d76783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575213795 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1575213795
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1253162084
Short name T128
Test name
Test status
Simulation time 146150262 ps
CPU time 1.77 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:52:38 AM PDT 24
Peak memory 215464 kb
Host smart-15713991-f2f5-4753-96d8-de41a583368a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253162084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
253162084
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1555610828
Short name T1114
Test name
Test status
Simulation time 71260146 ps
CPU time 0.69 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:52:37 AM PDT 24
Peak memory 204144 kb
Host smart-85a53b99-49c0-4111-8629-5061d5bf8d02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555610828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
555610828
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1766501772
Short name T1050
Test name
Test status
Simulation time 311859719 ps
CPU time 4.03 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:52:42 AM PDT 24
Peak memory 215724 kb
Host smart-34f70085-526b-4b49-8296-85e2a6a60bd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766501772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1766501772
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.810412109
Short name T1126
Test name
Test status
Simulation time 63760533 ps
CPU time 1.98 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:35 AM PDT 24
Peak memory 215992 kb
Host smart-025e712b-9627-401f-bde4-fc62c0ad4a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810412109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.810412109
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3599626507
Short name T1070
Test name
Test status
Simulation time 376190782 ps
CPU time 5.88 seconds
Started Jul 02 07:52:30 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 215664 kb
Host smart-693e3c3d-f7b9-4fad-b5db-ef9767edb201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599626507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3599626507
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.281497954
Short name T1035
Test name
Test status
Simulation time 51909068 ps
CPU time 1.83 seconds
Started Jul 02 07:52:31 AM PDT 24
Finished Jul 02 07:52:45 AM PDT 24
Peak memory 215776 kb
Host smart-c74ffce1-8ff8-4b41-a44d-1a523c0bf0c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281497954 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.281497954
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1367663000
Short name T1039
Test name
Test status
Simulation time 82478864 ps
CPU time 2.35 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 215568 kb
Host smart-f38503e4-3ba8-4068-a398-1c2fef7f0de2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367663000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
367663000
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.905834736
Short name T1017
Test name
Test status
Simulation time 13996777 ps
CPU time 0.72 seconds
Started Jul 02 07:52:29 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 204288 kb
Host smart-ec81f744-67bd-4e5c-80e8-fed237ff93d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905834736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.905834736
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1256076317
Short name T1041
Test name
Test status
Simulation time 74277843 ps
CPU time 2.49 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 215680 kb
Host smart-e9eb3ea2-dd02-4551-b80e-fc876f5709b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256076317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1256076317
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.682475969
Short name T1113
Test name
Test status
Simulation time 378007227 ps
CPU time 2.67 seconds
Started Jul 02 07:52:32 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 215904 kb
Host smart-4ecdeb4f-07d0-40ff-b74a-2378152b65f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682475969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.682475969
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3019969678
Short name T109
Test name
Test status
Simulation time 270219704 ps
CPU time 3.69 seconds
Started Jul 02 07:52:28 AM PDT 24
Finished Jul 02 07:52:45 AM PDT 24
Peak memory 218296 kb
Host smart-de7841cd-8add-40e8-a01b-8219ae491b3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019969678 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3019969678
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.80150792
Short name T1107
Test name
Test status
Simulation time 57670816 ps
CPU time 1.92 seconds
Started Jul 02 07:52:26 AM PDT 24
Finished Jul 02 07:52:39 AM PDT 24
Peak memory 215480 kb
Host smart-7d25eeac-35f7-4ba8-bf3d-402d56ac8de7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80150792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.80150792
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.695415328
Short name T1020
Test name
Test status
Simulation time 43698902 ps
CPU time 0.73 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 204268 kb
Host smart-d17148c3-894e-4a66-8577-63c1b9672c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695415328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.695415328
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3183829909
Short name T1096
Test name
Test status
Simulation time 79755777 ps
CPU time 2.64 seconds
Started Jul 02 07:52:34 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 215676 kb
Host smart-b68ba8c5-1cc3-49c2-8294-cc029956dc81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183829909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3183829909
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1289257130
Short name T62
Test name
Test status
Simulation time 112558459 ps
CPU time 2.55 seconds
Started Jul 02 07:52:27 AM PDT 24
Finished Jul 02 07:52:41 AM PDT 24
Peak memory 215848 kb
Host smart-665c6c5e-8742-437f-890b-ed8b2e40166e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289257130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
289257130
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3559594372
Short name T166
Test name
Test status
Simulation time 280480652 ps
CPU time 7.49 seconds
Started Jul 02 07:52:29 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 215852 kb
Host smart-23c0733b-6904-4e2c-9776-6fb1fcd17ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559594372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3559594372
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.218817123
Short name T1072
Test name
Test status
Simulation time 26417974 ps
CPU time 1.62 seconds
Started Jul 02 07:52:33 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 216852 kb
Host smart-6516d951-6929-473f-b45b-2fed805ebe31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218817123 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.218817123
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1437114728
Short name T1022
Test name
Test status
Simulation time 34276152 ps
CPU time 1.32 seconds
Started Jul 02 07:52:28 AM PDT 24
Finished Jul 02 07:52:42 AM PDT 24
Peak memory 215532 kb
Host smart-aa217001-662e-44a2-85be-80845efe90cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437114728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
437114728
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3939616997
Short name T1025
Test name
Test status
Simulation time 22184995 ps
CPU time 0.75 seconds
Started Jul 02 07:52:25 AM PDT 24
Finished Jul 02 07:52:37 AM PDT 24
Peak memory 204508 kb
Host smart-f85287e2-a100-4f58-a5f5-bf481c260887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939616997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
939616997
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.549141186
Short name T1120
Test name
Test status
Simulation time 306383350 ps
CPU time 2.88 seconds
Started Jul 02 07:52:34 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 215732 kb
Host smart-1f30af86-4ad1-4ed0-b2b1-0e925f1c58bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549141186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.549141186
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1845144961
Short name T1066
Test name
Test status
Simulation time 171315229 ps
CPU time 1.57 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:33 AM PDT 24
Peak memory 217096 kb
Host smart-7bbe9064-d4ab-45c1-b660-86dcd48e5e37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845144961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
845144961
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1859020866
Short name T61
Test name
Test status
Simulation time 209999737 ps
CPU time 6.45 seconds
Started Jul 02 07:52:24 AM PDT 24
Finished Jul 02 07:52:38 AM PDT 24
Peak memory 215784 kb
Host smart-905e9eb2-37ca-4936-9a4a-18a4c8689e78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859020866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1859020866
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4112628215
Short name T698
Test name
Test status
Simulation time 19647513 ps
CPU time 0.73 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:53:24 AM PDT 24
Peak memory 205404 kb
Host smart-140ab875-cb08-4e42-8a0d-79c9ff041fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112628215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
112628215
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1901978610
Short name T1006
Test name
Test status
Simulation time 283108981 ps
CPU time 5.38 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:53:28 AM PDT 24
Peak memory 232568 kb
Host smart-da97b6c6-d129-4624-878e-b662899a0e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901978610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1901978610
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1083708767
Short name T400
Test name
Test status
Simulation time 64926499 ps
CPU time 0.81 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:53:23 AM PDT 24
Peak memory 206528 kb
Host smart-5c5faf4b-67d5-4cfc-9c7f-5d15ddc22d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083708767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1083708767
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3739075357
Short name T960
Test name
Test status
Simulation time 23398240 ps
CPU time 0.79 seconds
Started Jul 02 07:53:19 AM PDT 24
Finished Jul 02 07:53:21 AM PDT 24
Peak memory 215660 kb
Host smart-d26ff3bd-19b7-449c-adec-fcda66273e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739075357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3739075357
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2864963421
Short name T981
Test name
Test status
Simulation time 4653978971 ps
CPU time 94.44 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:54:56 AM PDT 24
Peak memory 254356 kb
Host smart-ca464aa3-3a37-4c7f-888a-04958406c094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864963421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2864963421
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3006930245
Short name T533
Test name
Test status
Simulation time 71921308179 ps
CPU time 115.89 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:55:18 AM PDT 24
Peak memory 251732 kb
Host smart-c4fe8ae8-c6e7-42f9-9548-8682a8f68a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006930245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3006930245
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1761016942
Short name T211
Test name
Test status
Simulation time 2355370334 ps
CPU time 12.04 seconds
Started Jul 02 07:53:19 AM PDT 24
Finished Jul 02 07:53:39 AM PDT 24
Peak memory 224784 kb
Host smart-4579da02-c15c-4420-af99-b1fa9af96238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761016942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1761016942
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3205668853
Short name T901
Test name
Test status
Simulation time 501200629 ps
CPU time 2.1 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 223612 kb
Host smart-8b8e541a-a719-428a-8247-8915500dd7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205668853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3205668853
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.590766322
Short name T892
Test name
Test status
Simulation time 4732027506 ps
CPU time 9.82 seconds
Started Jul 02 07:53:26 AM PDT 24
Finished Jul 02 07:53:38 AM PDT 24
Peak memory 232712 kb
Host smart-6511db34-a535-453c-9e29-5364e193fab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590766322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.590766322
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1279860289
Short name T244
Test name
Test status
Simulation time 3803637694 ps
CPU time 6.69 seconds
Started Jul 02 07:53:23 AM PDT 24
Finished Jul 02 07:53:33 AM PDT 24
Peak memory 224368 kb
Host smart-f452df6c-d3a0-46e5-ae12-369ce98e6994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279860289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1279860289
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3785151684
Short name T545
Test name
Test status
Simulation time 2265371621 ps
CPU time 9.27 seconds
Started Jul 02 07:53:19 AM PDT 24
Finished Jul 02 07:53:31 AM PDT 24
Peak memory 222832 kb
Host smart-1aebc784-c2f5-4a6c-a05b-41456740dd33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3785151684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3785151684
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3360572548
Short name T279
Test name
Test status
Simulation time 16247243677 ps
CPU time 154.97 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:55:57 AM PDT 24
Peak memory 250824 kb
Host smart-7202be64-5870-432e-a574-97f73f1d9ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360572548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3360572548
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2539898606
Short name T928
Test name
Test status
Simulation time 8335066641 ps
CPU time 24.66 seconds
Started Jul 02 07:53:19 AM PDT 24
Finished Jul 02 07:53:45 AM PDT 24
Peak memory 216412 kb
Host smart-78a5ca4c-aa05-4202-902b-ba9b4138f481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539898606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2539898606
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.289698599
Short name T325
Test name
Test status
Simulation time 5924983577 ps
CPU time 3.43 seconds
Started Jul 02 07:53:24 AM PDT 24
Finished Jul 02 07:53:30 AM PDT 24
Peak memory 216448 kb
Host smart-b371d522-0f36-4458-b9f6-ebd1ff8f3395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289698599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.289698599
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1286855608
Short name T304
Test name
Test status
Simulation time 82050009 ps
CPU time 3.93 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:30 AM PDT 24
Peak memory 216048 kb
Host smart-0e2af717-9365-4fff-be9e-a108209d5af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286855608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1286855608
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1940934283
Short name T434
Test name
Test status
Simulation time 111149664 ps
CPU time 0.74 seconds
Started Jul 02 07:53:23 AM PDT 24
Finished Jul 02 07:53:27 AM PDT 24
Peak memory 205864 kb
Host smart-3e851503-ea25-4142-8d8c-00375d7ed134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940934283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1940934283
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1105086914
Short name T961
Test name
Test status
Simulation time 8405344857 ps
CPU time 9.83 seconds
Started Jul 02 07:53:17 AM PDT 24
Finished Jul 02 07:53:28 AM PDT 24
Peak memory 232684 kb
Host smart-e7bf72f9-f1b7-4c36-9283-a0a1eaef187e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105086914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1105086914
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2626976392
Short name T380
Test name
Test status
Simulation time 201612843 ps
CPU time 3.26 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:29 AM PDT 24
Peak memory 224336 kb
Host smart-eb4cf651-7061-4be3-b6df-1cec9c15ba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626976392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2626976392
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2892749219
Short name T446
Test name
Test status
Simulation time 17322877 ps
CPU time 0.77 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:53:24 AM PDT 24
Peak memory 206444 kb
Host smart-6c0d59fb-9022-413a-93b6-84892441550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892749219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2892749219
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4128627117
Short name T925
Test name
Test status
Simulation time 4161241533 ps
CPU time 24.98 seconds
Started Jul 02 07:53:44 AM PDT 24
Finished Jul 02 07:54:10 AM PDT 24
Peak memory 224492 kb
Host smart-f45d421d-2247-4033-9093-a8a250589f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128627117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4128627117
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1762189490
Short name T755
Test name
Test status
Simulation time 8435318469 ps
CPU time 30.74 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:56 AM PDT 24
Peak memory 232604 kb
Host smart-30b1175f-9857-479c-bdd8-ff44a00d2264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762189490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1762189490
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.720460993
Short name T339
Test name
Test status
Simulation time 353758751 ps
CPU time 3.67 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:29 AM PDT 24
Peak memory 232588 kb
Host smart-44a7ee20-7dca-43ca-8ff6-a03612bb553f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720460993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.720460993
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3983007814
Short name T255
Test name
Test status
Simulation time 38715183533 ps
CPU time 76.28 seconds
Started Jul 02 07:53:35 AM PDT 24
Finished Jul 02 07:54:53 AM PDT 24
Peak memory 232716 kb
Host smart-f5913397-a1a5-45a4-959f-a35ec317e019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983007814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3983007814
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2552809788
Short name T939
Test name
Test status
Simulation time 5288415190 ps
CPU time 15.79 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:41 AM PDT 24
Peak memory 232632 kb
Host smart-f14bea2a-a3b2-48a3-ae2d-389f0adf6499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552809788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2552809788
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.674766644
Short name T611
Test name
Test status
Simulation time 5195429340 ps
CPU time 10.41 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:35 AM PDT 24
Peak memory 224440 kb
Host smart-00edc3a0-8d0f-44e3-a89a-50f42bb7500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674766644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.674766644
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1001460360
Short name T773
Test name
Test status
Simulation time 161776967 ps
CPU time 3.24 seconds
Started Jul 02 07:53:30 AM PDT 24
Finished Jul 02 07:53:35 AM PDT 24
Peak memory 218744 kb
Host smart-5f94b3fd-2a2b-46ed-add0-40f273d8633b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1001460360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1001460360
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3514882522
Short name T66
Test name
Test status
Simulation time 161879958 ps
CPU time 0.91 seconds
Started Jul 02 07:53:20 AM PDT 24
Finished Jul 02 07:53:23 AM PDT 24
Peak memory 236436 kb
Host smart-247afb6d-150b-46e6-82f6-5c6dcd62940f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514882522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3514882522
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3031406102
Short name T153
Test name
Test status
Simulation time 8888040431 ps
CPU time 124.98 seconds
Started Jul 02 07:53:35 AM PDT 24
Finished Jul 02 07:55:41 AM PDT 24
Peak memory 267156 kb
Host smart-34b9cef6-26e6-4c45-aaa2-75251361a46f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031406102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3031406102
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.548812239
Short name T444
Test name
Test status
Simulation time 2293507775 ps
CPU time 11.63 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:36 AM PDT 24
Peak memory 216252 kb
Host smart-3cae0815-cd6a-408c-a54a-0c5f0d1dbff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548812239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.548812239
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.133343904
Short name T975
Test name
Test status
Simulation time 2725386393 ps
CPU time 5.39 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:30 AM PDT 24
Peak memory 216252 kb
Host smart-ca1b5608-1698-432d-a0d4-a3c0889682b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133343904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.133343904
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2962701310
Short name T985
Test name
Test status
Simulation time 654625220 ps
CPU time 3.94 seconds
Started Jul 02 07:53:35 AM PDT 24
Finished Jul 02 07:53:40 AM PDT 24
Peak memory 216176 kb
Host smart-dc7ecc00-9f7d-4338-ae50-19ece9b1331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962701310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2962701310
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1574571502
Short name T370
Test name
Test status
Simulation time 86682497 ps
CPU time 0.67 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 205512 kb
Host smart-3796cd90-14f0-4d2a-9776-b74a42b83dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574571502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1574571502
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1757047331
Short name T498
Test name
Test status
Simulation time 1530233434 ps
CPU time 14.12 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:39 AM PDT 24
Peak memory 240732 kb
Host smart-e2cccb3d-4ea3-4a7e-ad29-f9327bd24f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757047331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1757047331
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.866817736
Short name T615
Test name
Test status
Simulation time 14092458 ps
CPU time 0.76 seconds
Started Jul 02 07:53:42 AM PDT 24
Finished Jul 02 07:53:44 AM PDT 24
Peak memory 204844 kb
Host smart-dc51af4f-342e-420f-801b-87baa0d02620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866817736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.866817736
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1774343194
Short name T805
Test name
Test status
Simulation time 249616749 ps
CPU time 2.73 seconds
Started Jul 02 07:54:04 AM PDT 24
Finished Jul 02 07:54:13 AM PDT 24
Peak memory 232544 kb
Host smart-d376a3ea-5b56-4cfd-b9b3-69a5a1237f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774343194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1774343194
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3163940297
Short name T834
Test name
Test status
Simulation time 230972597 ps
CPU time 0.76 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:07 AM PDT 24
Peak memory 205740 kb
Host smart-a0231b62-444b-45ed-969c-15c0056dc099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163940297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3163940297
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1694071235
Short name T744
Test name
Test status
Simulation time 24405072 ps
CPU time 0.81 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:54:00 AM PDT 24
Peak memory 215668 kb
Host smart-1f9220af-fc37-4dc2-96e6-a8a3f9481bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694071235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1694071235
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3579107958
Short name T909
Test name
Test status
Simulation time 4706782665 ps
CPU time 56.49 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:54:53 AM PDT 24
Peak memory 249180 kb
Host smart-1dfd8c9b-58be-4cf6-ba71-a8da465250c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579107958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3579107958
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4174739187
Short name T752
Test name
Test status
Simulation time 194297132062 ps
CPU time 86.18 seconds
Started Jul 02 07:53:55 AM PDT 24
Finished Jul 02 07:55:27 AM PDT 24
Peak memory 255888 kb
Host smart-74031408-3e8e-4e45-b8c9-1a576654605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174739187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4174739187
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.760423676
Short name T1007
Test name
Test status
Simulation time 1602698708 ps
CPU time 16.45 seconds
Started Jul 02 07:53:52 AM PDT 24
Finished Jul 02 07:54:14 AM PDT 24
Peak memory 224400 kb
Host smart-304150fa-2ddf-4820-a371-3480011f439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760423676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.760423676
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1659186179
Short name T406
Test name
Test status
Simulation time 10539273004 ps
CPU time 73.42 seconds
Started Jul 02 07:54:07 AM PDT 24
Finished Jul 02 07:55:27 AM PDT 24
Peak memory 237968 kb
Host smart-ccb31efc-367f-4069-86dc-234ce75d37fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659186179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1659186179
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1672179396
Short name T935
Test name
Test status
Simulation time 947939534 ps
CPU time 10.33 seconds
Started Jul 02 07:53:56 AM PDT 24
Finished Jul 02 07:54:13 AM PDT 24
Peak memory 232588 kb
Host smart-2f5b1c5f-3b4a-4264-ac68-39393a8cf07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672179396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1672179396
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2756730177
Short name T420
Test name
Test status
Simulation time 4938678843 ps
CPU time 11.4 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:54:10 AM PDT 24
Peak memory 232612 kb
Host smart-d962b28f-e33c-43fe-bd0b-7848267680ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756730177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2756730177
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3510226868
Short name T718
Test name
Test status
Simulation time 1816525982 ps
CPU time 8.43 seconds
Started Jul 02 07:53:56 AM PDT 24
Finished Jul 02 07:54:11 AM PDT 24
Peak memory 232632 kb
Host smart-8f431cec-c047-4397-9df2-435481e07d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510226868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3510226868
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1101509624
Short name T245
Test name
Test status
Simulation time 2345761560 ps
CPU time 4.07 seconds
Started Jul 02 07:53:56 AM PDT 24
Finished Jul 02 07:54:06 AM PDT 24
Peak memory 224468 kb
Host smart-5232ecdc-8287-481c-abdb-9b9dfd21c985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101509624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1101509624
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3408398496
Short name T74
Test name
Test status
Simulation time 163385355 ps
CPU time 3.44 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 219480 kb
Host smart-b410a4dc-40d1-41ea-9cbc-602772f873d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3408398496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3408398496
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.176751020
Short name T12
Test name
Test status
Simulation time 108509585 ps
CPU time 1.1 seconds
Started Jul 02 07:53:52 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 207612 kb
Host smart-8f5832ed-7496-4212-b8db-0169aeeaa39e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176751020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.176751020
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3082441190
Short name T482
Test name
Test status
Simulation time 6943553048 ps
CPU time 20.72 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:54:17 AM PDT 24
Peak memory 216264 kb
Host smart-0c10bc94-7ee1-461a-94c5-48077f27deae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082441190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3082441190
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.249510485
Short name T697
Test name
Test status
Simulation time 23532698 ps
CPU time 0.74 seconds
Started Jul 02 07:53:35 AM PDT 24
Finished Jul 02 07:53:38 AM PDT 24
Peak memory 205636 kb
Host smart-191892a9-4529-4b4a-8b2f-56a13814f5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249510485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.249510485
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3151365882
Short name T947
Test name
Test status
Simulation time 119143744 ps
CPU time 1.95 seconds
Started Jul 02 07:53:56 AM PDT 24
Finished Jul 02 07:54:05 AM PDT 24
Peak memory 216144 kb
Host smart-583a268b-a419-469a-968b-7803de2d9354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151365882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3151365882
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.375843561
Short name T968
Test name
Test status
Simulation time 245249634 ps
CPU time 0.81 seconds
Started Jul 02 07:54:04 AM PDT 24
Finished Jul 02 07:54:11 AM PDT 24
Peak memory 205868 kb
Host smart-3bef54c6-fb11-4646-98ca-1e6e03da7824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375843561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.375843561
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2706272059
Short name T739
Test name
Test status
Simulation time 4241430514 ps
CPU time 8.19 seconds
Started Jul 02 07:53:47 AM PDT 24
Finished Jul 02 07:53:57 AM PDT 24
Peak memory 224536 kb
Host smart-0cccf285-e139-41c9-8041-c9f9c794bdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706272059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2706272059
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1987996136
Short name T9
Test name
Test status
Simulation time 14807507 ps
CPU time 0.72 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:06 AM PDT 24
Peak memory 205424 kb
Host smart-ff0a5539-827f-4777-9a8b-6bdfcd079f91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987996136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1987996136
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3910281720
Short name T719
Test name
Test status
Simulation time 332559994 ps
CPU time 3.46 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:10 AM PDT 24
Peak memory 224324 kb
Host smart-cecca814-2002-47a0-8ea6-5640ae33216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910281720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3910281720
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2099139417
Short name T795
Test name
Test status
Simulation time 12403157 ps
CPU time 0.73 seconds
Started Jul 02 07:53:47 AM PDT 24
Finished Jul 02 07:53:49 AM PDT 24
Peak memory 205496 kb
Host smart-9c6fec28-78a4-4cec-8bd5-1528ddfe8a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099139417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2099139417
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2230826358
Short name T675
Test name
Test status
Simulation time 259050698222 ps
CPU time 187.47 seconds
Started Jul 02 07:53:55 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 249140 kb
Host smart-ffdcd43d-dd47-48d8-bb3a-f2f64e279911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230826358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2230826358
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3201793337
Short name T262
Test name
Test status
Simulation time 2567748840 ps
CPU time 52.25 seconds
Started Jul 02 07:54:02 AM PDT 24
Finished Jul 02 07:55:00 AM PDT 24
Peak memory 248548 kb
Host smart-bc6202bd-ab03-4809-bf51-89eba411a37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201793337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3201793337
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1319237349
Short name T79
Test name
Test status
Simulation time 32417546688 ps
CPU time 256.01 seconds
Started Jul 02 07:53:52 AM PDT 24
Finished Jul 02 07:58:13 AM PDT 24
Peak memory 257324 kb
Host smart-7f5c638a-0b89-4412-b463-e682fce989cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319237349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1319237349
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.937011280
Short name T1011
Test name
Test status
Simulation time 5179903328 ps
CPU time 20.94 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 07:54:34 AM PDT 24
Peak memory 235924 kb
Host smart-df8dd6a9-429a-4db5-a24a-710a8ece2e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937011280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.937011280
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1223943277
Short name T561
Test name
Test status
Simulation time 4794389063 ps
CPU time 65.58 seconds
Started Jul 02 07:53:41 AM PDT 24
Finished Jul 02 07:54:48 AM PDT 24
Peak memory 249092 kb
Host smart-436bd9fd-80c0-43d5-acb2-4eafc2af6193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223943277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1223943277
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.853201483
Short name T15
Test name
Test status
Simulation time 27447824572 ps
CPU time 113.41 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:55:54 AM PDT 24
Peak memory 249708 kb
Host smart-dceda79c-3bc3-449c-9ebd-1174e5c7d913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853201483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.853201483
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2241814139
Short name T819
Test name
Test status
Simulation time 2691268915 ps
CPU time 9.6 seconds
Started Jul 02 07:53:48 AM PDT 24
Finished Jul 02 07:54:01 AM PDT 24
Peak memory 232704 kb
Host smart-3024aa89-2b83-4175-bc71-0109b2c4c398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241814139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2241814139
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.850080367
Short name T475
Test name
Test status
Simulation time 319007508 ps
CPU time 3.2 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:53:59 AM PDT 24
Peak memory 224364 kb
Host smart-322bec7c-7e73-4fb8-a730-e667102169f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850080367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.850080367
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3845136473
Short name T571
Test name
Test status
Simulation time 994467703 ps
CPU time 4.67 seconds
Started Jul 02 07:53:50 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 219148 kb
Host smart-46fbcb6b-84cf-4288-b34a-a5a317a4f3b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3845136473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3845136473
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.385269402
Short name T839
Test name
Test status
Simulation time 9556311594 ps
CPU time 25.97 seconds
Started Jul 02 07:53:56 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 216208 kb
Host smart-7ba907f6-3b48-4bd5-9e31-4f3d370fd2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385269402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.385269402
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1177153306
Short name T486
Test name
Test status
Simulation time 3774384278 ps
CPU time 10.46 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:54:06 AM PDT 24
Peak memory 216236 kb
Host smart-f5791638-d6ad-4be0-8305-792f3a66ad40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177153306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1177153306
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.147141734
Short name T836
Test name
Test status
Simulation time 1044781833 ps
CPU time 4.96 seconds
Started Jul 02 07:53:58 AM PDT 24
Finished Jul 02 07:54:09 AM PDT 24
Peak memory 216104 kb
Host smart-1d1fbc4a-3c3f-4a22-a12f-70c320dcf0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147141734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.147141734
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3070770400
Short name T588
Test name
Test status
Simulation time 63645306 ps
CPU time 0.89 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:07 AM PDT 24
Peak memory 206064 kb
Host smart-023ead51-e578-4f86-80e2-f667dd18e801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070770400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3070770400
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3530142005
Short name T940
Test name
Test status
Simulation time 5687150890 ps
CPU time 17.08 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 232672 kb
Host smart-82915afd-ee09-41cd-9a29-a4ef4908b089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530142005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3530142005
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2250522964
Short name T525
Test name
Test status
Simulation time 17294449 ps
CPU time 0.75 seconds
Started Jul 02 07:54:03 AM PDT 24
Finished Jul 02 07:54:10 AM PDT 24
Peak memory 205808 kb
Host smart-d5d312ba-98a6-4f5f-9c53-01754ac3ab82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250522964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2250522964
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2092969371
Short name T856
Test name
Test status
Simulation time 2787435948 ps
CPU time 10.6 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:18 AM PDT 24
Peak memory 224532 kb
Host smart-b5d2b035-540e-4587-9540-062373ccb046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092969371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2092969371
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2112525563
Short name T354
Test name
Test status
Simulation time 15144721 ps
CPU time 0.73 seconds
Started Jul 02 07:53:46 AM PDT 24
Finished Jul 02 07:53:48 AM PDT 24
Peak memory 206808 kb
Host smart-30c6213c-83c1-4aad-a998-a7a5ea6175c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112525563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2112525563
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.697485449
Short name T686
Test name
Test status
Simulation time 1623457751 ps
CPU time 16.07 seconds
Started Jul 02 07:53:57 AM PDT 24
Finished Jul 02 07:54:20 AM PDT 24
Peak memory 249320 kb
Host smart-62283faa-eb60-45e0-8e1a-1c2704410161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697485449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.697485449
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4154565112
Short name T948
Test name
Test status
Simulation time 1395911918 ps
CPU time 17.93 seconds
Started Jul 02 07:53:57 AM PDT 24
Finished Jul 02 07:54:21 AM PDT 24
Peak memory 217372 kb
Host smart-1fd2f0c0-f1d9-46be-b70f-7bdbb4e711ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154565112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4154565112
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2474233200
Short name T137
Test name
Test status
Simulation time 131440761661 ps
CPU time 297.74 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:59:17 AM PDT 24
Peak memory 250248 kb
Host smart-3b7d4758-c834-4892-bbb1-fa2615ca09e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474233200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2474233200
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3724578082
Short name T778
Test name
Test status
Simulation time 1417700850 ps
CPU time 14.47 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:21 AM PDT 24
Peak memory 240800 kb
Host smart-4355d443-a715-41c1-9cd5-596a51b13b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724578082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3724578082
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.82616545
Short name T792
Test name
Test status
Simulation time 18554600767 ps
CPU time 58.66 seconds
Started Jul 02 07:54:03 AM PDT 24
Finished Jul 02 07:55:08 AM PDT 24
Peak memory 256328 kb
Host smart-abad30ca-5a0f-4a8d-b894-1f89492bc6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82616545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.82616545
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2990618611
Short name T594
Test name
Test status
Simulation time 657106137 ps
CPU time 3.63 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 07:54:16 AM PDT 24
Peak memory 224308 kb
Host smart-b5d8f9c9-ccfb-4158-be79-7a5e15ff3a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990618611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2990618611
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2672658900
Short name T956
Test name
Test status
Simulation time 4410082700 ps
CPU time 48.73 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 07:55:01 AM PDT 24
Peak memory 224352 kb
Host smart-416f6788-d57e-461f-8d11-a8ec032f3ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672658900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2672658900
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3071576920
Short name T665
Test name
Test status
Simulation time 15647253491 ps
CPU time 9.41 seconds
Started Jul 02 07:54:03 AM PDT 24
Finished Jul 02 07:54:19 AM PDT 24
Peak memory 233000 kb
Host smart-66df682c-6012-4364-b1fc-b88af10f345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071576920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3071576920
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1451206952
Short name T246
Test name
Test status
Simulation time 3531910375 ps
CPU time 4 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:26 AM PDT 24
Peak memory 232592 kb
Host smart-189d9bf0-22e2-436b-86c2-ebc44a249d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451206952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1451206952
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1924156367
Short name T518
Test name
Test status
Simulation time 1979022749 ps
CPU time 6.04 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:54:05 AM PDT 24
Peak memory 220096 kb
Host smart-0c2fd5df-b3fa-4875-9ff9-74a09b47f3ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1924156367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1924156367
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1244080225
Short name T217
Test name
Test status
Simulation time 30001958502 ps
CPU time 80.91 seconds
Started Jul 02 07:54:03 AM PDT 24
Finished Jul 02 07:55:29 AM PDT 24
Peak memory 255800 kb
Host smart-9086b084-aec9-4936-acb0-466ffd397ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244080225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1244080225
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1484292612
Short name T293
Test name
Test status
Simulation time 3886787382 ps
CPU time 22.12 seconds
Started Jul 02 07:53:58 AM PDT 24
Finished Jul 02 07:54:26 AM PDT 24
Peak memory 219900 kb
Host smart-d2d8e724-bda3-4a46-bfed-66a03ad2e69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484292612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1484292612
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1069925906
Short name T565
Test name
Test status
Simulation time 66949974630 ps
CPU time 21.54 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:54:21 AM PDT 24
Peak memory 216416 kb
Host smart-af7958dd-f197-458c-b203-94813f818f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069925906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1069925906
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3223182082
Short name T501
Test name
Test status
Simulation time 114966154 ps
CPU time 1.36 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:07 AM PDT 24
Peak memory 216172 kb
Host smart-42905ce0-cf82-4c9e-b869-f83d32fd7f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223182082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3223182082
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.596649685
Short name T437
Test name
Test status
Simulation time 78971785 ps
CPU time 0.78 seconds
Started Jul 02 07:53:57 AM PDT 24
Finished Jul 02 07:54:04 AM PDT 24
Peak memory 206184 kb
Host smart-0800f924-93a3-441b-b66f-bc1427e92894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596649685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.596649685
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.479443917
Short name T906
Test name
Test status
Simulation time 22161296063 ps
CPU time 17.12 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 07:54:30 AM PDT 24
Peak memory 232604 kb
Host smart-b0c1149e-c754-4124-8c78-4f34860f3bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479443917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.479443917
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1182782769
Short name T674
Test name
Test status
Simulation time 30043983 ps
CPU time 0.76 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:06 AM PDT 24
Peak memory 205768 kb
Host smart-fd429e9c-5753-4dc4-87da-ea70e4e7ff57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182782769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1182782769
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2342730814
Short name T604
Test name
Test status
Simulation time 258802033 ps
CPU time 4.61 seconds
Started Jul 02 07:54:05 AM PDT 24
Finished Jul 02 07:54:16 AM PDT 24
Peak memory 224412 kb
Host smart-ff2b51a1-4176-4854-8359-518bde8939aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342730814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2342730814
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1932977195
Short name T457
Test name
Test status
Simulation time 41538174 ps
CPU time 0.8 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:07 AM PDT 24
Peak memory 206452 kb
Host smart-0a0df2a7-825f-42c0-b858-4d4864b991bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932977195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1932977195
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4064064050
Short name T529
Test name
Test status
Simulation time 3473231982 ps
CPU time 24.63 seconds
Started Jul 02 07:54:03 AM PDT 24
Finished Jul 02 07:54:34 AM PDT 24
Peak memory 240900 kb
Host smart-19ecf03b-1cfb-4baf-8339-569bbe63e3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064064050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4064064050
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3859096033
Short name T920
Test name
Test status
Simulation time 5518531550 ps
CPU time 60.18 seconds
Started Jul 02 07:53:57 AM PDT 24
Finished Jul 02 07:55:03 AM PDT 24
Peak memory 252492 kb
Host smart-8c02f6a6-3331-40c7-9028-008e0e47dcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859096033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3859096033
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1477696705
Short name T185
Test name
Test status
Simulation time 10442326792 ps
CPU time 92.95 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:55:39 AM PDT 24
Peak memory 256724 kb
Host smart-2af3a150-11b8-4daf-b4fa-37f120ed9b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477696705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1477696705
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3489139012
Short name T810
Test name
Test status
Simulation time 3769555699 ps
CPU time 8.08 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:14 AM PDT 24
Peak memory 224400 kb
Host smart-1f27ca20-e24b-4659-a811-bc283e6327aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489139012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3489139012
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2265386509
Short name T997
Test name
Test status
Simulation time 55138122000 ps
CPU time 398.75 seconds
Started Jul 02 07:54:05 AM PDT 24
Finished Jul 02 08:00:50 AM PDT 24
Peak memory 257096 kb
Host smart-ccd1c76a-d6bd-4abd-96a1-e11ae66a4f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265386509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2265386509
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2131888000
Short name T859
Test name
Test status
Simulation time 4821574579 ps
CPU time 14.28 seconds
Started Jul 02 07:54:07 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 224516 kb
Host smart-6829d715-0c35-458c-9fb1-b7e6d3dc3982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131888000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2131888000
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4082039805
Short name T637
Test name
Test status
Simulation time 30392847464 ps
CPU time 29.51 seconds
Started Jul 02 07:54:17 AM PDT 24
Finished Jul 02 07:54:57 AM PDT 24
Peak memory 224516 kb
Host smart-43b10f85-9c71-4593-bef3-6832d9ab6f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082039805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4082039805
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3512659503
Short name T488
Test name
Test status
Simulation time 59661146 ps
CPU time 2.27 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:09 AM PDT 24
Peak memory 224324 kb
Host smart-e30fbb16-0c64-467f-9da0-c42297fbb533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512659503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3512659503
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.712109674
Short name T259
Test name
Test status
Simulation time 1075382227 ps
CPU time 6.77 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 07:54:19 AM PDT 24
Peak memory 224348 kb
Host smart-ab14a934-2761-4414-89ac-d2c19d93ae2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712109674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.712109674
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2546205267
Short name T976
Test name
Test status
Simulation time 5044978126 ps
CPU time 9.3 seconds
Started Jul 02 07:53:58 AM PDT 24
Finished Jul 02 07:54:14 AM PDT 24
Peak memory 218952 kb
Host smart-57017fe9-13e4-4004-9cae-acbe885e7b79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2546205267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2546205267
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1311428776
Short name T20
Test name
Test status
Simulation time 26137143246 ps
CPU time 263.35 seconds
Started Jul 02 07:54:02 AM PDT 24
Finished Jul 02 07:58:32 AM PDT 24
Peak memory 249492 kb
Host smart-c1271c0a-bb50-4d98-9e58-fd5efb400fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311428776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1311428776
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3927581241
Short name T340
Test name
Test status
Simulation time 406942306 ps
CPU time 2.25 seconds
Started Jul 02 07:53:56 AM PDT 24
Finished Jul 02 07:54:05 AM PDT 24
Peak memory 216176 kb
Host smart-dea91ea0-ff93-4530-8167-a8c01f57810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927581241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3927581241
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1070289893
Short name T796
Test name
Test status
Simulation time 1628635433 ps
CPU time 6.37 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:12 AM PDT 24
Peak memory 216352 kb
Host smart-4aa36dba-3867-4d9a-95ad-854d1991ff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070289893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1070289893
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1254659663
Short name T493
Test name
Test status
Simulation time 89691326 ps
CPU time 1.13 seconds
Started Jul 02 07:54:21 AM PDT 24
Finished Jul 02 07:54:31 AM PDT 24
Peak memory 206952 kb
Host smart-eaf432e9-bc24-4f29-861e-370086af6359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254659663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1254659663
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2688285546
Short name T540
Test name
Test status
Simulation time 25733125 ps
CPU time 0.81 seconds
Started Jul 02 07:53:57 AM PDT 24
Finished Jul 02 07:54:04 AM PDT 24
Peak memory 205832 kb
Host smart-940879ea-bf36-452a-98ed-5f14651e9538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688285546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2688285546
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.667883311
Short name T260
Test name
Test status
Simulation time 7859121581 ps
CPU time 23.92 seconds
Started Jul 02 07:54:04 AM PDT 24
Finished Jul 02 07:54:34 AM PDT 24
Peak memory 224508 kb
Host smart-1cc8d0ae-b1e3-4395-a674-b9887af74e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667883311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.667883311
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2773861915
Short name T625
Test name
Test status
Simulation time 17892958 ps
CPU time 0.74 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 205452 kb
Host smart-2168d884-c75d-4a4f-8c19-1be58e7dac92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773861915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2773861915
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.111892603
Short name T936
Test name
Test status
Simulation time 103233185 ps
CPU time 3.96 seconds
Started Jul 02 07:53:52 AM PDT 24
Finished Jul 02 07:54:01 AM PDT 24
Peak memory 232612 kb
Host smart-33c8f3ae-4899-436e-b674-dd93162b816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111892603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.111892603
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3131652546
Short name T554
Test name
Test status
Simulation time 57934499 ps
CPU time 0.74 seconds
Started Jul 02 07:54:05 AM PDT 24
Finished Jul 02 07:54:12 AM PDT 24
Peak memory 205508 kb
Host smart-c486b79d-5fc3-4191-b1fd-30ae73726186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131652546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3131652546
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.780243940
Short name T178
Test name
Test status
Simulation time 18914106666 ps
CPU time 71.96 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 07:55:25 AM PDT 24
Peak memory 256508 kb
Host smart-6240c074-ba1a-44e8-aca5-3385cb519761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780243940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.780243940
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2340925589
Short name T315
Test name
Test status
Simulation time 1445405842 ps
CPU time 11.23 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:33 AM PDT 24
Peak memory 238476 kb
Host smart-4d24d474-5b33-43e1-a6b7-3ebf3c621856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340925589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2340925589
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.247628444
Short name T865
Test name
Test status
Simulation time 266124027 ps
CPU time 3.91 seconds
Started Jul 02 07:54:09 AM PDT 24
Finished Jul 02 07:54:21 AM PDT 24
Peak memory 232564 kb
Host smart-926eb792-13b8-4fe5-b894-6257f7a6c5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247628444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.247628444
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1994223919
Short name T598
Test name
Test status
Simulation time 591161228 ps
CPU time 14.24 seconds
Started Jul 02 07:54:05 AM PDT 24
Finished Jul 02 07:54:26 AM PDT 24
Peak memory 239484 kb
Host smart-fd34468c-7549-4182-8d18-496b380a3d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994223919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1994223919
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3457470022
Short name T390
Test name
Test status
Simulation time 1746449999 ps
CPU time 2.93 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:54:02 AM PDT 24
Peak memory 224364 kb
Host smart-ccb15f26-bacb-4d98-a141-31ee35fc25f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457470022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3457470022
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4068968433
Short name T330
Test name
Test status
Simulation time 875808018 ps
CPU time 2.21 seconds
Started Jul 02 07:53:48 AM PDT 24
Finished Jul 02 07:53:53 AM PDT 24
Peak memory 223628 kb
Host smart-09013898-9439-4ec7-921f-0b2a50afb165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068968433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4068968433
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2914532474
Short name T635
Test name
Test status
Simulation time 2724647179 ps
CPU time 9.71 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:31 AM PDT 24
Peak memory 222824 kb
Host smart-adeeef44-a36b-4d1d-a649-ebc1daca59cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2914532474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2914532474
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2189312462
Short name T19
Test name
Test status
Simulation time 6728614978 ps
CPU time 89.86 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:55:37 AM PDT 24
Peak memory 249220 kb
Host smart-ec1d4f90-baf7-4e47-8422-a24dabc04c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189312462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2189312462
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2115600626
Short name T584
Test name
Test status
Simulation time 17370033622 ps
CPU time 27.72 seconds
Started Jul 02 07:54:17 AM PDT 24
Finished Jul 02 07:54:55 AM PDT 24
Peak memory 216592 kb
Host smart-586b0b6c-46dc-4e67-8880-22af379d4d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115600626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2115600626
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.852768282
Short name T679
Test name
Test status
Simulation time 754022370 ps
CPU time 3.36 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:09 AM PDT 24
Peak memory 216120 kb
Host smart-b1c0dc16-ddde-4be1-bfd2-9af3d5b00d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852768282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.852768282
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1725234152
Short name T812
Test name
Test status
Simulation time 80156479 ps
CPU time 1.37 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:16 AM PDT 24
Peak memory 207940 kb
Host smart-cb9324ea-d9e2-43d4-9ca1-b1aedf002e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725234152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1725234152
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.392163705
Short name T574
Test name
Test status
Simulation time 110722321 ps
CPU time 0.81 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:17 AM PDT 24
Peak memory 205856 kb
Host smart-99452193-3e56-4765-b321-0bf9b116051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392163705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.392163705
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2068683063
Short name T682
Test name
Test status
Simulation time 6860111222 ps
CPU time 8.67 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:25 AM PDT 24
Peak memory 240796 kb
Host smart-57de005b-00b5-49b9-9772-6d3ad7777b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068683063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2068683063
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3205020376
Short name T490
Test name
Test status
Simulation time 14792685 ps
CPU time 0.7 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:17 AM PDT 24
Peak memory 205804 kb
Host smart-7f8f4827-995d-4f21-89f7-38516f6c92c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205020376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3205020376
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.182264117
Short name T26
Test name
Test status
Simulation time 90604598 ps
CPU time 2.39 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:09 AM PDT 24
Peak memory 224408 kb
Host smart-87a571bd-9b0d-463b-824e-81bf7bf947d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182264117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.182264117
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2721325195
Short name T919
Test name
Test status
Simulation time 19030033 ps
CPU time 0.74 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:18 AM PDT 24
Peak memory 205496 kb
Host smart-320d5077-f14d-45bc-b5c3-1e1d8b4b50b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721325195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2721325195
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4184764017
Short name T249
Test name
Test status
Simulation time 103742858363 ps
CPU time 349.7 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 08:00:02 AM PDT 24
Peak memory 253012 kb
Host smart-eae3643d-4bcc-4e76-b5a1-5a85b4cdfa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184764017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4184764017
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.118094821
Short name T748
Test name
Test status
Simulation time 4554719956 ps
CPU time 80.37 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:55:43 AM PDT 24
Peak memory 251856 kb
Host smart-41782f13-bc98-4a19-9755-64f6b7d3f4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118094821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.118094821
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1589739998
Short name T817
Test name
Test status
Simulation time 221090673268 ps
CPU time 520.14 seconds
Started Jul 02 07:53:58 AM PDT 24
Finished Jul 02 08:02:44 AM PDT 24
Peak memory 264808 kb
Host smart-4f0b2f62-9f9d-4e6f-805e-d4cd094b79ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589739998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1589739998
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2017880982
Short name T285
Test name
Test status
Simulation time 509742553 ps
CPU time 8.46 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:30 AM PDT 24
Peak memory 233680 kb
Host smart-64e93e34-8634-4ee8-8ce1-44552790eaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017880982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2017880982
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1376686444
Short name T96
Test name
Test status
Simulation time 2095395339 ps
CPU time 29.32 seconds
Started Jul 02 07:53:57 AM PDT 24
Finished Jul 02 07:54:33 AM PDT 24
Peak memory 253264 kb
Host smart-7e3d6179-7ea2-4012-becf-937a26b27242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376686444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1376686444
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.188027177
Short name T607
Test name
Test status
Simulation time 2138684247 ps
CPU time 21.31 seconds
Started Jul 02 07:54:04 AM PDT 24
Finished Jul 02 07:54:32 AM PDT 24
Peak memory 224376 kb
Host smart-be8b46d6-91ec-448c-9e01-80cb97b03615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188027177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.188027177
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.189558656
Short name T258
Test name
Test status
Simulation time 15984563349 ps
CPU time 56.24 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:55:18 AM PDT 24
Peak memory 232692 kb
Host smart-e32a2360-f8a4-43e5-861e-44d1964cbd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189558656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.189558656
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2267968452
Short name T853
Test name
Test status
Simulation time 19975075999 ps
CPU time 9.45 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:28 AM PDT 24
Peak memory 232696 kb
Host smart-49a9a9e7-2463-42d9-a994-73457da0175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267968452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2267968452
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1964253296
Short name T946
Test name
Test status
Simulation time 147646840 ps
CPU time 3.38 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 224360 kb
Host smart-c9f84ef1-b9fa-4cf4-ab65-2d4780756da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964253296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1964253296
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1312913990
Short name T458
Test name
Test status
Simulation time 129963049 ps
CPU time 3.6 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:09 AM PDT 24
Peak memory 222976 kb
Host smart-c7ed97c4-4893-455f-bc20-bb2bfa21f0d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1312913990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1312913990
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2106569000
Short name T21
Test name
Test status
Simulation time 69081530241 ps
CPU time 174.8 seconds
Started Jul 02 07:54:03 AM PDT 24
Finished Jul 02 07:57:04 AM PDT 24
Peak memory 249832 kb
Host smart-dcfa0a73-44f1-4f9a-9da4-d524c314d82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106569000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2106569000
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1165315257
Short name T917
Test name
Test status
Simulation time 15674271727 ps
CPU time 19.34 seconds
Started Jul 02 07:54:09 AM PDT 24
Finished Jul 02 07:54:36 AM PDT 24
Peak memory 216308 kb
Host smart-11c2ff6f-64cf-4219-ad76-78fd88ceb730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165315257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1165315257
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4173655176
Short name T706
Test name
Test status
Simulation time 521024171 ps
CPU time 4.35 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 07:54:28 AM PDT 24
Peak memory 216196 kb
Host smart-6b00ecbd-ac9a-4ca6-b50b-60124baf6dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173655176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4173655176
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.221992452
Short name T505
Test name
Test status
Simulation time 817540433 ps
CPU time 1.79 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:22 AM PDT 24
Peak memory 207888 kb
Host smart-0abbd09f-a4bd-4fe9-8783-a5fb9b7ffde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221992452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.221992452
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3920929845
Short name T87
Test name
Test status
Simulation time 69154661 ps
CPU time 0.71 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:20 AM PDT 24
Peak memory 205876 kb
Host smart-6275fe82-04ff-4800-9314-06f7b4fec15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920929845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3920929845
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1213139966
Short name T243
Test name
Test status
Simulation time 10858448492 ps
CPU time 5.72 seconds
Started Jul 02 07:54:05 AM PDT 24
Finished Jul 02 07:54:17 AM PDT 24
Peak memory 224428 kb
Host smart-1f83a637-24f6-42b1-9d99-0dbfd60cd24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213139966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1213139966
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1323375814
Short name T957
Test name
Test status
Simulation time 11868243 ps
CPU time 0.7 seconds
Started Jul 02 07:54:07 AM PDT 24
Finished Jul 02 07:54:15 AM PDT 24
Peak memory 205132 kb
Host smart-aec5c416-a63a-43a1-a5bf-9dd2a7a22dde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323375814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1323375814
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1002072482
Short name T788
Test name
Test status
Simulation time 206212154 ps
CPU time 3.64 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:10 AM PDT 24
Peak memory 224404 kb
Host smart-7cfa25bf-47de-4d7b-a948-522676e49f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002072482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1002072482
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1549471990
Short name T337
Test name
Test status
Simulation time 25542726 ps
CPU time 0.78 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:07 AM PDT 24
Peak memory 206500 kb
Host smart-c25607be-e5d8-4c8c-bc50-b8d951aa0850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549471990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1549471990
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3519038243
Short name T199
Test name
Test status
Simulation time 141320495226 ps
CPU time 350.8 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 08:00:12 AM PDT 24
Peak memory 265508 kb
Host smart-f41e90c2-3421-460a-85dc-8897c7e50a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519038243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3519038243
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4292010662
Short name T85
Test name
Test status
Simulation time 18692303456 ps
CPU time 34.96 seconds
Started Jul 02 07:54:20 AM PDT 24
Finished Jul 02 07:55:05 AM PDT 24
Peak memory 232824 kb
Host smart-62efe87f-f33d-42dd-8249-2fb49c9a8d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292010662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4292010662
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3697836354
Short name T980
Test name
Test status
Simulation time 7448577869 ps
CPU time 105.59 seconds
Started Jul 02 07:54:15 AM PDT 24
Finished Jul 02 07:56:11 AM PDT 24
Peak memory 265332 kb
Host smart-13335848-6679-4049-a450-9c5f54efd008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697836354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3697836354
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1088165436
Short name T502
Test name
Test status
Simulation time 403104317 ps
CPU time 3.26 seconds
Started Jul 02 07:54:15 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 232620 kb
Host smart-0d7f55a0-3b43-496d-ad00-ab9196259640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088165436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1088165436
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.184646461
Short name T870
Test name
Test status
Simulation time 3108126520 ps
CPU time 58.59 seconds
Started Jul 02 07:54:07 AM PDT 24
Finished Jul 02 07:55:13 AM PDT 24
Peak memory 249128 kb
Host smart-27c6c4b8-0155-41af-ab89-9a1294c52fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184646461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.184646461
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2397390083
Short name T362
Test name
Test status
Simulation time 608725389 ps
CPU time 3.52 seconds
Started Jul 02 07:54:07 AM PDT 24
Finished Jul 02 07:54:18 AM PDT 24
Peak memory 232492 kb
Host smart-6a7707f1-712b-414f-8b51-b79341a6bccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397390083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2397390083
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4255369686
Short name T511
Test name
Test status
Simulation time 3053509812 ps
CPU time 20.59 seconds
Started Jul 02 07:54:07 AM PDT 24
Finished Jul 02 07:54:35 AM PDT 24
Peak memory 232692 kb
Host smart-acdb620b-ea9e-4914-8a98-ad1d4c74f83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255369686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4255369686
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3857252313
Short name T184
Test name
Test status
Simulation time 10923662908 ps
CPU time 12.4 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:19 AM PDT 24
Peak memory 240692 kb
Host smart-75958bff-bc52-4189-a624-3dd2fed06784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857252313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3857252313
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.4120077020
Short name T692
Test name
Test status
Simulation time 1900183515 ps
CPU time 6.23 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:25 AM PDT 24
Peak memory 224416 kb
Host smart-6d6fc321-ed5a-4236-ab6d-031265676056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120077020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.4120077020
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3828836281
Short name T358
Test name
Test status
Simulation time 1125837276 ps
CPU time 4.69 seconds
Started Jul 02 07:54:09 AM PDT 24
Finished Jul 02 07:54:22 AM PDT 24
Peak memory 223008 kb
Host smart-d00b21c3-514b-45e6-ac47-1210922e629f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3828836281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3828836281
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2211816486
Short name T154
Test name
Test status
Simulation time 6776798267 ps
CPU time 103 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:56:08 AM PDT 24
Peak memory 263780 kb
Host smart-8c1ca96f-5fa3-487c-82a3-90f03fe44d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211816486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2211816486
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2285657384
Short name T659
Test name
Test status
Simulation time 14018648675 ps
CPU time 36.54 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:57 AM PDT 24
Peak memory 216264 kb
Host smart-4e24f17b-bb62-49dd-97b2-3673e5bbe075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285657384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2285657384
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.669258308
Short name T616
Test name
Test status
Simulation time 28828504064 ps
CPU time 16.19 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:39 AM PDT 24
Peak memory 216232 kb
Host smart-3def33a3-87cb-4837-aff3-a68f0dbd1473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669258308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.669258308
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3729538719
Short name T811
Test name
Test status
Simulation time 27313069 ps
CPU time 1.67 seconds
Started Jul 02 07:54:05 AM PDT 24
Finished Jul 02 07:54:13 AM PDT 24
Peak memory 216084 kb
Host smart-06b0959c-c434-472c-93a6-28dc9d9791bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729538719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3729538719
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4193917298
Short name T601
Test name
Test status
Simulation time 21009411 ps
CPU time 0.76 seconds
Started Jul 02 07:54:05 AM PDT 24
Finished Jul 02 07:54:12 AM PDT 24
Peak memory 205864 kb
Host smart-342dc884-f4bf-40a1-804c-f1f37abc145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193917298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4193917298
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2011173495
Short name T814
Test name
Test status
Simulation time 2698052837 ps
CPU time 11.72 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:33 AM PDT 24
Peak memory 232964 kb
Host smart-a6795320-5d6a-49ff-b064-7836369a67c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011173495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2011173495
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.332706544
Short name T655
Test name
Test status
Simulation time 34400745 ps
CPU time 0.71 seconds
Started Jul 02 07:54:15 AM PDT 24
Finished Jul 02 07:54:26 AM PDT 24
Peak memory 205488 kb
Host smart-7fe0c7d6-de85-4858-a805-71dd3d6f3a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332706544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.332706544
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2102870163
Short name T381
Test name
Test status
Simulation time 62170171 ps
CPU time 2.73 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:24 AM PDT 24
Peak memory 232592 kb
Host smart-4748aa0a-d9ca-4eca-b4a8-9448233bb7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102870163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2102870163
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3554436822
Short name T827
Test name
Test status
Simulation time 47549896 ps
CPU time 0.74 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:54:27 AM PDT 24
Peak memory 206800 kb
Host smart-0fc69f9a-c112-4b93-87f8-4fc351a75fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554436822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3554436822
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.759205508
Short name T888
Test name
Test status
Simulation time 1286954242 ps
CPU time 10.54 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:54:37 AM PDT 24
Peak memory 224432 kb
Host smart-39244620-50bd-48da-bcd2-8b10b6e04cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759205508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.759205508
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3388498323
Short name T388
Test name
Test status
Simulation time 5879033146 ps
CPU time 30.75 seconds
Started Jul 02 07:54:21 AM PDT 24
Finished Jul 02 07:55:01 AM PDT 24
Peak memory 224628 kb
Host smart-e453386d-cb28-48d6-9363-b681fea0ae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388498323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3388498323
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1696992324
Short name T278
Test name
Test status
Simulation time 8184549268 ps
CPU time 43.07 seconds
Started Jul 02 07:54:04 AM PDT 24
Finished Jul 02 07:54:53 AM PDT 24
Peak memory 233804 kb
Host smart-d7da711f-e26d-427e-a763-2bf92517b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696992324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1696992324
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.639622850
Short name T450
Test name
Test status
Simulation time 1820815690 ps
CPU time 8.53 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:30 AM PDT 24
Peak memory 230572 kb
Host smart-beed0d26-500f-479b-b1b2-f04d088105a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639622850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.639622850
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3880203045
Short name T506
Test name
Test status
Simulation time 49342753721 ps
CPU time 88.24 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:55:48 AM PDT 24
Peak memory 224520 kb
Host smart-8c81b110-3b81-4502-bbb5-07a9f5607c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880203045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3880203045
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1669264037
Short name T158
Test name
Test status
Simulation time 106585736 ps
CPU time 2.85 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:54:27 AM PDT 24
Peak memory 224348 kb
Host smart-69ca3e1b-81f8-4a72-8740-8b455ec3b0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669264037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1669264037
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.655270541
Short name T470
Test name
Test status
Simulation time 286035591 ps
CPU time 2.06 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:07 AM PDT 24
Peak memory 222688 kb
Host smart-ef14b9cd-3b7e-45bc-871f-6b98e485cdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655270541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.655270541
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1776052853
Short name T248
Test name
Test status
Simulation time 4868690459 ps
CPU time 18.27 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:40 AM PDT 24
Peak memory 239004 kb
Host smart-5f5d4160-b8bb-4f5f-ba13-1ea871e2ac78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776052853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1776052853
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3092297501
Short name T421
Test name
Test status
Simulation time 31594445375 ps
CPU time 8.8 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:24 AM PDT 24
Peak memory 224472 kb
Host smart-970c4951-029a-42a1-a982-a9f8543ac1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092297501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3092297501
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.282979321
Short name T610
Test name
Test status
Simulation time 258531014 ps
CPU time 3.27 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 07:54:15 AM PDT 24
Peak memory 218744 kb
Host smart-40a04457-9f2a-44c4-b300-834add6f3123
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=282979321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.282979321
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.609822596
Short name T50
Test name
Test status
Simulation time 115622615951 ps
CPU time 501.12 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 08:02:46 AM PDT 24
Peak memory 265148 kb
Host smart-0fa315a0-ca8d-45dc-a649-565cb0f67d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609822596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.609822596
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3153047228
Short name T603
Test name
Test status
Simulation time 7638472665 ps
CPU time 37.8 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:55:05 AM PDT 24
Peak memory 216448 kb
Host smart-73581304-b6dd-4cc6-ab8e-8efe392c272c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153047228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3153047228
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2949269162
Short name T602
Test name
Test status
Simulation time 780253951 ps
CPU time 4.75 seconds
Started Jul 02 07:54:01 AM PDT 24
Finished Jul 02 07:54:12 AM PDT 24
Peak memory 216028 kb
Host smart-10aff1e4-ff44-46db-b273-fea9868683a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949269162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2949269162
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4259720228
Short name T512
Test name
Test status
Simulation time 452028291 ps
CPU time 2.04 seconds
Started Jul 02 07:54:07 AM PDT 24
Finished Jul 02 07:54:15 AM PDT 24
Peak memory 216128 kb
Host smart-28cdcb92-3959-4e63-98d7-0c2b1c204f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259720228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4259720228
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3469422393
Short name T646
Test name
Test status
Simulation time 48661109 ps
CPU time 0.78 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:22 AM PDT 24
Peak memory 205920 kb
Host smart-5ce7e80a-e0ce-4365-b2cb-5c70eb109ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469422393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3469422393
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.735581592
Short name T562
Test name
Test status
Simulation time 13063014607 ps
CPU time 36.33 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:55:01 AM PDT 24
Peak memory 232720 kb
Host smart-91c0d0be-0808-4722-b6e8-6d36f9ebbde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735581592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.735581592
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1396795599
Short name T557
Test name
Test status
Simulation time 15165512 ps
CPU time 0.7 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:54:27 AM PDT 24
Peak memory 205420 kb
Host smart-de67c884-0a88-481e-88ba-5db524608ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396795599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1396795599
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3762697382
Short name T583
Test name
Test status
Simulation time 2916890757 ps
CPU time 12.69 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:30 AM PDT 24
Peak memory 232712 kb
Host smart-82220006-3b17-4cf2-8e21-72e3ee314263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762697382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3762697382
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1251345832
Short name T945
Test name
Test status
Simulation time 22743054 ps
CPU time 0.79 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:22 AM PDT 24
Peak memory 206848 kb
Host smart-39cb82ed-9802-451f-ae68-e913c1f23c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251345832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1251345832
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.4014376168
Short name T590
Test name
Test status
Simulation time 5065221217 ps
CPU time 13.47 seconds
Started Jul 02 07:54:15 AM PDT 24
Finished Jul 02 07:54:39 AM PDT 24
Peak memory 237688 kb
Host smart-3ed7e6a2-428e-4caa-aec3-8a1d4715afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014376168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4014376168
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1423838461
Short name T313
Test name
Test status
Simulation time 1481424066 ps
CPU time 22.22 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 07:54:45 AM PDT 24
Peak memory 248976 kb
Host smart-c64de486-7977-4d07-9db6-328d09d63b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423838461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1423838461
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.4147005292
Short name T926
Test name
Test status
Simulation time 7360887383 ps
CPU time 30.41 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:55:09 AM PDT 24
Peak memory 240880 kb
Host smart-06224295-a467-44e4-a611-71f3f7a5d367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147005292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.4147005292
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1698468583
Short name T723
Test name
Test status
Simulation time 94310195 ps
CPU time 3.05 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:21 AM PDT 24
Peak memory 232588 kb
Host smart-070a1c1b-cfab-460f-a5f0-2aa7c1c8221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698468583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1698468583
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1316349265
Short name T229
Test name
Test status
Simulation time 10362676200 ps
CPU time 24.25 seconds
Started Jul 02 07:54:22 AM PDT 24
Finished Jul 02 07:54:55 AM PDT 24
Peak memory 224508 kb
Host smart-17173b6d-d910-4cd3-bcfc-25c65e1d790a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316349265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1316349265
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4234405187
Short name T621
Test name
Test status
Simulation time 71828050284 ps
CPU time 14.29 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:40 AM PDT 24
Peak memory 232704 kb
Host smart-63eebe86-f8bb-4c32-8acb-6ea1fabfd373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234405187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4234405187
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4172618336
Short name T832
Test name
Test status
Simulation time 7397602843 ps
CPU time 11.46 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:54:36 AM PDT 24
Peak memory 239852 kb
Host smart-04406cd6-a91b-4583-8cb0-8264a5f9770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172618336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4172618336
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2401533585
Short name T538
Test name
Test status
Simulation time 672927296 ps
CPU time 4.1 seconds
Started Jul 02 07:54:18 AM PDT 24
Finished Jul 02 07:54:32 AM PDT 24
Peak memory 218928 kb
Host smart-a5335586-889a-435e-9b1d-f5723e7186c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2401533585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2401533585
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2176835917
Short name T36
Test name
Test status
Simulation time 4437875981 ps
CPU time 56.73 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:55:18 AM PDT 24
Peak memory 254052 kb
Host smart-68601571-4caf-4f11-8bc5-a672fe13b5e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176835917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2176835917
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2538170680
Short name T463
Test name
Test status
Simulation time 3858770936 ps
CPU time 20.83 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:36 AM PDT 24
Peak memory 216264 kb
Host smart-2ab0726b-9762-4aa6-ba20-57a83ca5764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538170680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2538170680
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3421506183
Short name T363
Test name
Test status
Simulation time 18826773645 ps
CPU time 14.95 seconds
Started Jul 02 07:54:17 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 216436 kb
Host smart-89c477b5-a673-4ba3-b27d-11948fa194a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421506183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3421506183
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1740681367
Short name T700
Test name
Test status
Simulation time 19846510 ps
CPU time 0.82 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:15 AM PDT 24
Peak memory 205832 kb
Host smart-d2e729b8-04c8-4035-a39a-22897a134346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740681367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1740681367
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1494287549
Short name T559
Test name
Test status
Simulation time 76571704 ps
CPU time 0.93 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:24 AM PDT 24
Peak memory 205824 kb
Host smart-613e3d38-6361-4fd1-98cd-90e56c1a4368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494287549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1494287549
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4117668938
Short name T642
Test name
Test status
Simulation time 7821231601 ps
CPU time 9.22 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 224552 kb
Host smart-bce9eded-ec81-4af9-9447-0f2fa73a4784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117668938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4117668938
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2524151837
Short name T335
Test name
Test status
Simulation time 38991675 ps
CPU time 0.75 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 204840 kb
Host smart-6748033c-f60c-427c-9611-55dc39ec54d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524151837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2524151837
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2899680931
Short name T798
Test name
Test status
Simulation time 321041065 ps
CPU time 3.03 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:21 AM PDT 24
Peak memory 224388 kb
Host smart-c1d57903-7512-4569-aa32-718606998021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899680931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2899680931
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1348226506
Short name T351
Test name
Test status
Simulation time 52744970 ps
CPU time 0.79 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:22 AM PDT 24
Peak memory 206564 kb
Host smart-3077d73c-0a73-4955-b485-9fa92e232966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348226506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1348226506
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3443493033
Short name T855
Test name
Test status
Simulation time 53032847656 ps
CPU time 413.83 seconds
Started Jul 02 07:54:09 AM PDT 24
Finished Jul 02 08:01:12 AM PDT 24
Peak memory 265244 kb
Host smart-8e6e5cb0-4f74-4412-9cdc-2cdc7fa63085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443493033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3443493033
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.129977763
Short name T177
Test name
Test status
Simulation time 208660633079 ps
CPU time 202.75 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:57:47 AM PDT 24
Peak memory 249176 kb
Host smart-21321b73-278f-42de-8d42-6d76604ea6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129977763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.129977763
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.198275168
Short name T264
Test name
Test status
Simulation time 10241568773 ps
CPU time 125.51 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:56:30 AM PDT 24
Peak memory 254476 kb
Host smart-bc8da9db-8d07-4a2e-b678-79059baa3d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198275168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.198275168
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3553440108
Short name T29
Test name
Test status
Simulation time 138271181 ps
CPU time 3.48 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 07:54:27 AM PDT 24
Peak memory 224384 kb
Host smart-f2e0946d-613d-44e2-8529-c5555709cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553440108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3553440108
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2039469352
Short name T617
Test name
Test status
Simulation time 14032511256 ps
CPU time 24.7 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 07:54:47 AM PDT 24
Peak memory 232760 kb
Host smart-36e570a1-6381-4fc5-8945-0b51b89b4758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039469352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2039469352
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2072424090
Short name T799
Test name
Test status
Simulation time 1483095263 ps
CPU time 23.71 seconds
Started Jul 02 07:54:03 AM PDT 24
Finished Jul 02 07:54:33 AM PDT 24
Peak memory 232648 kb
Host smart-119f62cf-3d6b-45c4-823c-38072bc79c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072424090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2072424090
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2743118514
Short name T609
Test name
Test status
Simulation time 4638871628 ps
CPU time 16.36 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:39 AM PDT 24
Peak memory 232700 kb
Host smart-78e7e75e-b6b7-4e49-b609-fc58a08562a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743118514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2743118514
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1555024201
Short name T900
Test name
Test status
Simulation time 192911870 ps
CPU time 2.37 seconds
Started Jul 02 07:54:07 AM PDT 24
Finished Jul 02 07:54:17 AM PDT 24
Peak memory 224404 kb
Host smart-3ba130e7-1efb-4796-8c90-972d23c443ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555024201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1555024201
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1231854127
Short name T451
Test name
Test status
Simulation time 1729442734 ps
CPU time 5.94 seconds
Started Jul 02 07:54:02 AM PDT 24
Finished Jul 02 07:54:14 AM PDT 24
Peak memory 218740 kb
Host smart-a003063a-5765-4e01-8bf1-7af0b190ffa0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1231854127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1231854127
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1355103438
Short name T581
Test name
Test status
Simulation time 4001996523 ps
CPU time 11.37 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:34 AM PDT 24
Peak memory 216612 kb
Host smart-ec577453-de43-4296-9787-d4b8b3c934b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355103438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1355103438
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.230209113
Short name T874
Test name
Test status
Simulation time 486295770 ps
CPU time 3.07 seconds
Started Jul 02 07:54:28 AM PDT 24
Finished Jul 02 07:54:38 AM PDT 24
Peak memory 216108 kb
Host smart-1bb847f2-171c-4d67-8cd4-d3d5aac4c832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230209113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.230209113
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2284822791
Short name T964
Test name
Test status
Simulation time 224648299 ps
CPU time 2.73 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 07:54:15 AM PDT 24
Peak memory 216128 kb
Host smart-fb7ee814-b57e-42ad-8c8e-c91c29509817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284822791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2284822791
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2080133223
Short name T484
Test name
Test status
Simulation time 141685587 ps
CPU time 0.78 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:19 AM PDT 24
Peak memory 205908 kb
Host smart-c4577609-5999-4586-b0a1-d639f02e65dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080133223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2080133223
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1706920452
Short name T1008
Test name
Test status
Simulation time 62930440 ps
CPU time 2.35 seconds
Started Jul 02 07:54:09 AM PDT 24
Finished Jul 02 07:54:19 AM PDT 24
Peak memory 224688 kb
Host smart-4afbd7c2-a542-41e8-95d5-e3df1fee7285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706920452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1706920452
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1225482460
Short name T663
Test name
Test status
Simulation time 14320940 ps
CPU time 0.73 seconds
Started Jul 02 07:53:34 AM PDT 24
Finished Jul 02 07:53:41 AM PDT 24
Peak memory 205400 kb
Host smart-bb20f1d2-2aed-41a7-a200-608c881c388f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225482460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
225482460
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2091125714
Short name T396
Test name
Test status
Simulation time 243738553 ps
CPU time 4.25 seconds
Started Jul 02 07:53:37 AM PDT 24
Finished Jul 02 07:53:43 AM PDT 24
Peak memory 224348 kb
Host smart-319c4b1d-64e7-4c43-a888-dfb45db19de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091125714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2091125714
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.85453697
Short name T599
Test name
Test status
Simulation time 30234518 ps
CPU time 0.75 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:27 AM PDT 24
Peak memory 206284 kb
Host smart-c52f25c3-4c4f-4b8e-bde0-79f01e54469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85453697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.85453697
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1300549099
Short name T221
Test name
Test status
Simulation time 5096387616 ps
CPU time 41.99 seconds
Started Jul 02 07:53:41 AM PDT 24
Finished Jul 02 07:54:24 AM PDT 24
Peak memory 240864 kb
Host smart-1988fd54-550e-4fbc-9013-c1c2103204d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300549099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1300549099
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3628466257
Short name T762
Test name
Test status
Simulation time 74793004705 ps
CPU time 124.28 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:55:28 AM PDT 24
Peak memory 256528 kb
Host smart-6748b871-901e-4cca-87bd-922f3e99f804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628466257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3628466257
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2618388280
Short name T52
Test name
Test status
Simulation time 9392114115 ps
CPU time 91.51 seconds
Started Jul 02 07:53:33 AM PDT 24
Finished Jul 02 07:55:06 AM PDT 24
Peak memory 251448 kb
Host smart-e6777c3f-5c99-4cbd-93dd-0f367d961c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618388280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2618388280
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2544526948
Short name T287
Test name
Test status
Simulation time 7139482386 ps
CPU time 45.86 seconds
Started Jul 02 07:53:37 AM PDT 24
Finished Jul 02 07:54:25 AM PDT 24
Peak memory 240400 kb
Host smart-d779b3fa-212d-4eb2-9073-5112008676ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544526948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2544526948
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3953216855
Short name T969
Test name
Test status
Simulation time 187845408500 ps
CPU time 316.49 seconds
Started Jul 02 07:53:29 AM PDT 24
Finished Jul 02 07:58:46 AM PDT 24
Peak memory 257296 kb
Host smart-b8546bea-4ccd-48cd-8769-da9ac7a3b6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953216855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3953216855
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.792692288
Short name T898
Test name
Test status
Simulation time 5105587136 ps
CPU time 22.78 seconds
Started Jul 02 07:53:44 AM PDT 24
Finished Jul 02 07:54:07 AM PDT 24
Peak memory 228968 kb
Host smart-9779e15c-b3af-4774-bd68-70598ed33692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792692288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.792692288
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2892025165
Short name T804
Test name
Test status
Simulation time 3393196341 ps
CPU time 5.01 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:54:01 AM PDT 24
Peak memory 224476 kb
Host smart-46a5ad5e-3e21-4c9e-9ad0-8e64481ec18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892025165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2892025165
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1961979259
Short name T890
Test name
Test status
Simulation time 220756887 ps
CPU time 2.76 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:27 AM PDT 24
Peak memory 232484 kb
Host smart-053e6f09-6dbf-4a7f-af70-c4610c8ac795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961979259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1961979259
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.372727842
Short name T724
Test name
Test status
Simulation time 7187447500 ps
CPU time 24.92 seconds
Started Jul 02 07:53:29 AM PDT 24
Finished Jul 02 07:54:00 AM PDT 24
Peak memory 248900 kb
Host smart-f38fcdc0-23d2-476c-9344-2a5a3817e36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372727842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.372727842
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3764622271
Short name T886
Test name
Test status
Simulation time 883687535 ps
CPU time 10.2 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:35 AM PDT 24
Peak memory 220564 kb
Host smart-1ddc16aa-aa31-4ac7-833a-c0f3da2f4526
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3764622271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3764622271
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1123285448
Short name T67
Test name
Test status
Simulation time 106477160 ps
CPU time 1.11 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:27 AM PDT 24
Peak memory 235900 kb
Host smart-9d709299-835e-4789-b6c8-0d0c571afb42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123285448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1123285448
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.151876077
Short name T671
Test name
Test status
Simulation time 189824150310 ps
CPU time 251.65 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:57:36 AM PDT 24
Peak memory 257356 kb
Host smart-c6602662-95ce-4225-915f-7f5465b2aca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151876077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.151876077
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1064220749
Short name T631
Test name
Test status
Simulation time 7254365877 ps
CPU time 23.94 seconds
Started Jul 02 07:53:28 AM PDT 24
Finished Jul 02 07:53:53 AM PDT 24
Peak memory 219784 kb
Host smart-dd4c9889-8b9f-4e65-99d6-2452f3cafb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064220749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1064220749
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3431948625
Short name T30
Test name
Test status
Simulation time 12525912065 ps
CPU time 6.31 seconds
Started Jul 02 07:53:28 AM PDT 24
Finished Jul 02 07:53:35 AM PDT 24
Peak memory 218716 kb
Host smart-865345a0-640b-4ced-adf8-94052e61ebb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431948625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3431948625
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3157386486
Short name T821
Test name
Test status
Simulation time 59921157 ps
CPU time 1.17 seconds
Started Jul 02 07:53:25 AM PDT 24
Finished Jul 02 07:53:28 AM PDT 24
Peak memory 216140 kb
Host smart-bce52134-99d8-45e9-83f9-efb9e04994ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157386486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3157386486
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2936416718
Short name T413
Test name
Test status
Simulation time 314241789 ps
CPU time 0.94 seconds
Started Jul 02 07:53:38 AM PDT 24
Finished Jul 02 07:53:41 AM PDT 24
Peak memory 206116 kb
Host smart-61259d95-ad90-41cb-af0e-97a7955868b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936416718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2936416718
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3543877257
Short name T921
Test name
Test status
Simulation time 1781147360 ps
CPU time 6.03 seconds
Started Jul 02 07:53:46 AM PDT 24
Finished Jul 02 07:53:53 AM PDT 24
Peak memory 232564 kb
Host smart-520b6706-9824-49fa-9859-ca3aae299163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543877257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3543877257
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.485227752
Short name T318
Test name
Test status
Simulation time 85227280 ps
CPU time 0.7 seconds
Started Jul 02 07:54:18 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 205404 kb
Host smart-b5e61e3d-094f-4b5e-852e-bf6a38333f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485227752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.485227752
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1195640698
Short name T787
Test name
Test status
Simulation time 439491069 ps
CPU time 4.22 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 232568 kb
Host smart-43933716-1bb8-472c-9041-15c1287f14d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195640698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1195640698
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.683853197
Short name T768
Test name
Test status
Simulation time 15937077 ps
CPU time 0.76 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 206848 kb
Host smart-cd4e7dbd-7b89-47c7-857a-0a6a92ba3fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683853197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.683853197
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3775420244
Short name T808
Test name
Test status
Simulation time 74407977364 ps
CPU time 96.9 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:55:56 AM PDT 24
Peak memory 252876 kb
Host smart-cb1e9467-8fec-400d-ad31-31a9e523b46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775420244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3775420244
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.872339262
Short name T290
Test name
Test status
Simulation time 303548410 ps
CPU time 7.69 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 07:54:30 AM PDT 24
Peak memory 224388 kb
Host smart-4dd9f346-e8a6-418c-8022-aab966a2af5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872339262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.872339262
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3720876076
Short name T372
Test name
Test status
Simulation time 34701943253 ps
CPU time 83.91 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:55:39 AM PDT 24
Peak memory 250496 kb
Host smart-30975837-c60e-4573-a958-3c5cf34ded08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720876076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3720876076
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1742730332
Short name T407
Test name
Test status
Simulation time 121261436 ps
CPU time 2.39 seconds
Started Jul 02 07:54:05 AM PDT 24
Finished Jul 02 07:54:13 AM PDT 24
Peak memory 232280 kb
Host smart-4c14cb67-7dbb-44ff-b437-ce583a95670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742730332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1742730332
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.563639566
Short name T532
Test name
Test status
Simulation time 46133905 ps
CPU time 2.41 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:24 AM PDT 24
Peak memory 232600 kb
Host smart-e1eceb26-a7ec-4ed0-a740-a7e4a45d0fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563639566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.563639566
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.7932952
Short name T916
Test name
Test status
Simulation time 453381732 ps
CPU time 3.82 seconds
Started Jul 02 07:54:24 AM PDT 24
Finished Jul 02 07:54:35 AM PDT 24
Peak memory 224448 kb
Host smart-216167d7-d019-47bd-aad8-dcf681e59523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7932952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.7932952
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4267504191
Short name T597
Test name
Test status
Simulation time 123444662 ps
CPU time 2.92 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 232524 kb
Host smart-98ff221d-5728-4642-8fa0-4b2094959414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267504191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4267504191
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2402573495
Short name T55
Test name
Test status
Simulation time 482305945 ps
CPU time 3.39 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:20 AM PDT 24
Peak memory 220532 kb
Host smart-ac4fadb6-2234-4495-b4aa-339326285f45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2402573495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2402573495
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1008951004
Short name T933
Test name
Test status
Simulation time 3958060302 ps
CPU time 51.84 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 224600 kb
Host smart-d732e1c7-b9cf-4331-b1c8-dce056be2a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008951004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1008951004
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.395035054
Short name T303
Test name
Test status
Simulation time 2013161927 ps
CPU time 4.2 seconds
Started Jul 02 07:54:29 AM PDT 24
Finished Jul 02 07:54:40 AM PDT 24
Peak memory 218700 kb
Host smart-66631621-4199-4832-b298-3601ca0a2edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395035054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.395035054
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1619744797
Short name T568
Test name
Test status
Simulation time 16641246 ps
CPU time 0.86 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:20 AM PDT 24
Peak memory 207080 kb
Host smart-f46975d0-de52-4b42-bb0d-15c3b348df06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619744797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1619744797
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2210038698
Short name T543
Test name
Test status
Simulation time 324016181 ps
CPU time 0.92 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 07:54:25 AM PDT 24
Peak memory 206248 kb
Host smart-587938a5-38ee-4c41-8482-78185e276797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210038698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2210038698
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2561167338
Short name T595
Test name
Test status
Simulation time 524756074 ps
CPU time 4.08 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:27 AM PDT 24
Peak memory 224272 kb
Host smart-f46457eb-4570-483e-881a-f66b046d8f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561167338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2561167338
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1126305075
Short name T333
Test name
Test status
Simulation time 17894903 ps
CPU time 0.71 seconds
Started Jul 02 07:54:08 AM PDT 24
Finished Jul 02 07:54:17 AM PDT 24
Peak memory 205452 kb
Host smart-f408d7af-1a72-473d-bd7b-f7f15494ca4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126305075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1126305075
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.665861172
Short name T519
Test name
Test status
Simulation time 5118180618 ps
CPU time 4.35 seconds
Started Jul 02 07:54:17 AM PDT 24
Finished Jul 02 07:54:32 AM PDT 24
Peak memory 224448 kb
Host smart-0337fb9f-8d60-47b7-8f74-511a27f7db61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665861172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.665861172
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1732641852
Short name T746
Test name
Test status
Simulation time 57700860 ps
CPU time 0.7 seconds
Started Jul 02 07:54:19 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 205844 kb
Host smart-fc5f3a7c-8604-450d-8523-cc2c2660b697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732641852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1732641852
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3889833511
Short name T903
Test name
Test status
Simulation time 24367699156 ps
CPU time 27.18 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:47 AM PDT 24
Peak memory 251072 kb
Host smart-13c3926d-2f38-4c47-8e58-2b7ac0639e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889833511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3889833511
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1367602194
Short name T527
Test name
Test status
Simulation time 14683983827 ps
CPU time 138.33 seconds
Started Jul 02 07:54:23 AM PDT 24
Finished Jul 02 07:56:55 AM PDT 24
Peak memory 236252 kb
Host smart-61c93e4f-f624-4a0f-a0fd-eb892b355d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367602194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1367602194
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2152308668
Short name T664
Test name
Test status
Simulation time 9796437539 ps
CPU time 25.42 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:47 AM PDT 24
Peak memory 241016 kb
Host smart-73df8244-0700-40b4-888f-6ccb16d699ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152308668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2152308668
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2373654599
Short name T884
Test name
Test status
Simulation time 338327862 ps
CPU time 2.83 seconds
Started Jul 02 07:54:06 AM PDT 24
Finished Jul 02 07:54:19 AM PDT 24
Peak memory 224104 kb
Host smart-a8f077cc-c418-4460-9439-53a2b65cf16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373654599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2373654599
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2841076731
Short name T670
Test name
Test status
Simulation time 1454613042 ps
CPU time 32.52 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:54 AM PDT 24
Peak memory 240728 kb
Host smart-21880e68-a4a8-4b4d-94c3-d4163e009b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841076731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2841076731
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3762114604
Short name T156
Test name
Test status
Simulation time 9647473964 ps
CPU time 27.7 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:54:52 AM PDT 24
Peak memory 233036 kb
Host smart-7eec57bd-33e4-4380-9a82-391821e98edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762114604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3762114604
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.956422533
Short name T552
Test name
Test status
Simulation time 635744269 ps
CPU time 9.36 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:54:34 AM PDT 24
Peak memory 224356 kb
Host smart-75256df6-3f9f-4da9-8c36-744ab06f11ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956422533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.956422533
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3584989894
Short name T282
Test name
Test status
Simulation time 18996707960 ps
CPU time 15.37 seconds
Started Jul 02 07:54:20 AM PDT 24
Finished Jul 02 07:54:44 AM PDT 24
Peak memory 232684 kb
Host smart-41302bc5-a419-435f-ad94-6f6142887083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584989894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3584989894
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2808289372
Short name T6
Test name
Test status
Simulation time 4384763159 ps
CPU time 4.62 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 232684 kb
Host smart-b6e11022-d99d-4874-838a-6f18e9e1fc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808289372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2808289372
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2285233723
Short name T711
Test name
Test status
Simulation time 391030525 ps
CPU time 4.49 seconds
Started Jul 02 07:54:28 AM PDT 24
Finished Jul 02 07:54:40 AM PDT 24
Peak memory 219792 kb
Host smart-80fbcc0f-38b5-4d58-860f-7dfc88fe5f4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2285233723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2285233723
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3153974255
Short name T432
Test name
Test status
Simulation time 54081405 ps
CPU time 1.04 seconds
Started Jul 02 07:54:30 AM PDT 24
Finished Jul 02 07:54:39 AM PDT 24
Peak memory 207632 kb
Host smart-425d184d-a8e4-41dc-a0b8-ff94195a89f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153974255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3153974255
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2874820365
Short name T297
Test name
Test status
Simulation time 1776464904 ps
CPU time 16.3 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:38 AM PDT 24
Peak memory 216248 kb
Host smart-e58c2017-c219-45ec-b811-7d1461953c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874820365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2874820365
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2146973692
Short name T361
Test name
Test status
Simulation time 980467416 ps
CPU time 1.7 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 207768 kb
Host smart-50d663cd-ebbe-4be4-9199-0edb84151564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146973692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2146973692
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2943450839
Short name T70
Test name
Test status
Simulation time 30773075 ps
CPU time 1.11 seconds
Started Jul 02 07:54:29 AM PDT 24
Finished Jul 02 07:54:37 AM PDT 24
Peak memory 207688 kb
Host smart-4b9a6ff8-f709-4a6c-9429-525738faf075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943450839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2943450839
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3243665028
Short name T666
Test name
Test status
Simulation time 87035020 ps
CPU time 0.7 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 205900 kb
Host smart-e2fc9219-5140-4b5a-a9cf-4ed667e1f4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243665028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3243665028
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3756707702
Short name T241
Test name
Test status
Simulation time 45505840 ps
CPU time 2.43 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 07:54:26 AM PDT 24
Peak memory 232520 kb
Host smart-bce9986b-a033-4d25-89ab-ef32902b1914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756707702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3756707702
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4173883607
Short name T508
Test name
Test status
Simulation time 24045815 ps
CPU time 0.72 seconds
Started Jul 02 07:54:24 AM PDT 24
Finished Jul 02 07:54:32 AM PDT 24
Peak memory 205432 kb
Host smart-9ae61aff-d363-4a60-acb9-9d5c2f20a129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173883607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4173883607
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3503466898
Short name T641
Test name
Test status
Simulation time 255438308 ps
CPU time 3.34 seconds
Started Jul 02 07:54:17 AM PDT 24
Finished Jul 02 07:54:31 AM PDT 24
Peak memory 224380 kb
Host smart-cc327c7a-0cb2-44b9-9012-df8b0eeadc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503466898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3503466898
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1245106604
Short name T694
Test name
Test status
Simulation time 14990523 ps
CPU time 0.73 seconds
Started Jul 02 07:54:28 AM PDT 24
Finished Jul 02 07:54:36 AM PDT 24
Peak memory 205448 kb
Host smart-296e825a-98db-4247-88d8-6eed557914be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245106604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1245106604
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2032831198
Short name T596
Test name
Test status
Simulation time 6724170024 ps
CPU time 59.85 seconds
Started Jul 02 07:54:18 AM PDT 24
Finished Jul 02 07:55:28 AM PDT 24
Peak memory 251756 kb
Host smart-8e498f4f-a087-463e-9167-249579a25759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032831198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2032831198
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2966421341
Short name T978
Test name
Test status
Simulation time 796924852 ps
CPU time 15.81 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:54:37 AM PDT 24
Peak memory 249028 kb
Host smart-3d80d06a-5b0b-41d6-a037-082106ad3f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966421341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2966421341
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.226790707
Short name T576
Test name
Test status
Simulation time 5725693916 ps
CPU time 75.28 seconds
Started Jul 02 07:54:12 AM PDT 24
Finished Jul 02 07:55:38 AM PDT 24
Peak memory 251568 kb
Host smart-8a19c197-ca85-402d-b37f-db6545cf2044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226790707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.226790707
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3749826350
Short name T627
Test name
Test status
Simulation time 4376806948 ps
CPU time 47.98 seconds
Started Jul 02 07:54:19 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 232748 kb
Host smart-e2fdf5dd-c751-4e2a-9a23-51463891dda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749826350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3749826350
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4019753097
Short name T847
Test name
Test status
Simulation time 9883243221 ps
CPU time 51.29 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:55:18 AM PDT 24
Peak memory 253124 kb
Host smart-788d9267-f48b-482e-be3d-3b6f566983a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019753097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4019753097
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2383705637
Short name T90
Test name
Test status
Simulation time 1259054633 ps
CPU time 9.59 seconds
Started Jul 02 07:54:26 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 232556 kb
Host smart-697a1d74-b800-408b-a7ae-026fd1d3674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383705637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2383705637
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3571679065
Short name T618
Test name
Test status
Simulation time 6864498978 ps
CPU time 5.65 seconds
Started Jul 02 07:54:17 AM PDT 24
Finished Jul 02 07:54:33 AM PDT 24
Peak memory 224492 kb
Host smart-89d13ef3-e61a-43a2-ba55-e582c075dcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571679065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3571679065
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3253176968
Short name T728
Test name
Test status
Simulation time 3556884122 ps
CPU time 11.65 seconds
Started Jul 02 07:54:23 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 232672 kb
Host smart-f67a28c3-5ad1-4b67-8665-a12985e4cec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253176968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3253176968
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1836868198
Short name T681
Test name
Test status
Simulation time 1792411231 ps
CPU time 9.05 seconds
Started Jul 02 07:54:10 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 232648 kb
Host smart-2c93d628-2436-460f-bf33-b7556081d376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836868198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1836868198
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3983466771
Short name T955
Test name
Test status
Simulation time 3622331447 ps
CPU time 7.94 seconds
Started Jul 02 07:54:21 AM PDT 24
Finished Jul 02 07:54:38 AM PDT 24
Peak memory 221092 kb
Host smart-f175d280-6d19-4f21-b883-49ccf88001ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3983466771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3983466771
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.958103904
Short name T911
Test name
Test status
Simulation time 230392627 ps
CPU time 1.1 seconds
Started Jul 02 07:54:29 AM PDT 24
Finished Jul 02 07:54:37 AM PDT 24
Peak memory 206836 kb
Host smart-6d6f5339-8fa0-4b26-90fb-345b57cb73b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958103904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.958103904
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1869684730
Short name T889
Test name
Test status
Simulation time 2859515432 ps
CPU time 4.85 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 216276 kb
Host smart-df0d278e-9ff3-4fd0-88cd-2705e1f692d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869684730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1869684730
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3588206279
Short name T592
Test name
Test status
Simulation time 9691722247 ps
CPU time 6.94 seconds
Started Jul 02 07:54:18 AM PDT 24
Finished Jul 02 07:54:35 AM PDT 24
Peak memory 216224 kb
Host smart-a6168eab-12b0-44db-a10e-d18aa6967b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588206279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3588206279
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1002479999
Short name T404
Test name
Test status
Simulation time 33356277 ps
CPU time 0.92 seconds
Started Jul 02 07:54:17 AM PDT 24
Finished Jul 02 07:54:31 AM PDT 24
Peak memory 206660 kb
Host smart-c061b91d-1ade-47fc-9c4c-6ac925eed79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002479999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1002479999
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2523792982
Short name T801
Test name
Test status
Simulation time 129169511 ps
CPU time 0.71 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:54:28 AM PDT 24
Peak memory 205856 kb
Host smart-080ded51-e1c1-4e16-b3f3-71017935bc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523792982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2523792982
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2833440517
Short name T59
Test name
Test status
Simulation time 1178444382 ps
CPU time 4.71 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 232516 kb
Host smart-d8deac05-8a4d-4d0e-a757-30db45593400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833440517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2833440517
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1351827773
Short name T851
Test name
Test status
Simulation time 12452133 ps
CPU time 0.72 seconds
Started Jul 02 07:54:28 AM PDT 24
Finished Jul 02 07:54:35 AM PDT 24
Peak memory 204904 kb
Host smart-6219550c-93df-401f-afee-b06d50e6114e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351827773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1351827773
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.464691855
Short name T902
Test name
Test status
Simulation time 851794726 ps
CPU time 9.41 seconds
Started Jul 02 07:54:23 AM PDT 24
Finished Jul 02 07:54:41 AM PDT 24
Peak memory 233640 kb
Host smart-5281ee1d-ff56-40dd-a47e-88e7cb3791e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464691855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.464691855
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1427808366
Short name T327
Test name
Test status
Simulation time 49801045 ps
CPU time 0.78 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 07:54:24 AM PDT 24
Peak memory 206540 kb
Host smart-d3bfd327-85f5-44ed-98fd-8e01c6a20077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427808366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1427808366
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3733520058
Short name T662
Test name
Test status
Simulation time 6464339101 ps
CPU time 55.24 seconds
Started Jul 02 07:54:33 AM PDT 24
Finished Jul 02 07:55:34 AM PDT 24
Peak memory 256548 kb
Host smart-6c289170-e9dc-4a8f-a11a-378e7160d37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733520058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3733520058
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3553466551
Short name T483
Test name
Test status
Simulation time 8541504885 ps
CPU time 12.9 seconds
Started Jul 02 07:54:21 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 217696 kb
Host smart-420b5166-4f93-4a08-8888-0f5133ac12e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553466551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3553466551
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1565788586
Short name T741
Test name
Test status
Simulation time 18043214588 ps
CPU time 170.32 seconds
Started Jul 02 07:54:15 AM PDT 24
Finished Jul 02 07:57:16 AM PDT 24
Peak memory 256180 kb
Host smart-3b33cc16-c098-49cb-8a0f-bc5da7214534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565788586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1565788586
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1995669443
Short name T652
Test name
Test status
Simulation time 1754030544 ps
CPU time 22.89 seconds
Started Jul 02 07:54:22 AM PDT 24
Finished Jul 02 07:54:53 AM PDT 24
Peak memory 224196 kb
Host smart-aeccef06-8398-434b-99ec-65266ed57e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995669443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1995669443
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.385302690
Short name T668
Test name
Test status
Simulation time 33612507 ps
CPU time 0.77 seconds
Started Jul 02 07:54:27 AM PDT 24
Finished Jul 02 07:54:35 AM PDT 24
Peak memory 215700 kb
Host smart-d0f2feba-1a58-49b9-a925-8ee1443e52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385302690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.385302690
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2965039219
Short name T904
Test name
Test status
Simulation time 570774518 ps
CPU time 2.9 seconds
Started Jul 02 07:54:33 AM PDT 24
Finished Jul 02 07:54:42 AM PDT 24
Peak memory 224360 kb
Host smart-f77c0977-83bb-4459-aea5-7b479e479964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965039219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2965039219
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1974924658
Short name T803
Test name
Test status
Simulation time 6964676032 ps
CPU time 80.36 seconds
Started Jul 02 07:54:15 AM PDT 24
Finished Jul 02 07:55:46 AM PDT 24
Peak memory 224564 kb
Host smart-73f23940-ebdd-4af3-b111-c9f58f755a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974924658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1974924658
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2850090066
Short name T251
Test name
Test status
Simulation time 4601001970 ps
CPU time 10.3 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:31 AM PDT 24
Peak memory 232656 kb
Host smart-d87ac384-ed56-4cbc-a99b-f319058a9e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850090066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2850090066
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1711455230
Short name T765
Test name
Test status
Simulation time 8514597745 ps
CPU time 10.44 seconds
Started Jul 02 07:55:12 AM PDT 24
Finished Jul 02 07:55:39 AM PDT 24
Peak memory 248024 kb
Host smart-a3785a13-7f63-4f6d-a00c-8db1485c8819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711455230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1711455230
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.455977583
Short name T879
Test name
Test status
Simulation time 941018356 ps
CPU time 11.46 seconds
Started Jul 02 07:54:28 AM PDT 24
Finished Jul 02 07:54:46 AM PDT 24
Peak memory 223052 kb
Host smart-3c33b868-5242-468d-af30-22f9ca1f2951
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=455977583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.455977583
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1731547698
Short name T970
Test name
Test status
Simulation time 133093097 ps
CPU time 1.17 seconds
Started Jul 02 07:54:13 AM PDT 24
Finished Jul 02 07:54:24 AM PDT 24
Peak memory 206964 kb
Host smart-3fc83065-c8fb-4a47-a02d-62760a4e132a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731547698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1731547698
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2252333901
Short name T550
Test name
Test status
Simulation time 34956473257 ps
CPU time 43.37 seconds
Started Jul 02 07:54:29 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 216304 kb
Host smart-5a01ae7e-1c62-42ab-998b-2a946ca643d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252333901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2252333901
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1274974874
Short name T379
Test name
Test status
Simulation time 1467930928 ps
CPU time 8.54 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:54:33 AM PDT 24
Peak memory 216128 kb
Host smart-2ded4f94-d69d-40eb-af9d-247d6a48059d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274974874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1274974874
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.823699798
Short name T491
Test name
Test status
Simulation time 1324662538 ps
CPU time 3.84 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:54:28 AM PDT 24
Peak memory 216100 kb
Host smart-7840c5e7-bdab-400b-8ede-3d86bfe95a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823699798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.823699798
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.631510862
Short name T918
Test name
Test status
Simulation time 118562152 ps
CPU time 0.83 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:54:39 AM PDT 24
Peak memory 205852 kb
Host smart-17232078-353f-44a5-b04b-689a86a9428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631510862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.631510862
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3810306448
Short name T500
Test name
Test status
Simulation time 815432308 ps
CPU time 3.71 seconds
Started Jul 02 07:54:22 AM PDT 24
Finished Jul 02 07:54:34 AM PDT 24
Peak memory 224184 kb
Host smart-3805fa4d-5f84-40c5-872d-25f55ae8178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810306448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3810306448
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2314215004
Short name T310
Test name
Test status
Simulation time 63113167 ps
CPU time 0.7 seconds
Started Jul 02 07:54:29 AM PDT 24
Finished Jul 02 07:54:36 AM PDT 24
Peak memory 204892 kb
Host smart-6e3b61ad-9e31-4924-8190-5837f32acc88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314215004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2314215004
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1288204743
Short name T441
Test name
Test status
Simulation time 1114740734 ps
CPU time 12.15 seconds
Started Jul 02 07:54:25 AM PDT 24
Finished Jul 02 07:54:44 AM PDT 24
Peak memory 232592 kb
Host smart-85f88ee5-c928-4151-9fc4-541d787a2efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288204743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1288204743
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2036084141
Short name T25
Test name
Test status
Simulation time 20344036 ps
CPU time 0.74 seconds
Started Jul 02 07:54:25 AM PDT 24
Finished Jul 02 07:54:32 AM PDT 24
Peak memory 205852 kb
Host smart-b2fe33e5-9c7f-4924-b7a0-b9e5d17426d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036084141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2036084141
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3958657835
Short name T829
Test name
Test status
Simulation time 34928753 ps
CPU time 0.76 seconds
Started Jul 02 07:54:17 AM PDT 24
Finished Jul 02 07:54:28 AM PDT 24
Peak memory 215648 kb
Host smart-976a50cb-a35f-43d5-a473-d7d9b1c98a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958657835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3958657835
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3545855677
Short name T205
Test name
Test status
Simulation time 30777982436 ps
CPU time 86.35 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:56:04 AM PDT 24
Peak memory 249156 kb
Host smart-00a3df06-be5b-44d6-a961-285b00acf941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545855677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3545855677
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4234471199
Short name T280
Test name
Test status
Simulation time 58387741033 ps
CPU time 384.6 seconds
Started Jul 02 07:54:30 AM PDT 24
Finished Jul 02 08:01:01 AM PDT 24
Peak memory 255868 kb
Host smart-21e85e7f-f70c-475e-bf99-a131eedfce65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234471199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4234471199
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3721525850
Short name T220
Test name
Test status
Simulation time 282514313 ps
CPU time 8.91 seconds
Started Jul 02 07:54:27 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 222448 kb
Host smart-1b273cbe-463c-4770-922f-067c5b23dce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721525850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3721525850
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2526765675
Short name T973
Test name
Test status
Simulation time 125022065536 ps
CPU time 168.23 seconds
Started Jul 02 07:54:33 AM PDT 24
Finished Jul 02 07:57:27 AM PDT 24
Peak memory 224504 kb
Host smart-e1a58fcd-d11a-49c7-9052-2526181f92cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526765675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2526765675
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1263053997
Short name T175
Test name
Test status
Simulation time 722393184 ps
CPU time 4.05 seconds
Started Jul 02 07:54:25 AM PDT 24
Finished Jul 02 07:54:36 AM PDT 24
Peak memory 232580 kb
Host smart-c7b5294e-3b4d-4b37-bf26-a4f6c2378356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263053997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1263053997
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2971649789
Short name T422
Test name
Test status
Simulation time 2111635766 ps
CPU time 10.74 seconds
Started Jul 02 07:54:11 AM PDT 24
Finished Jul 02 07:54:32 AM PDT 24
Peak memory 235216 kb
Host smart-1ad05b64-6101-4285-bffb-0f7d6f56bc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971649789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2971649789
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.774284119
Short name T573
Test name
Test status
Simulation time 6608666181 ps
CPU time 9.66 seconds
Started Jul 02 07:54:38 AM PDT 24
Finished Jul 02 07:54:50 AM PDT 24
Peak memory 224564 kb
Host smart-8b8b0a18-28e7-4dc3-9ce9-f76f1a4de553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774284119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.774284119
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1284542021
Short name T471
Test name
Test status
Simulation time 2068705530 ps
CPU time 9.04 seconds
Started Jul 02 07:54:33 AM PDT 24
Finished Jul 02 07:54:48 AM PDT 24
Peak memory 233688 kb
Host smart-3c208fed-7599-4298-b9ab-bd7b1ad03957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284542021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1284542021
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.212412056
Short name T366
Test name
Test status
Simulation time 3900872422 ps
CPU time 9.04 seconds
Started Jul 02 07:54:26 AM PDT 24
Finished Jul 02 07:54:42 AM PDT 24
Peak memory 218904 kb
Host smart-4e6f252f-689e-469b-8a7a-4df75b6c5fad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=212412056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.212412056
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1328460972
Short name T720
Test name
Test status
Simulation time 737843839 ps
CPU time 11.59 seconds
Started Jul 02 07:54:24 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 216388 kb
Host smart-054d696b-e367-494d-a943-7a5b339d570e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328460972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1328460972
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1538496147
Short name T915
Test name
Test status
Simulation time 1682492604 ps
CPU time 3.54 seconds
Started Jul 02 07:54:30 AM PDT 24
Finished Jul 02 07:54:41 AM PDT 24
Peak memory 216176 kb
Host smart-9fecbe24-f302-4a12-9a0a-2eb313b10604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538496147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1538496147
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.644249196
Short name T344
Test name
Test status
Simulation time 543065867 ps
CPU time 1.36 seconds
Started Jul 02 07:54:32 AM PDT 24
Finished Jul 02 07:54:40 AM PDT 24
Peak memory 207988 kb
Host smart-0cd216de-67ad-4dcd-b579-002964d526b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644249196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.644249196
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3269867526
Short name T863
Test name
Test status
Simulation time 55714464 ps
CPU time 0.69 seconds
Started Jul 02 07:54:24 AM PDT 24
Finished Jul 02 07:54:32 AM PDT 24
Peak memory 205888 kb
Host smart-f20403d6-51b4-460d-b2de-e4905539bd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269867526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3269867526
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3060936575
Short name T239
Test name
Test status
Simulation time 3958131964 ps
CPU time 12.15 seconds
Started Jul 02 07:54:33 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 249092 kb
Host smart-0e59fe96-e95b-4e34-b007-685f73a5bf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060936575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3060936575
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1353792030
Short name T953
Test name
Test status
Simulation time 31295778 ps
CPU time 0.75 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:54:39 AM PDT 24
Peak memory 205788 kb
Host smart-c3aa8f8f-3e2c-44b4-a3e8-897e1ea3f7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353792030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1353792030
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.460354632
Short name T977
Test name
Test status
Simulation time 4046706469 ps
CPU time 4.67 seconds
Started Jul 02 07:54:28 AM PDT 24
Finished Jul 02 07:54:39 AM PDT 24
Peak memory 224448 kb
Host smart-345f3775-5fe9-45c8-80d6-a197f37ef662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460354632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.460354632
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3761866129
Short name T521
Test name
Test status
Simulation time 61247725 ps
CPU time 0.8 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:54:28 AM PDT 24
Peak memory 206856 kb
Host smart-0eecf75d-0227-45c9-8b5f-7f3b6cf2df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761866129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3761866129
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3898579814
Short name T464
Test name
Test status
Simulation time 32629551255 ps
CPU time 151.59 seconds
Started Jul 02 07:54:24 AM PDT 24
Finished Jul 02 07:57:03 AM PDT 24
Peak memory 253856 kb
Host smart-0ef06108-e8f9-43b4-a155-f19a8dcc3ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898579814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3898579814
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.335080598
Short name T48
Test name
Test status
Simulation time 103393019003 ps
CPU time 218.12 seconds
Started Jul 02 07:54:41 AM PDT 24
Finished Jul 02 07:58:28 AM PDT 24
Peak memory 255600 kb
Host smart-947d61fc-f108-4524-9b42-846b16d723d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335080598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.335080598
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2381761233
Short name T191
Test name
Test status
Simulation time 193869421535 ps
CPU time 388.42 seconds
Started Jul 02 07:54:28 AM PDT 24
Finished Jul 02 08:01:03 AM PDT 24
Peak memory 265404 kb
Host smart-d2b79097-e108-456d-a771-53ddad3c3046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381761233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2381761233
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1356709827
Short name T632
Test name
Test status
Simulation time 2846474782 ps
CPU time 45.05 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:55:12 AM PDT 24
Peak memory 224552 kb
Host smart-14e10503-fb40-4d7c-9e7f-c76fef5f66cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356709827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1356709827
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1395750618
Short name T419
Test name
Test status
Simulation time 128213625384 ps
CPU time 222.43 seconds
Started Jul 02 07:54:33 AM PDT 24
Finished Jul 02 07:58:22 AM PDT 24
Peak memory 249128 kb
Host smart-b29dc934-0de2-4072-bad8-89ca1d2c8084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395750618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1395750618
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.625705938
Short name T234
Test name
Test status
Simulation time 1551196543 ps
CPU time 13.07 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:54:40 AM PDT 24
Peak memory 224288 kb
Host smart-211e3494-2d9b-4f43-b4ed-e59cb873f07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625705938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.625705938
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.937767031
Short name T232
Test name
Test status
Simulation time 2262045021 ps
CPU time 20.51 seconds
Started Jul 02 07:54:27 AM PDT 24
Finished Jul 02 07:54:54 AM PDT 24
Peak memory 235288 kb
Host smart-b2c029c8-1da3-4239-b1ad-201061c1bcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937767031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.937767031
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2874219959
Short name T47
Test name
Test status
Simulation time 15497763233 ps
CPU time 12.45 seconds
Started Jul 02 07:54:30 AM PDT 24
Finished Jul 02 07:54:50 AM PDT 24
Peak memory 240200 kb
Host smart-e29d464a-f85a-4eef-a900-0a8032f083e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874219959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2874219959
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2719205788
Short name T541
Test name
Test status
Simulation time 2521805162 ps
CPU time 4 seconds
Started Jul 02 07:54:32 AM PDT 24
Finished Jul 02 07:54:42 AM PDT 24
Peak memory 232652 kb
Host smart-f18f2169-100f-424f-9a0a-84e9a600db82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719205788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2719205788
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4217320345
Short name T630
Test name
Test status
Simulation time 2246106981 ps
CPU time 7.49 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:54:33 AM PDT 24
Peak memory 223120 kb
Host smart-f612abe3-10cc-456f-8b51-07fbb7e98dbe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4217320345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4217320345
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.675756932
Short name T689
Test name
Test status
Simulation time 68923001757 ps
CPU time 115.53 seconds
Started Jul 02 07:54:43 AM PDT 24
Finished Jul 02 07:56:40 AM PDT 24
Peak memory 265584 kb
Host smart-813f2a7b-2bbb-41e8-826d-3c7a819a0589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675756932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.675756932
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.190435755
Short name T983
Test name
Test status
Simulation time 531224627 ps
CPU time 3.12 seconds
Started Jul 02 07:54:16 AM PDT 24
Finished Jul 02 07:54:29 AM PDT 24
Peak memory 216140 kb
Host smart-9a64bd3e-8edb-42d1-83ee-39882ac75b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190435755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.190435755
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.801699253
Short name T852
Test name
Test status
Simulation time 2000958684 ps
CPU time 6.26 seconds
Started Jul 02 07:54:22 AM PDT 24
Finished Jul 02 07:54:37 AM PDT 24
Peak memory 216136 kb
Host smart-77809877-d344-40d1-874e-b847f98ed9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801699253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.801699253
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2543019834
Short name T938
Test name
Test status
Simulation time 111283626 ps
CPU time 0.73 seconds
Started Jul 02 07:54:27 AM PDT 24
Finished Jul 02 07:54:35 AM PDT 24
Peak memory 205868 kb
Host smart-a0702052-a049-4f3c-b1f3-63528f5f7870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543019834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2543019834
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1428354689
Short name T644
Test name
Test status
Simulation time 262529370 ps
CPU time 0.95 seconds
Started Jul 02 07:54:24 AM PDT 24
Finished Jul 02 07:54:32 AM PDT 24
Peak memory 205880 kb
Host smart-9d10368c-94af-415c-8273-3d07b1080eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428354689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1428354689
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.419003549
Short name T194
Test name
Test status
Simulation time 2505417781 ps
CPU time 11.26 seconds
Started Jul 02 07:54:29 AM PDT 24
Finished Jul 02 07:54:47 AM PDT 24
Peak memory 240640 kb
Host smart-6d0673f3-9c53-4b96-b3e8-1c3685155872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419003549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.419003549
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3016435141
Short name T587
Test name
Test status
Simulation time 10495675 ps
CPU time 0.68 seconds
Started Jul 02 07:54:35 AM PDT 24
Finished Jul 02 07:54:41 AM PDT 24
Peak memory 204844 kb
Host smart-4cc4833c-43ee-4b8d-b62a-8234f9442ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016435141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3016435141
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3399490084
Short name T456
Test name
Test status
Simulation time 321997541 ps
CPU time 3.47 seconds
Started Jul 02 07:54:25 AM PDT 24
Finished Jul 02 07:54:35 AM PDT 24
Peak memory 232568 kb
Host smart-ee7e9af1-593e-4fe2-ad85-1a52ac93c82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399490084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3399490084
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1719475929
Short name T772
Test name
Test status
Simulation time 37607741 ps
CPU time 0.72 seconds
Started Jul 02 07:54:35 AM PDT 24
Finished Jul 02 07:54:41 AM PDT 24
Peak memory 205516 kb
Host smart-1bf8cec6-2a67-4219-a2a0-45bc4ba04a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719475929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1719475929
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.172840713
Short name T710
Test name
Test status
Simulation time 6338097577 ps
CPU time 27.28 seconds
Started Jul 02 07:54:32 AM PDT 24
Finished Jul 02 07:55:06 AM PDT 24
Peak memory 240272 kb
Host smart-f089d5a1-a1f2-47de-86d0-49b443fad74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172840713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.172840713
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4043103094
Short name T187
Test name
Test status
Simulation time 3660329130 ps
CPU time 19.72 seconds
Started Jul 02 07:54:32 AM PDT 24
Finished Jul 02 07:54:58 AM PDT 24
Peak memory 224552 kb
Host smart-19460af2-3166-4545-9839-d0614b480ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043103094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4043103094
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.923829817
Short name T643
Test name
Test status
Simulation time 29173457737 ps
CPU time 271.81 seconds
Started Jul 02 07:54:50 AM PDT 24
Finished Jul 02 07:59:28 AM PDT 24
Peak memory 263936 kb
Host smart-18a2ec8e-21d1-453c-b445-0a8f0c2fcfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923829817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.923829817
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2203568061
Short name T355
Test name
Test status
Simulation time 277374941 ps
CPU time 5.68 seconds
Started Jul 02 07:54:28 AM PDT 24
Finished Jul 02 07:54:41 AM PDT 24
Peak memory 224344 kb
Host smart-79d09485-be46-4204-b5a6-2e378b31d3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203568061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2203568061
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.60923918
Short name T881
Test name
Test status
Simulation time 50647213872 ps
CPU time 94 seconds
Started Jul 02 07:54:32 AM PDT 24
Finished Jul 02 07:56:13 AM PDT 24
Peak memory 249128 kb
Host smart-180eb263-c3bc-450d-b1ba-8821b35e8829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60923918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.60923918
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.839401744
Short name T442
Test name
Test status
Simulation time 883983887 ps
CPU time 4.63 seconds
Started Jul 02 07:54:30 AM PDT 24
Finished Jul 02 07:54:42 AM PDT 24
Peak memory 232612 kb
Host smart-163a3049-d1f7-4ba0-b097-56800cfadf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839401744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.839401744
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3506699498
Short name T430
Test name
Test status
Simulation time 3209103092 ps
CPU time 35.23 seconds
Started Jul 02 07:54:14 AM PDT 24
Finished Jul 02 07:55:00 AM PDT 24
Peak memory 237276 kb
Host smart-e926019e-d4ef-41d4-8dc1-d42afe823c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506699498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3506699498
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1432775660
Short name T570
Test name
Test status
Simulation time 774591092 ps
CPU time 3.51 seconds
Started Jul 02 07:54:29 AM PDT 24
Finished Jul 02 07:54:40 AM PDT 24
Peak memory 224420 kb
Host smart-6c6ffb53-41fb-48bd-8c42-1fd65d7e93fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432775660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1432775660
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3777246131
Short name T797
Test name
Test status
Simulation time 8762374509 ps
CPU time 22.35 seconds
Started Jul 02 07:54:27 AM PDT 24
Finished Jul 02 07:54:57 AM PDT 24
Peak memory 232700 kb
Host smart-407b5f86-4a18-477a-bc45-321c301269e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777246131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3777246131
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.354904936
Short name T979
Test name
Test status
Simulation time 1428346272 ps
CPU time 12.21 seconds
Started Jul 02 07:54:30 AM PDT 24
Finished Jul 02 07:54:49 AM PDT 24
Peak memory 220140 kb
Host smart-160f038f-c086-499f-9add-35f18bd93d22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=354904936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.354904936
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2554034670
Short name T942
Test name
Test status
Simulation time 65598166959 ps
CPU time 117.49 seconds
Started Jul 02 07:54:25 AM PDT 24
Finished Jul 02 07:56:30 AM PDT 24
Peak memory 240056 kb
Host smart-3c401bdd-21a8-4a98-8f2d-d5f41eb19230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554034670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2554034670
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.429569237
Short name T485
Test name
Test status
Simulation time 22482277092 ps
CPU time 15.2 seconds
Started Jul 02 07:54:30 AM PDT 24
Finished Jul 02 07:54:52 AM PDT 24
Peak memory 217280 kb
Host smart-f5a805b8-f90b-40f2-8b5e-6ac33bfce350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429569237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.429569237
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2245998061
Short name T634
Test name
Test status
Simulation time 125033435 ps
CPU time 1.93 seconds
Started Jul 02 07:54:35 AM PDT 24
Finished Jul 02 07:54:42 AM PDT 24
Peak memory 216176 kb
Host smart-35f73109-c496-40bd-9270-d68e48472e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245998061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2245998061
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2501836256
Short name T357
Test name
Test status
Simulation time 64624525 ps
CPU time 0.96 seconds
Started Jul 02 07:54:35 AM PDT 24
Finished Jul 02 07:54:41 AM PDT 24
Peak memory 206880 kb
Host smart-787a42f4-aad1-4a8c-b71d-d7443aead60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501836256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2501836256
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1123608803
Short name T403
Test name
Test status
Simulation time 5633942447 ps
CPU time 4.27 seconds
Started Jul 02 07:54:26 AM PDT 24
Finished Jul 02 07:54:37 AM PDT 24
Peak memory 224504 kb
Host smart-0b3f3c38-cd5f-4a3c-ae59-e26f6dda076c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123608803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1123608803
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.523956480
Short name T497
Test name
Test status
Simulation time 10821104 ps
CPU time 0.72 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:54:38 AM PDT 24
Peak memory 205812 kb
Host smart-877d55b0-7de5-4706-ab8f-4e2d25b801f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523956480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.523956480
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3177199543
Short name T261
Test name
Test status
Simulation time 1954386407 ps
CPU time 6.12 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:54:44 AM PDT 24
Peak memory 224376 kb
Host smart-a44bab62-e0eb-4389-a116-bdf8a392dfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177199543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3177199543
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.950940565
Short name T428
Test name
Test status
Simulation time 46540152 ps
CPU time 0.82 seconds
Started Jul 02 07:54:32 AM PDT 24
Finished Jul 02 07:54:39 AM PDT 24
Peak memory 206508 kb
Host smart-500ccb37-aae5-49b8-9c86-c193942c91d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950940565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.950940565
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3351979441
Short name T758
Test name
Test status
Simulation time 237325419 ps
CPU time 5.32 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 235064 kb
Host smart-b0d78864-f1ea-4ed3-9da2-0b021fd7e578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351979441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3351979441
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.598251721
Short name T833
Test name
Test status
Simulation time 47767420036 ps
CPU time 77.37 seconds
Started Jul 02 07:54:37 AM PDT 24
Finished Jul 02 07:55:58 AM PDT 24
Peak memory 255340 kb
Host smart-ddd55b64-7de3-414b-b0f8-2e839a98c444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598251721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.598251721
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.108130
Short name T213
Test name
Test status
Simulation time 12302378578 ps
CPU time 13.6 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 249132 kb
Host smart-5ebfc836-c407-4192-83a7-19bce429e85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.108130
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1477934395
Short name T367
Test name
Test status
Simulation time 6203433355 ps
CPU time 24.33 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:55:14 AM PDT 24
Peak memory 240856 kb
Host smart-d5eb0d02-2e7c-4534-8b76-a35fb3b2471b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477934395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1477934395
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4035710241
Short name T95
Test name
Test status
Simulation time 10269069496 ps
CPU time 54.3 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:55:32 AM PDT 24
Peak memory 249092 kb
Host smart-a4738fa1-9fc6-4db6-b09e-0a6843287b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035710241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4035710241
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2288602722
Short name T647
Test name
Test status
Simulation time 1369057224 ps
CPU time 12.39 seconds
Started Jul 02 07:54:34 AM PDT 24
Finished Jul 02 07:54:52 AM PDT 24
Peak memory 224328 kb
Host smart-d0d0de0d-3897-4f2f-9471-18de3322f4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288602722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2288602722
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1644834557
Short name T887
Test name
Test status
Simulation time 8167537964 ps
CPU time 23.03 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:55:01 AM PDT 24
Peak memory 232672 kb
Host smart-d7b5c1df-ddd0-4296-b72e-a816778ee37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644834557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1644834557
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.535381299
Short name T263
Test name
Test status
Simulation time 6970535738 ps
CPU time 12.94 seconds
Started Jul 02 07:54:32 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 232612 kb
Host smart-620bb68e-b574-43ec-bcac-27305a6e6cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535381299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.535381299
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3777096505
Short name T974
Test name
Test status
Simulation time 111780843 ps
CPU time 2.31 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:52 AM PDT 24
Peak memory 224444 kb
Host smart-e59124c9-80aa-4a46-a2ac-4704e8ebafa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777096505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3777096505
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.412798010
Short name T882
Test name
Test status
Simulation time 638915209 ps
CPU time 8.78 seconds
Started Jul 02 07:54:40 AM PDT 24
Finished Jul 02 07:54:50 AM PDT 24
Peak memory 222032 kb
Host smart-1f968094-ca61-42ff-8b8f-0714ac881de9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=412798010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.412798010
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2893279504
Short name T566
Test name
Test status
Simulation time 10278784522 ps
CPU time 65.75 seconds
Started Jul 02 07:54:30 AM PDT 24
Finished Jul 02 07:55:43 AM PDT 24
Peak memory 253992 kb
Host smart-f7ffe4a6-2c57-43e4-b1ab-8b69ba5a79ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893279504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2893279504
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.441224553
Short name T292
Test name
Test status
Simulation time 4444589774 ps
CPU time 22.13 seconds
Started Jul 02 07:54:26 AM PDT 24
Finished Jul 02 07:54:55 AM PDT 24
Peak memory 216252 kb
Host smart-836a38bd-0f09-4813-98c6-5279a8845a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441224553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.441224553
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4026167507
Short name T650
Test name
Test status
Simulation time 1627382550 ps
CPU time 1.79 seconds
Started Jul 02 07:54:34 AM PDT 24
Finished Jul 02 07:54:41 AM PDT 24
Peak memory 207784 kb
Host smart-be74da3f-67f3-4bbd-9bbb-8efae9a89756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026167507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4026167507
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2814425984
Short name T747
Test name
Test status
Simulation time 74831164 ps
CPU time 4.16 seconds
Started Jul 02 07:54:39 AM PDT 24
Finished Jul 02 07:54:45 AM PDT 24
Peak memory 216084 kb
Host smart-5caf305e-441c-4afb-b1d0-f5062bb4a443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814425984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2814425984
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3553481911
Short name T27
Test name
Test status
Simulation time 30254479 ps
CPU time 0.73 seconds
Started Jul 02 07:54:32 AM PDT 24
Finished Jul 02 07:54:39 AM PDT 24
Peak memory 205892 kb
Host smart-e861e23f-4c9c-4cdc-9e88-913837dfca5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553481911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3553481911
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2361154728
Short name T473
Test name
Test status
Simulation time 1891413277 ps
CPU time 5.54 seconds
Started Jul 02 07:54:30 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 232540 kb
Host smart-afe9b76e-16e7-49b5-9699-94887111143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361154728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2361154728
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3167183749
Short name T1003
Test name
Test status
Simulation time 13891748 ps
CPU time 0.73 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:54:38 AM PDT 24
Peak memory 205388 kb
Host smart-339cba90-008b-48e1-85c7-cbee22443e6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167183749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3167183749
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2757356798
Short name T877
Test name
Test status
Simulation time 168601495 ps
CPU time 2.97 seconds
Started Jul 02 07:54:42 AM PDT 24
Finished Jul 02 07:54:47 AM PDT 24
Peak memory 232616 kb
Host smart-448a3738-6bf2-4c06-aba7-3fc4b2949902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757356798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2757356798
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2723561130
Short name T32
Test name
Test status
Simulation time 62483467 ps
CPU time 0.79 seconds
Started Jul 02 07:54:32 AM PDT 24
Finished Jul 02 07:54:39 AM PDT 24
Peak memory 206508 kb
Host smart-3ae68c89-304c-416f-bc36-20a3c3fcb17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723561130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2723561130
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1563551861
Short name T45
Test name
Test status
Simulation time 186318939278 ps
CPU time 336.02 seconds
Started Jul 02 07:54:26 AM PDT 24
Finished Jul 02 08:00:09 AM PDT 24
Peak memory 264648 kb
Host smart-6a3dbe4f-3cb8-44b6-acd0-ace11f17d3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563551861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1563551861
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2039565025
Short name T683
Test name
Test status
Simulation time 2265013643 ps
CPU time 45.12 seconds
Started Jul 02 07:54:24 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 249092 kb
Host smart-a88ede83-939f-4756-8f35-d0882a64ef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039565025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2039565025
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3789206923
Short name T198
Test name
Test status
Simulation time 2272520067 ps
CPU time 55 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:55:47 AM PDT 24
Peak memory 249648 kb
Host smart-476aa68c-74ac-4173-b3e5-09c242a0511f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789206923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3789206923
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1443756250
Short name T685
Test name
Test status
Simulation time 2466550387 ps
CPU time 8.98 seconds
Started Jul 02 07:54:39 AM PDT 24
Finished Jul 02 07:54:50 AM PDT 24
Peak memory 249132 kb
Host smart-f8dc9888-e5e5-4293-908b-b002d13d8507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443756250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1443756250
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.310958471
Short name T922
Test name
Test status
Simulation time 1610130439 ps
CPU time 37.84 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 254028 kb
Host smart-3318e15c-5ef1-463d-ab58-2ee7bd578c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310958471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.310958471
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1082947365
Short name T653
Test name
Test status
Simulation time 249805329 ps
CPU time 4.84 seconds
Started Jul 02 07:54:35 AM PDT 24
Finished Jul 02 07:54:45 AM PDT 24
Peak memory 232548 kb
Host smart-ff5ab2cb-d5b0-4c5c-9776-6fa2b7ae8d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082947365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1082947365
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4089415757
Short name T862
Test name
Test status
Simulation time 8239470707 ps
CPU time 57.68 seconds
Started Jul 02 07:54:51 AM PDT 24
Finished Jul 02 07:55:55 AM PDT 24
Peak memory 240656 kb
Host smart-b3baf2f2-0bd2-46bb-ac3d-1e501846a745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089415757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4089415757
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1070363148
Short name T495
Test name
Test status
Simulation time 11194281567 ps
CPU time 11.9 seconds
Started Jul 02 07:54:28 AM PDT 24
Finished Jul 02 07:54:47 AM PDT 24
Peak memory 232780 kb
Host smart-d5c37546-ac2f-4205-a43b-9becd9f2bb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070363148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1070363148
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2208072476
Short name T544
Test name
Test status
Simulation time 1858508021 ps
CPU time 10.54 seconds
Started Jul 02 07:54:29 AM PDT 24
Finished Jul 02 07:54:47 AM PDT 24
Peak memory 239056 kb
Host smart-ce533626-9239-4c3b-8940-859e877aa3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208072476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2208072476
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.863976619
Short name T743
Test name
Test status
Simulation time 1954913728 ps
CPU time 13.67 seconds
Started Jul 02 07:54:44 AM PDT 24
Finished Jul 02 07:55:00 AM PDT 24
Peak memory 221876 kb
Host smart-17d2a4f0-9969-4394-9d4e-9c04d2748764
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=863976619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.863976619
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.519526714
Short name T49
Test name
Test status
Simulation time 143178833279 ps
CPU time 340.01 seconds
Started Jul 02 07:54:36 AM PDT 24
Finished Jul 02 08:00:20 AM PDT 24
Peak memory 265624 kb
Host smart-69fcea1f-e935-44b8-a2f9-cbdd66654177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519526714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.519526714
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2773780063
Short name T385
Test name
Test status
Simulation time 52830610964 ps
CPU time 50 seconds
Started Jul 02 07:54:48 AM PDT 24
Finished Jul 02 07:55:44 AM PDT 24
Peak memory 216172 kb
Host smart-e382bbc7-75bf-493d-8bcf-c994366c8d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773780063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2773780063
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2860886008
Short name T494
Test name
Test status
Simulation time 4495174774 ps
CPU time 12.67 seconds
Started Jul 02 07:54:31 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 216296 kb
Host smart-33cc6a7c-31e9-4716-bf95-38247c6fffdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860886008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2860886008
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1132119130
Short name T816
Test name
Test status
Simulation time 42816622 ps
CPU time 0.68 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:49 AM PDT 24
Peak memory 205524 kb
Host smart-dc14779d-f9de-4e45-b028-f4843afabd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132119130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1132119130
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2576476541
Short name T387
Test name
Test status
Simulation time 13675583 ps
CPU time 0.72 seconds
Started Jul 02 07:54:41 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 205828 kb
Host smart-2e628040-b28c-4f28-8df6-1860614631ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576476541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2576476541
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.556679372
Short name T516
Test name
Test status
Simulation time 15710632343 ps
CPU time 12.79 seconds
Started Jul 02 07:54:27 AM PDT 24
Finished Jul 02 07:54:47 AM PDT 24
Peak memory 224532 kb
Host smart-46784469-fcbe-40a6-98f7-dd6826cbc47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556679372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.556679372
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1699585789
Short name T793
Test name
Test status
Simulation time 40595171 ps
CPU time 0.73 seconds
Started Jul 02 07:54:44 AM PDT 24
Finished Jul 02 07:54:48 AM PDT 24
Peak memory 205796 kb
Host smart-c5cf686e-990a-4210-b23e-a102d061803b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699585789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1699585789
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2187757347
Short name T92
Test name
Test status
Simulation time 142687243 ps
CPU time 3 seconds
Started Jul 02 07:54:49 AM PDT 24
Finished Jul 02 07:54:59 AM PDT 24
Peak memory 224380 kb
Host smart-5d534ea1-4a0a-48e1-ab20-7d53a6aeb6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187757347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2187757347
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3195796983
Short name T530
Test name
Test status
Simulation time 136275808 ps
CPU time 0.73 seconds
Started Jul 02 07:54:40 AM PDT 24
Finished Jul 02 07:54:42 AM PDT 24
Peak memory 205472 kb
Host smart-f94260c5-8a7e-4687-b50f-e5ec5ea0b496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195796983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3195796983
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1394193795
Short name T860
Test name
Test status
Simulation time 68882645262 ps
CPU time 187.99 seconds
Started Jul 02 07:54:44 AM PDT 24
Finished Jul 02 07:57:54 AM PDT 24
Peak memory 257568 kb
Host smart-eb0816c8-0aed-4748-b4a6-57e381ccb974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394193795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1394193795
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2183367106
Short name T995
Test name
Test status
Simulation time 10066727234 ps
CPU time 49.36 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:55:39 AM PDT 24
Peak memory 249156 kb
Host smart-e747d593-60d2-42bf-9b05-cadc526e9d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183367106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2183367106
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2122699201
Short name T317
Test name
Test status
Simulation time 2484414070 ps
CPU time 14.7 seconds
Started Jul 02 07:54:30 AM PDT 24
Finished Jul 02 07:54:52 AM PDT 24
Peak memory 240184 kb
Host smart-a5ad0bdd-c209-4a82-ae80-23328f12377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122699201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2122699201
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.523453806
Short name T531
Test name
Test status
Simulation time 29977885974 ps
CPU time 49.65 seconds
Started Jul 02 07:55:01 AM PDT 24
Finished Jul 02 07:55:59 AM PDT 24
Peak memory 253200 kb
Host smart-6cea562e-f027-4b90-8fa5-e4f860e91126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523453806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.523453806
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1114546840
Short name T687
Test name
Test status
Simulation time 1024764958 ps
CPU time 10.39 seconds
Started Jul 02 07:54:52 AM PDT 24
Finished Jul 02 07:55:09 AM PDT 24
Peak memory 232584 kb
Host smart-8288bfa2-f1fc-4cad-b0a6-6f404d2df62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114546840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1114546840
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.781585877
Short name T931
Test name
Test status
Simulation time 1335093090 ps
CPU time 24.71 seconds
Started Jul 02 07:54:48 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 240056 kb
Host smart-7c111438-0736-4f0c-9774-173a32e21005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781585877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.781585877
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.191036578
Short name T460
Test name
Test status
Simulation time 148894786 ps
CPU time 2.61 seconds
Started Jul 02 07:54:44 AM PDT 24
Finished Jul 02 07:54:49 AM PDT 24
Peak memory 232552 kb
Host smart-cf414daa-2825-4c3c-92d5-bd2a7730e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191036578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.191036578
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3407881433
Short name T551
Test name
Test status
Simulation time 8183911317 ps
CPU time 5.98 seconds
Started Jul 02 07:54:50 AM PDT 24
Finished Jul 02 07:55:02 AM PDT 24
Peak memory 232928 kb
Host smart-10ffa19e-7c45-45cc-bcc7-cd0269b6930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407881433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3407881433
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3991260473
Short name T721
Test name
Test status
Simulation time 2529258464 ps
CPU time 7.72 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:55:00 AM PDT 24
Peak memory 223224 kb
Host smart-89a1e992-2e4f-4cfb-827b-1b3a3bb8420f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3991260473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3991260473
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2659784248
Short name T760
Test name
Test status
Simulation time 5068145060 ps
CPU time 17.78 seconds
Started Jul 02 07:54:47 AM PDT 24
Finished Jul 02 07:55:11 AM PDT 24
Peak memory 216280 kb
Host smart-77f51500-76f1-46d3-90aa-47eb41c0ad84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659784248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2659784248
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1089694726
Short name T896
Test name
Test status
Simulation time 21019659 ps
CPU time 0.71 seconds
Started Jul 02 07:54:38 AM PDT 24
Finished Jul 02 07:54:42 AM PDT 24
Peak memory 205620 kb
Host smart-991a8528-5eb9-40af-a34c-88c83fa226e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089694726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1089694726
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1623831508
Short name T950
Test name
Test status
Simulation time 86646139 ps
CPU time 0.93 seconds
Started Jul 02 07:54:41 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 206516 kb
Host smart-604c3bba-b87c-45b0-9566-a9287cf0e1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623831508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1623831508
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2299627584
Short name T722
Test name
Test status
Simulation time 75246472 ps
CPU time 0.92 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:54:53 AM PDT 24
Peak memory 206844 kb
Host smart-da61d7e5-24b1-40f6-820c-373a1248c7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299627584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2299627584
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1444931222
Short name T943
Test name
Test status
Simulation time 209540896 ps
CPU time 2.85 seconds
Started Jul 02 07:54:44 AM PDT 24
Finished Jul 02 07:54:50 AM PDT 24
Peak memory 224440 kb
Host smart-feafb4bf-c7f3-4be9-b458-8c09fd56dead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444931222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1444931222
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2264783983
Short name T60
Test name
Test status
Simulation time 13985143 ps
CPU time 0.7 seconds
Started Jul 02 07:53:33 AM PDT 24
Finished Jul 02 07:53:34 AM PDT 24
Peak memory 204912 kb
Host smart-c8670c04-1565-455a-a51a-e3e8f69f1438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264783983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
264783983
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3374513564
Short name T257
Test name
Test status
Simulation time 426775663 ps
CPU time 3.21 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:29 AM PDT 24
Peak memory 232620 kb
Host smart-affa45b8-cf4c-406b-80b2-777c22492280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374513564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3374513564
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2749719431
Short name T476
Test name
Test status
Simulation time 21764653 ps
CPU time 0.82 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:26 AM PDT 24
Peak memory 206500 kb
Host smart-9c0f7892-3969-4790-a679-f79458ba1692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749719431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2749719431
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3219286665
Short name T266
Test name
Test status
Simulation time 4832224366 ps
CPU time 45.74 seconds
Started Jul 02 07:53:23 AM PDT 24
Finished Jul 02 07:54:12 AM PDT 24
Peak memory 240832 kb
Host smart-87b0a0ca-045a-45f0-8322-cac19b58d461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219286665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3219286665
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.345496666
Short name T202
Test name
Test status
Simulation time 36356802648 ps
CPU time 183.85 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:56:59 AM PDT 24
Peak memory 253768 kb
Host smart-14140c3a-76c4-40bb-a578-71ad4f6232b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345496666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.345496666
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1588606418
Short name T623
Test name
Test status
Simulation time 341539324569 ps
CPU time 286.57 seconds
Started Jul 02 07:53:47 AM PDT 24
Finished Jul 02 07:58:36 AM PDT 24
Peak memory 252956 kb
Host smart-43ad56e4-81be-470b-9a58-a6c702dfcbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588606418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1588606418
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1042930639
Short name T575
Test name
Test status
Simulation time 1177212199 ps
CPU time 11.94 seconds
Started Jul 02 07:53:23 AM PDT 24
Finished Jul 02 07:53:39 AM PDT 24
Peak memory 237380 kb
Host smart-9be9e1ab-3e83-4579-92be-0e2d4119a8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042930639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1042930639
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2736790434
Short name T802
Test name
Test status
Simulation time 1270720442 ps
CPU time 17.12 seconds
Started Jul 02 07:53:22 AM PDT 24
Finished Jul 02 07:53:43 AM PDT 24
Peak memory 224364 kb
Host smart-ea6256e8-c9c5-4eab-8864-8a6ffdf34023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736790434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2736790434
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1998861127
Short name T586
Test name
Test status
Simulation time 48559245 ps
CPU time 2.43 seconds
Started Jul 02 07:53:24 AM PDT 24
Finished Jul 02 07:53:29 AM PDT 24
Peak memory 232528 kb
Host smart-767dd2b3-ad88-4083-ad0b-6af7296123cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998861127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1998861127
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1165587938
Short name T272
Test name
Test status
Simulation time 5405759035 ps
CPU time 6.12 seconds
Started Jul 02 07:53:23 AM PDT 24
Finished Jul 02 07:53:33 AM PDT 24
Peak memory 232660 kb
Host smart-ea21544b-9418-4a36-b427-2136c26a39c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165587938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1165587938
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1579456489
Short name T849
Test name
Test status
Simulation time 961517682 ps
CPU time 8.13 seconds
Started Jul 02 07:53:21 AM PDT 24
Finished Jul 02 07:53:33 AM PDT 24
Peak memory 232656 kb
Host smart-e4231e62-5679-450f-870a-15bc6cc0a1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579456489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1579456489
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1458706318
Short name T520
Test name
Test status
Simulation time 164048295 ps
CPU time 4.19 seconds
Started Jul 02 07:53:45 AM PDT 24
Finished Jul 02 07:53:50 AM PDT 24
Peak memory 222660 kb
Host smart-f86c97ee-368e-4cc1-9c88-b0d7142ded20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1458706318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1458706318
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4200601124
Short name T68
Test name
Test status
Simulation time 86602312 ps
CPU time 1.14 seconds
Started Jul 02 07:53:34 AM PDT 24
Finished Jul 02 07:53:37 AM PDT 24
Peak memory 235480 kb
Host smart-f8cd9d3f-7c45-45ba-915a-6a378cbc372f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200601124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4200601124
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.937690792
Short name T302
Test name
Test status
Simulation time 22250015337 ps
CPU time 26.17 seconds
Started Jul 02 07:53:34 AM PDT 24
Finished Jul 02 07:54:01 AM PDT 24
Peak memory 216192 kb
Host smart-55e93954-b917-49eb-8eb9-9f58f5725561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937690792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.937690792
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2837248465
Short name T480
Test name
Test status
Simulation time 23796425565 ps
CPU time 18.65 seconds
Started Jul 02 07:53:23 AM PDT 24
Finished Jul 02 07:53:45 AM PDT 24
Peak memory 216252 kb
Host smart-5eb79b17-ee5f-4aa5-b352-f56b7aa9233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837248465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2837248465
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3718386622
Short name T842
Test name
Test status
Simulation time 21231466 ps
CPU time 1.25 seconds
Started Jul 02 07:53:26 AM PDT 24
Finished Jul 02 07:53:29 AM PDT 24
Peak memory 216084 kb
Host smart-89a9fdfc-b3cb-400e-8acb-a703fae3c713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718386622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3718386622
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.377692736
Short name T982
Test name
Test status
Simulation time 39024862 ps
CPU time 0.67 seconds
Started Jul 02 07:53:34 AM PDT 24
Finished Jul 02 07:53:36 AM PDT 24
Peak memory 205512 kb
Host smart-f8d2056a-1e64-4aaa-a6ae-2302b7db586b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377692736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.377692736
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.812072577
Short name T883
Test name
Test status
Simulation time 8452602147 ps
CPU time 28.76 seconds
Started Jul 02 07:53:24 AM PDT 24
Finished Jul 02 07:53:56 AM PDT 24
Peak memory 237184 kb
Host smart-542fcf0f-6814-4297-99a7-d842581a0846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812072577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.812072577
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4063203552
Short name T605
Test name
Test status
Simulation time 11094713 ps
CPU time 0.75 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:11 AM PDT 24
Peak memory 205764 kb
Host smart-caa8d513-ea31-45da-8c65-5e9b69d25db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063203552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4063203552
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1023038652
Short name T923
Test name
Test status
Simulation time 3232557881 ps
CPU time 7.69 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:55:00 AM PDT 24
Peak memory 224580 kb
Host smart-dfbca655-a29b-4510-b9d1-2b7d2219b7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023038652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1023038652
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1072701599
Short name T11
Test name
Test status
Simulation time 173188513 ps
CPU time 0.77 seconds
Started Jul 02 07:54:41 AM PDT 24
Finished Jul 02 07:54:44 AM PDT 24
Peak memory 206508 kb
Host smart-4b006367-0c6e-40db-ad0c-560b20c77acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072701599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1072701599
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3130369190
Short name T770
Test name
Test status
Simulation time 55945325 ps
CPU time 0.95 seconds
Started Jul 02 07:54:55 AM PDT 24
Finished Jul 02 07:55:01 AM PDT 24
Peak memory 215772 kb
Host smart-68a1fcc1-71a6-4ccf-ba83-bb992ec70344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130369190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3130369190
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.220896238
Short name T402
Test name
Test status
Simulation time 8179005230 ps
CPU time 67.51 seconds
Started Jul 02 07:54:56 AM PDT 24
Finished Jul 02 07:56:09 AM PDT 24
Peak memory 255244 kb
Host smart-58d748fc-dce7-4d9d-b019-9a9eef2caa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220896238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.220896238
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.281782715
Short name T173
Test name
Test status
Simulation time 8526605956 ps
CPU time 28.22 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:55:18 AM PDT 24
Peak memory 238420 kb
Host smart-faa2922d-fc6b-4669-a6bd-e003ef56e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281782715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.281782715
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1197934836
Short name T753
Test name
Test status
Simulation time 2229106836 ps
CPU time 16.98 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:55:07 AM PDT 24
Peak memory 224420 kb
Host smart-1230d065-3bbc-4861-9b11-a7857cb43345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197934836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1197934836
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2784560960
Short name T453
Test name
Test status
Simulation time 6431831448 ps
CPU time 30.9 seconds
Started Jul 02 07:54:43 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 249052 kb
Host smart-e8962815-4aa0-4c67-8b5c-37a69634fa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784560960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2784560960
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1035892608
Short name T214
Test name
Test status
Simulation time 2843214059 ps
CPU time 12.51 seconds
Started Jul 02 07:54:48 AM PDT 24
Finished Jul 02 07:55:07 AM PDT 24
Peak memory 224452 kb
Host smart-f15d7600-4e4d-4913-b9a7-c9164c99c532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035892608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1035892608
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3535331366
Short name T433
Test name
Test status
Simulation time 646354421 ps
CPU time 8.35 seconds
Started Jul 02 07:54:38 AM PDT 24
Finished Jul 02 07:54:49 AM PDT 24
Peak memory 232556 kb
Host smart-ac295528-3a7f-4306-950a-b4ed2861d411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535331366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3535331366
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2208111830
Short name T424
Test name
Test status
Simulation time 28813963176 ps
CPU time 14.1 seconds
Started Jul 02 07:54:47 AM PDT 24
Finished Jul 02 07:55:07 AM PDT 24
Peak memory 232980 kb
Host smart-84715324-d89d-4e56-9f0d-d604e0b04010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208111830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2208111830
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2951725931
Short name T914
Test name
Test status
Simulation time 185374686 ps
CPU time 2.09 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 224060 kb
Host smart-530838ac-92c7-4b0b-b0b2-7cbab40d6983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951725931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2951725931
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2799632
Short name T703
Test name
Test status
Simulation time 3199863062 ps
CPU time 12.92 seconds
Started Jul 02 07:54:47 AM PDT 24
Finished Jul 02 07:55:06 AM PDT 24
Peak memory 222068 kb
Host smart-30bb3d40-d5a8-4250-8e3f-c270d2e92efb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2799632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.2799632
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3018960460
Short name T150
Test name
Test status
Simulation time 15432230435 ps
CPU time 198.54 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:58:08 AM PDT 24
Peak memory 273688 kb
Host smart-07139a75-ef28-45bf-9aea-c1ed699200a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018960460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3018960460
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4079188029
Short name T786
Test name
Test status
Simulation time 748381584 ps
CPU time 11.93 seconds
Started Jul 02 07:54:33 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 216064 kb
Host smart-6b08d9ef-a3e4-41f2-81dc-c723014f1c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079188029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4079188029
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1178821348
Short name T72
Test name
Test status
Simulation time 6187629744 ps
CPU time 6.29 seconds
Started Jul 02 07:54:33 AM PDT 24
Finished Jul 02 07:54:45 AM PDT 24
Peak memory 216252 kb
Host smart-cef0d05b-6b00-4bf2-88d7-5479462336a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178821348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1178821348
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1663400734
Short name T633
Test name
Test status
Simulation time 52198087 ps
CPU time 2.21 seconds
Started Jul 02 07:54:32 AM PDT 24
Finished Jul 02 07:54:41 AM PDT 24
Peak memory 216064 kb
Host smart-9ff2a2ae-951e-44cc-8ca9-6b7d6fc2198b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663400734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1663400734
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.252317272
Short name T695
Test name
Test status
Simulation time 31677762 ps
CPU time 0.77 seconds
Started Jul 02 07:54:39 AM PDT 24
Finished Jul 02 07:54:42 AM PDT 24
Peak memory 205820 kb
Host smart-ca654f6d-8ef9-489f-9521-7b319f8aa208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252317272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.252317272
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4090323689
Short name T448
Test name
Test status
Simulation time 537445381 ps
CPU time 2.15 seconds
Started Jul 02 07:54:51 AM PDT 24
Finished Jul 02 07:55:00 AM PDT 24
Peak memory 224000 kb
Host smart-3ca49ecd-7f26-4a31-8817-ef8c5bf51460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090323689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4090323689
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.313442790
Short name T731
Test name
Test status
Simulation time 91452241 ps
CPU time 0.73 seconds
Started Jul 02 07:54:50 AM PDT 24
Finished Jul 02 07:54:58 AM PDT 24
Peak memory 205464 kb
Host smart-68990156-993e-4cca-9cc0-53c3de0580b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313442790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.313442790
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1718709233
Short name T479
Test name
Test status
Simulation time 240157702 ps
CPU time 3 seconds
Started Jul 02 07:54:50 AM PDT 24
Finished Jul 02 07:54:59 AM PDT 24
Peak memory 224416 kb
Host smart-7734f1c3-9cf8-4d45-8488-ec2d7249c21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718709233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1718709233
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.4073054529
Short name T410
Test name
Test status
Simulation time 57838068 ps
CPU time 0.75 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:54:52 AM PDT 24
Peak memory 205540 kb
Host smart-1528ceaa-4be8-45e0-9c3d-d54630382d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073054529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.4073054529
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2511872614
Short name T186
Test name
Test status
Simulation time 6546474589 ps
CPU time 35.32 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 249516 kb
Host smart-cc9ee2d1-85e3-46c4-985f-a66b2252ea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511872614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2511872614
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3396783035
Short name T676
Test name
Test status
Simulation time 40504288184 ps
CPU time 128.07 seconds
Started Jul 02 07:54:48 AM PDT 24
Finished Jul 02 07:57:03 AM PDT 24
Peak memory 249976 kb
Host smart-85a69e75-9725-43ae-b25a-88285dc3c016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396783035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3396783035
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.524993360
Short name T171
Test name
Test status
Simulation time 27177458118 ps
CPU time 221.67 seconds
Started Jul 02 07:54:42 AM PDT 24
Finished Jul 02 07:58:26 AM PDT 24
Peak memory 262372 kb
Host smart-0e92384f-0613-4fc6-9e9d-da4b82f79f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524993360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.524993360
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2908159994
Short name T780
Test name
Test status
Simulation time 1979599354 ps
CPU time 15.58 seconds
Started Jul 02 07:54:56 AM PDT 24
Finished Jul 02 07:55:17 AM PDT 24
Peak memory 240752 kb
Host smart-599adb52-1ee3-4257-94b2-c6457cb77993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908159994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2908159994
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.996418278
Short name T167
Test name
Test status
Simulation time 635139416 ps
CPU time 4.39 seconds
Started Jul 02 07:54:57 AM PDT 24
Finished Jul 02 07:55:06 AM PDT 24
Peak memory 238284 kb
Host smart-b0bceebc-72b4-4638-abb2-85097c4887e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996418278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.996418278
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3219627176
Short name T467
Test name
Test status
Simulation time 521455850 ps
CPU time 5.61 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:54 AM PDT 24
Peak memory 224440 kb
Host smart-157d3de0-6b8a-4653-9497-c8de2f4ff71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219627176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3219627176
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3464361332
Short name T227
Test name
Test status
Simulation time 8438857549 ps
CPU time 95.42 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:56:26 AM PDT 24
Peak memory 236272 kb
Host smart-67b4c1a2-f2de-4aad-a3d3-0263c7c7f7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464361332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3464361332
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.596990061
Short name T707
Test name
Test status
Simulation time 285845820 ps
CPU time 3 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 224396 kb
Host smart-5692d6c0-3027-4366-8b9b-ed9a9c263506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596990061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.596990061
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1861830434
Short name T179
Test name
Test status
Simulation time 1928047228 ps
CPU time 3.48 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:53 AM PDT 24
Peak memory 224396 kb
Host smart-b444f995-3b9f-4970-ba68-bdc6814a94da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861830434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1861830434
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2206592702
Short name T777
Test name
Test status
Simulation time 298244059 ps
CPU time 4.53 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:53 AM PDT 24
Peak memory 223036 kb
Host smart-789c756f-84c6-4096-bba5-72a512873f78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2206592702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2206592702
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1231793110
Short name T899
Test name
Test status
Simulation time 90576467 ps
CPU time 0.97 seconds
Started Jul 02 07:54:42 AM PDT 24
Finished Jul 02 07:54:45 AM PDT 24
Peak memory 206536 kb
Host smart-a6de5682-c657-4ca1-a405-bde3857f1255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231793110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1231793110
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3200023206
Short name T356
Test name
Test status
Simulation time 214791336 ps
CPU time 2.09 seconds
Started Jul 02 07:54:50 AM PDT 24
Finished Jul 02 07:54:59 AM PDT 24
Peak memory 216128 kb
Host smart-d7caaad9-56c1-4ade-a269-0a3c95396cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200023206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3200023206
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3970911572
Short name T613
Test name
Test status
Simulation time 3399014620 ps
CPU time 2.94 seconds
Started Jul 02 07:54:40 AM PDT 24
Finished Jul 02 07:54:44 AM PDT 24
Peak memory 207984 kb
Host smart-63e02057-7a41-450c-bc8a-0612892b1139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970911572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3970911572
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3870644662
Short name T735
Test name
Test status
Simulation time 37628603 ps
CPU time 1.16 seconds
Started Jul 02 07:54:50 AM PDT 24
Finished Jul 02 07:54:58 AM PDT 24
Peak memory 207808 kb
Host smart-124750be-f697-4e2c-9e13-09353eb7f322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870644662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3870644662
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4062446691
Short name T771
Test name
Test status
Simulation time 20010483 ps
CPU time 0.78 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 205832 kb
Host smart-5b0c6c70-53dc-4e60-8b53-2122ca293378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062446691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4062446691
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.114490093
Short name T526
Test name
Test status
Simulation time 2313129971 ps
CPU time 9.11 seconds
Started Jul 02 07:54:54 AM PDT 24
Finished Jul 02 07:55:09 AM PDT 24
Peak memory 238960 kb
Host smart-3b032eb4-025c-452f-9cb0-207bc082d014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114490093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.114490093
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2590024061
Short name T875
Test name
Test status
Simulation time 13625773 ps
CPU time 0.72 seconds
Started Jul 02 07:54:51 AM PDT 24
Finished Jul 02 07:54:58 AM PDT 24
Peak memory 205428 kb
Host smart-a362aa79-7fd5-4f7b-a709-069e6f975cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590024061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2590024061
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2197369236
Short name T397
Test name
Test status
Simulation time 269050839 ps
CPU time 3.77 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:53 AM PDT 24
Peak memory 232588 kb
Host smart-80faba74-8880-4df5-9a0b-27e8ec2825bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197369236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2197369236
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.988237506
Short name T481
Test name
Test status
Simulation time 14651086 ps
CPU time 0.79 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 206504 kb
Host smart-0eb2f806-22bd-4b1f-aeb1-553d2a3d99bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988237506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.988237506
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4124171052
Short name T857
Test name
Test status
Simulation time 3120776312 ps
CPU time 24.48 seconds
Started Jul 02 07:54:47 AM PDT 24
Finished Jul 02 07:55:18 AM PDT 24
Peak memory 249096 kb
Host smart-58264ae6-bc27-47f6-acc7-db493483790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124171052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4124171052
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.706864240
Short name T716
Test name
Test status
Simulation time 7527588805 ps
CPU time 79.14 seconds
Started Jul 02 07:54:42 AM PDT 24
Finished Jul 02 07:56:03 AM PDT 24
Peak memory 255568 kb
Host smart-558a3b52-cadd-4fc5-bbc8-c6d01b7f567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706864240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.706864240
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1271429523
Short name T465
Test name
Test status
Simulation time 8301523776 ps
CPU time 92.99 seconds
Started Jul 02 07:54:49 AM PDT 24
Finished Jul 02 07:56:28 AM PDT 24
Peak memory 249084 kb
Host smart-7505ca80-095b-4adb-a330-6b581342623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271429523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1271429523
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.957661830
Short name T569
Test name
Test status
Simulation time 8430185038 ps
CPU time 29.48 seconds
Started Jul 02 07:54:58 AM PDT 24
Finished Jul 02 07:55:33 AM PDT 24
Peak memory 240840 kb
Host smart-7780669e-ba56-4c92-995d-1162d88a1718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957661830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.957661830
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2836245314
Short name T897
Test name
Test status
Simulation time 5269988829 ps
CPU time 72.19 seconds
Started Jul 02 07:54:49 AM PDT 24
Finished Jul 02 07:56:08 AM PDT 24
Peak memory 249676 kb
Host smart-bdde0b14-a877-4fe5-ba14-1aa44aa14d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836245314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2836245314
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1113049631
Short name T238
Test name
Test status
Simulation time 914594348 ps
CPU time 4.74 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:54:55 AM PDT 24
Peak memory 224388 kb
Host smart-6fe830eb-3df1-4f27-8e58-49197e67c5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113049631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1113049631
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1915781277
Short name T91
Test name
Test status
Simulation time 1287001643 ps
CPU time 16.45 seconds
Started Jul 02 07:54:44 AM PDT 24
Finished Jul 02 07:55:04 AM PDT 24
Peak memory 232512 kb
Host smart-7d717853-0c7d-450b-a2d7-03a08926c63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915781277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1915781277
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.275850172
Short name T854
Test name
Test status
Simulation time 32894944 ps
CPU time 2.3 seconds
Started Jul 02 07:54:52 AM PDT 24
Finished Jul 02 07:55:01 AM PDT 24
Peak memory 232244 kb
Host smart-cfd33b34-0218-4958-83bf-3647adfc1885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275850172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.275850172
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4210379885
Short name T822
Test name
Test status
Simulation time 859287743 ps
CPU time 3.21 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 224460 kb
Host smart-0723371e-f59f-4f6c-9bb8-3cdb0e34005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210379885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4210379885
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2768731516
Short name T103
Test name
Test status
Simulation time 3466887713 ps
CPU time 9.16 seconds
Started Jul 02 07:54:47 AM PDT 24
Finished Jul 02 07:55:03 AM PDT 24
Peak memory 222744 kb
Host smart-1b62bc42-26cc-4244-a255-e89e419f6f9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2768731516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2768731516
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.688470403
Short name T276
Test name
Test status
Simulation time 29814895372 ps
CPU time 202.62 seconds
Started Jul 02 07:54:54 AM PDT 24
Finished Jul 02 07:58:22 AM PDT 24
Peak memory 273112 kb
Host smart-ed30cd22-6316-4659-8a99-b1c633bdbaca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688470403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.688470403
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2524915492
Short name T861
Test name
Test status
Simulation time 20804233 ps
CPU time 0.72 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:13 AM PDT 24
Peak memory 205660 kb
Host smart-9afcccd1-a751-4ab2-b38b-f4e282960b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524915492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2524915492
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.854552057
Short name T756
Test name
Test status
Simulation time 1042223103 ps
CPU time 7.4 seconds
Started Jul 02 07:54:55 AM PDT 24
Finished Jul 02 07:55:08 AM PDT 24
Peak memory 216092 kb
Host smart-b0203c0f-cea3-401d-aa26-8f4ab56cd403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854552057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.854552057
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1118451126
Short name T331
Test name
Test status
Simulation time 59451379 ps
CPU time 0.99 seconds
Started Jul 02 07:55:07 AM PDT 24
Finished Jul 02 07:55:22 AM PDT 24
Peak memory 207480 kb
Host smart-c4420b93-14ca-4299-b603-5ba493f90c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118451126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1118451126
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3740340371
Short name T893
Test name
Test status
Simulation time 142473273 ps
CPU time 0.83 seconds
Started Jul 02 07:54:48 AM PDT 24
Finished Jul 02 07:54:55 AM PDT 24
Peak memory 205924 kb
Host smart-9b275374-c5e1-445d-87f7-88ee99dba149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740340371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3740340371
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1524820966
Short name T656
Test name
Test status
Simulation time 863935756 ps
CPU time 2.53 seconds
Started Jul 02 07:55:00 AM PDT 24
Finished Jul 02 07:55:09 AM PDT 24
Peak memory 224408 kb
Host smart-ab8b722f-6349-4ffa-8340-efe2e5b70a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524820966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1524820966
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1855855279
Short name T555
Test name
Test status
Simulation time 38841088 ps
CPU time 0.67 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 205436 kb
Host smart-6fc1a66f-b46b-48e4-8cc1-fca91016c1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855855279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1855855279
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1712821390
Short name T991
Test name
Test status
Simulation time 5942683230 ps
CPU time 10.35 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:55:00 AM PDT 24
Peak memory 224444 kb
Host smart-283994a6-fbb4-46f3-8164-8eba3b1fb1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712821390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1712821390
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2533781742
Short name T77
Test name
Test status
Simulation time 20618298 ps
CPU time 0.75 seconds
Started Jul 02 07:54:54 AM PDT 24
Finished Jul 02 07:55:01 AM PDT 24
Peak memory 206492 kb
Host smart-b4c39e91-d3aa-490f-976d-0affa388c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533781742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2533781742
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3295933145
Short name T78
Test name
Test status
Simulation time 176622301608 ps
CPU time 307.78 seconds
Started Jul 02 07:54:57 AM PDT 24
Finished Jul 02 08:00:10 AM PDT 24
Peak memory 252888 kb
Host smart-da25c7d9-d4f4-4318-9874-089b3aefeb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295933145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3295933145
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2404288078
Short name T577
Test name
Test status
Simulation time 4810262117 ps
CPU time 76.1 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:56:35 AM PDT 24
Peak memory 254708 kb
Host smart-960a710c-edf0-4da9-a9d9-0e1e38af3b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404288078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2404288078
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1011807971
Short name T864
Test name
Test status
Simulation time 28678438831 ps
CPU time 272.39 seconds
Started Jul 02 07:54:44 AM PDT 24
Finished Jul 02 07:59:20 AM PDT 24
Peak memory 256332 kb
Host smart-a0baee77-cb48-4d1e-bd8a-fb902b8e15d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011807971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1011807971
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.846521309
Short name T144
Test name
Test status
Simulation time 549209503 ps
CPU time 7.03 seconds
Started Jul 02 07:54:50 AM PDT 24
Finished Jul 02 07:55:04 AM PDT 24
Peak memory 232628 kb
Host smart-20bf628c-f134-4d64-9846-b34e9de5743f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846521309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.846521309
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2137253071
Short name T383
Test name
Test status
Simulation time 7527775779 ps
CPU time 15.5 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:55:07 AM PDT 24
Peak memory 234992 kb
Host smart-acbd4adf-78eb-4da5-9643-a5af8b1b4a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137253071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2137253071
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1350537608
Short name T183
Test name
Test status
Simulation time 1047970296 ps
CPU time 10.76 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:55:00 AM PDT 24
Peak memory 232540 kb
Host smart-faed0256-20f9-4367-90ad-0d6a8fd79d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350537608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1350537608
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3479692342
Short name T401
Test name
Test status
Simulation time 53336764 ps
CPU time 2.37 seconds
Started Jul 02 07:54:44 AM PDT 24
Finished Jul 02 07:54:49 AM PDT 24
Peak memory 232208 kb
Host smart-e8d71439-7951-4c25-9f14-0e51a3834945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479692342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3479692342
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1428475298
Short name T284
Test name
Test status
Simulation time 845827553 ps
CPU time 6.3 seconds
Started Jul 02 07:54:44 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 232552 kb
Host smart-a0da08c7-337d-4493-b13b-81f3d687d83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428475298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1428475298
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3871298457
Short name T228
Test name
Test status
Simulation time 135674837 ps
CPU time 2.88 seconds
Started Jul 02 07:54:48 AM PDT 24
Finished Jul 02 07:54:58 AM PDT 24
Peak memory 224372 kb
Host smart-22db6921-c727-4beb-8057-956c1e63f1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871298457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3871298457
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.87538504
Short name T143
Test name
Test status
Simulation time 2738684945 ps
CPU time 11 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:55:02 AM PDT 24
Peak memory 221264 kb
Host smart-0d286e8c-fcda-4df0-b329-7e149bea3fc6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=87538504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direc
t.87538504
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.661203681
Short name T1000
Test name
Test status
Simulation time 22392263955 ps
CPU time 186.6 seconds
Started Jul 02 07:54:44 AM PDT 24
Finished Jul 02 07:57:54 AM PDT 24
Peak memory 253768 kb
Host smart-d064ebdc-38a0-4b22-9549-b414b87fa1dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661203681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.661203681
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2840179935
Short name T930
Test name
Test status
Simulation time 856256392 ps
CPU time 15.1 seconds
Started Jul 02 07:54:49 AM PDT 24
Finished Jul 02 07:55:10 AM PDT 24
Peak memory 216128 kb
Host smart-9068b903-0e76-455d-aa59-cf98df08fec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840179935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2840179935
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.950993213
Short name T638
Test name
Test status
Simulation time 1253366010 ps
CPU time 4.63 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:55:01 AM PDT 24
Peak memory 216076 kb
Host smart-cdda291e-6952-410f-a6fa-1e470b13cf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950993213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.950993213
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.235178535
Short name T774
Test name
Test status
Simulation time 82666452 ps
CPU time 1.81 seconds
Started Jul 02 07:54:47 AM PDT 24
Finished Jul 02 07:54:54 AM PDT 24
Peak memory 216124 kb
Host smart-af088c71-6025-490d-9d30-a29b6a66d37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235178535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.235178535
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1852272522
Short name T305
Test name
Test status
Simulation time 125872642 ps
CPU time 0.86 seconds
Started Jul 02 07:54:51 AM PDT 24
Finished Jul 02 07:54:58 AM PDT 24
Peak memory 206940 kb
Host smart-8add9016-bb1e-488d-92ad-65e25f972def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852272522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1852272522
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2662142966
Short name T423
Test name
Test status
Simulation time 5951975349 ps
CPU time 22.09 seconds
Started Jul 02 07:54:47 AM PDT 24
Finished Jul 02 07:55:15 AM PDT 24
Peak memory 232732 kb
Host smart-3551fd8e-31ed-4f88-b0de-8d32aaf96a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662142966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2662142966
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.918057238
Short name T312
Test name
Test status
Simulation time 12869421 ps
CPU time 0.75 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:49 AM PDT 24
Peak memory 206060 kb
Host smart-ab234ce9-e72f-4edb-ae7d-d2eecf50b701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918057238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.918057238
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4086561431
Short name T593
Test name
Test status
Simulation time 63620813 ps
CPU time 2.59 seconds
Started Jul 02 07:54:57 AM PDT 24
Finished Jul 02 07:55:05 AM PDT 24
Peak memory 232644 kb
Host smart-0aa79653-c179-4c69-bb20-0154c63abed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086561431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4086561431
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.123652246
Short name T823
Test name
Test status
Simulation time 65605044 ps
CPU time 0.76 seconds
Started Jul 02 07:54:45 AM PDT 24
Finished Jul 02 07:54:49 AM PDT 24
Peak memory 206500 kb
Host smart-cc4db0f3-49de-451f-9e1e-02800751b3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123652246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.123652246
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2205587314
Short name T614
Test name
Test status
Simulation time 13817963503 ps
CPU time 23.88 seconds
Started Jul 02 07:54:58 AM PDT 24
Finished Jul 02 07:55:27 AM PDT 24
Peak memory 240868 kb
Host smart-fb00eebd-4f1c-4c08-80ec-ba33c842acb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205587314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2205587314
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2783229573
Short name T639
Test name
Test status
Simulation time 35262165566 ps
CPU time 356.04 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 08:01:11 AM PDT 24
Peak memory 256460 kb
Host smart-fb0f1c81-3a8a-4826-a6dd-d3dda086c259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783229573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2783229573
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.558526105
Short name T455
Test name
Test status
Simulation time 7901010699 ps
CPU time 13.88 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:31 AM PDT 24
Peak memory 219396 kb
Host smart-d0892982-fc5f-44c0-aeb2-93eccf7c4fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558526105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.558526105
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.266730832
Short name T690
Test name
Test status
Simulation time 207966774 ps
CPU time 2.71 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:17 AM PDT 24
Peak memory 232556 kb
Host smart-3c9c5d54-40c5-40f6-b970-cd151d2a056f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266730832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.266730832
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1353749909
Short name T200
Test name
Test status
Simulation time 26685711449 ps
CPU time 231.21 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:59:06 AM PDT 24
Peak memory 263924 kb
Host smart-a47c6d8f-19ad-46fd-a8f6-7247adc1ce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353749909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1353749909
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.380379418
Short name T542
Test name
Test status
Simulation time 357439544 ps
CPU time 4.08 seconds
Started Jul 02 07:55:08 AM PDT 24
Finished Jul 02 07:55:27 AM PDT 24
Peak memory 232552 kb
Host smart-49dd4cad-5a66-431b-bfa0-db9541031a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380379418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.380379418
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3988716483
Short name T658
Test name
Test status
Simulation time 398626408 ps
CPU time 4.66 seconds
Started Jul 02 07:54:50 AM PDT 24
Finished Jul 02 07:55:01 AM PDT 24
Peak memory 224360 kb
Host smart-4d69f118-5ec5-4206-b971-fd136ea17685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988716483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3988716483
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.49556204
Short name T878
Test name
Test status
Simulation time 5721937352 ps
CPU time 18.45 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:32 AM PDT 24
Peak memory 239224 kb
Host smart-bd72f22f-4d45-49bf-86fc-4a43f5b967a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49556204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.49556204
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2415374435
Short name T672
Test name
Test status
Simulation time 7010301196 ps
CPU time 6.98 seconds
Started Jul 02 07:54:56 AM PDT 24
Finished Jul 02 07:55:08 AM PDT 24
Peak memory 232644 kb
Host smart-0313dff1-4024-42de-a1c3-4979871aefd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415374435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2415374435
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.928693737
Short name T472
Test name
Test status
Simulation time 441289399 ps
CPU time 4.97 seconds
Started Jul 02 07:54:58 AM PDT 24
Finished Jul 02 07:55:08 AM PDT 24
Peak memory 222004 kb
Host smart-4d50e4f8-1fd7-4929-95a3-1cdc1be5e607
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=928693737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.928693737
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3986854541
Short name T761
Test name
Test status
Simulation time 108688616 ps
CPU time 1.18 seconds
Started Jul 02 07:54:57 AM PDT 24
Finished Jul 02 07:55:04 AM PDT 24
Peak memory 206936 kb
Host smart-7bfb1d03-a941-45c9-a7fa-27b30e7701ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986854541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3986854541
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1169369249
Short name T377
Test name
Test status
Simulation time 1453719818 ps
CPU time 12.66 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:30 AM PDT 24
Peak memory 216308 kb
Host smart-44bd6317-a198-43ea-91b6-ca0a5ad6aee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169369249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1169369249
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1928168994
Short name T622
Test name
Test status
Simulation time 940650864 ps
CPU time 5.16 seconds
Started Jul 02 07:54:57 AM PDT 24
Finished Jul 02 07:55:08 AM PDT 24
Peak memory 216180 kb
Host smart-a9edc905-1042-4ba3-aeb5-dee154de4107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928168994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1928168994
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1079492345
Short name T1012
Test name
Test status
Simulation time 168969109 ps
CPU time 1 seconds
Started Jul 02 07:54:52 AM PDT 24
Finished Jul 02 07:54:59 AM PDT 24
Peak memory 207272 kb
Host smart-542e3b83-49fd-446d-9681-cf24a93a4d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079492345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1079492345
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2265884417
Short name T709
Test name
Test status
Simulation time 106203750 ps
CPU time 0.73 seconds
Started Jul 02 07:55:01 AM PDT 24
Finished Jul 02 07:55:10 AM PDT 24
Peak memory 205916 kb
Host smart-ad380995-9310-466e-b5a2-c3ba10858c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265884417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2265884417
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2472562259
Short name T181
Test name
Test status
Simulation time 6156110640 ps
CPU time 13.25 seconds
Started Jul 02 07:54:48 AM PDT 24
Finished Jul 02 07:55:08 AM PDT 24
Peak memory 240876 kb
Host smart-2f4c1e65-5c9b-4504-ba6b-f866b1d2d9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472562259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2472562259
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1151512355
Short name T56
Test name
Test status
Simulation time 34075967 ps
CPU time 0.69 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:22 AM PDT 24
Peak memory 205708 kb
Host smart-419d6eb6-d5e5-4047-8bbd-15afc2c6f098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151512355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1151512355
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3530509322
Short name T907
Test name
Test status
Simulation time 728375680 ps
CPU time 3.77 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:17 AM PDT 24
Peak memory 224340 kb
Host smart-40ceb9d2-7f8f-48f8-bcdc-60dc16f62efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530509322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3530509322
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3250950208
Short name T373
Test name
Test status
Simulation time 71110595 ps
CPU time 0.81 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:15 AM PDT 24
Peak memory 206484 kb
Host smart-434c8e79-e9c0-4517-908c-cf7e13ef7d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250950208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3250950208
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3135418375
Short name T38
Test name
Test status
Simulation time 33800636084 ps
CPU time 86.9 seconds
Started Jul 02 07:54:55 AM PDT 24
Finished Jul 02 07:56:27 AM PDT 24
Peak memory 252288 kb
Host smart-23eaba60-300d-4bd4-875d-811865c6324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135418375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3135418375
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.909701924
Short name T838
Test name
Test status
Simulation time 2185212530 ps
CPU time 10.6 seconds
Started Jul 02 07:54:50 AM PDT 24
Finished Jul 02 07:55:07 AM PDT 24
Peak memory 233720 kb
Host smart-5e07264b-cded-431f-8fe6-f48a677df1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909701924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.909701924
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3852085246
Short name T267
Test name
Test status
Simulation time 628555144987 ps
CPU time 302.59 seconds
Started Jul 02 07:54:54 AM PDT 24
Finished Jul 02 08:00:02 AM PDT 24
Peak memory 256000 kb
Host smart-a488b295-6b55-443f-9a88-df4e6f303a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852085246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3852085246
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3453645363
Short name T660
Test name
Test status
Simulation time 46725737 ps
CPU time 0.76 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 215248 kb
Host smart-f582100d-08a6-4b4c-9326-27bc822e55f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453645363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3453645363
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3468736620
Short name T57
Test name
Test status
Simulation time 8417472037 ps
CPU time 13.08 seconds
Started Jul 02 07:55:01 AM PDT 24
Finished Jul 02 07:55:22 AM PDT 24
Peak memory 232712 kb
Host smart-604c9d5c-1e8e-44cf-8686-fd028c71ebd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468736620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3468736620
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3335562813
Short name T535
Test name
Test status
Simulation time 584023513 ps
CPU time 4.84 seconds
Started Jul 02 07:54:46 AM PDT 24
Finished Jul 02 07:54:55 AM PDT 24
Peak memory 232588 kb
Host smart-a71e671f-bcdd-4de9-8c89-dea9fac17609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335562813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3335562813
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.900343904
Short name T782
Test name
Test status
Simulation time 917062591 ps
CPU time 2.45 seconds
Started Jul 02 07:54:59 AM PDT 24
Finished Jul 02 07:55:07 AM PDT 24
Peak memory 224336 kb
Host smart-cb9afe1e-2ca7-43fd-908f-0acfdb111007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900343904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.900343904
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.887513309
Short name T447
Test name
Test status
Simulation time 6689818841 ps
CPU time 10.79 seconds
Started Jul 02 07:54:58 AM PDT 24
Finished Jul 02 07:55:15 AM PDT 24
Peak memory 232708 kb
Host smart-5acbefe5-be88-43c3-aeed-2eeb1e436d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887513309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.887513309
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2299453552
Short name T342
Test name
Test status
Simulation time 1521265408 ps
CPU time 6.51 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:26 AM PDT 24
Peak memory 218628 kb
Host smart-360934f6-95c4-4686-b473-e7bad22a8544
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2299453552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2299453552
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.79344152
Short name T301
Test name
Test status
Simulation time 46637335547 ps
CPU time 189.39 seconds
Started Jul 02 07:54:56 AM PDT 24
Finished Jul 02 07:58:11 AM PDT 24
Peak memory 263612 kb
Host smart-07930cb8-d8e9-438f-ab5f-27622c0e270c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79344152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress
_all.79344152
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3532176163
Short name T316
Test name
Test status
Simulation time 13129044 ps
CPU time 0.71 seconds
Started Jul 02 07:54:52 AM PDT 24
Finished Jul 02 07:54:59 AM PDT 24
Peak memory 205940 kb
Host smart-74d87685-7cca-43dc-a689-ceb2c682d8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532176163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3532176163
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1592847649
Short name T558
Test name
Test status
Simulation time 6060426019 ps
CPU time 5.88 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 216176 kb
Host smart-9a1b4de9-5133-4185-843e-53684b2a8b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592847649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1592847649
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1053508272
Short name T429
Test name
Test status
Simulation time 111584827 ps
CPU time 2.17 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 216136 kb
Host smart-19bf5a0d-308f-470f-831b-a5b369974d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053508272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1053508272
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1575863300
Short name T967
Test name
Test status
Simulation time 167824142 ps
CPU time 0.99 seconds
Started Jul 02 07:54:51 AM PDT 24
Finished Jul 02 07:54:59 AM PDT 24
Peak memory 206300 kb
Host smart-77ea1be9-3057-4172-819c-c73ba92b1cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575863300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1575863300
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.708506999
Short name T225
Test name
Test status
Simulation time 7006617082 ps
CPU time 7.55 seconds
Started Jul 02 07:54:59 AM PDT 24
Finished Jul 02 07:55:13 AM PDT 24
Peak memory 240868 kb
Host smart-38e75032-0c2c-495c-bbdd-ed17ec22a09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708506999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.708506999
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3963269753
Short name T769
Test name
Test status
Simulation time 42168985 ps
CPU time 0.75 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:13 AM PDT 24
Peak memory 205408 kb
Host smart-1678b73f-b049-4441-8557-be23342684ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963269753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3963269753
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2373289251
Short name T399
Test name
Test status
Simulation time 1397437868 ps
CPU time 7.04 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:26 AM PDT 24
Peak memory 224348 kb
Host smart-4728f3f7-0b55-4859-96af-4f20a5320837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373289251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2373289251
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1925969375
Short name T850
Test name
Test status
Simulation time 32750919 ps
CPU time 0.73 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:13 AM PDT 24
Peak memory 205484 kb
Host smart-a1b82776-0580-46a6-9f04-9a4bb22df677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925969375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1925969375
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.295431681
Short name T579
Test name
Test status
Simulation time 262122061112 ps
CPU time 306.43 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 08:00:27 AM PDT 24
Peak memory 262600 kb
Host smart-7f2f00f4-0ac7-4c16-8f73-00da0cfdee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295431681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.295431681
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1815127360
Short name T763
Test name
Test status
Simulation time 6887156474 ps
CPU time 66.37 seconds
Started Jul 02 07:54:58 AM PDT 24
Finished Jul 02 07:56:11 AM PDT 24
Peak memory 249184 kb
Host smart-5f0eddcc-37b3-4716-a147-d51af41c72af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815127360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1815127360
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3184588956
Short name T951
Test name
Test status
Simulation time 153122977 ps
CPU time 3.05 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:21 AM PDT 24
Peak memory 232512 kb
Host smart-c4075578-e32e-45d4-868e-86c34febf3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184588956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3184588956
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.905362011
Short name T338
Test name
Test status
Simulation time 3416330359 ps
CPU time 9.88 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 233816 kb
Host smart-a0786850-a4a3-4be3-a64b-484bc06c58ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905362011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.905362011
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2618199785
Short name T431
Test name
Test status
Simulation time 826018208 ps
CPU time 4.17 seconds
Started Jul 02 07:54:50 AM PDT 24
Finished Jul 02 07:55:01 AM PDT 24
Peak memory 232604 kb
Host smart-d059ab50-fd1f-48ed-8904-2774824cf3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618199785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2618199785
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3923759213
Short name T1009
Test name
Test status
Simulation time 1770209729 ps
CPU time 10.44 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:27 AM PDT 24
Peak memory 224344 kb
Host smart-53452748-85d7-4a3d-8076-51e8fe4fe5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923759213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3923759213
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3308818233
Short name T971
Test name
Test status
Simulation time 4335917959 ps
CPU time 17.22 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:31 AM PDT 24
Peak memory 238464 kb
Host smart-3a79d169-cf3d-4ab8-9a6d-8f5389b2f402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308818233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3308818233
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1523576706
Short name T547
Test name
Test status
Simulation time 1467092679 ps
CPU time 4.3 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:25 AM PDT 24
Peak memory 224396 kb
Host smart-d04b59ef-6ff1-4027-bdbe-07ae2d30ce6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523576706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1523576706
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.998499790
Short name T785
Test name
Test status
Simulation time 1738880013 ps
CPU time 15.5 seconds
Started Jul 02 07:55:10 AM PDT 24
Finished Jul 02 07:55:40 AM PDT 24
Peak memory 222184 kb
Host smart-3b4fb9a5-1414-43d1-aada-94d0224c9546
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=998499790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.998499790
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.395311197
Short name T578
Test name
Test status
Simulation time 26687458468 ps
CPU time 258.92 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:59:32 AM PDT 24
Peak memory 252816 kb
Host smart-758ba311-15ba-4b5c-9229-5ab260c4961e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395311197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.395311197
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.511538805
Short name T949
Test name
Test status
Simulation time 2246360881 ps
CPU time 18.94 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:29 AM PDT 24
Peak memory 216228 kb
Host smart-83de0372-6ee6-4d08-aedc-b6d33d22270f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511538805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.511538805
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2026236033
Short name T869
Test name
Test status
Simulation time 6605951242 ps
CPU time 21.84 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:33 AM PDT 24
Peak memory 216164 kb
Host smart-797df23e-1c66-46d9-aff2-fa8ddcc8d613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026236033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2026236033
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1036515913
Short name T524
Test name
Test status
Simulation time 129694936 ps
CPU time 1.86 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 216008 kb
Host smart-32aef587-435b-4f48-8a1d-a06d92dc02bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036515913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1036515913
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1906448862
Short name T86
Test name
Test status
Simulation time 95931230 ps
CPU time 0.89 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:15 AM PDT 24
Peak memory 205844 kb
Host smart-1de9c308-f46c-4114-aa69-666c25bfb1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906448862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1906448862
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2163764598
Short name T790
Test name
Test status
Simulation time 177571334 ps
CPU time 2.8 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:14 AM PDT 24
Peak memory 232608 kb
Host smart-70c2724f-c95c-4906-997b-410d35e2ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163764598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2163764598
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2891545103
Short name T733
Test name
Test status
Simulation time 70367405 ps
CPU time 0.72 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:14 AM PDT 24
Peak memory 204864 kb
Host smart-6b070a2a-8334-445e-8b9d-0a219c5fe6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891545103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2891545103
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.148626898
Short name T994
Test name
Test status
Simulation time 934738295 ps
CPU time 8.56 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:25 AM PDT 24
Peak memory 224376 kb
Host smart-8a6696b1-dce1-4130-ad50-e653d0dc04b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148626898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.148626898
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2526538600
Short name T959
Test name
Test status
Simulation time 14784110 ps
CPU time 0.75 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:15 AM PDT 24
Peak memory 206512 kb
Host smart-f3a547a3-c3d3-4f79-a1cf-92ecec77611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526538600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2526538600
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.946563649
Short name T71
Test name
Test status
Simulation time 8301606728 ps
CPU time 48.84 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:56:10 AM PDT 24
Peak memory 249060 kb
Host smart-333db157-64d7-4fa8-acf9-5a87e951918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946563649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.946563649
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.221146433
Short name T294
Test name
Test status
Simulation time 63071223200 ps
CPU time 106.02 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:57:01 AM PDT 24
Peak memory 249148 kb
Host smart-22656a72-f445-4270-ac17-cdec53717b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221146433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.221146433
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.385068571
Short name T589
Test name
Test status
Simulation time 2691026104 ps
CPU time 10.22 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 235728 kb
Host smart-c2b0cd67-6448-402d-a293-650ef3c1bce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385068571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.385068571
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.964768518
Short name T42
Test name
Test status
Simulation time 520662669766 ps
CPU time 252.46 seconds
Started Jul 02 07:55:00 AM PDT 24
Finished Jul 02 07:59:18 AM PDT 24
Peak memory 254084 kb
Host smart-0a60ee8c-439e-4baa-8959-6eda7037f9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964768518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.964768518
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3842228419
Short name T648
Test name
Test status
Simulation time 6171404550 ps
CPU time 17.63 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:28 AM PDT 24
Peak memory 224472 kb
Host smart-84a5fe08-c7c8-4511-bc5f-1a932bc4a243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842228419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3842228419
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3914872662
Short name T201
Test name
Test status
Simulation time 643458266 ps
CPU time 12.19 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:23 AM PDT 24
Peak memory 232616 kb
Host smart-b16b9527-1af7-4d60-90e6-e63a6065da82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914872662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3914872662
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2111501223
Short name T894
Test name
Test status
Simulation time 5552456488 ps
CPU time 16.12 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:37 AM PDT 24
Peak memory 248984 kb
Host smart-2bd47920-0e64-4772-a48a-16c193502a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111501223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2111501223
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1300599219
Short name T252
Test name
Test status
Simulation time 154438325 ps
CPU time 3.49 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:23 AM PDT 24
Peak memory 232564 kb
Host smart-f6c24d59-3acf-4b83-b3d4-591cfe6dc225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300599219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1300599219
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.22031181
Short name T58
Test name
Test status
Simulation time 1976417320 ps
CPU time 6.54 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 222544 kb
Host smart-82caed99-1101-4d6a-a027-7f39de417bc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=22031181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direc
t.22031181
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1939713509
Short name T151
Test name
Test status
Simulation time 36171896323 ps
CPU time 276.75 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:59:54 AM PDT 24
Peak memory 251280 kb
Host smart-ff64d26f-18f5-4a71-a118-601a51a34312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939713509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1939713509
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3885119037
Short name T667
Test name
Test status
Simulation time 21019795862 ps
CPU time 21.51 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:43 AM PDT 24
Peak memory 216496 kb
Host smart-1393a722-8e59-45c4-b536-d53821f10a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885119037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3885119037
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3180938348
Short name T820
Test name
Test status
Simulation time 3083727578 ps
CPU time 11.88 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:33 AM PDT 24
Peak memory 216160 kb
Host smart-7472acc1-ae34-4b34-9607-0537ce1ab87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180938348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3180938348
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2060625250
Short name T496
Test name
Test status
Simulation time 29163703 ps
CPU time 0.82 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:13 AM PDT 24
Peak memory 206856 kb
Host smart-727238f6-de16-4479-bdec-1d686ff88a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060625250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2060625250
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1288055271
Short name T729
Test name
Test status
Simulation time 72916554 ps
CPU time 0.87 seconds
Started Jul 02 07:55:01 AM PDT 24
Finished Jul 02 07:55:10 AM PDT 24
Peak memory 205916 kb
Host smart-626b06ea-4efe-456f-8cd6-3966d51c4d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288055271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1288055271
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.405447262
Short name T222
Test name
Test status
Simulation time 1582529679 ps
CPU time 6.52 seconds
Started Jul 02 07:55:09 AM PDT 24
Finished Jul 02 07:55:29 AM PDT 24
Peak memory 224280 kb
Host smart-a76ed72d-a120-4c0b-9ee3-000860571f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405447262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.405447262
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.851047204
Short name T835
Test name
Test status
Simulation time 14376493 ps
CPU time 0.74 seconds
Started Jul 02 07:55:08 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 205852 kb
Host smart-32356aba-b53a-48a8-bde4-da6854e63e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851047204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.851047204
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3268867459
Short name T320
Test name
Test status
Simulation time 18034453721 ps
CPU time 9.23 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:22 AM PDT 24
Peak memory 232708 kb
Host smart-78553706-62a9-403e-961a-2106f3889a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268867459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3268867459
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.999799627
Short name T507
Test name
Test status
Simulation time 18975766 ps
CPU time 0.75 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:11 AM PDT 24
Peak memory 205852 kb
Host smart-98063e14-8e0a-4b4a-90cd-c9ad52272e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999799627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.999799627
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.294740813
Short name T237
Test name
Test status
Simulation time 47915140035 ps
CPU time 354.86 seconds
Started Jul 02 07:55:00 AM PDT 24
Finished Jul 02 08:01:14 AM PDT 24
Peak memory 273216 kb
Host smart-61b9257a-d18e-4163-8e32-d845edf4ee80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294740813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.294740813
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1931095788
Short name T873
Test name
Test status
Simulation time 139794616592 ps
CPU time 236.46 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:59:41 AM PDT 24
Peak memory 257032 kb
Host smart-43171fd9-5a59-4948-b08b-110058bead33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931095788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1931095788
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2136679992
Short name T33
Test name
Test status
Simulation time 37058737553 ps
CPU time 144.92 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:57:43 AM PDT 24
Peak memory 249152 kb
Host smart-f943c87f-2cd9-4c56-aa59-e89178fb9548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136679992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2136679992
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.469579413
Short name T492
Test name
Test status
Simulation time 2593933011 ps
CPU time 13.59 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:30 AM PDT 24
Peak memory 224508 kb
Host smart-dfb03715-39c0-4ab8-8919-1d5baacd2a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469579413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.469579413
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1666283231
Short name T645
Test name
Test status
Simulation time 16047704067 ps
CPU time 129.17 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:57:22 AM PDT 24
Peak memory 251636 kb
Host smart-f6215668-cf8c-41a8-9882-7c408b6e3787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666283231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1666283231
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2320935061
Short name T1010
Test name
Test status
Simulation time 297852304 ps
CPU time 4.35 seconds
Started Jul 02 07:54:59 AM PDT 24
Finished Jul 02 07:55:09 AM PDT 24
Peak memory 224336 kb
Host smart-3a76f62e-5317-4cce-8a86-27bd33e0aeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320935061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2320935061
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.741949667
Short name T368
Test name
Test status
Simulation time 137143530 ps
CPU time 2 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:17 AM PDT 24
Peak memory 223564 kb
Host smart-1a59216e-b202-4875-9f91-6927a7df525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741949667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.741949667
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3642178518
Short name T210
Test name
Test status
Simulation time 11421914974 ps
CPU time 9.51 seconds
Started Jul 02 07:55:01 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 239564 kb
Host smart-42d851cc-3241-4c7e-bc21-ac3c303aa39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642178518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3642178518
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.642477948
Short name T794
Test name
Test status
Simulation time 1060787226 ps
CPU time 3.51 seconds
Started Jul 02 07:55:01 AM PDT 24
Finished Jul 02 07:55:13 AM PDT 24
Peak memory 232508 kb
Host smart-3960145f-f5b7-4467-b9eb-03ea7fd89c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642477948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.642477948
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3308834723
Short name T371
Test name
Test status
Simulation time 367076734 ps
CPU time 3.8 seconds
Started Jul 02 07:55:00 AM PDT 24
Finished Jul 02 07:55:10 AM PDT 24
Peak memory 220404 kb
Host smart-f545ddf8-d9f6-47ff-8ead-33ce3a2e91d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3308834723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3308834723
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2726008212
Short name T924
Test name
Test status
Simulation time 64750128228 ps
CPU time 506.19 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 08:03:44 AM PDT 24
Peak memory 269052 kb
Host smart-367be8d0-80c0-497d-841f-11fb885a9304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726008212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2726008212
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2329144435
Short name T696
Test name
Test status
Simulation time 28890201842 ps
CPU time 35.32 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:49 AM PDT 24
Peak memory 216312 kb
Host smart-a297f45f-ae39-4a51-b0d9-873c44cee161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329144435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2329144435
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.322308621
Short name T740
Test name
Test status
Simulation time 13802887 ps
CPU time 0.71 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 205588 kb
Host smart-326c9a40-8744-45ba-afc1-c01e4ff7bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322308621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.322308621
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2820411464
Short name T414
Test name
Test status
Simulation time 96222982 ps
CPU time 0.8 seconds
Started Jul 02 07:55:01 AM PDT 24
Finished Jul 02 07:55:08 AM PDT 24
Peak memory 205896 kb
Host smart-eb559dfe-8161-47ca-b36e-37dacdf248dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820411464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2820411464
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4234846894
Short name T393
Test name
Test status
Simulation time 264955130 ps
CPU time 0.89 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 206908 kb
Host smart-9edb76b9-e71b-4f82-89db-63c8088c91f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234846894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4234846894
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.4128744365
Short name T963
Test name
Test status
Simulation time 6022543796 ps
CPU time 12.72 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:26 AM PDT 24
Peak memory 239820 kb
Host smart-233ebbd6-36ce-4082-be92-7a768e8f82e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128744365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4128744365
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1596817154
Short name T651
Test name
Test status
Simulation time 45043702 ps
CPU time 0.7 seconds
Started Jul 02 07:55:22 AM PDT 24
Finished Jul 02 07:55:39 AM PDT 24
Peak memory 205480 kb
Host smart-a98e568e-2a0d-494c-99f2-ac6667ee0eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596817154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1596817154
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1900090401
Short name T998
Test name
Test status
Simulation time 81638127 ps
CPU time 2.91 seconds
Started Jul 02 07:55:35 AM PDT 24
Finished Jul 02 07:55:56 AM PDT 24
Peak memory 224404 kb
Host smart-bc5cffed-ca06-4a3b-ab74-93d44b2d317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900090401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1900090401
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1885013237
Short name T952
Test name
Test status
Simulation time 17450778 ps
CPU time 0.79 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 206484 kb
Host smart-4bd534eb-adcd-45dd-a6e1-dbd515ff6955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885013237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1885013237
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1625837465
Short name T283
Test name
Test status
Simulation time 90453031987 ps
CPU time 206.45 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:58:43 AM PDT 24
Peak memory 250832 kb
Host smart-515e6167-1f31-4407-a5cb-6903612b5820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625837465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1625837465
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1897330957
Short name T395
Test name
Test status
Simulation time 25924483284 ps
CPU time 65.03 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:56:49 AM PDT 24
Peak memory 248588 kb
Host smart-35c50b6a-bc12-409b-98da-f95439ea433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897330957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1897330957
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3965151316
Short name T461
Test name
Test status
Simulation time 116701053884 ps
CPU time 157.68 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:57:55 AM PDT 24
Peak memory 249116 kb
Host smart-0eb4e2ba-04dc-4803-8ed9-dbd3f8fe21ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965151316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3965151316
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.920410380
Short name T291
Test name
Test status
Simulation time 3033248259 ps
CPU time 9.19 seconds
Started Jul 02 07:55:23 AM PDT 24
Finished Jul 02 07:55:49 AM PDT 24
Peak memory 224424 kb
Host smart-bac27dfd-0fd1-4284-8218-ac76856adaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920410380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.920410380
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3927919278
Short name T972
Test name
Test status
Simulation time 26025093825 ps
CPU time 176.62 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:58:15 AM PDT 24
Peak memory 249144 kb
Host smart-6611e2bf-3c8f-4c9e-bc50-99fbaefdf492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927919278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3927919278
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2731564443
Short name T536
Test name
Test status
Simulation time 2284465663 ps
CPU time 6.54 seconds
Started Jul 02 07:55:09 AM PDT 24
Finished Jul 02 07:55:31 AM PDT 24
Peak memory 224376 kb
Host smart-7e9fd5ec-e70e-4e03-a0c2-95aa91d6e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731564443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2731564443
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4244140202
Short name T813
Test name
Test status
Simulation time 2380041732 ps
CPU time 26.23 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:47 AM PDT 24
Peak memory 250872 kb
Host smart-32592839-a310-487f-8d3d-62265ea257d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244140202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4244140202
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4205974527
Short name T1005
Test name
Test status
Simulation time 1722946300 ps
CPU time 4.48 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:17 AM PDT 24
Peak memory 232624 kb
Host smart-ae8a935f-a368-4b65-b843-7171cb9c01e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205974527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4205974527
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2181781965
Short name T619
Test name
Test status
Simulation time 763888934 ps
CPU time 7.06 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:21 AM PDT 24
Peak memory 234452 kb
Host smart-40e5ecf7-f0bb-4453-a842-88647f16ab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181781965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2181781965
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.845201975
Short name T408
Test name
Test status
Simulation time 388074507 ps
CPU time 5.72 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:23 AM PDT 24
Peak memory 220304 kb
Host smart-dac8c997-13ba-4f7e-8ff5-e91b897130b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=845201975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.845201975
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1312453370
Short name T509
Test name
Test status
Simulation time 10856968 ps
CPU time 0.71 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:17 AM PDT 24
Peak memory 205672 kb
Host smart-4f0bec93-e162-4d0c-a4de-228550319a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312453370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1312453370
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2535366264
Short name T789
Test name
Test status
Simulation time 40831310 ps
CPU time 0.69 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 205608 kb
Host smart-dec9dc7d-ab2d-423c-8d09-d70cf4b1aab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535366264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2535366264
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3962875504
Short name T426
Test name
Test status
Simulation time 17646477 ps
CPU time 1.08 seconds
Started Jul 02 07:55:10 AM PDT 24
Finished Jul 02 07:55:26 AM PDT 24
Peak memory 215972 kb
Host smart-ef6399e0-2675-44fc-93b9-0ac89983700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962875504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3962875504
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2245354073
Short name T436
Test name
Test status
Simulation time 11320767 ps
CPU time 0.68 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:22 AM PDT 24
Peak memory 205524 kb
Host smart-805dce49-cd84-4a59-add6-b5a33ba3abb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245354073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2245354073
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3888194315
Short name T349
Test name
Test status
Simulation time 59379258 ps
CPU time 2.03 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 224008 kb
Host smart-1f8ed4a3-647f-4982-b9be-c4ac5ff6db48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888194315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3888194315
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.115950911
Short name T345
Test name
Test status
Simulation time 74313099 ps
CPU time 0.75 seconds
Started Jul 02 07:53:39 AM PDT 24
Finished Jul 02 07:53:41 AM PDT 24
Peak memory 205472 kb
Host smart-291b725f-a535-47f8-882f-d791b0b080ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115950911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.115950911
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.88230365
Short name T848
Test name
Test status
Simulation time 674948747 ps
CPU time 5.49 seconds
Started Jul 02 07:53:49 AM PDT 24
Finished Jul 02 07:53:59 AM PDT 24
Peak memory 224384 kb
Host smart-7e3d8474-3948-4e4a-9a94-2e3d58584c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88230365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.88230365
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1230600370
Short name T966
Test name
Test status
Simulation time 104597075 ps
CPU time 0.83 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:54:06 AM PDT 24
Peak memory 206820 kb
Host smart-cfe89a14-734a-4825-a3c0-9e6116618c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230600370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1230600370
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2935258762
Short name T268
Test name
Test status
Simulation time 4485689174 ps
CPU time 24.85 seconds
Started Jul 02 07:53:39 AM PDT 24
Finished Jul 02 07:54:05 AM PDT 24
Peak memory 235656 kb
Host smart-6728fd62-c4d3-4116-be6d-2a1536bb6e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935258762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2935258762
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1156193141
Short name T253
Test name
Test status
Simulation time 35805489731 ps
CPU time 281.23 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:58:39 AM PDT 24
Peak memory 264944 kb
Host smart-039c4e41-7f0a-4db3-88f3-8db833175346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156193141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1156193141
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4188446606
Short name T954
Test name
Test status
Simulation time 76468505373 ps
CPU time 180.23 seconds
Started Jul 02 07:53:45 AM PDT 24
Finished Jul 02 07:56:47 AM PDT 24
Peak memory 257372 kb
Host smart-4ca98e8c-c543-4ef2-a6ac-0535c9cdc67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188446606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.4188446606
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2818927934
Short name T219
Test name
Test status
Simulation time 1266883672 ps
CPU time 12.53 seconds
Started Jul 02 07:53:33 AM PDT 24
Finished Jul 02 07:53:47 AM PDT 24
Peak memory 249000 kb
Host smart-a65c011e-7e68-4d77-b656-87c4509d7e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818927934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2818927934
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1537713198
Short name T230
Test name
Test status
Simulation time 5347968859 ps
CPU time 28.9 seconds
Started Jul 02 07:53:52 AM PDT 24
Finished Jul 02 07:54:26 AM PDT 24
Peak memory 228956 kb
Host smart-4b87dd15-f3a7-41ad-924e-e6cfd5ba9ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537713198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1537713198
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4089815317
Short name T204
Test name
Test status
Simulation time 4679476057 ps
CPU time 35.76 seconds
Started Jul 02 07:53:53 AM PDT 24
Finished Jul 02 07:54:34 AM PDT 24
Peak memory 224416 kb
Host smart-2029375b-c504-4461-b6bb-eb5226aad498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089815317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4089815317
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4135888646
Short name T563
Test name
Test status
Simulation time 143473825 ps
CPU time 2.12 seconds
Started Jul 02 07:53:35 AM PDT 24
Finished Jul 02 07:53:39 AM PDT 24
Peak memory 224316 kb
Host smart-5d4fefdd-2b2e-4eef-aa60-04abdd330414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135888646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4135888646
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4071088496
Short name T322
Test name
Test status
Simulation time 93263345 ps
CPU time 2.06 seconds
Started Jul 02 07:53:45 AM PDT 24
Finished Jul 02 07:53:49 AM PDT 24
Peak memory 223384 kb
Host smart-c7849b18-3ce9-4332-b661-46732aab24f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071088496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4071088496
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2622606478
Short name T726
Test name
Test status
Simulation time 163448903 ps
CPU time 3.64 seconds
Started Jul 02 07:53:40 AM PDT 24
Finished Jul 02 07:53:44 AM PDT 24
Peak memory 218764 kb
Host smart-65f9340a-89fd-4ad3-b8ec-5c0f6ecf93ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2622606478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2622606478
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2115886374
Short name T69
Test name
Test status
Simulation time 155229243 ps
CPU time 1.16 seconds
Started Jul 02 07:53:41 AM PDT 24
Finished Jul 02 07:53:43 AM PDT 24
Peak memory 236416 kb
Host smart-0ba0a278-0fb3-4c9c-9c51-012ead71e33d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115886374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2115886374
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3372201489
Short name T564
Test name
Test status
Simulation time 3351465981 ps
CPU time 25.32 seconds
Started Jul 02 07:53:39 AM PDT 24
Finished Jul 02 07:54:06 AM PDT 24
Peak memory 216252 kb
Host smart-855e685f-0961-4011-87a6-0b0526a9d126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372201489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3372201489
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3633165279
Short name T365
Test name
Test status
Simulation time 5134041631 ps
CPU time 4.2 seconds
Started Jul 02 07:53:46 AM PDT 24
Finished Jul 02 07:53:51 AM PDT 24
Peak memory 216324 kb
Host smart-a3f2652d-f42f-46b4-b1c6-7456f92e4ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633165279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3633165279
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4107958263
Short name T876
Test name
Test status
Simulation time 66893476 ps
CPU time 1.14 seconds
Started Jul 02 07:53:37 AM PDT 24
Finished Jul 02 07:53:40 AM PDT 24
Peak memory 207820 kb
Host smart-d50f769b-83c9-4a98-911d-a0c5955546ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107958263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4107958263
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.892977628
Short name T374
Test name
Test status
Simulation time 74525093 ps
CPU time 0.88 seconds
Started Jul 02 07:53:41 AM PDT 24
Finished Jul 02 07:53:43 AM PDT 24
Peak memory 205904 kb
Host smart-60144988-56bb-4a03-b293-e2bcd7471029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892977628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.892977628
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.36791753
Short name T606
Test name
Test status
Simulation time 32366555169 ps
CPU time 26.44 seconds
Started Jul 02 07:53:41 AM PDT 24
Finished Jul 02 07:54:13 AM PDT 24
Peak memory 232604 kb
Host smart-00ef3555-febe-4872-952d-91317d783605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36791753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.36791753
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1387698717
Short name T10
Test name
Test status
Simulation time 41034723 ps
CPU time 0.71 seconds
Started Jul 02 07:55:11 AM PDT 24
Finished Jul 02 07:55:27 AM PDT 24
Peak memory 204920 kb
Host smart-01b43415-ab3a-4c06-be99-d0faa1e5106c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387698717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1387698717
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4029208489
Short name T328
Test name
Test status
Simulation time 482952249 ps
CPU time 2.3 seconds
Started Jul 02 07:55:03 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 224388 kb
Host smart-f389d996-c05d-4283-b0af-050884859404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029208489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4029208489
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3871509901
Short name T398
Test name
Test status
Simulation time 13042762 ps
CPU time 0.7 seconds
Started Jul 02 07:55:09 AM PDT 24
Finished Jul 02 07:55:25 AM PDT 24
Peak memory 205524 kb
Host smart-4a15958f-ae99-4437-b1fa-843d60817495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871509901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3871509901
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2258860021
Short name T212
Test name
Test status
Simulation time 4516816112 ps
CPU time 61.01 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:56:18 AM PDT 24
Peak memory 249680 kb
Host smart-1e928965-a794-43dd-8f9e-880061cb40e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258860021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2258860021
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1866205281
Short name T295
Test name
Test status
Simulation time 10266937743 ps
CPU time 30.44 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:50 AM PDT 24
Peak memory 240920 kb
Host smart-194f5fae-3815-42e5-a3c8-9433161bde36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866205281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1866205281
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1656347118
Short name T717
Test name
Test status
Simulation time 122358273575 ps
CPU time 172.19 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:58:13 AM PDT 24
Peak memory 263080 kb
Host smart-96046f77-48da-46b6-97b2-7a2452e990b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656347118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1656347118
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3226840680
Short name T332
Test name
Test status
Simulation time 678267036 ps
CPU time 4.38 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 234624 kb
Host smart-73776626-0e96-42a9-ba92-15f29dd9caa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226840680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3226840680
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.194383847
Short name T274
Test name
Test status
Simulation time 68671969783 ps
CPU time 243.96 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:59:23 AM PDT 24
Peak memory 252320 kb
Host smart-c0f0b13a-4d85-428c-92a0-0dccb48c93a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194383847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.194383847
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4195991625
Short name T734
Test name
Test status
Simulation time 2085441629 ps
CPU time 10.61 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:26 AM PDT 24
Peak memory 224300 kb
Host smart-fb80cfc6-4501-466e-aff4-f31739f31781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195991625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4195991625
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3551314853
Short name T807
Test name
Test status
Simulation time 3516720212 ps
CPU time 30.7 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:50 AM PDT 24
Peak memory 235996 kb
Host smart-49d88af0-b5e4-462e-b4d1-6053451e0349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551314853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3551314853
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3119158564
Short name T46
Test name
Test status
Simulation time 7856250666 ps
CPU time 12.66 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:33 AM PDT 24
Peak memory 239824 kb
Host smart-f9197b26-c3e3-4838-8eec-23d2ebacf434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119158564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3119158564
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3422890192
Short name T534
Test name
Test status
Simulation time 2973278382 ps
CPU time 8.34 seconds
Started Jul 02 07:55:23 AM PDT 24
Finished Jul 02 07:55:48 AM PDT 24
Peak memory 224468 kb
Host smart-35c9792c-7c6d-4b2c-94f9-eb4b8759dea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422890192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3422890192
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2893574018
Short name T868
Test name
Test status
Simulation time 1535907427 ps
CPU time 15.21 seconds
Started Jul 02 07:55:21 AM PDT 24
Finished Jul 02 07:55:52 AM PDT 24
Peak memory 222028 kb
Host smart-5b66cd57-7cd2-46fa-8000-50f63b5d55fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2893574018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2893574018
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2394462092
Short name T908
Test name
Test status
Simulation time 40716293230 ps
CPU time 96.51 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:56:53 AM PDT 24
Peak memory 240300 kb
Host smart-dd361456-3dc4-4599-b33f-df810ab4c8de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394462092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2394462092
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.4229720547
Short name T427
Test name
Test status
Simulation time 3162108831 ps
CPU time 15.68 seconds
Started Jul 02 07:55:09 AM PDT 24
Finished Jul 02 07:55:40 AM PDT 24
Peak memory 220040 kb
Host smart-1b6deeab-a409-4715-bf60-75dfccca85fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229720547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.4229720547
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.406222193
Short name T306
Test name
Test status
Simulation time 652651825 ps
CPU time 4.98 seconds
Started Jul 02 07:55:12 AM PDT 24
Finished Jul 02 07:55:32 AM PDT 24
Peak memory 216124 kb
Host smart-8992ede8-f497-432f-b6d2-c723a8c2a997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406222193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.406222193
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3281756048
Short name T405
Test name
Test status
Simulation time 318691618 ps
CPU time 2 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 216132 kb
Host smart-17d8a0a7-229c-4044-9c1f-031d19052f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281756048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3281756048
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.579670759
Short name T669
Test name
Test status
Simulation time 49895724 ps
CPU time 0.87 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:18 AM PDT 24
Peak memory 205924 kb
Host smart-a76c8ba0-141d-487d-bdd4-bfd9de8f444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579670759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.579670759
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.36246798
Short name T44
Test name
Test status
Simulation time 225777842 ps
CPU time 4.66 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 224360 kb
Host smart-58ca3006-e1e5-45e5-8678-a458be4c0243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36246798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.36246798
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2742666607
Short name T684
Test name
Test status
Simulation time 20171277 ps
CPU time 0.74 seconds
Started Jul 02 07:55:19 AM PDT 24
Finished Jul 02 07:55:36 AM PDT 24
Peak memory 205776 kb
Host smart-f36a516e-b652-4cb5-b733-3bc763ab0ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742666607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2742666607
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3367401220
Short name T489
Test name
Test status
Simulation time 629214973 ps
CPU time 2.89 seconds
Started Jul 02 07:55:04 AM PDT 24
Finished Jul 02 07:55:18 AM PDT 24
Peak memory 224328 kb
Host smart-29a65a2d-63ca-4d5e-9f89-59bf735ddf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367401220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3367401220
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.140223833
Short name T336
Test name
Test status
Simulation time 16739057 ps
CPU time 0.78 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 206492 kb
Host smart-b1161bfe-830a-4358-a8d6-0da62ab16b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140223833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.140223833
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1407243654
Short name T640
Test name
Test status
Simulation time 25294942600 ps
CPU time 202.89 seconds
Started Jul 02 07:55:31 AM PDT 24
Finished Jul 02 07:59:11 AM PDT 24
Peak memory 251432 kb
Host smart-676c74a8-1c53-4727-a3c4-33c1bad1202f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407243654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1407243654
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2587845452
Short name T196
Test name
Test status
Simulation time 4503195143 ps
CPU time 53.61 seconds
Started Jul 02 07:55:12 AM PDT 24
Finished Jul 02 07:56:22 AM PDT 24
Peak memory 253032 kb
Host smart-a2765a71-a5b7-424a-870b-4dc3c7dc9f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587845452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2587845452
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.346647938
Short name T51
Test name
Test status
Simulation time 10989309022 ps
CPU time 164.16 seconds
Started Jul 02 07:55:07 AM PDT 24
Finished Jul 02 07:58:05 AM PDT 24
Peak memory 265492 kb
Host smart-2e486983-2f35-4afa-b393-5593c6d373f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346647938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.346647938
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2425743096
Short name T517
Test name
Test status
Simulation time 3286686738 ps
CPU time 6.5 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:26 AM PDT 24
Peak memory 224512 kb
Host smart-89b67050-12ba-49db-9dd4-404d077cc8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425743096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2425743096
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.891163061
Short name T224
Test name
Test status
Simulation time 159636700 ps
CPU time 3.27 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:23 AM PDT 24
Peak memory 224360 kb
Host smart-52951b76-ba3d-4d68-b875-b168b3a49d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891163061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.891163061
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3751532207
Short name T97
Test name
Test status
Simulation time 40975442397 ps
CPU time 77.58 seconds
Started Jul 02 07:55:08 AM PDT 24
Finished Jul 02 07:56:40 AM PDT 24
Peak memory 233912 kb
Host smart-6e5cc765-7974-412e-a7ed-2638c5263223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751532207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3751532207
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1841078512
Short name T324
Test name
Test status
Simulation time 28985532 ps
CPU time 1.98 seconds
Started Jul 02 07:55:21 AM PDT 24
Finished Jul 02 07:55:39 AM PDT 24
Peak memory 224028 kb
Host smart-dd5f0097-c923-49b4-a816-ebd2ac3bbf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841078512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1841078512
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.661623309
Short name T223
Test name
Test status
Simulation time 114892123 ps
CPU time 3.46 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:23 AM PDT 24
Peak memory 232484 kb
Host smart-c4342fc0-5a12-45b2-a8fd-87e8342b50d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661623309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.661623309
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.312817632
Short name T503
Test name
Test status
Simulation time 1488010916 ps
CPU time 6.37 seconds
Started Jul 02 07:55:34 AM PDT 24
Finished Jul 02 07:55:58 AM PDT 24
Peak memory 221916 kb
Host smart-315e76bd-4581-4706-8067-93b2604b4cf9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=312817632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.312817632
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2631720141
Short name T844
Test name
Test status
Simulation time 171486260 ps
CPU time 0.81 seconds
Started Jul 02 07:55:10 AM PDT 24
Finished Jul 02 07:55:25 AM PDT 24
Peak memory 205728 kb
Host smart-df01cb9d-7351-4607-a902-ba33186b9809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631720141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2631720141
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.935849279
Short name T831
Test name
Test status
Simulation time 1479684801 ps
CPU time 3.41 seconds
Started Jul 02 07:55:02 AM PDT 24
Finished Jul 02 07:55:14 AM PDT 24
Peak memory 216264 kb
Host smart-948b8df0-826b-489c-82cb-8604e2f86ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935849279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.935849279
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.524179874
Short name T715
Test name
Test status
Simulation time 9185860620 ps
CPU time 24.39 seconds
Started Jul 02 07:55:07 AM PDT 24
Finished Jul 02 07:55:45 AM PDT 24
Peak memory 216236 kb
Host smart-4a90687d-0604-451e-9921-624cfbb1f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524179874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.524179874
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.727682749
Short name T369
Test name
Test status
Simulation time 267891006 ps
CPU time 8.77 seconds
Started Jul 02 07:55:07 AM PDT 24
Finished Jul 02 07:55:30 AM PDT 24
Peak memory 216236 kb
Host smart-2b5b3d7f-ec62-4a6e-8236-20078b43eac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727682749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.727682749
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3174866184
Short name T775
Test name
Test status
Simulation time 11060073 ps
CPU time 0.69 seconds
Started Jul 02 07:55:16 AM PDT 24
Finished Jul 02 07:55:33 AM PDT 24
Peak memory 205480 kb
Host smart-9627ef26-e392-4fb2-8d23-b72a3b311960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174866184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3174866184
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.721491317
Short name T468
Test name
Test status
Simulation time 3790884014 ps
CPU time 16.33 seconds
Started Jul 02 07:55:10 AM PDT 24
Finished Jul 02 07:55:41 AM PDT 24
Peak memory 240076 kb
Host smart-cbb9a591-614e-48ed-8193-9df6ae21b3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721491317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.721491317
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.160526992
Short name T375
Test name
Test status
Simulation time 16749912 ps
CPU time 0.69 seconds
Started Jul 02 07:55:11 AM PDT 24
Finished Jul 02 07:55:27 AM PDT 24
Peak memory 205748 kb
Host smart-06f87999-6bfc-4bec-8d65-f658313d5440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160526992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.160526992
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3295056513
Short name T708
Test name
Test status
Simulation time 252210083 ps
CPU time 2.91 seconds
Started Jul 02 07:55:21 AM PDT 24
Finished Jul 02 07:55:39 AM PDT 24
Peak memory 232584 kb
Host smart-bfce72b6-53ff-4fc3-9c38-a0449cbeb0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295056513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3295056513
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2505664485
Short name T376
Test name
Test status
Simulation time 25626644 ps
CPU time 0.76 seconds
Started Jul 02 07:55:08 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 206452 kb
Host smart-26dc5f03-4ec6-4d80-9950-95272a09d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505664485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2505664485
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3132437257
Short name T218
Test name
Test status
Simulation time 188017405434 ps
CPU time 335.05 seconds
Started Jul 02 07:55:29 AM PDT 24
Finished Jul 02 08:01:21 AM PDT 24
Peak memory 249400 kb
Host smart-d7586770-d1a8-4449-b4d9-57e64a27cb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132437257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3132437257
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2305889855
Short name T800
Test name
Test status
Simulation time 1898915040 ps
CPU time 42.04 seconds
Started Jul 02 07:55:07 AM PDT 24
Finished Jul 02 07:56:04 AM PDT 24
Peak memory 249160 kb
Host smart-d75a24f9-7e7a-4d3b-9cb6-87185761328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305889855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2305889855
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3435624659
Short name T725
Test name
Test status
Simulation time 125231037287 ps
CPU time 283.24 seconds
Started Jul 02 07:55:20 AM PDT 24
Finished Jul 02 08:00:19 AM PDT 24
Peak memory 249148 kb
Host smart-2f3b6c89-c094-4382-bd65-315e89a355b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435624659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3435624659
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2518574371
Short name T288
Test name
Test status
Simulation time 2965023237 ps
CPU time 18 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:36 AM PDT 24
Peak memory 232776 kb
Host smart-e5ce3150-78f7-4435-b99f-71984bf2c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518574371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2518574371
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3336753958
Short name T649
Test name
Test status
Simulation time 94794821894 ps
CPU time 162.23 seconds
Started Jul 02 07:55:08 AM PDT 24
Finished Jul 02 07:58:05 AM PDT 24
Peak memory 238052 kb
Host smart-4d30123c-4e52-45e8-b072-99d1a3c91bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336753958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3336753958
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1300887945
Short name T394
Test name
Test status
Simulation time 3516918778 ps
CPU time 8.01 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:55:53 AM PDT 24
Peak memory 218788 kb
Host smart-2768922c-7a4e-42ed-ace0-630273c4b511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300887945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1300887945
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.459369247
Short name T693
Test name
Test status
Simulation time 2061959312 ps
CPU time 12.25 seconds
Started Jul 02 07:55:30 AM PDT 24
Finished Jul 02 07:56:00 AM PDT 24
Peak memory 224368 kb
Host smart-414ec28d-aa7c-46e7-abbe-03b6e1685025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459369247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.459369247
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.787304805
Short name T965
Test name
Test status
Simulation time 49034442 ps
CPU time 2.67 seconds
Started Jul 02 07:55:09 AM PDT 24
Finished Jul 02 07:55:26 AM PDT 24
Peak memory 232484 kb
Host smart-e8f436ff-8050-4a32-afb8-5ffc0ef346d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787304805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.787304805
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.718862885
Short name T779
Test name
Test status
Simulation time 8897587720 ps
CPU time 9.71 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:31 AM PDT 24
Peak memory 241128 kb
Host smart-46a30ce7-174b-41f0-b26c-916d1b911532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718862885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.718862885
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1010968318
Short name T582
Test name
Test status
Simulation time 5617895594 ps
CPU time 13.26 seconds
Started Jul 02 07:55:29 AM PDT 24
Finished Jul 02 07:55:59 AM PDT 24
Peak memory 222752 kb
Host smart-a674a1b9-c49b-4258-b299-20bcd4806954
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1010968318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1010968318
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.533022861
Short name T265
Test name
Test status
Simulation time 93604890945 ps
CPU time 735.06 seconds
Started Jul 02 07:55:24 AM PDT 24
Finished Jul 02 08:07:55 AM PDT 24
Peak memory 288156 kb
Host smart-4f53484d-6bc1-4b10-b011-5210543563e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533022861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.533022861
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3967043204
Short name T73
Test name
Test status
Simulation time 7096778485 ps
CPU time 12.63 seconds
Started Jul 02 07:55:22 AM PDT 24
Finished Jul 02 07:55:51 AM PDT 24
Peak memory 216288 kb
Host smart-07bf1bfe-efc4-42d3-92c5-66dc303f035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967043204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3967043204
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2659435341
Short name T553
Test name
Test status
Simulation time 11526757094 ps
CPU time 6.85 seconds
Started Jul 02 07:55:11 AM PDT 24
Finished Jul 02 07:55:33 AM PDT 24
Peak memory 216120 kb
Host smart-148cf8be-eb7f-498c-9c9a-e493e5d7b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659435341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2659435341
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3771209505
Short name T4
Test name
Test status
Simulation time 25566484 ps
CPU time 0.9 seconds
Started Jul 02 07:55:09 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 206916 kb
Host smart-ac70e41b-dcbb-4601-b7b0-f2789bc13842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771209505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3771209505
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3361957333
Short name T736
Test name
Test status
Simulation time 251903436 ps
CPU time 1.04 seconds
Started Jul 02 07:55:10 AM PDT 24
Finished Jul 02 07:55:26 AM PDT 24
Peak memory 206944 kb
Host smart-60efbf67-1796-4687-b6e9-3c888fead705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361957333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3361957333
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.723278026
Short name T8
Test name
Test status
Simulation time 1067257070 ps
CPU time 5.59 seconds
Started Jul 02 07:55:06 AM PDT 24
Finished Jul 02 07:55:27 AM PDT 24
Peak memory 224096 kb
Host smart-cf724200-bdf7-41fc-baf3-277a395ca9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723278026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.723278026
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1881601433
Short name T567
Test name
Test status
Simulation time 18084800 ps
CPU time 0.73 seconds
Started Jul 02 07:55:12 AM PDT 24
Finished Jul 02 07:55:29 AM PDT 24
Peak memory 205128 kb
Host smart-30649612-9cb3-44c6-84f3-3fb43575e359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881601433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1881601433
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.553778035
Short name T872
Test name
Test status
Simulation time 890226079 ps
CPU time 6.51 seconds
Started Jul 02 07:55:18 AM PDT 24
Finished Jul 02 07:55:41 AM PDT 24
Peak memory 224344 kb
Host smart-7baddc85-9df8-445e-b3af-6bffd6cd2dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553778035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.553778035
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3933675603
Short name T353
Test name
Test status
Simulation time 19289277 ps
CPU time 0.79 seconds
Started Jul 02 07:55:08 AM PDT 24
Finished Jul 02 07:55:23 AM PDT 24
Peak memory 206804 kb
Host smart-3ce6856d-a8a1-44ee-bab9-14c099878e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933675603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3933675603
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.897386273
Short name T791
Test name
Test status
Simulation time 30040963583 ps
CPU time 205.31 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:59:10 AM PDT 24
Peak memory 260492 kb
Host smart-621a51c7-5582-474f-9f7d-297b99aadc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897386273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.897386273
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4006863533
Short name T549
Test name
Test status
Simulation time 65615708308 ps
CPU time 579.53 seconds
Started Jul 02 07:55:26 AM PDT 24
Finished Jul 02 08:05:22 AM PDT 24
Peak memory 266680 kb
Host smart-554eaacf-534d-45b0-a137-059f3cbb72b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006863533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4006863533
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1098572718
Short name T704
Test name
Test status
Simulation time 1472446322 ps
CPU time 7.99 seconds
Started Jul 02 07:55:25 AM PDT 24
Finished Jul 02 07:55:49 AM PDT 24
Peak memory 239024 kb
Host smart-21e13bd9-d016-49e1-8599-d5580a876572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098572718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1098572718
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.255576752
Short name T826
Test name
Test status
Simulation time 25236104393 ps
CPU time 202.42 seconds
Started Jul 02 07:55:11 AM PDT 24
Finished Jul 02 07:58:48 AM PDT 24
Peak memory 257280 kb
Host smart-80e42915-6a0f-431b-8f71-aa23283d4454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255576752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.255576752
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2056971536
Short name T523
Test name
Test status
Simulation time 858367003 ps
CPU time 5.77 seconds
Started Jul 02 07:55:28 AM PDT 24
Finished Jul 02 07:55:51 AM PDT 24
Peak memory 232536 kb
Host smart-078cea8c-9955-406f-858d-6ba7d189110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056971536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2056971536
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.649640416
Short name T895
Test name
Test status
Simulation time 42856172329 ps
CPU time 27.17 seconds
Started Jul 02 07:55:22 AM PDT 24
Finished Jul 02 07:56:05 AM PDT 24
Peak memory 224468 kb
Host smart-1bb4a9b4-8c51-4abf-8b92-2e69d6fc143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649640416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.649640416
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.254437207
Short name T628
Test name
Test status
Simulation time 701731301 ps
CPU time 3.31 seconds
Started Jul 02 07:55:22 AM PDT 24
Finished Jul 02 07:55:42 AM PDT 24
Peak memory 224344 kb
Host smart-a3135c5d-cb36-4522-8c02-5a94604fbc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254437207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.254437207
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.151649947
Short name T24
Test name
Test status
Simulation time 58932216 ps
CPU time 2.31 seconds
Started Jul 02 07:55:09 AM PDT 24
Finished Jul 02 07:55:27 AM PDT 24
Peak memory 232200 kb
Host smart-978c5ec1-8f34-4aba-ac4c-e148d8a31569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151649947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.151649947
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2519923847
Short name T346
Test name
Test status
Simulation time 282120650 ps
CPU time 4.27 seconds
Started Jul 02 07:55:19 AM PDT 24
Finished Jul 02 07:55:40 AM PDT 24
Peak memory 222616 kb
Host smart-f3cfb99c-edb6-480a-970f-627cdec49a22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2519923847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2519923847
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4088969622
Short name T409
Test name
Test status
Simulation time 102902281 ps
CPU time 1.08 seconds
Started Jul 02 07:55:17 AM PDT 24
Finished Jul 02 07:55:34 AM PDT 24
Peak memory 207096 kb
Host smart-c3e0c479-df06-407f-9992-181edc38ecf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088969622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4088969622
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.442709526
Short name T585
Test name
Test status
Simulation time 1217088451 ps
CPU time 3.21 seconds
Started Jul 02 07:55:07 AM PDT 24
Finished Jul 02 07:55:24 AM PDT 24
Peak memory 216100 kb
Host smart-4676c8c1-b8ea-4051-954c-c40826d0609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442709526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.442709526
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.491520728
Short name T478
Test name
Test status
Simulation time 2463175420 ps
CPU time 8.76 seconds
Started Jul 02 07:55:07 AM PDT 24
Finished Jul 02 07:55:30 AM PDT 24
Peak memory 216128 kb
Host smart-a7d431bb-88c1-457b-acf2-c72dba0b6ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491520728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.491520728
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4067805327
Short name T591
Test name
Test status
Simulation time 69061400 ps
CPU time 1.24 seconds
Started Jul 02 07:55:19 AM PDT 24
Finished Jul 02 07:55:37 AM PDT 24
Peak memory 216168 kb
Host smart-39c7e94b-dcf4-4a67-9464-641bd58fb2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067805327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4067805327
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.143892469
Short name T392
Test name
Test status
Simulation time 262278948 ps
CPU time 0.87 seconds
Started Jul 02 07:55:12 AM PDT 24
Finished Jul 02 07:55:29 AM PDT 24
Peak memory 206240 kb
Host smart-e2c87265-a2cb-4433-bb62-20c321e14909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143892469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.143892469
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1094473028
Short name T311
Test name
Test status
Simulation time 167266295 ps
CPU time 2.15 seconds
Started Jul 02 07:55:05 AM PDT 24
Finished Jul 02 07:55:19 AM PDT 24
Peak memory 224040 kb
Host smart-a03da795-3b6b-4d55-a739-bf190f632057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094473028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1094473028
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2921497805
Short name T999
Test name
Test status
Simulation time 14904897 ps
CPU time 0.76 seconds
Started Jul 02 07:55:20 AM PDT 24
Finished Jul 02 07:55:37 AM PDT 24
Peak memory 205800 kb
Host smart-ae5c65c8-36df-4188-b307-668c69d63b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921497805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2921497805
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2811943644
Short name T891
Test name
Test status
Simulation time 316670599 ps
CPU time 2.34 seconds
Started Jul 02 07:55:29 AM PDT 24
Finished Jul 02 07:55:49 AM PDT 24
Peak memory 224372 kb
Host smart-b77f9732-2a04-4e77-afc2-aa3e1ea05d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811943644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2811943644
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2930971816
Short name T513
Test name
Test status
Simulation time 13791647 ps
CPU time 0.73 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:55:45 AM PDT 24
Peak memory 205844 kb
Host smart-8f6ca7fc-f409-4889-b460-dcf5abdbeab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930971816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2930971816
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.392498178
Short name T1002
Test name
Test status
Simulation time 5955043777 ps
CPU time 45.63 seconds
Started Jul 02 07:55:24 AM PDT 24
Finished Jul 02 07:56:26 AM PDT 24
Peak memory 249724 kb
Host smart-af136075-df3f-4f4d-b49c-b24afa6ab605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392498178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.392498178
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3601704455
Short name T192
Test name
Test status
Simulation time 4982802665 ps
CPU time 35.14 seconds
Started Jul 02 07:55:21 AM PDT 24
Finished Jul 02 07:56:11 AM PDT 24
Peak memory 252032 kb
Host smart-b65f66f5-39e4-4456-9bdc-0bfa291cfa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601704455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3601704455
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.666242578
Short name T296
Test name
Test status
Simulation time 6880913437 ps
CPU time 41.62 seconds
Started Jul 02 07:55:23 AM PDT 24
Finished Jul 02 07:56:22 AM PDT 24
Peak memory 224596 kb
Host smart-0bafcddb-3b22-44fd-ac29-1db79f542420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666242578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.666242578
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2927274539
Short name T537
Test name
Test status
Simulation time 681866986 ps
CPU time 11.09 seconds
Started Jul 02 07:55:16 AM PDT 24
Finished Jul 02 07:55:43 AM PDT 24
Peak memory 240760 kb
Host smart-af3c89f9-6005-4f22-84c0-df831f91857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927274539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2927274539
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2672844338
Short name T742
Test name
Test status
Simulation time 4235357365 ps
CPU time 55.65 seconds
Started Jul 02 07:55:33 AM PDT 24
Finished Jul 02 07:56:46 AM PDT 24
Peak memory 240936 kb
Host smart-6eb64206-3b3d-4791-98f3-9eb5d773bf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672844338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2672844338
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1501069103
Short name T858
Test name
Test status
Simulation time 285717934 ps
CPU time 3.53 seconds
Started Jul 02 07:55:24 AM PDT 24
Finished Jul 02 07:55:44 AM PDT 24
Peak memory 232652 kb
Host smart-d054a220-0416-46bb-b1d0-0de7a74d996c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501069103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1501069103
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3357813269
Short name T207
Test name
Test status
Simulation time 1737084722 ps
CPU time 15.69 seconds
Started Jul 02 07:55:24 AM PDT 24
Finished Jul 02 07:55:57 AM PDT 24
Peak memory 251984 kb
Host smart-13ace44e-2041-4065-94d6-140ada39fe51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357813269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3357813269
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2530085942
Short name T309
Test name
Test status
Simulation time 152816069 ps
CPU time 2.29 seconds
Started Jul 02 07:55:11 AM PDT 24
Finished Jul 02 07:55:28 AM PDT 24
Peak memory 232196 kb
Host smart-ea75f471-9211-43c1-99fd-bd049a3732c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530085942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2530085942
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.826768500
Short name T987
Test name
Test status
Simulation time 30301388 ps
CPU time 2.15 seconds
Started Jul 02 07:55:31 AM PDT 24
Finished Jul 02 07:55:51 AM PDT 24
Peak memory 224040 kb
Host smart-08a34472-d281-46ab-b416-8346238428a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826768500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.826768500
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1581665209
Short name T145
Test name
Test status
Simulation time 3016538179 ps
CPU time 12.75 seconds
Started Jul 02 07:55:37 AM PDT 24
Finished Jul 02 07:56:08 AM PDT 24
Peak memory 218872 kb
Host smart-eff93f65-134c-4996-bf76-358f029d9920
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1581665209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1581665209
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2516604463
Short name T510
Test name
Test status
Simulation time 69566644 ps
CPU time 1.09 seconds
Started Jul 02 07:55:29 AM PDT 24
Finished Jul 02 07:55:48 AM PDT 24
Peak memory 207460 kb
Host smart-97a9cebe-eafa-42a7-925d-dc21bb5e56e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516604463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2516604463
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2812948734
Short name T944
Test name
Test status
Simulation time 2503384118 ps
CPU time 13.08 seconds
Started Jul 02 07:55:21 AM PDT 24
Finished Jul 02 07:55:50 AM PDT 24
Peak memory 216200 kb
Host smart-227f609e-ebc4-492e-b25f-51c85b95d0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812948734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2812948734
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3648358379
Short name T415
Test name
Test status
Simulation time 2555550559 ps
CPU time 8.09 seconds
Started Jul 02 07:55:29 AM PDT 24
Finished Jul 02 07:55:54 AM PDT 24
Peak memory 216252 kb
Host smart-d1766c01-764f-45cd-9627-36d76dc46001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648358379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3648358379
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2438180842
Short name T913
Test name
Test status
Simulation time 150942581 ps
CPU time 1.22 seconds
Started Jul 02 07:55:21 AM PDT 24
Finished Jul 02 07:55:38 AM PDT 24
Peak memory 216016 kb
Host smart-6d96ad83-ef4c-4d6c-8d5a-2fc82bb5cd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438180842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2438180842
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.822690466
Short name T417
Test name
Test status
Simulation time 20229102 ps
CPU time 0.75 seconds
Started Jul 02 07:55:25 AM PDT 24
Finished Jul 02 07:55:42 AM PDT 24
Peak memory 205872 kb
Host smart-ad6fdd40-0d6e-432c-98be-592bfe5ad745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822690466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.822690466
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.492910629
Short name T454
Test name
Test status
Simulation time 1683087333 ps
CPU time 11.13 seconds
Started Jul 02 07:55:28 AM PDT 24
Finished Jul 02 07:55:57 AM PDT 24
Peak memory 232644 kb
Host smart-09e18712-fe1c-4e47-8d5e-dae3beba15aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492910629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.492910629
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2568824962
Short name T323
Test name
Test status
Simulation time 23147901 ps
CPU time 0.71 seconds
Started Jul 02 07:55:32 AM PDT 24
Finished Jul 02 07:55:50 AM PDT 24
Peak memory 205468 kb
Host smart-4ab0e017-fd9a-47f5-aebb-edc05ae35c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568824962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2568824962
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3440754849
Short name T89
Test name
Test status
Simulation time 486390878 ps
CPU time 6.18 seconds
Started Jul 02 07:55:26 AM PDT 24
Finished Jul 02 07:55:49 AM PDT 24
Peak memory 224376 kb
Host smart-15fb8bb7-8235-4c11-9783-e66027c908e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440754849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3440754849
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2338214930
Short name T713
Test name
Test status
Simulation time 31642298 ps
CPU time 0.72 seconds
Started Jul 02 07:55:22 AM PDT 24
Finished Jul 02 07:55:39 AM PDT 24
Peak memory 205428 kb
Host smart-28d41d7f-24e5-4418-bf68-1e786ebeb04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338214930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2338214930
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2611954193
Short name T776
Test name
Test status
Simulation time 5725187492 ps
CPU time 14.07 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:55:58 AM PDT 24
Peak memory 219020 kb
Host smart-27509d78-395c-40b8-965c-9cc799f9f620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611954193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2611954193
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1174059694
Short name T88
Test name
Test status
Simulation time 11215520453 ps
CPU time 40.43 seconds
Started Jul 02 07:55:23 AM PDT 24
Finished Jul 02 07:56:21 AM PDT 24
Peak memory 240944 kb
Host smart-78407908-3f33-4493-ba60-6a5ab31f5e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174059694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1174059694
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.605602144
Short name T910
Test name
Test status
Simulation time 32501738101 ps
CPU time 299.94 seconds
Started Jul 02 07:55:11 AM PDT 24
Finished Jul 02 08:00:27 AM PDT 24
Peak memory 257328 kb
Host smart-3ca69143-4a26-4cbd-a952-79699f0e8e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605602144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.605602144
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4240046821
Short name T941
Test name
Test status
Simulation time 779344212 ps
CPU time 14.31 seconds
Started Jul 02 07:55:22 AM PDT 24
Finished Jul 02 07:55:53 AM PDT 24
Peak memory 248944 kb
Host smart-b58d75d7-0c17-4132-bcc5-aa39eb2d7366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240046821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4240046821
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3894031703
Short name T934
Test name
Test status
Simulation time 5614907361 ps
CPU time 59.75 seconds
Started Jul 02 07:55:25 AM PDT 24
Finished Jul 02 07:56:41 AM PDT 24
Peak memory 250128 kb
Host smart-bba1c297-7d9d-4501-8fad-b6d305363f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894031703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3894031703
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.450151563
Short name T439
Test name
Test status
Simulation time 150908563 ps
CPU time 2.99 seconds
Started Jul 02 07:55:22 AM PDT 24
Finished Jul 02 07:55:41 AM PDT 24
Peak memory 232596 kb
Host smart-903fb622-4cab-4dc8-bab8-ea7a7d7e508a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450151563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.450151563
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2349766548
Short name T1001
Test name
Test status
Simulation time 1449557976 ps
CPU time 20.69 seconds
Started Jul 02 07:55:19 AM PDT 24
Finished Jul 02 07:55:56 AM PDT 24
Peak memory 224340 kb
Host smart-0a60c60b-5248-45a3-8ddb-ba398209cf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349766548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2349766548
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.395767737
Short name T487
Test name
Test status
Simulation time 7475274395 ps
CPU time 11.29 seconds
Started Jul 02 07:55:23 AM PDT 24
Finished Jul 02 07:55:51 AM PDT 24
Peak memory 239216 kb
Host smart-8656eed5-1e41-4df4-855b-8b36b871d35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395767737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.395767737
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3744538394
Short name T657
Test name
Test status
Simulation time 221166255 ps
CPU time 2.25 seconds
Started Jul 02 07:55:13 AM PDT 24
Finished Jul 02 07:55:31 AM PDT 24
Peak memory 224436 kb
Host smart-3cfdd16d-0427-43e4-8746-a9ca930d8727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744538394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3744538394
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2840906135
Short name T745
Test name
Test status
Simulation time 445694852 ps
CPU time 4.5 seconds
Started Jul 02 07:55:31 AM PDT 24
Finished Jul 02 07:55:53 AM PDT 24
Peak memory 218648 kb
Host smart-c3b2e0d6-4cab-4ce9-946d-eea8e21dfa95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2840906135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2840906135
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.316356211
Short name T514
Test name
Test status
Simulation time 19966566 ps
CPU time 0.73 seconds
Started Jul 02 07:55:14 AM PDT 24
Finished Jul 02 07:55:30 AM PDT 24
Peak memory 205628 kb
Host smart-0bd75f50-8ff2-447f-be51-7326bbe5bdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316356211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.316356211
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.816292601
Short name T825
Test name
Test status
Simulation time 6274125854 ps
CPU time 12.98 seconds
Started Jul 02 07:55:19 AM PDT 24
Finished Jul 02 07:55:48 AM PDT 24
Peak memory 216288 kb
Host smart-bc6e2cc0-7bd1-41b0-a505-06ab7a66322f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816292601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.816292601
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.644484834
Short name T334
Test name
Test status
Simulation time 137617151 ps
CPU time 2.66 seconds
Started Jul 02 07:55:22 AM PDT 24
Finished Jul 02 07:55:41 AM PDT 24
Peak memory 216132 kb
Host smart-09b8e556-3f9d-436b-9550-ce43280a6852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644484834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.644484834
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1799483241
Short name T712
Test name
Test status
Simulation time 344498147 ps
CPU time 0.9 seconds
Started Jul 02 07:55:43 AM PDT 24
Finished Jul 02 07:56:04 AM PDT 24
Peak memory 205844 kb
Host smart-fed31eff-3dc2-4110-9339-ac4376761758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799483241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1799483241
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.4043783524
Short name T905
Test name
Test status
Simulation time 2797534267 ps
CPU time 9.43 seconds
Started Jul 02 07:55:15 AM PDT 24
Finished Jul 02 07:55:42 AM PDT 24
Peak memory 238452 kb
Host smart-d875883d-ab0e-44c6-90ef-2b26b9d7b0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043783524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4043783524
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.824112294
Short name T522
Test name
Test status
Simulation time 41385074 ps
CPU time 0.69 seconds
Started Jul 02 07:55:42 AM PDT 24
Finished Jul 02 07:56:03 AM PDT 24
Peak memory 204896 kb
Host smart-8d296c3d-611e-4f06-a7ae-0a3f43bf74fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824112294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.824112294
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3227426217
Short name T469
Test name
Test status
Simulation time 3890270407 ps
CPU time 33.25 seconds
Started Jul 02 07:55:28 AM PDT 24
Finished Jul 02 07:56:18 AM PDT 24
Peak memory 224408 kb
Host smart-68c26833-9976-46d2-84c3-bc90ca04ef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227426217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3227426217
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2029006831
Short name T546
Test name
Test status
Simulation time 31216166 ps
CPU time 0.79 seconds
Started Jul 02 07:55:18 AM PDT 24
Finished Jul 02 07:55:35 AM PDT 24
Peak memory 206852 kb
Host smart-5c0931d6-f2fc-460b-bec7-75cee4f84df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029006831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2029006831
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.928576712
Short name T738
Test name
Test status
Simulation time 4459929564 ps
CPU time 44.92 seconds
Started Jul 02 07:55:28 AM PDT 24
Finished Jul 02 07:56:30 AM PDT 24
Peak memory 250076 kb
Host smart-94e9a619-8f4b-4037-befc-eb51496f6caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928576712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.928576712
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.544064910
Short name T319
Test name
Test status
Simulation time 1022877810 ps
CPU time 9.09 seconds
Started Jul 02 07:55:30 AM PDT 24
Finished Jul 02 07:55:57 AM PDT 24
Peak memory 224376 kb
Host smart-6f506c92-03e9-48cc-971d-9cf787ea23a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544064910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.544064910
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1656199455
Short name T170
Test name
Test status
Simulation time 10395848880 ps
CPU time 71.04 seconds
Started Jul 02 07:55:26 AM PDT 24
Finished Jul 02 07:56:54 AM PDT 24
Peak memory 239180 kb
Host smart-1e433843-f821-487e-b690-336cbac8f952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656199455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1656199455
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3806763045
Short name T560
Test name
Test status
Simulation time 2574985903 ps
CPU time 17.43 seconds
Started Jul 02 07:55:35 AM PDT 24
Finished Jul 02 07:56:10 AM PDT 24
Peak memory 224504 kb
Host smart-bd823b7a-d684-4098-9462-e597ead9d4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806763045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3806763045
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1424538530
Short name T203
Test name
Test status
Simulation time 16290698743 ps
CPU time 31.91 seconds
Started Jul 02 07:55:28 AM PDT 24
Finished Jul 02 07:56:18 AM PDT 24
Peak memory 238924 kb
Host smart-f8e1b107-4323-4533-862c-f539fdec499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424538530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1424538530
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1951632636
Short name T929
Test name
Test status
Simulation time 3234689133 ps
CPU time 18.88 seconds
Started Jul 02 07:55:33 AM PDT 24
Finished Jul 02 07:56:10 AM PDT 24
Peak memory 251824 kb
Host smart-5ef0d206-b0c6-490f-aceb-9fdfae19c36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951632636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1951632636
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3121936555
Short name T256
Test name
Test status
Simulation time 3187419879 ps
CPU time 14.33 seconds
Started Jul 02 07:55:28 AM PDT 24
Finished Jul 02 07:56:00 AM PDT 24
Peak memory 224504 kb
Host smart-93c156a0-71ef-4854-a3cc-5e980f84f5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121936555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3121936555
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3758955594
Short name T732
Test name
Test status
Simulation time 5564361541 ps
CPU time 11.73 seconds
Started Jul 02 07:55:32 AM PDT 24
Finished Jul 02 07:56:00 AM PDT 24
Peak memory 219452 kb
Host smart-c0eb8227-4ec5-4613-afa7-175eb41fb822
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3758955594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3758955594
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.717519064
Short name T155
Test name
Test status
Simulation time 24269250513 ps
CPU time 188.22 seconds
Started Jul 02 07:55:34 AM PDT 24
Finished Jul 02 07:59:01 AM PDT 24
Peak memory 244716 kb
Host smart-9307d39e-9b54-4061-9a57-59d67d1a7f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717519064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.717519064
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2237322053
Short name T418
Test name
Test status
Simulation time 12585821 ps
CPU time 0.73 seconds
Started Jul 02 07:55:19 AM PDT 24
Finished Jul 02 07:55:36 AM PDT 24
Peak memory 205896 kb
Host smart-002e188e-4869-488b-8ce8-b5cd658d58e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237322053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2237322053
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.937653693
Short name T680
Test name
Test status
Simulation time 13771954219 ps
CPU time 15.62 seconds
Started Jul 02 07:55:13 AM PDT 24
Finished Jul 02 07:55:44 AM PDT 24
Peak memory 216252 kb
Host smart-c4d47bbd-8bdc-4f79-8c68-d395d838c194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937653693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.937653693
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2136670303
Short name T818
Test name
Test status
Simulation time 45274582 ps
CPU time 1.43 seconds
Started Jul 02 07:55:26 AM PDT 24
Finished Jul 02 07:55:44 AM PDT 24
Peak memory 216212 kb
Host smart-bc3d2fa6-7729-4819-97e2-111548493833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136670303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2136670303
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.371281267
Short name T382
Test name
Test status
Simulation time 229844835 ps
CPU time 1.04 seconds
Started Jul 02 07:55:31 AM PDT 24
Finished Jul 02 07:55:49 AM PDT 24
Peak memory 206856 kb
Host smart-17890cca-7a43-4455-8d11-0e67b150864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371281267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.371281267
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2333936330
Short name T215
Test name
Test status
Simulation time 7128928948 ps
CPU time 13.95 seconds
Started Jul 02 07:55:16 AM PDT 24
Finished Jul 02 07:55:46 AM PDT 24
Peak memory 232712 kb
Host smart-f239c701-1c16-4d54-8de5-4425068af03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333936330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2333936330
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.31434204
Short name T843
Test name
Test status
Simulation time 12538595 ps
CPU time 0.69 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:55:45 AM PDT 24
Peak memory 205500 kb
Host smart-c34684cb-417f-4491-b320-e78396547409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31434204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.31434204
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.920295720
Short name T677
Test name
Test status
Simulation time 702800554 ps
CPU time 5.72 seconds
Started Jul 02 07:55:24 AM PDT 24
Finished Jul 02 07:55:47 AM PDT 24
Peak memory 232520 kb
Host smart-7e8b57d6-88ba-4b44-89db-04decda16a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920295720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.920295720
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1143693675
Short name T764
Test name
Test status
Simulation time 22156476 ps
CPU time 0.8 seconds
Started Jul 02 07:55:19 AM PDT 24
Finished Jul 02 07:55:36 AM PDT 24
Peak memory 206536 kb
Host smart-9c86c2e1-cc61-4e73-adf7-b002049ccf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143693675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1143693675
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3152992941
Short name T988
Test name
Test status
Simulation time 5172440642 ps
CPU time 24.05 seconds
Started Jul 02 07:55:34 AM PDT 24
Finished Jul 02 07:56:16 AM PDT 24
Peak memory 239872 kb
Host smart-9391cb9c-f821-4728-bbd1-93c0e6efdf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152992941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3152992941
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1468474883
Short name T809
Test name
Test status
Simulation time 42414697932 ps
CPU time 152.38 seconds
Started Jul 02 07:55:16 AM PDT 24
Finished Jul 02 07:58:05 AM PDT 24
Peak memory 252652 kb
Host smart-19c30125-2d72-4f49-be56-b0cc3887c908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468474883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1468474883
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1920678777
Short name T474
Test name
Test status
Simulation time 498014963 ps
CPU time 7.32 seconds
Started Jul 02 07:55:23 AM PDT 24
Finished Jul 02 07:55:47 AM PDT 24
Peak memory 224456 kb
Host smart-068ee521-5258-45b1-a17f-aad9ceb1781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920678777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1920678777
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.251460880
Short name T273
Test name
Test status
Simulation time 70985089519 ps
CPU time 485.81 seconds
Started Jul 02 07:55:28 AM PDT 24
Finished Jul 02 08:03:52 AM PDT 24
Peak memory 263172 kb
Host smart-2c3dac01-18f9-4857-843c-00ed186f4bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251460880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.251460880
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3562131248
Short name T242
Test name
Test status
Simulation time 226945830 ps
CPU time 4.04 seconds
Started Jul 02 07:55:37 AM PDT 24
Finished Jul 02 07:56:00 AM PDT 24
Peak memory 224292 kb
Host smart-f03863ba-5d9c-440a-95a9-e7ed79292996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562131248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3562131248
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3237743926
Short name T783
Test name
Test status
Simulation time 28234798245 ps
CPU time 130.46 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:57:55 AM PDT 24
Peak memory 248516 kb
Host smart-0e4f1f13-6252-4517-b362-f65a0b03d212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237743926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3237743926
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3441421564
Short name T806
Test name
Test status
Simulation time 28084207596 ps
CPU time 13.9 seconds
Started Jul 02 07:55:25 AM PDT 24
Finished Jul 02 07:55:56 AM PDT 24
Peak memory 232716 kb
Host smart-5ca8eb5c-9683-4d6b-b9aa-c587e684e3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441421564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3441421564
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2186052021
Short name T462
Test name
Test status
Simulation time 6107494916 ps
CPU time 8.25 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:55:53 AM PDT 24
Peak memory 224412 kb
Host smart-6cffc151-f379-45bf-b921-69bce69dd044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186052021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2186052021
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1076510706
Short name T364
Test name
Test status
Simulation time 1908923415 ps
CPU time 9.14 seconds
Started Jul 02 07:55:39 AM PDT 24
Finished Jul 02 07:56:08 AM PDT 24
Peak memory 218640 kb
Host smart-3774ef54-8c14-44ab-b284-d07ef06a06bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1076510706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1076510706
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1175039614
Short name T17
Test name
Test status
Simulation time 34089117530 ps
CPU time 127.86 seconds
Started Jul 02 07:55:29 AM PDT 24
Finished Jul 02 07:57:55 AM PDT 24
Peak memory 251884 kb
Host smart-4e879b28-7fb0-4d64-9556-316cb6d446e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175039614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1175039614
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.540855252
Short name T528
Test name
Test status
Simulation time 21153920897 ps
CPU time 54.02 seconds
Started Jul 02 07:55:23 AM PDT 24
Finished Jul 02 07:56:34 AM PDT 24
Peak memory 216268 kb
Host smart-2a6662ba-1c9e-455c-a7f5-804c4643b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540855252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.540855252
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2747096897
Short name T815
Test name
Test status
Simulation time 5574961097 ps
CPU time 16.89 seconds
Started Jul 02 07:55:32 AM PDT 24
Finished Jul 02 07:56:06 AM PDT 24
Peak memory 216168 kb
Host smart-e1a7299b-6f64-4ca2-a43a-52a6039d21b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747096897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2747096897
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3236769453
Short name T714
Test name
Test status
Simulation time 293387173 ps
CPU time 1.82 seconds
Started Jul 02 07:55:35 AM PDT 24
Finished Jul 02 07:55:55 AM PDT 24
Peak memory 216120 kb
Host smart-89e7b3c1-e767-40fb-b8a2-e59473c725de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236769453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3236769453
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1606811444
Short name T749
Test name
Test status
Simulation time 87608974 ps
CPU time 0.88 seconds
Started Jul 02 07:55:23 AM PDT 24
Finished Jul 02 07:55:41 AM PDT 24
Peak memory 206892 kb
Host smart-f6aaa58f-87e6-42ed-a3ab-ed5eae65fe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606811444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1606811444
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2049432815
Short name T636
Test name
Test status
Simulation time 565588786 ps
CPU time 2.75 seconds
Started Jul 02 07:55:26 AM PDT 24
Finished Jul 02 07:55:45 AM PDT 24
Peak memory 224360 kb
Host smart-8f522629-b6e4-4181-bf90-86a60469805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049432815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2049432815
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2473654494
Short name T359
Test name
Test status
Simulation time 51680322 ps
CPU time 0.71 seconds
Started Jul 02 07:55:32 AM PDT 24
Finished Jul 02 07:55:50 AM PDT 24
Peak memory 205364 kb
Host smart-58c3187e-0857-4d46-aea0-1c457243ad91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473654494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2473654494
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3464103157
Short name T867
Test name
Test status
Simulation time 445953671 ps
CPU time 4.02 seconds
Started Jul 02 07:55:49 AM PDT 24
Finished Jul 02 07:56:16 AM PDT 24
Peak memory 224332 kb
Host smart-df5c45a9-c7fd-486d-b8e2-ea8b5c92f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464103157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3464103157
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2496743886
Short name T477
Test name
Test status
Simulation time 17797898 ps
CPU time 0.79 seconds
Started Jul 02 07:55:35 AM PDT 24
Finished Jul 02 07:55:54 AM PDT 24
Peak memory 206520 kb
Host smart-c0bfdaa5-1c05-4d7c-8305-7894d11be5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496743886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2496743886
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.813641430
Short name T757
Test name
Test status
Simulation time 20186802025 ps
CPU time 170.98 seconds
Started Jul 02 07:55:21 AM PDT 24
Finished Jul 02 07:58:28 AM PDT 24
Peak memory 256916 kb
Host smart-0633228e-835d-484c-9e78-74428de7ad10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813641430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.813641430
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3851139761
Short name T678
Test name
Test status
Simulation time 8213817111 ps
CPU time 126.59 seconds
Started Jul 02 07:55:33 AM PDT 24
Finished Jul 02 07:57:58 AM PDT 24
Peak memory 256128 kb
Host smart-d489e4c7-d2bc-4156-b6a4-b24595108c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851139761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3851139761
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3863328389
Short name T620
Test name
Test status
Simulation time 1463330078 ps
CPU time 39.37 seconds
Started Jul 02 07:55:34 AM PDT 24
Finished Jul 02 07:56:31 AM PDT 24
Peak memory 249004 kb
Host smart-73ac1fd4-2fef-4d26-b9fb-ec8a51823917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863328389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3863328389
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.371004982
Short name T691
Test name
Test status
Simulation time 201421453 ps
CPU time 4.06 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:55:48 AM PDT 24
Peak memory 224440 kb
Host smart-31199c9b-82b7-4919-8898-56abaf191edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371004982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.371004982
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1325786382
Short name T927
Test name
Test status
Simulation time 2209190127 ps
CPU time 7.95 seconds
Started Jul 02 07:55:22 AM PDT 24
Finished Jul 02 07:55:46 AM PDT 24
Peak memory 232616 kb
Host smart-2e6757dd-d6db-42b9-b522-c45e176974c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325786382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1325786382
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1368286710
Short name T885
Test name
Test status
Simulation time 417906185 ps
CPU time 4.72 seconds
Started Jul 02 07:55:28 AM PDT 24
Finished Jul 02 07:55:49 AM PDT 24
Peak memory 224336 kb
Host smart-8daf2ef4-9f11-4e90-87cf-5c281142de84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368286710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1368286710
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1475961231
Short name T231
Test name
Test status
Simulation time 2731618417 ps
CPU time 3.68 seconds
Started Jul 02 07:55:21 AM PDT 24
Finished Jul 02 07:55:40 AM PDT 24
Peak memory 224508 kb
Host smart-07b86d63-588c-4ddf-a124-39157952ddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475961231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1475961231
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3564677367
Short name T384
Test name
Test status
Simulation time 1687072817 ps
CPU time 7.72 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:55:52 AM PDT 24
Peak memory 222020 kb
Host smart-875a5d6d-16bb-4087-8b56-9c594fce8a07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3564677367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3564677367
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3216367954
Short name T14
Test name
Test status
Simulation time 8885816036 ps
CPU time 90.3 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:57:14 AM PDT 24
Peak memory 253444 kb
Host smart-e299a1f7-12c2-4d9d-af65-ab37c351805b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216367954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3216367954
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3871280627
Short name T299
Test name
Test status
Simulation time 6360946769 ps
CPU time 12.29 seconds
Started Jul 02 07:55:25 AM PDT 24
Finished Jul 02 07:55:54 AM PDT 24
Peak memory 216208 kb
Host smart-38810e31-9f1d-493e-8bfe-401a6e4aa150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871280627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3871280627
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.68935169
Short name T348
Test name
Test status
Simulation time 17232116638 ps
CPU time 17.61 seconds
Started Jul 02 07:55:36 AM PDT 24
Finished Jul 02 07:56:11 AM PDT 24
Peak memory 216248 kb
Host smart-045e5215-e583-45c7-a61a-1a0bdf841b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68935169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.68935169
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3735464419
Short name T846
Test name
Test status
Simulation time 36261516 ps
CPU time 0.68 seconds
Started Jul 02 07:55:34 AM PDT 24
Finished Jul 02 07:55:53 AM PDT 24
Peak memory 205564 kb
Host smart-16ce12d7-1a15-4f2f-874c-f32004c75265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735464419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3735464419
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.822332440
Short name T341
Test name
Test status
Simulation time 164453309 ps
CPU time 0.85 seconds
Started Jul 02 07:55:27 AM PDT 24
Finished Jul 02 07:55:45 AM PDT 24
Peak memory 205900 kb
Host smart-935182d0-d4a6-4650-84e4-d435a696e62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822332440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.822332440
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3993996813
Short name T701
Test name
Test status
Simulation time 70246523 ps
CPU time 2.27 seconds
Started Jul 02 07:55:30 AM PDT 24
Finished Jul 02 07:55:49 AM PDT 24
Peak memory 224008 kb
Host smart-38b9bdbf-3a77-48c8-b706-c7a95e3b2a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993996813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3993996813
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3762514654
Short name T984
Test name
Test status
Simulation time 13538307 ps
CPU time 0.7 seconds
Started Jul 02 07:55:35 AM PDT 24
Finished Jul 02 07:55:53 AM PDT 24
Peak memory 204812 kb
Host smart-15f9ad60-793d-4771-bae1-b946fda08ff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762514654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3762514654
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.878909528
Short name T172
Test name
Test status
Simulation time 42660151 ps
CPU time 2.53 seconds
Started Jul 02 07:55:24 AM PDT 24
Finished Jul 02 07:55:44 AM PDT 24
Peak memory 232544 kb
Host smart-f163260b-c94c-4450-9ea6-b9380a34e5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878909528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.878909528
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1032217746
Short name T612
Test name
Test status
Simulation time 18452194 ps
CPU time 0.74 seconds
Started Jul 02 07:55:45 AM PDT 24
Finished Jul 02 07:56:07 AM PDT 24
Peak memory 205832 kb
Host smart-4c81e248-2cf4-466d-a32c-a5d732e847c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032217746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1032217746
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1116290876
Short name T737
Test name
Test status
Simulation time 17609534442 ps
CPU time 114.34 seconds
Started Jul 02 07:55:33 AM PDT 24
Finished Jul 02 07:57:44 AM PDT 24
Peak memory 249112 kb
Host smart-7bb895c4-38a0-4526-aed7-e5d33a070d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116290876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1116290876
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.247797583
Short name T766
Test name
Test status
Simulation time 89023090131 ps
CPU time 234.8 seconds
Started Jul 02 07:55:37 AM PDT 24
Finished Jul 02 07:59:51 AM PDT 24
Peak memory 249128 kb
Host smart-2aca66d2-4a97-43fa-9346-084ce7f41804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247797583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.247797583
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3058898129
Short name T31
Test name
Test status
Simulation time 29626512558 ps
CPU time 107.25 seconds
Started Jul 02 07:55:35 AM PDT 24
Finished Jul 02 07:57:40 AM PDT 24
Peak memory 269400 kb
Host smart-da1c6521-c838-486c-9a08-90197dd99103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058898129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3058898129
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2975541760
Short name T932
Test name
Test status
Simulation time 1908109162 ps
CPU time 14.67 seconds
Started Jul 02 07:55:31 AM PDT 24
Finished Jul 02 07:56:03 AM PDT 24
Peak memory 224440 kb
Host smart-f2983423-2b3f-4dd1-ae1b-50af94b68cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975541760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2975541760
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3446059879
Short name T216
Test name
Test status
Simulation time 501434827 ps
CPU time 4.66 seconds
Started Jul 02 07:55:33 AM PDT 24
Finished Jul 02 07:55:56 AM PDT 24
Peak memory 232592 kb
Host smart-396f102e-8651-465e-8b34-0b92d6f42036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446059879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3446059879
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3423832207
Short name T673
Test name
Test status
Simulation time 10243086565 ps
CPU time 34.52 seconds
Started Jul 02 07:55:31 AM PDT 24
Finished Jul 02 07:56:23 AM PDT 24
Peak memory 238912 kb
Host smart-5d6e6e4a-222e-4618-9bc7-305e0ac62593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423832207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3423832207
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.81587183
Short name T435
Test name
Test status
Simulation time 110759024510 ps
CPU time 32.25 seconds
Started Jul 02 07:55:43 AM PDT 24
Finished Jul 02 07:56:36 AM PDT 24
Peak memory 248972 kb
Host smart-48a2cf62-e237-45db-b21e-5c42c8100750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81587183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.81587183
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3645741585
Short name T962
Test name
Test status
Simulation time 159633605 ps
CPU time 3.75 seconds
Started Jul 02 07:55:35 AM PDT 24
Finished Jul 02 07:55:57 AM PDT 24
Peak memory 232600 kb
Host smart-6423c2a5-9360-47f3-b3cd-972525eebe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645741585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3645741585
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1366907146
Short name T459
Test name
Test status
Simulation time 246825165 ps
CPU time 4.67 seconds
Started Jul 02 07:55:43 AM PDT 24
Finished Jul 02 07:56:08 AM PDT 24
Peak memory 220196 kb
Host smart-79e32533-99f1-4efc-8ec9-2dee31990f55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1366907146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1366907146
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1117480328
Short name T750
Test name
Test status
Simulation time 13270702419 ps
CPU time 99.45 seconds
Started Jul 02 07:55:29 AM PDT 24
Finished Jul 02 07:57:26 AM PDT 24
Peak memory 250988 kb
Host smart-18f57221-760c-4ad3-82cf-e2b5d1c4cb62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117480328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1117480328
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2055533357
Short name T298
Test name
Test status
Simulation time 4187776870 ps
CPU time 21.18 seconds
Started Jul 02 07:55:40 AM PDT 24
Finished Jul 02 07:56:21 AM PDT 24
Peak memory 216272 kb
Host smart-5c3e1c98-1bf5-4500-b358-274607c98ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055533357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2055533357
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3242671193
Short name T727
Test name
Test status
Simulation time 541951476 ps
CPU time 1.93 seconds
Started Jul 02 07:55:38 AM PDT 24
Finished Jul 02 07:56:00 AM PDT 24
Peak memory 216004 kb
Host smart-2877c557-4646-42f8-8baf-e86f18cc5838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242671193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3242671193
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4085119167
Short name T556
Test name
Test status
Simulation time 112757895 ps
CPU time 3.55 seconds
Started Jul 02 07:55:35 AM PDT 24
Finished Jul 02 07:55:57 AM PDT 24
Peak memory 216128 kb
Host smart-02c11e41-1429-4f2a-a153-abf42d135620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085119167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4085119167
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2025773854
Short name T321
Test name
Test status
Simulation time 13934043 ps
CPU time 0.68 seconds
Started Jul 02 07:55:29 AM PDT 24
Finished Jul 02 07:55:48 AM PDT 24
Peak memory 205896 kb
Host smart-0f9391c5-270a-4432-bee9-d79dafc4db4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025773854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2025773854
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2602890451
Short name T688
Test name
Test status
Simulation time 1302378770 ps
CPU time 7.98 seconds
Started Jul 02 07:55:39 AM PDT 24
Finished Jul 02 07:56:07 AM PDT 24
Peak memory 224412 kb
Host smart-8225d6c6-e5cb-46d3-ac4d-fd627de2abfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602890451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2602890451
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3934157030
Short name T360
Test name
Test status
Simulation time 42343757 ps
CPU time 0.73 seconds
Started Jul 02 07:53:42 AM PDT 24
Finished Jul 02 07:53:44 AM PDT 24
Peak memory 205748 kb
Host smart-4d28e659-851f-45de-862a-ed8e92bc8675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934157030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
934157030
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.323370423
Short name T845
Test name
Test status
Simulation time 2318059479 ps
CPU time 7.95 seconds
Started Jul 02 07:53:43 AM PDT 24
Finished Jul 02 07:53:52 AM PDT 24
Peak memory 224452 kb
Host smart-a05c8a98-a2b3-43f6-ab16-a93049513f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323370423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.323370423
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1352082754
Short name T308
Test name
Test status
Simulation time 16744934 ps
CPU time 0.82 seconds
Started Jul 02 07:53:49 AM PDT 24
Finished Jul 02 07:53:55 AM PDT 24
Peak memory 206876 kb
Host smart-420bf33a-5652-4cb1-a07b-796d9cd9b22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352082754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1352082754
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.985140721
Short name T235
Test name
Test status
Simulation time 26000789959 ps
CPU time 75.33 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:55:22 AM PDT 24
Peak memory 255340 kb
Host smart-446094ac-6794-475f-8958-cb072f48b7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985140721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.985140721
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.446124768
Short name T1004
Test name
Test status
Simulation time 4444536169 ps
CPU time 58.49 seconds
Started Jul 02 07:53:29 AM PDT 24
Finished Jul 02 07:54:28 AM PDT 24
Peak memory 239400 kb
Host smart-de40532d-1fda-4045-ad84-fcbb92607513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446124768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.446124768
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.504911150
Short name T136
Test name
Test status
Simulation time 213333904048 ps
CPU time 497.95 seconds
Started Jul 02 07:53:33 AM PDT 24
Finished Jul 02 08:01:52 AM PDT 24
Peak memory 265540 kb
Host smart-c22c1b7a-73c7-4dc0-a9c3-151a2adf314f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504911150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
504911150
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1404778931
Short name T702
Test name
Test status
Simulation time 315800635 ps
CPU time 7.21 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:54:07 AM PDT 24
Peak memory 224384 kb
Host smart-ce60f7ca-d7e9-4173-854c-d937200051fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404778931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1404778931
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1461863732
Short name T837
Test name
Test status
Simulation time 1451284568 ps
CPU time 31.91 seconds
Started Jul 02 07:53:41 AM PDT 24
Finished Jul 02 07:54:14 AM PDT 24
Peak memory 250448 kb
Host smart-f2bc5b96-a5a6-4d14-97b7-53b6502c3e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461863732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1461863732
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1573119958
Short name T830
Test name
Test status
Simulation time 354106465 ps
CPU time 5.38 seconds
Started Jul 02 07:53:49 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 232628 kb
Host smart-e039191a-9cb2-4b9f-b4d7-73fe7c07daa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573119958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1573119958
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1159654938
Short name T13
Test name
Test status
Simulation time 598039337 ps
CPU time 6.02 seconds
Started Jul 02 07:53:36 AM PDT 24
Finished Jul 02 07:53:44 AM PDT 24
Peak memory 224352 kb
Host smart-0726fad0-5c03-4831-b33f-9b6621140b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159654938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1159654938
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3602195359
Short name T600
Test name
Test status
Simulation time 1001938578 ps
CPU time 3.65 seconds
Started Jul 02 07:53:46 AM PDT 24
Finished Jul 02 07:53:52 AM PDT 24
Peak memory 232540 kb
Host smart-c20dcc64-9143-4f06-adbd-20722a02e2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602195359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3602195359
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3768809775
Short name T840
Test name
Test status
Simulation time 15624872066 ps
CPU time 23.75 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 232740 kb
Host smart-c47130e9-9c96-43c5-b33b-14aa2f642d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768809775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3768809775
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2702880288
Short name T993
Test name
Test status
Simulation time 6520974379 ps
CPU time 20.76 seconds
Started Jul 02 07:53:36 AM PDT 24
Finished Jul 02 07:53:59 AM PDT 24
Peak memory 220212 kb
Host smart-b8c80a45-8355-470c-9913-bfee715e6575
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2702880288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2702880288
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1275449798
Short name T445
Test name
Test status
Simulation time 118682585139 ps
CPU time 575.9 seconds
Started Jul 02 07:53:44 AM PDT 24
Finished Jul 02 08:03:22 AM PDT 24
Peak memory 265584 kb
Host smart-dffb2cd6-0f51-4aed-ad87-7b4acea457e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275449798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1275449798
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.938898058
Short name T866
Test name
Test status
Simulation time 12078688 ps
CPU time 0.72 seconds
Started Jul 02 07:53:42 AM PDT 24
Finished Jul 02 07:53:44 AM PDT 24
Peak memory 205652 kb
Host smart-fc92a32f-d921-4bbe-a91f-48834c3d3689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938898058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.938898058
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.874841356
Short name T767
Test name
Test status
Simulation time 1098073074 ps
CPU time 2.7 seconds
Started Jul 02 07:53:34 AM PDT 24
Finished Jul 02 07:53:38 AM PDT 24
Peak memory 216044 kb
Host smart-8436c4ff-5aca-471a-b126-db3e45b96b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874841356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.874841356
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3854124373
Short name T75
Test name
Test status
Simulation time 120619975 ps
CPU time 0.93 seconds
Started Jul 02 07:53:46 AM PDT 24
Finished Jul 02 07:53:48 AM PDT 24
Peak memory 206956 kb
Host smart-697f7c92-a271-4bf4-84e0-884576d0d677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854124373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3854124373
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1638135777
Short name T784
Test name
Test status
Simulation time 32585495 ps
CPU time 0.71 seconds
Started Jul 02 07:53:37 AM PDT 24
Finished Jul 02 07:53:39 AM PDT 24
Peak memory 205864 kb
Host smart-c482bc71-349f-4c94-8e57-950b6628bc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638135777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1638135777
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.759765386
Short name T236
Test name
Test status
Simulation time 162266927 ps
CPU time 3.14 seconds
Started Jul 02 07:53:31 AM PDT 24
Finished Jul 02 07:53:35 AM PDT 24
Peak memory 224292 kb
Host smart-3dfa9e22-af57-4ccf-9227-234bf077a6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759765386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.759765386
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1011974225
Short name T624
Test name
Test status
Simulation time 100692917 ps
CPU time 0.68 seconds
Started Jul 02 07:53:30 AM PDT 24
Finished Jul 02 07:53:33 AM PDT 24
Peak memory 204816 kb
Host smart-122622d7-4732-4c86-b4a5-a1929c584322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011974225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
011974225
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2246893780
Short name T661
Test name
Test status
Simulation time 5190813373 ps
CPU time 8.86 seconds
Started Jul 02 07:53:37 AM PDT 24
Finished Jul 02 07:53:47 AM PDT 24
Peak memory 232732 kb
Host smart-7aa72ab1-f75e-40a6-ba9a-85f661dbef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246893780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2246893780
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.987663593
Short name T386
Test name
Test status
Simulation time 60675715 ps
CPU time 0.78 seconds
Started Jul 02 07:53:38 AM PDT 24
Finished Jul 02 07:53:41 AM PDT 24
Peak memory 206456 kb
Host smart-ba1bad22-dea2-4faf-8be0-ca0e749e8354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987663593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.987663593
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1251922588
Short name T174
Test name
Test status
Simulation time 287281712029 ps
CPU time 179.54 seconds
Started Jul 02 07:54:05 AM PDT 24
Finished Jul 02 07:57:11 AM PDT 24
Peak memory 238328 kb
Host smart-f3cacf12-58a2-4ef0-93dd-8f9735a4ffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251922588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1251922588
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.656359063
Short name T300
Test name
Test status
Simulation time 86073577387 ps
CPU time 75.44 seconds
Started Jul 02 07:53:48 AM PDT 24
Finished Jul 02 07:55:06 AM PDT 24
Peak memory 232680 kb
Host smart-ecea3b0f-0079-4b2e-a208-1e4a3a3079e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656359063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.656359063
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3153232373
Short name T43
Test name
Test status
Simulation time 137997037495 ps
CPU time 280.85 seconds
Started Jul 02 07:53:56 AM PDT 24
Finished Jul 02 07:58:44 AM PDT 24
Peak memory 249148 kb
Host smart-08b9fd8d-2547-4b47-a309-26c17d7510e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153232373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3153232373
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.371160811
Short name T7
Test name
Test status
Simulation time 1504633516 ps
CPU time 7.34 seconds
Started Jul 02 07:53:53 AM PDT 24
Finished Jul 02 07:54:05 AM PDT 24
Peak memory 224360 kb
Host smart-0bfaeca5-b597-4ec8-b71d-c9d8ce88c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371160811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.371160811
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.536893867
Short name T989
Test name
Test status
Simulation time 51050962202 ps
CPU time 62.31 seconds
Started Jul 02 07:53:59 AM PDT 24
Finished Jul 02 07:55:08 AM PDT 24
Peak memory 252444 kb
Host smart-5c1ed62e-ed5e-4ffb-9903-d8366b3bc001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536893867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
536893867
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2790584268
Short name T781
Test name
Test status
Simulation time 122394691 ps
CPU time 4.28 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:54:00 AM PDT 24
Peak memory 232556 kb
Host smart-5b84e429-b5cd-4a87-b290-bdd8e6f963c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790584268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2790584268
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4143946033
Short name T449
Test name
Test status
Simulation time 542729812 ps
CPU time 13.1 seconds
Started Jul 02 07:53:49 AM PDT 24
Finished Jul 02 07:54:05 AM PDT 24
Peak memory 233604 kb
Host smart-0c6144a2-ff4d-48d6-abf0-ddc3ba417f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143946033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4143946033
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1920541153
Short name T705
Test name
Test status
Simulation time 5812198087 ps
CPU time 15.61 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:54:12 AM PDT 24
Peak memory 232692 kb
Host smart-c9c74467-b329-444b-a7f0-52e417d6c827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920541153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1920541153
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2035837305
Short name T824
Test name
Test status
Simulation time 161417506 ps
CPU time 2.29 seconds
Started Jul 02 07:53:57 AM PDT 24
Finished Jul 02 07:54:05 AM PDT 24
Peak memory 232200 kb
Host smart-b592faae-6ba2-491a-b941-dc895fc2db27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035837305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2035837305
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1692423935
Short name T28
Test name
Test status
Simulation time 1336104508 ps
CPU time 14.48 seconds
Started Jul 02 07:53:52 AM PDT 24
Finished Jul 02 07:54:11 AM PDT 24
Peak memory 219836 kb
Host smart-69e5e3b4-194a-4a25-8111-3cab4784fb0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1692423935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1692423935
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3496152744
Short name T281
Test name
Test status
Simulation time 54218629165 ps
CPU time 644.58 seconds
Started Jul 02 07:53:36 AM PDT 24
Finished Jul 02 08:04:22 AM PDT 24
Peak memory 301912 kb
Host smart-ac474e1c-ba19-4871-a280-e56515ad68a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496152744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3496152744
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3324050054
Short name T440
Test name
Test status
Simulation time 1145644903 ps
CPU time 1.97 seconds
Started Jul 02 07:54:09 AM PDT 24
Finished Jul 02 07:54:20 AM PDT 24
Peak memory 217740 kb
Host smart-02d15e24-7832-47ae-9c72-c92232ffa4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324050054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3324050054
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.486682470
Short name T759
Test name
Test status
Simulation time 653809281 ps
CPU time 4.6 seconds
Started Jul 02 07:53:28 AM PDT 24
Finished Jul 02 07:53:34 AM PDT 24
Peak memory 216064 kb
Host smart-27e424b3-13bb-486d-8d42-3503c72569f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486682470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.486682470
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3068405306
Short name T416
Test name
Test status
Simulation time 240517064 ps
CPU time 1.12 seconds
Started Jul 02 07:53:52 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 207752 kb
Host smart-bbc33dcb-761d-4372-95b7-039032ac2356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068405306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3068405306
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3330423328
Short name T391
Test name
Test status
Simulation time 34615118 ps
CPU time 0.76 seconds
Started Jul 02 07:54:03 AM PDT 24
Finished Jul 02 07:54:10 AM PDT 24
Peak memory 205840 kb
Host smart-79af3fa6-be73-4ec2-bad3-8e86e0553f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330423328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3330423328
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3137675028
Short name T157
Test name
Test status
Simulation time 3650888890 ps
CPU time 7.28 seconds
Started Jul 02 07:53:48 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 224372 kb
Host smart-93471517-d059-4b55-ae87-d71bc757f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137675028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3137675028
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1216039654
Short name T347
Test name
Test status
Simulation time 14076498 ps
CPU time 0.72 seconds
Started Jul 02 07:53:30 AM PDT 24
Finished Jul 02 07:53:33 AM PDT 24
Peak memory 205788 kb
Host smart-a6a4f1c5-469f-4dc7-9f79-61f93882c9e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216039654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
216039654
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1389889243
Short name T996
Test name
Test status
Simulation time 3095803766 ps
CPU time 16.56 seconds
Started Jul 02 07:53:38 AM PDT 24
Finished Jul 02 07:53:56 AM PDT 24
Peak memory 224476 kb
Host smart-685cdbd0-6ebe-48c1-a1e2-36843c3f17d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389889243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1389889243
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3943967550
Short name T314
Test name
Test status
Simulation time 20077453 ps
CPU time 0.81 seconds
Started Jul 02 07:53:57 AM PDT 24
Finished Jul 02 07:54:04 AM PDT 24
Peak memory 206772 kb
Host smart-717e6a8b-21c4-429a-8cdb-d32bde7f8b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943967550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3943967550
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.498240945
Short name T1013
Test name
Test status
Simulation time 24544545778 ps
CPU time 124.54 seconds
Started Jul 02 07:53:56 AM PDT 24
Finished Jul 02 07:56:07 AM PDT 24
Peak memory 249144 kb
Host smart-7ba6037b-1cf1-41f6-8b25-440e9fb3db4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498240945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.498240945
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3735839100
Short name T828
Test name
Test status
Simulation time 19257612675 ps
CPU time 76.95 seconds
Started Jul 02 07:53:38 AM PDT 24
Finished Jul 02 07:54:56 AM PDT 24
Peak memory 249176 kb
Host smart-a232c5fc-5f41-492f-b524-c4a035f40c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735839100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3735839100
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3679305961
Short name T53
Test name
Test status
Simulation time 32117032205 ps
CPU time 89.24 seconds
Started Jul 02 07:53:45 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 251020 kb
Host smart-dc7b7c8d-f823-4bd1-8372-8392a909303c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679305961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3679305961
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.531674690
Short name T1
Test name
Test status
Simulation time 1503956096 ps
CPU time 20.75 seconds
Started Jul 02 07:53:50 AM PDT 24
Finished Jul 02 07:54:15 AM PDT 24
Peak memory 234948 kb
Host smart-b65c1d8a-ab60-4226-94e5-bce487bbadb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531674690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.531674690
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3382143969
Short name T190
Test name
Test status
Simulation time 62079568842 ps
CPU time 146.23 seconds
Started Jul 02 07:53:42 AM PDT 24
Finished Jul 02 07:56:10 AM PDT 24
Peak memory 253568 kb
Host smart-87cfb13f-1c3e-4975-bb05-c4ec0466e38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382143969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3382143969
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4190376361
Short name T992
Test name
Test status
Simulation time 5787623510 ps
CPU time 16.11 seconds
Started Jul 02 07:53:38 AM PDT 24
Finished Jul 02 07:53:55 AM PDT 24
Peak memory 232664 kb
Host smart-3a8be603-e31e-46a2-9ae0-fad9ebc67b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190376361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4190376361
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2449924449
Short name T240
Test name
Test status
Simulation time 138932488 ps
CPU time 2.65 seconds
Started Jul 02 07:53:44 AM PDT 24
Finished Jul 02 07:53:48 AM PDT 24
Peak memory 224276 kb
Host smart-fe2a54c3-9cab-4af8-9708-63c302ffd8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449924449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2449924449
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3408653034
Short name T350
Test name
Test status
Simulation time 143063770 ps
CPU time 2.22 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:54:00 AM PDT 24
Peak memory 223808 kb
Host smart-afde6937-199a-4c56-b9ac-ffc8dbfdb016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408653034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3408653034
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2136784820
Short name T539
Test name
Test status
Simulation time 1728707858 ps
CPU time 10.13 seconds
Started Jul 02 07:53:38 AM PDT 24
Finished Jul 02 07:53:50 AM PDT 24
Peak memory 224452 kb
Host smart-e94dadf4-75c5-48c0-8e67-dfa67ad53c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136784820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2136784820
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3237938066
Short name T880
Test name
Test status
Simulation time 1327285107 ps
CPU time 9.93 seconds
Started Jul 02 07:53:48 AM PDT 24
Finished Jul 02 07:54:00 AM PDT 24
Peak memory 220140 kb
Host smart-b441c1ab-81d8-4995-8988-3f1170b4431a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3237938066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3237938066
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3519099228
Short name T209
Test name
Test status
Simulation time 10830191386 ps
CPU time 160.42 seconds
Started Jul 02 07:53:43 AM PDT 24
Finished Jul 02 07:56:24 AM PDT 24
Peak memory 256832 kb
Host smart-c119e1e4-5d8e-44d7-b29f-c00149b5f42b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519099228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3519099228
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1112120692
Short name T499
Test name
Test status
Simulation time 33795705 ps
CPU time 0.73 seconds
Started Jul 02 07:53:58 AM PDT 24
Finished Jul 02 07:54:05 AM PDT 24
Peak memory 205652 kb
Host smart-cd59a227-6c53-4b47-b2f8-2ddb8f4c7011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112120692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1112120692
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.921130110
Short name T841
Test name
Test status
Simulation time 14760498884 ps
CPU time 15.64 seconds
Started Jul 02 07:53:36 AM PDT 24
Finished Jul 02 07:53:53 AM PDT 24
Peak memory 217560 kb
Host smart-efd9fbcd-186a-412c-99d0-674419f1a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921130110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.921130110
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.819848112
Short name T352
Test name
Test status
Simulation time 52132999 ps
CPU time 0.94 seconds
Started Jul 02 07:53:55 AM PDT 24
Finished Jul 02 07:54:02 AM PDT 24
Peak memory 206904 kb
Host smart-6f3c3bd2-76fe-4359-9140-628bf453ed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819848112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.819848112
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.944482854
Short name T699
Test name
Test status
Simulation time 90425645 ps
CPU time 0.77 seconds
Started Jul 02 07:53:33 AM PDT 24
Finished Jul 02 07:53:35 AM PDT 24
Peak memory 205876 kb
Host smart-0ce32998-e313-4188-94ad-36a9e4a6b6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944482854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.944482854
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2331068633
Short name T871
Test name
Test status
Simulation time 15255575209 ps
CPU time 12.51 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:54:13 AM PDT 24
Peak memory 232672 kb
Host smart-bfb91db5-57f6-4c50-ae7a-5ada95c7535e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331068633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2331068633
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3126628384
Short name T443
Test name
Test status
Simulation time 14923104 ps
CPU time 0.73 seconds
Started Jul 02 07:53:50 AM PDT 24
Finished Jul 02 07:53:56 AM PDT 24
Peak memory 204900 kb
Host smart-3e11fd35-ce67-4524-b283-b011c8768f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126628384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
126628384
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3423388531
Short name T76
Test name
Test status
Simulation time 268625540 ps
CPU time 4.34 seconds
Started Jul 02 07:54:00 AM PDT 24
Finished Jul 02 07:54:11 AM PDT 24
Peak memory 224460 kb
Host smart-99ec47f1-86a5-4f77-bcd9-74e9057a1c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423388531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3423388531
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2863054810
Short name T626
Test name
Test status
Simulation time 75379548 ps
CPU time 0.8 seconds
Started Jul 02 07:53:42 AM PDT 24
Finished Jul 02 07:53:44 AM PDT 24
Peak memory 206836 kb
Host smart-78bef49b-b1c2-4ef1-9bc0-2f8576a682cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863054810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2863054810
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3673100719
Short name T208
Test name
Test status
Simulation time 20572192766 ps
CPU time 147.46 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:56:28 AM PDT 24
Peak memory 256820 kb
Host smart-86463a95-2222-4a4d-9caf-2ce93bfab02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673100719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3673100719
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.4272532469
Short name T572
Test name
Test status
Simulation time 2620395733 ps
CPU time 70.56 seconds
Started Jul 02 07:53:49 AM PDT 24
Finished Jul 02 07:55:03 AM PDT 24
Peak memory 249152 kb
Host smart-9021e1d7-4432-473d-b0e3-0f9b707e2c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272532469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.4272532469
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1796763081
Short name T270
Test name
Test status
Simulation time 99480126712 ps
CPU time 211.94 seconds
Started Jul 02 07:53:33 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 250912 kb
Host smart-cc4c775d-aa99-4cac-b15a-e12317a54e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796763081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1796763081
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2544571686
Short name T986
Test name
Test status
Simulation time 1447514372 ps
CPU time 25.77 seconds
Started Jul 02 07:53:45 AM PDT 24
Finished Jul 02 07:54:12 AM PDT 24
Peak memory 236092 kb
Host smart-d290bdb3-098a-4160-91c9-1c1f5f6b531d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544571686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2544571686
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3237826536
Short name T438
Test name
Test status
Simulation time 2714956545 ps
CPU time 10.32 seconds
Started Jul 02 07:53:45 AM PDT 24
Finished Jul 02 07:53:56 AM PDT 24
Peak memory 234748 kb
Host smart-1786bd81-cbcf-4def-806c-d2869cd81086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237826536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3237826536
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3849754185
Short name T466
Test name
Test status
Simulation time 898854175 ps
CPU time 5.14 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 07:54:04 AM PDT 24
Peak memory 232528 kb
Host smart-bac61f74-4257-460a-8aa7-e0a31c7e4d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849754185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3849754185
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2411476842
Short name T452
Test name
Test status
Simulation time 53001373 ps
CPU time 2.19 seconds
Started Jul 02 07:54:04 AM PDT 24
Finished Jul 02 07:54:12 AM PDT 24
Peak memory 223780 kb
Host smart-e60290aa-c532-4b38-8209-b77f41199076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411476842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2411476842
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.158049862
Short name T515
Test name
Test status
Simulation time 1144219361 ps
CPU time 3.59 seconds
Started Jul 02 07:53:48 AM PDT 24
Finished Jul 02 07:53:55 AM PDT 24
Peak memory 232624 kb
Host smart-8cba3167-e7d6-41e2-9036-481c5faa1070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158049862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
158049862
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.962664183
Short name T754
Test name
Test status
Simulation time 9389048671 ps
CPU time 11.18 seconds
Started Jul 02 07:54:05 AM PDT 24
Finished Jul 02 07:54:23 AM PDT 24
Peak memory 232728 kb
Host smart-efc5b433-bd61-4233-a932-f39b87646136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962664183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.962664183
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1942565281
Short name T629
Test name
Test status
Simulation time 3201224003 ps
CPU time 8.86 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:54:06 AM PDT 24
Peak memory 219192 kb
Host smart-fe91bf41-f297-4db1-9fc3-3e33dc22c9b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1942565281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1942565281
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.675729180
Short name T751
Test name
Test status
Simulation time 741610046 ps
CPU time 10.73 seconds
Started Jul 02 07:53:36 AM PDT 24
Finished Jul 02 07:53:48 AM PDT 24
Peak memory 216204 kb
Host smart-8980eb24-14f9-46f2-8cc7-c4d938ad32e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675729180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.675729180
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2638438009
Short name T504
Test name
Test status
Simulation time 411548975 ps
CPU time 1.73 seconds
Started Jul 02 07:53:44 AM PDT 24
Finished Jul 02 07:53:47 AM PDT 24
Peak memory 207784 kb
Host smart-74b7f5d5-f8e1-4087-a3d4-b1554312bbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638438009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2638438009
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2755475383
Short name T937
Test name
Test status
Simulation time 47677497 ps
CPU time 0.85 seconds
Started Jul 02 07:53:49 AM PDT 24
Finished Jul 02 07:53:55 AM PDT 24
Peak memory 206920 kb
Host smart-8fbf4709-0080-45d4-a007-f51c1882106d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755475383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2755475383
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4026661980
Short name T343
Test name
Test status
Simulation time 46607942 ps
CPU time 0.72 seconds
Started Jul 02 07:53:52 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 205924 kb
Host smart-1d14f6f8-c45d-4a21-9429-a30ee5265b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026661980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4026661980
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4238955753
Short name T412
Test name
Test status
Simulation time 8105269316 ps
CPU time 24.6 seconds
Started Jul 02 07:53:32 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 240308 kb
Host smart-de9f52c4-78f9-49c1-b722-025437fa0596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238955753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4238955753
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3959501602
Short name T990
Test name
Test status
Simulation time 45225527 ps
CPU time 0.75 seconds
Started Jul 02 07:53:53 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 205732 kb
Host smart-74056294-1ed7-4383-a50c-9dbe58c73986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959501602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
959501602
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1849191458
Short name T226
Test name
Test status
Simulation time 6741685165 ps
CPU time 7.12 seconds
Started Jul 02 07:53:48 AM PDT 24
Finished Jul 02 07:53:59 AM PDT 24
Peak memory 232680 kb
Host smart-69f7d71d-7371-4923-887e-2874d07a24dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849191458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1849191458
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2023218047
Short name T411
Test name
Test status
Simulation time 15392229 ps
CPU time 0.75 seconds
Started Jul 02 07:53:53 AM PDT 24
Finished Jul 02 07:53:58 AM PDT 24
Peak memory 205852 kb
Host smart-85984b13-adb9-47cf-a859-850f34fb25a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023218047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2023218047
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.321076024
Short name T269
Test name
Test status
Simulation time 56606392053 ps
CPU time 414.26 seconds
Started Jul 02 07:53:54 AM PDT 24
Finished Jul 02 08:00:55 AM PDT 24
Peak memory 254588 kb
Host smart-32f55c21-271f-4fdb-848b-e54571997370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321076024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.321076024
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1784526001
Short name T37
Test name
Test status
Simulation time 11218512296 ps
CPU time 146.25 seconds
Started Jul 02 07:54:01 AM PDT 24
Finished Jul 02 07:56:34 AM PDT 24
Peak memory 250924 kb
Host smart-a87b6d0d-f96b-4705-ad6d-586df01c327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784526001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1784526001
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4058217175
Short name T254
Test name
Test status
Simulation time 43644072903 ps
CPU time 198.32 seconds
Started Jul 02 07:53:52 AM PDT 24
Finished Jul 02 07:57:15 AM PDT 24
Peak memory 250380 kb
Host smart-a2e2de40-6837-4826-9c3a-159b7d530f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058217175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4058217175
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.555953658
Short name T169
Test name
Test status
Simulation time 9114445048 ps
CPU time 29.32 seconds
Started Jul 02 07:53:58 AM PDT 24
Finished Jul 02 07:54:34 AM PDT 24
Peak memory 240920 kb
Host smart-c9f8e0c3-9606-41a3-bb2d-974976f10f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555953658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
555953658
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.907626825
Short name T654
Test name
Test status
Simulation time 841251968 ps
CPU time 6.63 seconds
Started Jul 02 07:53:48 AM PDT 24
Finished Jul 02 07:54:04 AM PDT 24
Peak memory 232640 kb
Host smart-2342b868-00ee-4280-9559-3a0bf49b70cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907626825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.907626825
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2688902285
Short name T548
Test name
Test status
Simulation time 6455708357 ps
CPU time 12.21 seconds
Started Jul 02 07:53:53 AM PDT 24
Finished Jul 02 07:54:11 AM PDT 24
Peak memory 237136 kb
Host smart-7a50fd92-3d37-4a25-8874-feb701740b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688902285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2688902285
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3794435716
Short name T608
Test name
Test status
Simulation time 6252108400 ps
CPU time 11.51 seconds
Started Jul 02 07:53:48 AM PDT 24
Finished Jul 02 07:54:03 AM PDT 24
Peak memory 218844 kb
Host smart-07f05657-63e9-4776-8a76-898b7a458ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794435716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3794435716
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3808479679
Short name T958
Test name
Test status
Simulation time 700940146 ps
CPU time 4.79 seconds
Started Jul 02 07:53:35 AM PDT 24
Finished Jul 02 07:53:40 AM PDT 24
Peak memory 239212 kb
Host smart-fdf58fb7-541e-4245-ac09-025f3da2d859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808479679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3808479679
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1673843012
Short name T134
Test name
Test status
Simulation time 10600722107 ps
CPU time 13.71 seconds
Started Jul 02 07:53:47 AM PDT 24
Finished Jul 02 07:54:03 AM PDT 24
Peak memory 223292 kb
Host smart-afbb1008-80b2-43f5-b88e-dbeccde9315e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1673843012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1673843012
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.205943200
Short name T378
Test name
Test status
Simulation time 36018157 ps
CPU time 0.94 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:53:56 AM PDT 24
Peak memory 206544 kb
Host smart-bd36b6ff-0c8c-476b-8561-5285a9e6ff74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205943200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.205943200
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4136371416
Short name T1014
Test name
Test status
Simulation time 4028271274 ps
CPU time 11.53 seconds
Started Jul 02 07:53:39 AM PDT 24
Finished Jul 02 07:53:52 AM PDT 24
Peak memory 216392 kb
Host smart-ed27c79b-eab6-4dc1-bf67-c3ff10261fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136371416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4136371416
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.693878531
Short name T730
Test name
Test status
Simulation time 1456422906 ps
CPU time 3.87 seconds
Started Jul 02 07:53:46 AM PDT 24
Finished Jul 02 07:53:51 AM PDT 24
Peak memory 216076 kb
Host smart-171785a1-290b-429b-97f1-5c6dbe613547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693878531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.693878531
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2527809868
Short name T580
Test name
Test status
Simulation time 36483877 ps
CPU time 0.68 seconds
Started Jul 02 07:53:51 AM PDT 24
Finished Jul 02 07:53:57 AM PDT 24
Peak memory 205572 kb
Host smart-206366cd-1ada-4602-989a-febf3e16b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527809868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2527809868
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.97367949
Short name T389
Test name
Test status
Simulation time 85052962 ps
CPU time 0.88 seconds
Started Jul 02 07:53:57 AM PDT 24
Finished Jul 02 07:54:04 AM PDT 24
Peak memory 206948 kb
Host smart-7e89b54e-0b2d-4ea9-bba3-a6f416bdec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97367949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.97367949
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.827061522
Short name T425
Test name
Test status
Simulation time 184349688 ps
CPU time 2.28 seconds
Started Jul 02 07:53:35 AM PDT 24
Finished Jul 02 07:53:39 AM PDT 24
Peak memory 232628 kb
Host smart-648bb7d0-f16f-47fd-85d5-669156afa071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827061522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.827061522
Directory /workspace/9.spi_device_upload/latest
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