Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2641441	1			T1	101		T2	22		T3	2815
all_values[1]	2641441	1			T1	101		T2	22		T3	2815
all_values[2]	2641441	1			T1	101		T2	22		T3	2815
all_values[3]	2641441	1			T1	101		T2	22		T3	2815
all_values[4]	2641441	1			T1	101		T2	22		T3	2815
all_values[5]	2641441	1			T1	101		T2	22		T3	2815
all_values[6]	2641441	1			T1	101		T2	22		T3	2815
all_values[7]	2641441	1			T1	101		T2	22		T3	2815

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20959101

1

T1

808

T2

176

T3

22469

auto[1]

172427

1

T3

51

T6

52

T13

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21106238

1

T1

808

T2

176

T3

22319

auto[1]

25290

1

T3

201

T6

52

T13

232

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2620138	1			T1	101		T2	22		T3	2753
all_values[0]	auto[0]	auto[1]	12067	1			T3	60		T6	17		T13	134
all_values[0]	auto[1]	auto[0]	8946	1			T13	3		T17	3		T18	7
all_values[0]	auto[1]	auto[1]	290	1			T3	2		T6	3		T13	1
all_values[1]	auto[0]	auto[0]	2593840	1			T1	101		T2	22		T3	2749
all_values[1]	auto[0]	auto[1]	7666	1			T3	57		T6	1		T13	58
all_values[1]	auto[1]	auto[0]	39633	1			T3	9		T6	8		T13	2
all_values[1]	auto[1]	auto[1]	302	1			T6	1		T13	2		T17	2
all_values[2]	auto[0]	auto[0]	2633292	1			T1	101		T2	22		T3	2749
all_values[2]	auto[0]	auto[1]	2858	1			T3	57		T6	3		T13	26
all_values[2]	auto[1]	auto[0]	5079	1			T3	8		T6	5		T13	5
all_values[2]	auto[1]	auto[1]	212	1			T3	1		T6	3		T13	2
all_values[3]	auto[0]	auto[0]	2635242	1			T1	101		T2	22		T3	2806
all_values[3]	auto[0]	auto[1]	223	1			T3	3		T6	4		T17	2
all_values[3]	auto[1]	auto[0]	5803	1			T3	4		T6	5		T13	8
all_values[3]	auto[1]	auto[1]	173	1			T3	2		T13	3		T17	2
all_values[4]	auto[0]	auto[0]	2637280	1			T1	101		T2	22		T3	2811
all_values[4]	auto[0]	auto[1]	186	1			T3	2		T6	4		T17	1
all_values[4]	auto[1]	auto[0]	3785	1			T3	2		T6	1		T13	6
all_values[4]	auto[1]	auto[1]	190	1			T6	1		T17	11		T18	1
all_values[5]	auto[0]	auto[0]	2592591	1			T1	101		T2	22		T3	2804
all_values[5]	auto[0]	auto[1]	151	1			T3	2		T6	1		T13	1
all_values[5]	auto[1]	auto[0]	48513	1			T3	7		T6	7		T13	5
all_values[5]	auto[1]	auto[1]	186	1			T3	2		T6	3		T13	2
all_values[6]	auto[0]	auto[0]	2602803	1			T1	101		T2	22		T3	2802
all_values[6]	auto[0]	auto[1]	189	1			T3	3		T6	2		T17	6
all_values[6]	auto[1]	auto[0]	38244	1			T3	7		T6	7		T13	5
all_values[6]	auto[1]	auto[1]	205	1			T3	3		T6	3		T13	1
all_values[7]	auto[0]	auto[0]	2620360	1			T1	101		T2	22		T3	2806
all_values[7]	auto[0]	auto[1]	215	1			T3	5		T6	3		T13	1
all_values[7]	auto[1]	auto[0]	20689	1			T3	2		T6	2		T13	1
all_values[7]	auto[1]	auto[1]	177	1			T3	2		T6	3		T13	1