Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31522	1			T1	61		T3	103		T4	4
auto[SpiFlashAddrCfg]	7323	1			T1	21		T3	24		T6	17
auto[SpiFlashAddr3b]	8773	1			T1	18		T3	27		T6	4
auto[SpiFlashAddr4b]	7344	1			T1	20		T3	22		T6	5

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30712

1

T1

76

T3

120

T4

4

auto[1]

24250

1

T1

44

T3

56

T6

80

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30095

1

T1

71

T3

83

T4

2

auto[1]

24867

1

T1

49

T3

93

T4

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	36009	1			T1	65		T3	113		T4	4
values[1]	1007	1			T1	2		T3	4		T6	3
values[2]	1398	1			T1	9		T3	4		T12	4
values[3]	1350	1			T1	6		T3	6		T13	9
values[4]	1389	1			T3	2		T6	5		T13	6
values[5]	1428	1			T1	2		T3	5		T13	10
values[6]	1483	1			T1	8		T3	4		T11	2
values[7]	1423	1			T3	7		T13	7		T15	8
values[8]	9475	1			T1	28		T3	31		T6	9

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31778

1

T4

4

T6

108

T8

22

auto[1]

23184

1

T1

120

T3

176

T15

80

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

51882

1

T1

107

T3

169

T4

4

write

3080

1

T1

13

T3

7

T6

7

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18401

1

T1

56

T3

68

T6

14

valids[0x1]

36561

1

T1

64

T3

108

T4

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1519	1			T1	5		T3	5		T4	2
internal_process_ops[0x5a]	1523	1			T1	1		T3	3		T13	1
internal_process_ops[0x05]	18282	1			T1	4		T3	49		T6	68
internal_process_ops[0x35]	1538	1			T1	7		T3	6		T4	2
internal_process_ops[0x15]	1455	1			T1	2		T3	6		T6	2
internal_process_ops[0x03]	1055	1			T1	2		T3	3		T13	14
internal_process_ops[0x0b]	1004	1			T1	2		T13	6		T31	7
internal_process_ops[0x3b]	996	1			T3	1		T6	1		T13	4
internal_process_ops[0x6b]	1063	1			T3	3		T6	4		T13	3
internal_process_ops[0xbb]	1011	1			T1	3		T3	3		T12	4
internal_process_ops[0xeb]	1052	1			T1	3		T3	1		T6	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53442

1

T1

112

T3

172

T4

4

auto[1]

1520

1

T1

8

T3

4

T6

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52725

1

T1

112

T3

167

T4

4

auto[1]

2237

1

T1

8

T3

9

T6

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10464

1

T4

4

T6

17

T8

22

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6823

1

T6

65

T13

35

T31

7

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2075

1

T6

5

T10

2

T11

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1976

1

T6

9

T13

28

T31

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2561

1

T6

1

T10

2

T13

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2224

1

T6

3

T13

11

T31

9

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2225

1

T6

1

T11

4

T13

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1832

1

T13

14

T31

20

T32

9

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

107

1

T13

1

T31

2

T91

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T17

1

T18

6

T19

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

76

1

T32

1

T41

1

T42

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T32

3

T18

3

T19

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

110

1

T13

1

T17

1

T18

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

87

1

T13

4

T18

1

T19

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

88

1

T6

3

T13

1

T41

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

97

1

T31

2

T40

4

T41

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

143

1

T39

2

T31

1

T107

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

99

1

T13

1

T42

1

T43

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

112

1

T13

1

T30

2

T172

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

101

1

T18

3

T42

2

T173

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

110

1

T31

1

T41

2

T43

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

105

1

T6

4

T32

1

T18

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

73

1

T13

2

T32

1

T19

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

94

1

T19

3

T42

1

T43

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7605

1

T1

39

T3

86

T15

20

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5915

1

T1

15

T3

15

T15

5

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1274

1

T1

13

T3

15

T15

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1226

1

T1

6

T3

6

T15

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1648

1

T1

7

T3

11

T15

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1515

1

T1

11

T3

16

T15

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1271

1

T1

13

T3

6

T15

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1248

1

T1

3

T3

14

T15

8

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

67

1

T74

1

T21

5

T164

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

87

1

T1

2

T47

5

T90

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

90

1

T1

4

T3

2

T47

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

92

1

T1

1

T47

2

T90

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

116

1

T47

1

T90

2

T74

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

112

1

T1

1

T3

2

T74

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

85

1

T3

1

T47

5

T90

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

77

1

T1

1

T15

1

T47

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

85

1

T47

1

T90

2

T74

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

77

1

T47

1

T90

1

T19

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

114

1

T47

3

T74

2

T19

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

94

1

T47

1

T90

2

T74

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

94

1

T1

1

T47

1

T90

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

92

1

T74

3

T19

4

T75

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

90

1

T47

1

T19

2

T75

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

110

1

T1

3

T3

2

T15

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4135	1			T6	6		T8	22		T12	2
auto[0]	values[0]	valids[0x1]	16198	1			T4	4		T6	85		T10	8
auto[0]	values[1]	valids[0x1]	569	1			T6	3		T10	2		T12	2
auto[0]	values[2]	valids[0x0]	520	1			T12	4		T13	5		T31	5
auto[0]	values[2]	valids[0x1]	303	1			T13	2		T17	3		T41	7
auto[0]	values[3]	valids[0x0]	578	1			T13	3		T32	4		T30	3
auto[0]	values[3]	valids[0x1]	268	1			T13	6		T31	1		T32	2
auto[0]	values[4]	valids[0x0]	550	1			T6	1		T13	3		T31	2
auto[0]	values[4]	valids[0x1]	304	1			T6	4		T13	3		T31	1
auto[0]	values[5]	valids[0x0]	579	1			T13	6		T39	6		T31	6
auto[0]	values[5]	valids[0x1]	303	1			T13	4		T18	4		T19	5
auto[0]	values[6]	valids[0x0]	585	1			T13	4		T31	2		T32	4
auto[0]	values[6]	valids[0x1]	314	1			T11	2		T31	3		T32	3
auto[0]	values[7]	valids[0x0]	559	1			T13	4		T31	7		T32	2
auto[0]	values[7]	valids[0x1]	306	1			T13	3		T31	4		T32	1
auto[0]	values[8]	valids[0x0]	3557	1			T6	7		T11	6		T13	33
auto[0]	values[8]	valids[0x1]	2150	1			T6	2		T12	2		T13	26
auto[1]	values[0]	valids[0x0]	3255	1			T1	26		T3	35		T15	16
auto[1]	values[0]	valids[0x1]	12421	1			T1	39		T3	78		T15	21
auto[1]	values[1]	valids[0x1]	438	1			T1	2		T3	4		T47	3
auto[1]	values[2]	valids[0x0]	363	1			T1	6		T3	3		T90	11
auto[1]	values[2]	valids[0x1]	212	1			T1	3		T3	1		T15	1
auto[1]	values[3]	valids[0x0]	307	1			T1	3		T3	3		T47	6
auto[1]	values[3]	valids[0x1]	197	1			T1	3		T3	3		T15	2
auto[1]	values[4]	valids[0x0]	307	1			T3	2		T15	1		T47	2
auto[1]	values[4]	valids[0x1]	228	1			T15	1		T47	2		T90	3
auto[1]	values[5]	valids[0x0]	318	1			T3	2		T15	2		T35	1
auto[1]	values[5]	valids[0x1]	228	1			T1	2		T3	3		T15	2
auto[1]	values[6]	valids[0x0]	341	1			T1	4		T3	1		T47	1
auto[1]	values[6]	valids[0x1]	243	1			T1	4		T3	3		T15	2
auto[1]	values[7]	valids[0x0]	293	1			T3	3		T15	1		T47	3
auto[1]	values[7]	valids[0x1]	265	1			T3	4		T15	7		T47	7
auto[1]	values[8]	valids[0x0]	2154	1			T1	17		T3	19		T15	19
auto[1]	values[8]	valids[0x1]	1614	1			T1	11		T3	12		T15	5