Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3340075

1

T1

4112

T2

1

T3

12061

auto[1]

25058

1

T1

331

T3

36

T6

68

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

920797

1

T1

283

T2

1

T3

50

auto[1]

2444336

1

T1

4160

T3

12047

T6

1103

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	636349	1			T1	175		T2	1		T3	4932
auto[524288:1048575]	376069	1			T1	2955		T3	2191		T6	261
auto[1048576:1572863]	404818	1			T1	10		T3	1477		T6	39
auto[1572864:2097151]	381477	1			T1	311		T3	1		T8	4
auto[2097152:2621439]	356203	1			T1	643		T3	3		T4	1
auto[2621440:3145727]	395376	1			T1	303		T3	257		T4	292
auto[3145728:3670015]	402741	1			T1	27		T3	2693		T6	512
auto[3670016:4194303]	412100	1			T1	19		T3	543		T13	18

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2477177

1

T1

4441

T2

1

T3

12097

auto[1]

887956

1

T1

2

T4

1463

T6

6

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2911982

1

T1

542

T2

1

T3

11838

auto[1]

453151

1

T1

3901

T3

259

T6

816

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	188732	1			T1	43		T2	1		T3	4
auto[0]	auto[0]	auto[0:524287]	auto[1]	370996	1			T1	132		T3	4924		T10	1032
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	98669	1			T1	10		T3	11		T8	393
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	214603	1			T3	2179		T13	3218		T31	2011
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	114006	1			T1	10		T3	10		T6	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	229957	1			T3	1453		T13	3254		T31	6715
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	100942	1			T1	3		T8	4		T13	6
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	221946	1			T13	4016		T31	512		T32	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	106261	1			T1	23		T3	3		T4	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	206120	1			T6	270		T13	391		T47	1819
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	113869	1			T1	9		T3	1		T4	292
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	216867	1			T3	256		T13	5598		T15	2201
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	92662	1			T1	10		T3	3		T13	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	266732	1			T1	2		T3	2690		T13	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	92214	1			T1	19		T3	6		T13	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	256769	1			T3	262		T13	2		T31	289
auto[0]	auto[1]	auto[0:524287]	auto[0]	728	1			T6	2		T13	2		T15	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	71535	1			T6	1		T13	256		T47	3079
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	646	1			T1	44		T6	2		T13	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	59536	1			T1	2624		T6	257		T13	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	746	1			T3	1		T6	3		T13	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56595	1			T6	1		T13	513		T32	641
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	707	1			T1	7		T3	1		T31	46
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54186	1			T1	272		T31	389		T47	1188
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1741	1			T1	12		T13	3		T32	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	39414	1			T1	599		T13	1		T32	513
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1455	1			T1	29		T15	15		T90	14
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	59928	1			T1	262		T15	2438		T47	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1822	1			T1	2		T13	1		T31	13
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	38957	1			T6	512		T31	256		T19	1942
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1814	1			T3	1		T30	1		T90	11
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	58920	1			T3	256		T13	4		T90	4
auto[1]	auto[0]	auto[0:524287]	auto[0]	521	1			T3	1		T13	1		T31	8
auto[1]	auto[0]	auto[0:524287]	auto[1]	3422	1			T3	3		T31	256		T32	5
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	359	1			T1	3		T3	1		T47	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1760	1			T1	256		T47	14		T74	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	436	1			T3	5		T13	2		T31	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2494	1			T3	8		T13	9		T17	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	384	1			T13	2		T31	3		T30	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2411	1			T13	12		T47	1		T41	19
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	433	1			T1	9		T6	3		T13	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1803	1			T6	27		T13	2		T47	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	342	1			T13	1		T30	1		T47	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2411	1			T13	5		T30	7		T47	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	312	1			T1	13		T41	1		T18	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1876	1			T41	19		T18	16		T19	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	355	1			T3	2		T13	2		T47	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1318	1			T3	16		T13	6		T41	12
auto[1]	auto[1]	auto[0:524287]	auto[0]	57	1			T6	1		T47	1		T18	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	358	1			T6	1		T47	5		T18	9
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	123	1			T1	18		T6	1		T74	7
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	373	1			T6	1		T19	1		T34	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	91	1			T6	1		T13	1		T32	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	493	1			T6	33		T13	2		T32	37
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	107	1			T1	16		T47	1		T90	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	794	1			T1	13		T90	6		T41	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	59	1			T13	1		T32	1		T19	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	372	1			T13	9		T32	9		T19	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	62	1			T1	3		T15	14		T199	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	442	1			T199	53		T76	75		T211	17
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	67	1			T19	1		T43	1		T76	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	313	1			T19	7		T43	12		T76	13
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	75	1			T18	1		T75	3		T211	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	635	1			T18	11		T211	46		T173	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2009325	1			T1	261		T2	1		T3	11802
auto[0]	auto[0]	auto[1]	882020	1			T4	1463		T6	3		T8	390
auto[0]	auto[1]	auto[0]	443465	1			T1	3851		T3	259		T6	778
auto[0]	auto[1]	auto[1]	5265	1			T32	1		T18	1		T211	2
auto[1]	auto[0]	auto[0]	20083	1			T1	280		T3	36		T6	29
auto[1]	auto[0]	auto[1]	554	1			T1	1		T6	1		T31	3
auto[1]	auto[1]	auto[0]	4304	1			T1	49		T6	36		T13	13
auto[1]	auto[1]	auto[1]	117	1			T1	1		T6	2		T32	2