Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2641441	1			T1	101		T2	22		T3	2815
all_pins[1]	2641441	1			T1	101		T2	22		T3	2815
all_pins[2]	2641441	1			T1	101		T2	22		T3	2815
all_pins[3]	2641441	1			T1	101		T2	22		T3	2815
all_pins[4]	2641441	1			T1	101		T2	22		T3	2815
all_pins[5]	2641441	1			T1	101		T2	22		T3	2815
all_pins[6]	2641441	1			T1	101		T2	22		T3	2815
all_pins[7]	2641441	1			T1	101		T2	22		T3	2815

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21093623	1			T1	808		T2	176		T3	22508
values[0x1]	37905	1			T3	12		T6	17		T13	12
transitions[0x0=>0x1]	36521	1			T3	9		T6	12		T13	10
transitions[0x1=>0x0]	36533	1			T3	9		T6	12		T13	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2641117	1			T1	101		T2	22		T3	2813
all_pins[0]	values[0x1]	324	1			T3	2		T6	3		T13	1
all_pins[0]	transitions[0x0=>0x1]	279	1			T3	2		T6	2		T17	3
all_pins[0]	transitions[0x1=>0x0]	269	1			T13	1		T17	2		T18	1
all_pins[1]	values[0x0]	2641127	1			T1	101		T2	22		T3	2815
all_pins[1]	values[0x1]	314	1			T6	1		T13	2		T17	2
all_pins[1]	transitions[0x0=>0x1]	255	1			T13	2		T18	1		T19	1
all_pins[1]	transitions[0x1=>0x0]	159	1			T3	1		T6	2		T13	2
all_pins[2]	values[0x0]	2641223	1			T1	101		T2	22		T3	2814
all_pins[2]	values[0x1]	218	1			T3	1		T6	3		T13	2
all_pins[2]	transitions[0x0=>0x1]	180	1			T3	1		T6	3		T13	2
all_pins[2]	transitions[0x1=>0x0]	135	1			T3	2		T13	3		T17	1
all_pins[3]	values[0x0]	2641268	1			T1	101		T2	22		T3	2813
all_pins[3]	values[0x1]	173	1			T3	2		T13	3		T17	2
all_pins[3]	transitions[0x0=>0x1]	135	1			T3	2		T13	3		T17	1
all_pins[3]	transitions[0x1=>0x0]	152	1			T6	1		T17	10		T18	1
all_pins[4]	values[0x0]	2641251	1			T1	101		T2	22		T3	2815
all_pins[4]	values[0x1]	190	1			T6	1		T17	11		T18	1
all_pins[4]	transitions[0x0=>0x1]	146	1			T6	1		T17	9		T18	1
all_pins[4]	transitions[0x1=>0x0]	1573	1			T3	2		T6	3		T13	2
all_pins[5]	values[0x0]	2639824	1			T1	101		T2	22		T3	2813
all_pins[5]	values[0x1]	1617	1			T3	2		T6	3		T13	2
all_pins[5]	transitions[0x0=>0x1]	552	1			T3	1		T6	3		T13	1
all_pins[5]	transitions[0x1=>0x0]	33827	1			T3	2		T6	3		T17	2
all_pins[6]	values[0x0]	2606549	1			T1	101		T2	22		T3	2812
all_pins[6]	values[0x1]	34892	1			T3	3		T6	3		T13	1
all_pins[6]	transitions[0x0=>0x1]	34845	1			T3	1		T6	1		T13	1
all_pins[6]	transitions[0x1=>0x0]	130	1			T6	1		T13	1		T17	3
all_pins[7]	values[0x0]	2641264	1			T1	101		T2	22		T3	2813
all_pins[7]	values[0x1]	177	1			T3	2		T6	3		T13	1
all_pins[7]	transitions[0x0=>0x1]	129	1			T3	2		T6	2		T13	1
all_pins[7]	transitions[0x1=>0x0]	288	1			T3	2		T6	2		T13	1