Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18184

1

T4

4

T6

28

T8

22

auto[1]

13594

1

T6

80

T13

92

T31

57

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3899	1			T13	60		T32	20		T40	18
values[1]	4388	1			T13	42		T31	20		T32	84
values[2]	3651	1			T4	4		T31	20		T237	10
values[3]	4745	1			T8	22		T13	87		T31	20
values[4]	3749	1			T11	14		T13	22		T31	40
values[5]	4061	1			T6	108		T12	12		T13	43
values[6]	3525	1			T39	12		T96	20		T107	14
values[7]	3760	1			T10	10		T13	23		T31	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3728	1			T13	21		T30	21		T41	41
values[1]	4571	1			T6	24		T10	10		T13	20
values[2]	3479	1			T13	22		T40	18		T238	2
values[3]	4236	1			T6	84		T13	23		T39	12
values[4]	4320	1			T8	22		T91	18		T96	20
values[5]	3632	1			T4	4		T13	43		T31	20
values[6]	3615	1			T11	14		T12	12		T13	105
values[7]	4197	1			T13	43		T31	20		T32	64

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	376	1			T19	9		T43	36		T198	18
auto[0]	values[0]	values[1]	406	1			T13	15		T32	11		T21	12
auto[0]	values[0]	values[2]	133	1			T172	11		T125	22		T132	10
auto[0]	values[0]	values[3]	283	1			T19	14		T212	15		T190	31
auto[0]	values[0]	values[4]	406	1			T229	24		T172	41		T76	68
auto[0]	values[0]	values[5]	323	1			T17	15		T200	11		T126	73
auto[0]	values[0]	values[6]	140	1			T13	11		T42	11		T190	10
auto[0]	values[0]	values[7]	228	1			T13	11		T210	6		T211	14
auto[0]	values[1]	values[0]	225	1			T18	13		T19	10		T76	16
auto[0]	values[1]	values[1]	350	1			T32	8		T214	9		T239	6
auto[0]	values[1]	values[2]	263	1			T238	2		T19	13		T21	12
auto[0]	values[1]	values[3]	210	1			T147	6		T230	16		T184	11
auto[0]	values[1]	values[4]	354	1			T19	12		T172	15		T211	32
auto[0]	values[1]	values[5]	329	1			T43	18		T76	15		T189	7
auto[0]	values[1]	values[6]	325	1			T13	33		T31	14		T19	15
auto[0]	values[1]	values[7]	534	1			T32	52		T172	23		T211	12
auto[0]	values[2]	values[0]	227	1			T240	8		T21	8		T172	11
auto[0]	values[2]	values[1]	207	1			T18	8		T184	12		T209	11
auto[0]	values[2]	values[2]	139	1			T184	16		T190	6		T214	13
auto[0]	values[2]	values[3]	318	1			T18	62		T211	8		T202	13
auto[0]	values[2]	values[4]	243	1			T241	12		T227	14		T76	6
auto[0]	values[2]	values[5]	271	1			T4	4		T31	11		T18	94
auto[0]	values[2]	values[6]	302	1			T172	12		T123	10		T125	21
auto[0]	values[2]	values[7]	309	1			T221	10		T173	16		T207	11
auto[0]	values[3]	values[0]	246	1			T13	16		T18	23		T242	14
auto[0]	values[3]	values[1]	445	1			T211	60		T209	9		T132	10
auto[0]	values[3]	values[2]	460	1			T243	4		T21	14		T189	22
auto[0]	values[3]	values[3]	357	1			T13	16		T18	12		T172	14
auto[0]	values[3]	values[4]	320	1			T8	22		T17	19		T200	12
auto[0]	values[3]	values[5]	313	1			T30	11		T172	9		T189	14
auto[0]	values[3]	values[6]	368	1			T13	31		T31	11		T202	15
auto[0]	values[3]	values[7]	312	1			T17	9		T18	11		T184	14
auto[0]	values[4]	values[0]	203	1			T18	46		T211	12		T244	16
auto[0]	values[4]	values[1]	142	1			T31	10		T41	17		T21	15
auto[0]	values[4]	values[2]	197	1			T13	13		T172	10		T76	12
auto[0]	values[4]	values[3]	401	1			T41	17		T245	16		T173	11
auto[0]	values[4]	values[4]	347	1			T18	15		T19	13		T173	73
auto[0]	values[4]	values[5]	281	1			T195	22		T43	14		T76	7
auto[0]	values[4]	values[6]	271	1			T11	14		T31	14		T41	14
auto[0]	values[4]	values[7]	346	1			T246	20		T247	12		T189	36
auto[0]	values[5]	values[0]	328	1			T30	17		T41	35		T43	14
auto[0]	values[5]	values[1]	253	1			T6	16		T17	16		T41	12
auto[0]	values[5]	values[2]	236	1			T41	11		T184	19		T123	10
auto[0]	values[5]	values[3]	225	1			T6	12		T225	14		T211	13
auto[0]	values[5]	values[4]	260	1			T91	18		T41	25		T19	13
auto[0]	values[5]	values[5]	214	1			T13	12		T17	10		T212	20
auto[0]	values[5]	values[6]	229	1			T12	12		T41	31		T173	23
auto[0]	values[5]	values[7]	437	1			T13	17		T18	34		T19	18
auto[0]	values[6]	values[0]	488	1			T19	11		T42	13		T76	38
auto[0]	values[6]	values[1]	392	1			T43	10		T211	88		T125	22
auto[0]	values[6]	values[2]	252	1			T211	19		T197	61		T187	24
auto[0]	values[6]	values[3]	269	1			T39	12		T18	10		T43	84
auto[0]	values[6]	values[4]	249	1			T96	20		T19	10		T196	13
auto[0]	values[6]	values[5]	139	1			T205	17		T185	18		T233	10
auto[0]	values[6]	values[6]	235	1			T107	14		T19	13		T214	12
auto[0]	values[6]	values[7]	174	1			T213	12		T209	8		T248	28
auto[0]	values[7]	values[0]	158	1			T189	15		T197	60		T132	11
auto[0]	values[7]	values[1]	319	1			T10	10		T31	11		T19	9
auto[0]	values[7]	values[2]	189	1			T18	9		T123	39		T249	15
auto[0]	values[7]	values[3]	328	1			T223	8		T76	90		T173	8
auto[0]	values[7]	values[4]	310	1			T30	11		T192	10		T202	10
auto[0]	values[7]	values[5]	151	1			T13	10		T32	22		T41	7
auto[0]	values[7]	values[6]	305	1			T42	7		T250	20		T184	12
auto[0]	values[7]	values[7]	134	1			T31	12		T251	4		T252	2
auto[1]	values[0]	values[0]	289	1			T19	11		T43	149		T234	7
auto[1]	values[0]	values[1]	262	1			T13	5		T32	9		T21	9
auto[1]	values[0]	values[2]	180	1			T40	18		T172	15		T125	15
auto[1]	values[0]	values[3]	327	1			T19	6		T212	10		T190	48
auto[1]	values[0]	values[4]	136	1			T172	10		T76	12		T184	9
auto[1]	values[0]	values[5]	154	1			T17	6		T200	9		T126	7
auto[1]	values[0]	values[6]	127	1			T13	9		T42	9		T190	10
auto[1]	values[0]	values[7]	129	1			T13	9		T211	10		T123	12
auto[1]	values[1]	values[0]	191	1			T18	7		T19	14		T76	4
auto[1]	values[1]	values[1]	200	1			T32	12		T214	17		T253	6
auto[1]	values[1]	values[2]	159	1			T19	9		T21	8		T76	3
auto[1]	values[1]	values[3]	163	1			T184	9		T212	10		T123	58
auto[1]	values[1]	values[4]	226	1			T19	9		T172	5		T211	7
auto[1]	values[1]	values[5]	412	1			T43	2		T76	56		T189	28
auto[1]	values[1]	values[6]	135	1			T13	9		T31	6		T19	8
auto[1]	values[1]	values[7]	312	1			T32	12		T172	31		T211	55
auto[1]	values[2]	values[0]	109	1			T21	12		T172	9		T126	6
auto[1]	values[2]	values[1]	274	1			T18	40		T44	18		T184	8
auto[1]	values[2]	values[2]	226	1			T237	10		T184	4		T190	14
auto[1]	values[2]	values[3]	146	1			T18	10		T211	42		T202	8
auto[1]	values[2]	values[4]	324	1			T76	128		T184	4		T209	34
auto[1]	values[2]	values[5]	154	1			T31	9		T18	9		T173	5
auto[1]	values[2]	values[6]	219	1			T172	8		T123	10		T125	9
auto[1]	values[2]	values[7]	183	1			T208	16		T45	16		T173	4
auto[1]	values[3]	values[0]	285	1			T13	5		T18	28		T126	35
auto[1]	values[3]	values[1]	281	1			T211	8		T209	65		T132	10
auto[1]	values[3]	values[2]	198	1			T21	6		T189	10		T209	15
auto[1]	values[3]	values[3]	335	1			T13	7		T18	12		T172	44
auto[1]	values[3]	values[4]	165	1			T17	6		T200	8		T125	9
auto[1]	values[3]	values[5]	209	1			T30	9		T172	51		T189	6
auto[1]	values[3]	values[6]	164	1			T13	12		T31	9		T202	6
auto[1]	values[3]	values[7]	287	1			T17	11		T18	9		T184	6
auto[1]	values[4]	values[0]	78	1			T18	3		T211	8		T254	7
auto[1]	values[4]	values[1]	177	1			T31	10		T41	8		T21	5
auto[1]	values[4]	values[2]	175	1			T13	9		T172	10		T76	8
auto[1]	values[4]	values[3]	176	1			T41	3		T173	9		T123	6
auto[1]	values[4]	values[4]	206	1			T18	8		T19	7		T173	6
auto[1]	values[4]	values[5]	208	1			T43	27		T76	13		T255	8
auto[1]	values[4]	values[6]	335	1			T31	6		T41	94		T205	9
auto[1]	values[4]	values[7]	206	1			T189	6		T256	8		T257	10
auto[1]	values[5]	values[0]	203	1			T30	4		T41	6		T43	6
auto[1]	values[5]	values[1]	275	1			T6	8		T17	4		T41	8
auto[1]	values[5]	values[2]	221	1			T41	9		T184	1		T123	24
auto[1]	values[5]	values[3]	280	1			T6	72		T211	7		T184	7
auto[1]	values[5]	values[4]	185	1			T41	8		T19	11		T212	12
auto[1]	values[5]	values[5]	237	1			T13	8		T17	11		T212	6
auto[1]	values[5]	values[6]	103	1			T41	9		T173	7		T209	5
auto[1]	values[5]	values[7]	375	1			T13	6		T18	7		T19	5
auto[1]	values[6]	values[0]	259	1			T19	10		T42	7		T76	8
auto[1]	values[6]	values[1]	167	1			T43	10		T211	4		T125	20
auto[1]	values[6]	values[2]	135	1			T211	12		T197	18		T217	13
auto[1]	values[6]	values[3]	212	1			T18	27		T43	25		T21	6
auto[1]	values[6]	values[4]	284	1			T19	18		T196	11		T123	14
auto[1]	values[6]	values[5]	101	1			T205	10		T233	10		T258	4
auto[1]	values[6]	values[6]	123	1			T19	9		T214	8		T218	19
auto[1]	values[6]	values[7]	46	1			T209	12		T132	9		T155	7
auto[1]	values[7]	values[0]	63	1			T189	8		T197	4		T132	13
auto[1]	values[7]	values[1]	421	1			T31	9		T19	11		T197	24
auto[1]	values[7]	values[2]	316	1			T18	27		T123	9		T249	18
auto[1]	values[7]	values[3]	206	1			T76	13		T173	12		T184	8
auto[1]	values[7]	values[4]	305	1			T30	17		T224	10		T202	10
auto[1]	values[7]	values[5]	136	1			T13	13		T32	8		T41	13
auto[1]	values[7]	values[6]	234	1			T42	13		T184	8		T125	35
auto[1]	values[7]	values[7]	185	1			T31	8		T259	8		T260	9