Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	426	1			T13	1		T32	1		T17	3
auto[ReadAddrCrossIntoMailbox]	269	1			T13	2		T41	8		T18	1
auto[ReadAddrCrossOutOfMailbox]	373	1			T6	1		T13	2		T41	4
auto[ReadAddrCrossAllMailbox]	229	1			T13	2		T32	2		T17	2
auto[ReadAddrOutsideMailbox]	3575	1			T6	5		T12	4		T13	43

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2442

1

T6

4

T12

2

T13

36

auto[1]

2430

1

T6

2

T12

2

T13

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	823	1			T13	14		T31	6		T32	3
read_ops[0x0b]	795	1			T13	6		T31	7		T32	4
read_ops[0x3b]	793	1			T6	1		T13	4		T39	4
read_ops[0x6b]	832	1			T6	4		T13	3		T31	5
read_ops[0xbb]	797	1			T12	4		T13	8		T31	6
read_ops[0xeb]	832	1			T6	1		T13	15		T31	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T18	2		T19	1		T21	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T172	1		T76	1		T173	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T76	1		T189	1		T190	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T41	3		T19	1		T212	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	37	1			T19	1		T223	1		T76	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T19	1		T223	1		T125	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T32	1		T17	1		T223	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T13	1		T43	1		T223	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T13	10		T31	3		T32	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T13	3		T31	3		T32	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T18	2		T223	1		T221	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T18	1		T43	1		T223	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T41	1		T19	1		T211	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T43	1		T202	1		T184	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T18	2		T211	1		T202	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T13	1		T212	1		T126	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T18	1		T19	1		T21	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T214	1		T215	1		T262	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T13	2		T31	3		T32	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T13	3		T31	4		T40	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T76	1		T184	1		T209	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T17	1		T18	2		T207	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T13	1		T41	1		T243	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T41	1		T243	1		T189	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T41	1		T21	1		T223	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	36	1			T18	1		T19	1		T223	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T243	1		T132	1		T218	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T19	1		T243	1		T76	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T13	3		T39	2		T31	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T6	1		T39	2		T31	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T18	1		T19	1		T43	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T17	2		T41	2		T209	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T43	2		T172	1		T184	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T41	1		T209	1		T263	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T18	1		T19	2		T76	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T6	1		T41	2		T42	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T32	1		T18	1		T19	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T125	1		T155	1		T157	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T6	3		T13	3		T31	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T40	1		T30	1		T17	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T18	1		T76	1		T173	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T32	1		T19	1		T202	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T18	1		T21	1		T172	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T189	1		T123	1		T214	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T41	1		T173	1		T184	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T123	1		T190	1		T206	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T19	1		T132	1		T214	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T17	1		T21	1		T200	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T12	2		T13	5		T31	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T12	2		T13	3		T31	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T13	1		T221	2		T173	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T221	2		T211	2		T155	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T41	1		T21	1		T173	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T13	1		T19	1		T215	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T13	1		T19	1		T172	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T18	1		T211	1		T202	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T13	1		T18	1		T202	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T18	1		T76	1		T211	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T6	1		T13	9		T31	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T13	2		T31	5		T32	1