Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3468	1			T13	40		T31	40		T32	64
values[1]	3639	1			T4	4		T31	20		T32	20
values[2]	4542	1			T6	84		T11	14		T13	41
values[3]	3679	1			T12	12		T13	45		T31	20
values[4]	3969	1			T31	60		T91	18		T147	6
values[5]	4442	1			T6	24		T8	22		T10	10
values[6]	3940	1			T13	20		T96	20		T41	20
values[7]	4099	1			T13	65		T32	30		T17	41

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4157	1			T10	10		T13	20		T31	40
values[1]	3403	1			T6	24		T13	21		T39	12
values[2]	3390	1			T13	20		T31	20		T41	25
values[3]	3898	1			T6	84		T13	20		T31	20
values[4]	3527	1			T4	4		T8	22		T13	88
values[5]	4048	1			T12	12		T32	20		T17	21
values[6]	4412	1			T11	14		T13	43		T31	40
values[7]	4943	1			T13	65		T30	20		T195	22

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30999

1

T4

4

T6

104

T8

22

auto[1]

779

1

T6

4

T13

5

T31

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	489	1			T31	20		T190	20		T193	18
auto[0]	values[0]	values[1]	253	1			T123	41		T133	22		T217	22
auto[0]	values[0]	values[2]	484	1			T13	19		T31	20		T19	24
auto[0]	values[0]	values[3]	403	1			T32	64		T237	10		T211	41
auto[0]	values[0]	values[4]	249	1			T19	20		T86	20		T87	14
auto[0]	values[0]	values[5]	568	1			T41	20		T221	10		T173	27
auto[0]	values[0]	values[6]	491	1			T13	20		T190	20		T86	20
auto[0]	values[0]	values[7]	449	1			T173	24		T209	74		T190	20
auto[0]	values[1]	values[0]	350	1			T211	20		T190	36		T264	12
auto[0]	values[1]	values[1]	560	1			T31	20		T19	20		T200	20
auto[0]	values[1]	values[2]	336	1			T41	25		T18	16		T172	57
auto[0]	values[1]	values[3]	402	1			T17	21		T18	37		T125	20
auto[0]	values[1]	values[4]	418	1			T4	4		T17	19		T224	10
auto[0]	values[1]	values[5]	423	1			T32	20		T21	40		T76	20
auto[0]	values[1]	values[6]	486	1			T18	48		T43	82		T213	12
auto[0]	values[1]	values[7]	575	1			T43	25		T76	77		T184	20
auto[0]	values[2]	values[0]	616	1			T19	20		T197	58		T198	18
auto[0]	values[2]	values[1]	276	1			T13	20		T123	20		T190	18
auto[0]	values[2]	values[2]	526	1			T172	20		T211	88		T212	18
auto[0]	values[2]	values[3]	626	1			T6	80		T13	20		T41	20
auto[0]	values[2]	values[4]	530	1			T40	14		T30	21		T241	12
auto[0]	values[2]	values[5]	394	1			T173	47		T265	2		T249	18
auto[0]	values[2]	values[6]	521	1			T11	14		T107	14		T211	39
auto[0]	values[2]	values[7]	949	1			T30	20		T41	107		T245	16
auto[0]	values[3]	values[0]	501	1			T31	20		T30	28		T227	14
auto[0]	values[3]	values[1]	374	1			T32	20		T212	45		T132	24
auto[0]	values[3]	values[2]	390	1			T229	24		T172	20		T211	30
auto[0]	values[3]	values[3]	460	1			T18	36		T19	21		T43	151
auto[0]	values[3]	values[4]	438	1			T13	22		T240	8		T200	20
auto[0]	values[3]	values[5]	576	1			T12	12		T43	53		T172	58
auto[0]	values[3]	values[6]	336	1			T13	23		T184	20		T212	20
auto[0]	values[3]	values[7]	493	1			T18	40		T76	103		T261	20
auto[0]	values[4]	values[0]	535	1			T172	33		T184	15		T189	30
auto[0]	values[4]	values[1]	487	1			T91	18		T19	20		T243	4
auto[0]	values[4]	values[2]	425	1			T172	20		T76	20		T266	2
auto[0]	values[4]	values[3]	436	1			T31	20		T147	6		T184	20
auto[0]	values[4]	values[4]	516	1			T18	44		T19	21		T76	134
auto[0]	values[4]	values[5]	299	1			T42	16		T212	21		T267	2
auto[0]	values[4]	values[6]	416	1			T31	38		T19	25		T172	64
auto[0]	values[4]	values[7]	737	1			T195	22		T17	25		T43	88
auto[0]	values[5]	values[0]	550	1			T10	10		T209	58		T212	20
auto[0]	values[5]	values[1]	567	1			T6	24		T39	12		T41	20
auto[0]	values[5]	values[2]	345	1			T251	4		T42	19		T209	50
auto[0]	values[5]	values[3]	527	1			T43	20		T21	20		T209	107
auto[0]	values[5]	values[4]	421	1			T8	22		T13	43		T21	18
auto[0]	values[5]	values[5]	640	1			T18	41		T196	22		T84	10
auto[0]	values[5]	values[6]	709	1			T41	40		T18	18		T208	16
auto[0]	values[5]	values[7]	595	1			T13	22		T242	14		T225	14
auto[0]	values[6]	values[0]	525	1			T13	20		T18	30		T211	87
auto[0]	values[6]	values[1]	427	1			T172	20		T189	21		T132	23
auto[0]	values[6]	values[2]	514	1			T43	38		T252	2		T212	26
auto[0]	values[6]	values[3]	283	1			T197	56		T132	22		T268	10
auto[0]	values[6]	values[4]	403	1			T96	20		T41	20		T19	20
auto[0]	values[6]	values[5]	433	1			T19	22		T172	52		T125	19
auto[0]	values[6]	values[6]	891	1			T44	16		T246	20		T76	46
auto[0]	values[6]	values[7]	374	1			T172	26		T76	20		T173	78
auto[0]	values[7]	values[0]	487	1			T19	23		T173	20		T209	20
auto[0]	values[7]	values[1]	363	1			T32	26		T269	14		T135	26
auto[0]	values[7]	values[2]	294	1			T42	19		T184	20		T190	52
auto[0]	values[7]	values[3]	664	1			T41	33		T18	51		T45	14
auto[0]	values[7]	values[4]	468	1			T13	21		T43	19		T250	20
auto[0]	values[7]	values[5]	628	1			T17	21		T18	47		T172	51
auto[0]	values[7]	values[6]	441	1			T41	41		T19	21		T216	20
auto[0]	values[7]	values[7]	657	1			T13	42		T17	20		T238	2
auto[1]	values[0]	values[0]	11	1			T193	2		T159	1		T161	1
auto[1]	values[0]	values[1]	10	1			T123	2		T133	2		T270	2
auto[1]	values[0]	values[2]	9	1			T13	1		T254	1		T271	2
auto[1]	values[0]	values[3]	9	1			T125	1		T133	3		T272	2
auto[1]	values[0]	values[4]	6	1			T132	2		T273	2		T274	2
auto[1]	values[0]	values[5]	13	1			T173	3		T155	2		T215	1
auto[1]	values[0]	values[6]	20	1			T206	4		T275	1		T222	1
auto[1]	values[0]	values[7]	4	1			T190	1		T276	2		T277	1
auto[1]	values[1]	values[0]	11	1			T190	1		T264	2		T214	1
auto[1]	values[1]	values[1]	14	1			T215	4		T194	1		T159	2
auto[1]	values[1]	values[2]	8	1			T18	4		T172	3		T189	1
auto[1]	values[1]	values[3]	11	1			T194	4		T139	2		T50	2
auto[1]	values[1]	values[4]	7	1			T17	1		T173	1		T205	2
auto[1]	values[1]	values[5]	6	1			T21	1		T202	1		T217	1
auto[1]	values[1]	values[6]	16	1			T18	1		T132	3		T222	1
auto[1]	values[1]	values[7]	16	1			T43	2		T76	2		T278	1
auto[1]	values[2]	values[0]	13	1			T197	1		T155	3		T218	1
auto[1]	values[2]	values[1]	8	1			T13	1		T190	2		T272	2
auto[1]	values[2]	values[2]	11	1			T211	4		T212	3		T278	1
auto[1]	values[2]	values[3]	17	1			T6	4		T19	2		T125	3
auto[1]	values[2]	values[4]	15	1			T40	4		T211	1		T212	4
auto[1]	values[2]	values[5]	7	1			T173	2		T249	2		T279	3
auto[1]	values[2]	values[6]	9	1			T209	2		T205	1		T214	1
auto[1]	values[2]	values[7]	24	1			T41	1		T123	3		T126	2
auto[1]	values[3]	values[0]	4	1			T189	1		T217	1		T257	1
auto[1]	values[3]	values[1]	18	1			T212	4		T233	1		T249	3
auto[1]	values[3]	values[2]	19	1			T211	1		T126	3		T133	4
auto[1]	values[3]	values[3]	20	1			T43	1		T184	1		T125	1
auto[1]	values[3]	values[4]	8	1			T123	1		T218	1		T278	3
auto[1]	values[3]	values[5]	12	1			T184	1		T278	1		T259	1
auto[1]	values[3]	values[6]	11	1			T253	1		T49	3		T258	1
auto[1]	values[3]	values[7]	19	1			T18	1		T255	4		T155	7
auto[1]	values[4]	values[0]	27	1			T172	1		T184	5		T189	2
auto[1]	values[4]	values[1]	16	1			T19	3		T125	3		T190	1
auto[1]	values[4]	values[2]	9	1			T280	1		T281	2		T138	1
auto[1]	values[4]	values[3]	8	1			T157	2		T260	1		T49	1
auto[1]	values[4]	values[4]	14	1			T19	3		T156	2		T222	1
auto[1]	values[4]	values[5]	14	1			T42	4		T212	5		T206	1
auto[1]	values[4]	values[6]	15	1			T31	2		T19	3		T172	1
auto[1]	values[4]	values[7]	15	1			T43	1		T207	2		T155	1
auto[1]	values[5]	values[0]	11	1			T209	2		T125	2		T282	2
auto[1]	values[5]	values[1]	8	1			T209	1		T283	2		T138	1
auto[1]	values[5]	values[2]	10	1			T42	1		T205	1		T284	1
auto[1]	values[5]	values[3]	10	1			T125	1		T132	1		T133	1
auto[1]	values[5]	values[4]	11	1			T21	2		T197	2		T285	3
auto[1]	values[5]	values[5]	13	1			T18	2		T196	2		T234	1
auto[1]	values[5]	values[6]	12	1			T18	2		T283	1		T281	1
auto[1]	values[5]	values[7]	13	1			T13	1		T214	3		T279	2
auto[1]	values[6]	values[0]	10	1			T18	1		T184	2		T282	1
auto[1]	values[6]	values[1]	11	1			T189	2		T253	2		T286	1
auto[1]	values[6]	values[2]	7	1			T43	3		T215	1		T287	1
auto[1]	values[6]	values[3]	8	1			T197	2		T275	2		T138	1
auto[1]	values[6]	values[4]	11	1			T19	2		T172	2		T184	2
auto[1]	values[6]	values[5]	8	1			T172	3		T125	1		T190	1
auto[1]	values[6]	values[6]	26	1			T44	2		T126	3		T135	4
auto[1]	values[6]	values[7]	9	1			T173	1		T288	1		T289	1
auto[1]	values[7]	values[0]	17	1			T126	2		T190	1		T214	5
auto[1]	values[7]	values[1]	11	1			T32	4		T135	1		T157	2
auto[1]	values[7]	values[2]	3	1			T42	1		T190	1		T159	1
auto[1]	values[7]	values[3]	14	1			T18	1		T45	2		T202	2
auto[1]	values[7]	values[4]	12	1			T13	2		T43	1		T123	2
auto[1]	values[7]	values[5]	14	1			T18	1		T209	1		T123	1
auto[1]	values[7]	values[6]	12	1			T249	2		T279	2		T29	4
auto[1]	values[7]	values[7]	14	1			T18	3		T125	3		T155	2