Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

Group : spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_prev_wr_en	2	0	2	100.00	100	1	1	2
cp_wr_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_write_enable_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	4	0	4	100.00	100	1	1	0

Summary for Variable cp_prev_wr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_prev_wr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2220

1

T1

10

T3

6

T6

4

auto[1]

638

1

T1

4

T3

1

T13

2

---

Summary for Variable cp_wr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1446

1

T1

6

T3

4

T6

2

auto[1]

1412

1

T1

8

T3

3

T6

2

---

Summary for Cross cr_all

Samples crossed: cp_wr_en cp_prev_wr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_wr_en

cp_prev_wr_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

1153

1

T1

5

T3

4

T6

2

auto[0]

auto[1]

293

1

T1

1

T47

2

T90

3

auto[1]

auto[0]

1067

1

T1

5

T3

2

T6

2

auto[1]

auto[1]

345

1

T1

3

T3

1

T13

2