Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	824	1			T3	11		T6	11		T13	11
all_values[1]	824	1			T3	11		T6	11		T13	11
all_values[2]	824	1			T3	11		T6	11		T13	11
all_values[3]	824	1			T3	11		T6	11		T13	11
all_values[4]	824	1			T3	11		T6	11		T13	11
all_values[5]	824	1			T3	11		T6	11		T13	11
all_values[6]	824	1			T3	11		T6	11		T13	11
all_values[7]	824	1			T3	11		T6	11		T13	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3507

1

T3

47

T6

46

T13

49

auto[1]

3085

1

T3

41

T6

42

T13

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2730

1

T3

46

T6

37

T13

49

auto[1]

3862

1

T3

42

T6

51

T13

39

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3790

1

T3

55

T6

50

T13

58

auto[1]

2802

1

T3

33

T6

38

T13

30

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	181	1			T3	6		T6	2		T13	1
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T6	1		T13	2		T17	5
all_values[0]	auto[0]	auto[1]	auto[0]	169	1			T13	2		T17	3		T18	6
all_values[0]	auto[0]	auto[1]	auto[1]	62	1			T6	1		T17	1		T18	1
all_values[0]	auto[1]	auto[0]	auto[1]	197	1			T3	3		T6	4		T13	4
all_values[0]	auto[1]	auto[1]	auto[1]	143	1			T3	2		T6	3		T13	2
all_values[1]	auto[0]	auto[0]	auto[0]	177	1			T3	6		T6	3		T13	4
all_values[1]	auto[0]	auto[0]	auto[1]	81	1			T13	1		T17	1		T18	2
all_values[1]	auto[0]	auto[1]	auto[0]	163	1			T3	3		T6	5		T13	1
all_values[1]	auto[0]	auto[1]	auto[1]	75	1			T6	2		T13	1		T17	1
all_values[1]	auto[1]	auto[0]	auto[1]	183	1			T3	2		T6	1		T13	2
all_values[1]	auto[1]	auto[1]	auto[1]	145	1			T13	2		T17	4		T20	2
all_values[2]	auto[0]	auto[0]	auto[0]	154	1			T3	5		T6	2		T17	4
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T6	1		T13	2		T17	4
all_values[2]	auto[0]	auto[1]	auto[0]	147	1			T3	4		T6	3		T13	3
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T6	1		T13	1		T17	1
all_values[2]	auto[1]	auto[0]	auto[1]	177	1			T13	2		T17	3		T18	1
all_values[2]	auto[1]	auto[1]	auto[1]	190	1			T3	2		T6	4		T13	3
all_values[3]	auto[0]	auto[0]	auto[0]	173	1			T3	2		T6	1		T13	1
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T3	2		T6	1		T17	2
all_values[3]	auto[0]	auto[1]	auto[0]	145	1			T3	2		T6	4		T13	3
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T3	1		T13	1		T19	2
all_values[3]	auto[1]	auto[0]	auto[1]	195	1			T3	3		T6	5		T13	3
all_values[3]	auto[1]	auto[1]	auto[1]	152	1			T3	1		T13	3		T17	2
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T3	3		T6	5		T13	5
all_values[4]	auto[0]	auto[0]	auto[1]	67	1			T3	1		T6	3		T17	1
all_values[4]	auto[0]	auto[1]	auto[0]	163	1			T3	3		T13	5		T18	3
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T17	3		T18	1		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	193	1			T3	4		T6	2		T13	1
all_values[4]	auto[1]	auto[1]	auto[1]	154	1			T6	1		T17	11		T18	2
all_values[5]	auto[0]	auto[0]	auto[0]	244	1			T3	2		T6	2		T13	2
all_values[5]	auto[0]	auto[1]	auto[0]	243	1			T3	5		T6	5		T13	6
all_values[5]	auto[1]	auto[0]	auto[1]	191	1			T3	1		T6	1		T13	3
all_values[5]	auto[1]	auto[1]	auto[1]	146	1			T3	3		T6	3		T17	4
all_values[6]	auto[0]	auto[0]	auto[0]	157	1			T3	1		T13	6		T17	2
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T3	1		T17	3		T18	2
all_values[6]	auto[0]	auto[1]	auto[0]	152	1			T3	2		T6	3		T13	3
all_values[6]	auto[0]	auto[1]	auto[1]	80	1			T6	2		T19	1		T21	2
all_values[6]	auto[1]	auto[0]	auto[1]	192	1			T6	5		T13	1		T17	4
all_values[6]	auto[1]	auto[1]	auto[1]	173	1			T3	7		T6	1		T13	1
all_values[7]	auto[0]	auto[0]	auto[0]	171	1			T6	2		T13	6		T17	6
all_values[7]	auto[0]	auto[0]	auto[1]	92	1			T3	3		T13	1		T18	1
all_values[7]	auto[0]	auto[1]	auto[0]	118	1			T3	2		T13	1		T17	3
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T3	1		T6	1		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	209	1			T3	2		T6	5		T13	2
all_values[7]	auto[1]	auto[1]	auto[1]	162	1			T3	3		T6	3		T13	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal