Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1687

1

T3

5

T5

3

T9

7

auto[1]

1781

1

T3

3

T5

6

T6

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1904

1

T3

7

T6

1

T13

4

auto[1]

1564

1

T3

1

T5

9

T9

21

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2701

1

T3

2

T5

9

T6

1

auto[1]

767

1

T3

6

T13

2

T23

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	713	1			T5	2		T9	4		T13	1
valid[1]	666	1			T3	3		T5	2		T9	5
valid[2]	709	1			T3	3		T5	1		T9	6
valid[3]	693	1			T3	1		T5	1		T9	1
valid[4]	687	1			T3	1		T5	3		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	115	1			T47	1		T19	3		T297	1
auto[0]	auto[0]	valid[0]	auto[1]	163	1			T5	1		T9	2		T23	1
auto[0]	auto[0]	valid[1]	auto[0]	104	1			T81	5		T296	3		T76	1
auto[0]	auto[0]	valid[1]	auto[1]	147	1			T9	2		T26	5		T82	5
auto[0]	auto[0]	valid[2]	auto[0]	112	1			T23	1		T30	2		T47	4
auto[0]	auto[0]	valid[2]	auto[1]	165	1			T3	1		T9	2		T16	2
auto[0]	auto[0]	valid[3]	auto[0]	105	1			T47	1		T18	2		T81	3
auto[0]	auto[0]	valid[3]	auto[1]	127	1			T16	1		T25	4		T26	5
auto[0]	auto[0]	valid[4]	auto[0]	107	1			T30	1		T47	1		T18	1
auto[0]	auto[0]	valid[4]	auto[1]	153	1			T5	2		T9	1		T16	2
auto[0]	auto[1]	valid[0]	auto[0]	126	1			T30	2		T47	3		T18	1
auto[0]	auto[1]	valid[0]	auto[1]	168	1			T5	1		T9	2		T13	1
auto[0]	auto[1]	valid[1]	auto[0]	96	1			T13	1		T81	3		T19	1
auto[0]	auto[1]	valid[1]	auto[1]	158	1			T5	2		T9	3		T16	1
auto[0]	auto[1]	valid[2]	auto[0]	106	1			T13	1		T17	1		T18	1
auto[0]	auto[1]	valid[2]	auto[1]	166	1			T5	1		T9	4		T25	1
auto[0]	auto[1]	valid[3]	auto[0]	148	1			T3	1		T30	1		T47	4
auto[0]	auto[1]	valid[3]	auto[1]	159	1			T5	1		T9	1		T25	3
auto[0]	auto[1]	valid[4]	auto[0]	118	1			T6	1		T47	1		T17	1
auto[0]	auto[1]	valid[4]	auto[1]	158	1			T5	1		T9	4		T16	4
auto[1]	auto[0]	valid[0]	auto[0]	75	1			T47	1		T17	1		T18	2
auto[1]	auto[0]	valid[1]	auto[0]	85	1			T3	2		T23	1		T17	1
auto[1]	auto[0]	valid[2]	auto[0]	75	1			T3	2		T17	1		T18	1
auto[1]	auto[0]	valid[3]	auto[0]	68	1			T17	1		T18	1		T19	1
auto[1]	auto[0]	valid[4]	auto[0]	86	1			T296	2		T306	1		T21	3
auto[1]	auto[1]	valid[0]	auto[0]	66	1			T23	1		T18	1		T19	2
auto[1]	auto[1]	valid[1]	auto[0]	76	1			T3	1		T47	1		T18	1
auto[1]	auto[1]	valid[2]	auto[0]	85	1			T13	1		T23	1		T17	1
auto[1]	auto[1]	valid[3]	auto[0]	86	1			T13	1		T23	1		T47	2
auto[1]	auto[1]	valid[4]	auto[0]	65	1			T3	1		T17	2		T81	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal