Summary for Variable cp_is_hw_return
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_is_hw_return
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48627 |
1 |
|
|
T3 |
223 |
|
T6 |
22 |
|
T7 |
3 |
auto[1] |
16885 |
1 |
|
|
T3 |
49 |
|
T5 |
9 |
|
T9 |
196 |
Summary for Variable cp_is_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_is_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47593 |
1 |
|
|
T3 |
177 |
|
T5 |
9 |
|
T6 |
15 |
auto[1] |
17919 |
1 |
|
|
T3 |
95 |
|
T6 |
7 |
|
T7 |
1 |
Summary for Variable cp_transfer_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
7 |
0 |
7 |
100.00 |
User Defined Bins for cp_transfer_size
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
others[0] |
33646 |
1 |
|
|
T3 |
141 |
|
T5 |
9 |
|
T6 |
12 |
others[1] |
5424 |
1 |
|
|
T3 |
29 |
|
T6 |
1 |
|
T9 |
17 |
others[2] |
5529 |
1 |
|
|
T3 |
21 |
|
T6 |
2 |
|
T7 |
1 |
others[3] |
6228 |
1 |
|
|
T3 |
22 |
|
T6 |
2 |
|
T9 |
14 |
interest[1] |
3699 |
1 |
|
|
T3 |
20 |
|
T6 |
2 |
|
T9 |
14 |
interest[4] |
21966 |
1 |
|
|
T3 |
94 |
|
T5 |
9 |
|
T6 |
9 |
interest[64] |
10986 |
1 |
|
|
T3 |
39 |
|
T6 |
3 |
|
T9 |
35 |
Summary for Cross cr_all
Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
21 |
0 |
21 |
100.00 |
|
Automatically Generated Cross Bins |
21 |
0 |
21 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cr_all
Bins
cp_is_write | cp_is_hw_return | cp_transfer_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
others[0] |
15643 |
1 |
|
|
T3 |
70 |
|
T6 |
8 |
|
T7 |
1 |
auto[0] |
auto[0] |
others[1] |
2554 |
1 |
|
|
T3 |
14 |
|
T13 |
11 |
|
T23 |
3 |
auto[0] |
auto[0] |
others[2] |
2589 |
1 |
|
|
T3 |
12 |
|
T6 |
2 |
|
T7 |
1 |
auto[0] |
auto[0] |
others[3] |
2962 |
1 |
|
|
T3 |
6 |
|
T6 |
2 |
|
T13 |
14 |
auto[0] |
auto[0] |
interest[1] |
1757 |
1 |
|
|
T3 |
8 |
|
T6 |
2 |
|
T13 |
8 |
auto[0] |
auto[0] |
interest[4] |
10163 |
1 |
|
|
T3 |
48 |
|
T6 |
6 |
|
T7 |
1 |
auto[0] |
auto[0] |
interest[64] |
5203 |
1 |
|
|
T3 |
18 |
|
T6 |
1 |
|
T13 |
26 |
auto[0] |
auto[1] |
others[0] |
8885 |
1 |
|
|
T3 |
24 |
|
T5 |
9 |
|
T9 |
96 |
auto[0] |
auto[1] |
others[1] |
1339 |
1 |
|
|
T3 |
6 |
|
T9 |
17 |
|
T13 |
8 |
auto[0] |
auto[1] |
others[2] |
1396 |
1 |
|
|
T3 |
4 |
|
T9 |
20 |
|
T13 |
5 |
auto[0] |
auto[1] |
others[3] |
1539 |
1 |
|
|
T3 |
5 |
|
T9 |
14 |
|
T13 |
4 |
auto[0] |
auto[1] |
interest[1] |
984 |
1 |
|
|
T3 |
5 |
|
T9 |
14 |
|
T13 |
2 |
auto[0] |
auto[1] |
interest[4] |
5852 |
1 |
|
|
T3 |
17 |
|
T5 |
9 |
|
T9 |
58 |
auto[0] |
auto[1] |
interest[64] |
2742 |
1 |
|
|
T3 |
5 |
|
T9 |
35 |
|
T13 |
8 |
auto[1] |
auto[0] |
others[0] |
9118 |
1 |
|
|
T3 |
47 |
|
T6 |
4 |
|
T7 |
1 |
auto[1] |
auto[0] |
others[1] |
1531 |
1 |
|
|
T3 |
9 |
|
T6 |
1 |
|
T13 |
7 |
auto[1] |
auto[0] |
others[2] |
1544 |
1 |
|
|
T3 |
5 |
|
T13 |
10 |
|
T23 |
5 |
auto[1] |
auto[0] |
others[3] |
1727 |
1 |
|
|
T3 |
11 |
|
T13 |
8 |
|
T23 |
2 |
auto[1] |
auto[0] |
interest[1] |
958 |
1 |
|
|
T3 |
7 |
|
T13 |
3 |
|
T23 |
3 |
auto[1] |
auto[0] |
interest[4] |
5951 |
1 |
|
|
T3 |
29 |
|
T6 |
3 |
|
T7 |
1 |
auto[1] |
auto[0] |
interest[64] |
3041 |
1 |
|
|
T3 |
16 |
|
T6 |
2 |
|
T13 |
22 |
User Defined Cross Bins for cr_all
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Illegal |