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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 94.01 98.62 89.36 97.21 95.45 99.26


Total test records in report: 1131
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T152 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.731582661 Jul 03 05:08:13 PM PDT 24 Jul 03 05:08:15 PM PDT 24 96685439 ps
T103 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3497651813 Jul 03 05:07:56 PM PDT 24 Jul 03 05:07:58 PM PDT 24 56886420 ps
T115 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.347011920 Jul 03 05:07:44 PM PDT 24 Jul 03 05:07:46 PM PDT 24 35311142 ps
T1030 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3338973303 Jul 03 05:07:53 PM PDT 24 Jul 03 05:07:56 PM PDT 24 60159666 ps
T100 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1463322968 Jul 03 05:08:08 PM PDT 24 Jul 03 05:08:11 PM PDT 24 165511138 ps
T1031 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.701062222 Jul 03 05:08:16 PM PDT 24 Jul 03 05:08:17 PM PDT 24 38956120 ps
T1032 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1964418063 Jul 03 05:08:00 PM PDT 24 Jul 03 05:08:02 PM PDT 24 15518594 ps
T1033 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.525842789 Jul 03 05:08:17 PM PDT 24 Jul 03 05:08:18 PM PDT 24 13977063 ps
T1034 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2191407117 Jul 03 05:08:12 PM PDT 24 Jul 03 05:08:14 PM PDT 24 88548271 ps
T181 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2422096979 Jul 03 05:08:03 PM PDT 24 Jul 03 05:08:27 PM PDT 24 853996167 ps
T116 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1642688043 Jul 03 05:07:49 PM PDT 24 Jul 03 05:08:13 PM PDT 24 929978545 ps
T1035 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1944599575 Jul 03 05:07:58 PM PDT 24 Jul 03 05:08:01 PM PDT 24 90784826 ps
T1036 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.86119065 Jul 03 05:08:13 PM PDT 24 Jul 03 05:08:15 PM PDT 24 29003588 ps
T1037 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1230452810 Jul 03 05:08:19 PM PDT 24 Jul 03 05:08:20 PM PDT 24 13466848 ps
T1038 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3704167296 Jul 03 05:07:41 PM PDT 24 Jul 03 05:07:43 PM PDT 24 168909839 ps
T183 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1278577818 Jul 03 05:07:47 PM PDT 24 Jul 03 05:07:54 PM PDT 24 512308967 ps
T104 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2356996152 Jul 03 05:07:46 PM PDT 24 Jul 03 05:07:50 PM PDT 24 62728522 ps
T1039 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2791999114 Jul 03 05:08:05 PM PDT 24 Jul 03 05:08:08 PM PDT 24 79201142 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3650087051 Jul 03 05:07:46 PM PDT 24 Jul 03 05:07:49 PM PDT 24 372432088 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1438058751 Jul 03 05:07:46 PM PDT 24 Jul 03 05:07:47 PM PDT 24 172268817 ps
T1040 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4184047611 Jul 03 05:08:16 PM PDT 24 Jul 03 05:08:17 PM PDT 24 30540096 ps
T149 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2027847645 Jul 03 05:07:53 PM PDT 24 Jul 03 05:07:57 PM PDT 24 583423335 ps
T1041 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1584507347 Jul 03 05:07:58 PM PDT 24 Jul 03 05:08:01 PM PDT 24 119174157 ps
T1042 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.811557206 Jul 03 05:07:51 PM PDT 24 Jul 03 05:07:52 PM PDT 24 16808013 ps
T1043 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3569716352 Jul 03 05:07:47 PM PDT 24 Jul 03 05:07:48 PM PDT 24 15932870 ps
T117 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2341466705 Jul 03 05:07:42 PM PDT 24 Jul 03 05:07:45 PM PDT 24 235866437 ps
T1044 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2176856554 Jul 03 05:07:55 PM PDT 24 Jul 03 05:07:56 PM PDT 24 26956044 ps
T178 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1196243833 Jul 03 05:07:44 PM PDT 24 Jul 03 05:08:03 PM PDT 24 598634505 ps
T1045 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1625717133 Jul 03 05:08:04 PM PDT 24 Jul 03 05:08:07 PM PDT 24 178328005 ps
T1046 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3828354664 Jul 03 05:07:56 PM PDT 24 Jul 03 05:07:59 PM PDT 24 155314357 ps
T1047 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.432228786 Jul 03 05:07:59 PM PDT 24 Jul 03 05:08:01 PM PDT 24 28866032 ps
T1048 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3303056059 Jul 03 05:08:20 PM PDT 24 Jul 03 05:08:21 PM PDT 24 137249505 ps
T179 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3774602761 Jul 03 05:08:02 PM PDT 24 Jul 03 05:08:24 PM PDT 24 978754899 ps
T118 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2276462422 Jul 03 05:08:02 PM PDT 24 Jul 03 05:08:05 PM PDT 24 239883842 ps
T1049 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2951701051 Jul 03 05:08:11 PM PDT 24 Jul 03 05:08:12 PM PDT 24 55890909 ps
T1050 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3048813091 Jul 03 05:07:45 PM PDT 24 Jul 03 05:07:58 PM PDT 24 636073825 ps
T150 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1750784962 Jul 03 05:07:58 PM PDT 24 Jul 03 05:08:13 PM PDT 24 622545311 ps
T182 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3199635249 Jul 03 05:07:52 PM PDT 24 Jul 03 05:08:14 PM PDT 24 3314386690 ps
T1051 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3184314929 Jul 03 05:08:08 PM PDT 24 Jul 03 05:08:11 PM PDT 24 79187283 ps
T1052 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3043577640 Jul 03 05:07:51 PM PDT 24 Jul 03 05:07:52 PM PDT 24 11973636 ps
T1053 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3495124260 Jul 03 05:07:40 PM PDT 24 Jul 03 05:07:44 PM PDT 24 124253619 ps
T1054 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.378320891 Jul 03 05:07:58 PM PDT 24 Jul 03 05:08:01 PM PDT 24 47243142 ps
T1055 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.615753163 Jul 03 05:08:17 PM PDT 24 Jul 03 05:08:19 PM PDT 24 33835193 ps
T99 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1699495351 Jul 03 05:08:05 PM PDT 24 Jul 03 05:08:08 PM PDT 24 50931688 ps
T1056 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.305814384 Jul 03 05:07:59 PM PDT 24 Jul 03 05:08:01 PM PDT 24 65615961 ps
T79 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4276377784 Jul 03 05:07:48 PM PDT 24 Jul 03 05:07:51 PM PDT 24 181123937 ps
T1057 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2008990665 Jul 03 05:08:19 PM PDT 24 Jul 03 05:08:20 PM PDT 24 18214626 ps
T1058 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3918549781 Jul 03 05:08:08 PM PDT 24 Jul 03 05:08:12 PM PDT 24 482637881 ps
T1059 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1799637528 Jul 03 05:08:10 PM PDT 24 Jul 03 05:08:12 PM PDT 24 34079835 ps
T1060 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2827868418 Jul 03 05:08:03 PM PDT 24 Jul 03 05:08:05 PM PDT 24 17401157 ps
T174 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.600891923 Jul 03 05:07:45 PM PDT 24 Jul 03 05:07:50 PM PDT 24 280730630 ps
T1061 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1857377344 Jul 03 05:08:20 PM PDT 24 Jul 03 05:08:21 PM PDT 24 14623091 ps
T1062 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.347666376 Jul 03 05:08:17 PM PDT 24 Jul 03 05:08:25 PM PDT 24 3512804422 ps
T151 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1863741440 Jul 03 05:07:47 PM PDT 24 Jul 03 05:07:55 PM PDT 24 747388784 ps
T1063 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.153031882 Jul 03 05:07:38 PM PDT 24 Jul 03 05:07:39 PM PDT 24 49167623 ps
T153 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2559555771 Jul 03 05:08:01 PM PDT 24 Jul 03 05:08:06 PM PDT 24 1527254213 ps
T1064 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3339543451 Jul 03 05:08:07 PM PDT 24 Jul 03 05:08:08 PM PDT 24 46401605 ps
T1065 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1991183946 Jul 03 05:08:19 PM PDT 24 Jul 03 05:08:20 PM PDT 24 21967799 ps
T1066 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.485162021 Jul 03 05:08:20 PM PDT 24 Jul 03 05:08:21 PM PDT 24 21950070 ps
T1067 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3982987320 Jul 03 05:08:12 PM PDT 24 Jul 03 05:08:13 PM PDT 24 13604006 ps
T1068 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.685555627 Jul 03 05:07:59 PM PDT 24 Jul 03 05:08:01 PM PDT 24 39096393 ps
T1069 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2718333787 Jul 03 05:08:00 PM PDT 24 Jul 03 05:08:02 PM PDT 24 35169678 ps
T1070 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.949502313 Jul 03 05:07:44 PM PDT 24 Jul 03 05:08:19 PM PDT 24 1810269303 ps
T1071 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1101972015 Jul 03 05:07:53 PM PDT 24 Jul 03 05:07:56 PM PDT 24 62422084 ps
T101 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.963998056 Jul 03 05:07:56 PM PDT 24 Jul 03 05:08:19 PM PDT 24 1055935011 ps
T1072 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4270578286 Jul 03 05:08:15 PM PDT 24 Jul 03 05:08:15 PM PDT 24 24326526 ps
T1073 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4138973801 Jul 03 05:08:09 PM PDT 24 Jul 03 05:08:11 PM PDT 24 199578987 ps
T1074 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2068561973 Jul 03 05:08:02 PM PDT 24 Jul 03 05:08:05 PM PDT 24 402628265 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2257295425 Jul 03 05:07:45 PM PDT 24 Jul 03 05:07:50 PM PDT 24 219250964 ps
T1076 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4044723549 Jul 03 05:08:16 PM PDT 24 Jul 03 05:08:19 PM PDT 24 105886669 ps
T1077 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3262704722 Jul 03 05:07:51 PM PDT 24 Jul 03 05:07:55 PM PDT 24 461890651 ps
T176 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2301545044 Jul 03 05:08:00 PM PDT 24 Jul 03 05:08:17 PM PDT 24 1286956078 ps
T1078 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1849706318 Jul 03 05:08:06 PM PDT 24 Jul 03 05:08:08 PM PDT 24 27826035 ps
T105 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3935513340 Jul 03 05:07:56 PM PDT 24 Jul 03 05:08:00 PM PDT 24 113142704 ps
T80 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1684613844 Jul 03 05:07:41 PM PDT 24 Jul 03 05:07:42 PM PDT 24 24424317 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1499382097 Jul 03 05:07:48 PM PDT 24 Jul 03 05:07:51 PM PDT 24 174613008 ps
T1080 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3356079855 Jul 03 05:08:06 PM PDT 24 Jul 03 05:08:10 PM PDT 24 61785336 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3227425808 Jul 03 05:07:47 PM PDT 24 Jul 03 05:08:09 PM PDT 24 368652431 ps
T1082 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2070638090 Jul 03 05:08:14 PM PDT 24 Jul 03 05:08:15 PM PDT 24 55879259 ps
T1083 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2480974117 Jul 03 05:07:55 PM PDT 24 Jul 03 05:07:56 PM PDT 24 30897741 ps
T1084 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.383976963 Jul 03 05:07:50 PM PDT 24 Jul 03 05:07:52 PM PDT 24 42411860 ps
T1085 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1919220439 Jul 03 05:08:17 PM PDT 24 Jul 03 05:08:18 PM PDT 24 45938810 ps
T1086 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.223391399 Jul 03 05:08:12 PM PDT 24 Jul 03 05:08:14 PM PDT 24 88426329 ps
T1087 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1067440806 Jul 03 05:07:53 PM PDT 24 Jul 03 05:07:56 PM PDT 24 115839898 ps
T1088 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.287264490 Jul 03 05:08:19 PM PDT 24 Jul 03 05:08:20 PM PDT 24 32319318 ps
T1089 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2817207635 Jul 03 05:08:04 PM PDT 24 Jul 03 05:08:08 PM PDT 24 521693814 ps
T1090 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1016997743 Jul 03 05:08:18 PM PDT 24 Jul 03 05:08:19 PM PDT 24 45329284 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2777097427 Jul 03 05:07:44 PM PDT 24 Jul 03 05:07:48 PM PDT 24 130954080 ps
T1092 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2614339468 Jul 03 05:07:58 PM PDT 24 Jul 03 05:08:00 PM PDT 24 224263802 ps
T175 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3488585336 Jul 03 05:07:55 PM PDT 24 Jul 03 05:08:00 PM PDT 24 179841211 ps
T1093 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.273188976 Jul 03 05:08:03 PM PDT 24 Jul 03 05:08:17 PM PDT 24 739730020 ps
T1094 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2346392858 Jul 03 05:08:13 PM PDT 24 Jul 03 05:08:14 PM PDT 24 36792773 ps
T1095 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2229883933 Jul 03 05:08:15 PM PDT 24 Jul 03 05:08:18 PM PDT 24 579229325 ps
T1096 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2196339829 Jul 03 05:07:54 PM PDT 24 Jul 03 05:08:06 PM PDT 24 373105494 ps
T1097 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2171450086 Jul 03 05:08:01 PM PDT 24 Jul 03 05:08:17 PM PDT 24 2226286062 ps
T1098 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2659372816 Jul 03 05:07:59 PM PDT 24 Jul 03 05:08:02 PM PDT 24 155950169 ps
T1099 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.51921728 Jul 03 05:07:54 PM PDT 24 Jul 03 05:08:03 PM PDT 24 322806667 ps
T1100 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4084402721 Jul 03 05:08:17 PM PDT 24 Jul 03 05:08:18 PM PDT 24 15094175 ps
T1101 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3370636955 Jul 03 05:07:58 PM PDT 24 Jul 03 05:08:00 PM PDT 24 41981503 ps
T1102 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.763780478 Jul 03 05:08:06 PM PDT 24 Jul 03 05:08:09 PM PDT 24 75869891 ps
T1103 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1562403103 Jul 03 05:07:51 PM PDT 24 Jul 03 05:07:52 PM PDT 24 47109795 ps
T1104 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2759900335 Jul 03 05:07:49 PM PDT 24 Jul 03 05:07:54 PM PDT 24 312354230 ps
T1105 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3649612102 Jul 03 05:08:12 PM PDT 24 Jul 03 05:08:13 PM PDT 24 30116389 ps
T1106 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2487992946 Jul 03 05:07:37 PM PDT 24 Jul 03 05:07:55 PM PDT 24 309161665 ps
T1107 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2070509660 Jul 03 05:07:55 PM PDT 24 Jul 03 05:07:57 PM PDT 24 70000573 ps
T1108 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3171393917 Jul 03 05:07:54 PM PDT 24 Jul 03 05:08:13 PM PDT 24 1397754198 ps
T1109 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4103004051 Jul 03 05:08:12 PM PDT 24 Jul 03 05:08:13 PM PDT 24 114378868 ps
T1110 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3412257420 Jul 03 05:08:20 PM PDT 24 Jul 03 05:08:21 PM PDT 24 25619349 ps
T1111 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1621309487 Jul 03 05:08:20 PM PDT 24 Jul 03 05:08:21 PM PDT 24 17599517 ps
T1112 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2227685217 Jul 03 05:08:19 PM PDT 24 Jul 03 05:08:20 PM PDT 24 15772087 ps
T1113 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2434411824 Jul 03 05:08:17 PM PDT 24 Jul 03 05:08:18 PM PDT 24 57935632 ps
T1114 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3461438222 Jul 03 05:07:45 PM PDT 24 Jul 03 05:07:46 PM PDT 24 47139173 ps
T1115 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2799970706 Jul 03 05:07:46 PM PDT 24 Jul 03 05:07:47 PM PDT 24 107252071 ps
T1116 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2965049275 Jul 03 05:08:21 PM PDT 24 Jul 03 05:08:22 PM PDT 24 37114803 ps
T180 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1328029119 Jul 03 05:08:08 PM PDT 24 Jul 03 05:08:31 PM PDT 24 2418635435 ps
T1117 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1364182422 Jul 03 05:08:00 PM PDT 24 Jul 03 05:08:04 PM PDT 24 88082786 ps
T1118 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2339978129 Jul 03 05:08:01 PM PDT 24 Jul 03 05:08:03 PM PDT 24 68117830 ps
T1119 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3750914692 Jul 03 05:07:44 PM PDT 24 Jul 03 05:07:49 PM PDT 24 275250823 ps
T1120 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2327903627 Jul 03 05:07:50 PM PDT 24 Jul 03 05:08:04 PM PDT 24 3746801037 ps
T1121 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2610655235 Jul 03 05:08:03 PM PDT 24 Jul 03 05:08:06 PM PDT 24 113590842 ps
T177 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2775722674 Jul 03 05:08:13 PM PDT 24 Jul 03 05:08:38 PM PDT 24 13832193396 ps
T1122 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1683552177 Jul 03 05:07:44 PM PDT 24 Jul 03 05:08:00 PM PDT 24 3057272627 ps
T1123 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.509898452 Jul 03 05:07:37 PM PDT 24 Jul 03 05:07:42 PM PDT 24 687189450 ps
T1124 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1659227916 Jul 03 05:08:14 PM PDT 24 Jul 03 05:08:17 PM PDT 24 256617698 ps
T1125 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3226948610 Jul 03 05:08:01 PM PDT 24 Jul 03 05:08:04 PM PDT 24 191589006 ps
T1126 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2408315451 Jul 03 05:07:56 PM PDT 24 Jul 03 05:08:00 PM PDT 24 526418500 ps
T1127 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3055299625 Jul 03 05:07:41 PM PDT 24 Jul 03 05:07:42 PM PDT 24 13865177 ps
T1128 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3212861037 Jul 03 05:08:00 PM PDT 24 Jul 03 05:08:20 PM PDT 24 1276758602 ps
T1129 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1861808338 Jul 03 05:07:48 PM PDT 24 Jul 03 05:08:05 PM PDT 24 2933818860 ps
T1130 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.897300104 Jul 03 05:08:00 PM PDT 24 Jul 03 05:08:05 PM PDT 24 1867442083 ps
T1131 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.122578500 Jul 03 05:08:08 PM PDT 24 Jul 03 05:08:11 PM PDT 24 222186630 ps

Test location /workspace/coverage/default/35.spi_device_stress_all.870577866
Short name T3
Test name
Test status
Simulation time 16899009449 ps
CPU time 62.01 seconds
Started Jul 03 05:18:42 PM PDT 24
Finished Jul 03 05:19:45 PM PDT 24
Peak memory 253100 kb
Host smart-51eab37a-45eb-4570-9896-5d364a0ad0cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870577866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.870577866
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2855362068
Short name T13
Test name
Test status
Simulation time 22505654232 ps
CPU time 164.33 seconds
Started Jul 03 05:18:29 PM PDT 24
Finished Jul 03 05:21:14 PM PDT 24
Peak memory 256568 kb
Host smart-50a20901-f409-4946-b35f-21cdcc9c7c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855362068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2855362068
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1031589149
Short name T19
Test name
Test status
Simulation time 210094831734 ps
CPU time 972.25 seconds
Started Jul 03 05:17:51 PM PDT 24
Finished Jul 03 05:34:04 PM PDT 24
Peak memory 268272 kb
Host smart-23fa6c96-e5a8-446f-bf8f-ec2a9e4adb40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031589149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1031589149
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3511165236
Short name T95
Test name
Test status
Simulation time 1879303997 ps
CPU time 21.39 seconds
Started Jul 03 05:07:46 PM PDT 24
Finished Jul 03 05:08:08 PM PDT 24
Peak memory 215956 kb
Host smart-663e4bc1-0c58-4987-973d-3fd1ab46ed54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511165236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3511165236
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2525915517
Short name T76
Test name
Test status
Simulation time 38922387948 ps
CPU time 191.63 seconds
Started Jul 03 05:16:48 PM PDT 24
Finished Jul 03 05:20:00 PM PDT 24
Peak memory 271028 kb
Host smart-3b5df315-466e-4d73-8c04-091c5ca094f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525915517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2525915517
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2039260111
Short name T68
Test name
Test status
Simulation time 16086894 ps
CPU time 0.74 seconds
Started Jul 03 05:16:39 PM PDT 24
Finished Jul 03 05:16:41 PM PDT 24
Peak memory 216072 kb
Host smart-d5e1696e-4169-4e0b-acdf-6b772ace8452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039260111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2039260111
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3237247392
Short name T18
Test name
Test status
Simulation time 43074083919 ps
CPU time 158.02 seconds
Started Jul 03 05:18:00 PM PDT 24
Finished Jul 03 05:20:38 PM PDT 24
Peak memory 272864 kb
Host smart-6acba7fa-b38f-40fe-b6fb-503560596c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237247392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3237247392
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3201783339
Short name T155
Test name
Test status
Simulation time 25912337899 ps
CPU time 326.51 seconds
Started Jul 03 05:18:47 PM PDT 24
Finished Jul 03 05:24:14 PM PDT 24
Peak memory 265676 kb
Host smart-a0e1a15a-00f9-49a0-87c9-da70788c2219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201783339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3201783339
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2559298358
Short name T93
Test name
Test status
Simulation time 295246441 ps
CPU time 4.91 seconds
Started Jul 03 05:08:06 PM PDT 24
Finished Jul 03 05:08:11 PM PDT 24
Peak memory 215968 kb
Host smart-d8d2d322-ba4b-4906-bca1-48d1f8bf56c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559298358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2559298358
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.548794165
Short name T212
Test name
Test status
Simulation time 101333578527 ps
CPU time 712.15 seconds
Started Jul 03 05:17:25 PM PDT 24
Finished Jul 03 05:29:18 PM PDT 24
Peak memory 270752 kb
Host smart-fb8fc2df-dce8-4cc8-bbbc-714d0fef9da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548794165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.548794165
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3144646750
Short name T14
Test name
Test status
Simulation time 89157091 ps
CPU time 1.24 seconds
Started Jul 03 05:16:55 PM PDT 24
Finished Jul 03 05:16:56 PM PDT 24
Peak memory 237632 kb
Host smart-0e137b99-229d-456c-ac4a-add8c3f3abaa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144646750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3144646750
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2140310631
Short name T132
Test name
Test status
Simulation time 488597951870 ps
CPU time 462.8 seconds
Started Jul 03 05:18:51 PM PDT 24
Finished Jul 03 05:26:35 PM PDT 24
Peak memory 256504 kb
Host smart-dfe9eda1-1542-4ee3-8ac4-fae468d7a7be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140310631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2140310631
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.174913640
Short name T144
Test name
Test status
Simulation time 3290935566 ps
CPU time 20.36 seconds
Started Jul 03 05:18:31 PM PDT 24
Finished Jul 03 05:18:52 PM PDT 24
Peak memory 236176 kb
Host smart-393f5194-125e-4b3f-9942-2c35ad880641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174913640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.174913640
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1439514648
Short name T214
Test name
Test status
Simulation time 21730648338 ps
CPU time 335.55 seconds
Started Jul 03 05:17:24 PM PDT 24
Finished Jul 03 05:23:01 PM PDT 24
Peak memory 281028 kb
Host smart-1083d031-65ea-4160-933e-5549359b8252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439514648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1439514648
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.488741294
Short name T184
Test name
Test status
Simulation time 11952378296 ps
CPU time 77.69 seconds
Started Jul 03 05:17:00 PM PDT 24
Finished Jul 03 05:18:18 PM PDT 24
Peak memory 265088 kb
Host smart-c7a1aaf0-cdc6-4d5d-b02d-7d5e717c1ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488741294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
488741294
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1156373588
Short name T114
Test name
Test status
Simulation time 1598061558 ps
CPU time 16.14 seconds
Started Jul 03 05:07:48 PM PDT 24
Finished Jul 03 05:08:05 PM PDT 24
Peak memory 215708 kb
Host smart-3e4527c8-20e8-435d-9296-c3898b53636f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156373588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1156373588
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3688283558
Short name T21
Test name
Test status
Simulation time 81159768035 ps
CPU time 696.21 seconds
Started Jul 03 05:16:54 PM PDT 24
Finished Jul 03 05:28:32 PM PDT 24
Peak memory 265644 kb
Host smart-bc42a371-61da-4925-b842-00dde8947c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688283558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3688283558
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3177878765
Short name T209
Test name
Test status
Simulation time 292539679948 ps
CPU time 249.92 seconds
Started Jul 03 05:18:20 PM PDT 24
Finished Jul 03 05:22:30 PM PDT 24
Peak memory 267108 kb
Host smart-487e5784-12e7-4901-9c2c-1d09d6d72a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177878765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3177878765
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.363301435
Short name T49
Test name
Test status
Simulation time 59602891685 ps
CPU time 268.95 seconds
Started Jul 03 05:18:02 PM PDT 24
Finished Jul 03 05:22:32 PM PDT 24
Peak memory 254516 kb
Host smart-d4dd5848-1461-4f4b-9b82-68b2af369d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363301435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.363301435
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3000925652
Short name T135
Test name
Test status
Simulation time 4621207080 ps
CPU time 110.76 seconds
Started Jul 03 05:17:35 PM PDT 24
Finished Jul 03 05:19:26 PM PDT 24
Peak memory 269232 kb
Host smart-376143fe-95db-46dc-90ff-51244dd9c55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000925652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3000925652
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3901641975
Short name T123
Test name
Test status
Simulation time 6126129854 ps
CPU time 121.28 seconds
Started Jul 03 05:17:10 PM PDT 24
Finished Jul 03 05:19:11 PM PDT 24
Peak memory 269048 kb
Host smart-e22780a9-9970-4193-92d6-34501aebe68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901641975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3901641975
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1731595271
Short name T636
Test name
Test status
Simulation time 58307246835 ps
CPU time 394.87 seconds
Started Jul 03 05:18:32 PM PDT 24
Finished Jul 03 05:25:08 PM PDT 24
Peak memory 263680 kb
Host smart-01a699b0-89db-447e-be32-643c3df6d14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731595271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1731595271
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.747627422
Short name T277
Test name
Test status
Simulation time 69093955096 ps
CPU time 467.78 seconds
Started Jul 03 05:16:49 PM PDT 24
Finished Jul 03 05:24:37 PM PDT 24
Peak memory 262588 kb
Host smart-47caf993-e8a0-44f0-956e-25b4763055e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747627422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.747627422
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3177367439
Short name T319
Test name
Test status
Simulation time 92821974 ps
CPU time 0.76 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:18:06 PM PDT 24
Peak memory 205504 kb
Host smart-7c990a48-c6aa-4142-aada-5f77a87097dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177367439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3177367439
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.808942255
Short name T28
Test name
Test status
Simulation time 383307954216 ps
CPU time 1012.04 seconds
Started Jul 03 05:18:26 PM PDT 24
Finished Jul 03 05:35:19 PM PDT 24
Peak memory 301320 kb
Host smart-ddb7fdad-abb8-4fe3-b996-0e617d6bc921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808942255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.808942255
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2481360552
Short name T9
Test name
Test status
Simulation time 10530165123 ps
CPU time 7.95 seconds
Started Jul 03 05:19:08 PM PDT 24
Finished Jul 03 05:19:16 PM PDT 24
Peak memory 216344 kb
Host smart-f3f0e26f-7da7-4178-8825-c61dd185fbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481360552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2481360552
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.963998056
Short name T101
Test name
Test status
Simulation time 1055935011 ps
CPU time 22.77 seconds
Started Jul 03 05:07:56 PM PDT 24
Finished Jul 03 05:08:19 PM PDT 24
Peak memory 216200 kb
Host smart-48898a33-b8d7-4223-ac4c-a58c236b5c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963998056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.963998056
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2160764799
Short name T190
Test name
Test status
Simulation time 46448848830 ps
CPU time 181.11 seconds
Started Jul 03 05:18:00 PM PDT 24
Finished Jul 03 05:21:02 PM PDT 24
Peak memory 265676 kb
Host smart-2ee4d2cf-9039-4681-87b9-f4ea55300601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160764799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2160764799
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.637273820
Short name T31
Test name
Test status
Simulation time 5661176838 ps
CPU time 80.6 seconds
Started Jul 03 05:18:37 PM PDT 24
Finished Jul 03 05:19:59 PM PDT 24
Peak memory 251396 kb
Host smart-77728ade-4ee8-46b5-b130-31a2aaa723a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637273820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.637273820
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1113037676
Short name T913
Test name
Test status
Simulation time 123657946369 ps
CPU time 655.32 seconds
Started Jul 03 05:17:41 PM PDT 24
Finished Jul 03 05:28:37 PM PDT 24
Peak memory 285332 kb
Host smart-11c3b090-f9d3-4850-8e04-f274cf5e6fd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113037676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1113037676
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1118725671
Short name T159
Test name
Test status
Simulation time 291033177301 ps
CPU time 456.13 seconds
Started Jul 03 05:18:24 PM PDT 24
Finished Jul 03 05:26:00 PM PDT 24
Peak memory 257076 kb
Host smart-87d53ed6-1298-47ed-a6dd-94b3cc663074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118725671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1118725671
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1079746990
Short name T293
Test name
Test status
Simulation time 2107420827 ps
CPU time 17.66 seconds
Started Jul 03 05:18:27 PM PDT 24
Finished Jul 03 05:18:45 PM PDT 24
Peak memory 242560 kb
Host smart-cbb408ff-f10f-4d88-b37d-da0ee991fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079746990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1079746990
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.4288106184
Short name T1
Test name
Test status
Simulation time 1230263717 ps
CPU time 27.38 seconds
Started Jul 03 05:19:09 PM PDT 24
Finished Jul 03 05:19:37 PM PDT 24
Peak memory 251940 kb
Host smart-4b891b6a-1389-492d-8881-de1086c5cf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288106184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.4288106184
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2525025294
Short name T30
Test name
Test status
Simulation time 23152496138 ps
CPU time 74.96 seconds
Started Jul 03 05:17:31 PM PDT 24
Finished Jul 03 05:18:46 PM PDT 24
Peak memory 249236 kb
Host smart-0e6b2ab1-4177-49e1-bec6-b6844eb285ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525025294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2525025294
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.600891923
Short name T174
Test name
Test status
Simulation time 280730630 ps
CPU time 3.81 seconds
Started Jul 03 05:07:45 PM PDT 24
Finished Jul 03 05:07:50 PM PDT 24
Peak memory 215988 kb
Host smart-d3781241-16e8-4c6d-a8fe-ca079df56937
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600891923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.600891923
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1196243833
Short name T178
Test name
Test status
Simulation time 598634505 ps
CPU time 18.85 seconds
Started Jul 03 05:07:44 PM PDT 24
Finished Jul 03 05:08:03 PM PDT 24
Peak memory 216028 kb
Host smart-01606ce0-42c3-4ef7-99d2-97cf07dcb48d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196243833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1196243833
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1015796206
Short name T161
Test name
Test status
Simulation time 287587802536 ps
CPU time 639.56 seconds
Started Jul 03 05:16:41 PM PDT 24
Finished Jul 03 05:27:21 PM PDT 24
Peak memory 269524 kb
Host smart-5e024db8-ab75-4874-a205-e750198eed09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015796206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1015796206
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.810412995
Short name T279
Test name
Test status
Simulation time 144298287421 ps
CPU time 702.2 seconds
Started Jul 03 05:17:22 PM PDT 24
Finished Jul 03 05:29:05 PM PDT 24
Peak memory 273572 kb
Host smart-4f2089c3-9235-4ebc-89ce-b1fa9f7a8677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810412995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.810412995
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2791274756
Short name T290
Test name
Test status
Simulation time 368968440 ps
CPU time 6.12 seconds
Started Jul 03 05:18:14 PM PDT 24
Finished Jul 03 05:18:21 PM PDT 24
Peak memory 224440 kb
Host smart-9af537a3-be04-4c22-b0d7-bf6c05da78fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791274756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2791274756
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2227508357
Short name T301
Test name
Test status
Simulation time 2732532933 ps
CPU time 57.06 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:19:39 PM PDT 24
Peak memory 241060 kb
Host smart-4e0e40e9-a4f0-48db-89f6-e18999e8ae8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227508357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2227508357
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1328029119
Short name T180
Test name
Test status
Simulation time 2418635435 ps
CPU time 22.6 seconds
Started Jul 03 05:08:08 PM PDT 24
Finished Jul 03 05:08:31 PM PDT 24
Peak memory 215848 kb
Host smart-c36f8b48-c53d-4435-a7bb-269781db652e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328029119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1328029119
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3095071197
Short name T189
Test name
Test status
Simulation time 35920674083 ps
CPU time 239.87 seconds
Started Jul 03 05:17:25 PM PDT 24
Finished Jul 03 05:21:25 PM PDT 24
Peak memory 256304 kb
Host smart-cb0f6efd-61a4-487b-bee1-ed2270766390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095071197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3095071197
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3438961012
Short name T81
Test name
Test status
Simulation time 59528227617 ps
CPU time 47.07 seconds
Started Jul 03 05:17:17 PM PDT 24
Finished Jul 03 05:18:04 PM PDT 24
Peak memory 216408 kb
Host smart-0635c211-bbe9-4f0b-97cd-21611f06e3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438961012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3438961012
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.637109776
Short name T86
Test name
Test status
Simulation time 26325053423 ps
CPU time 95.23 seconds
Started Jul 03 05:17:34 PM PDT 24
Finished Jul 03 05:19:10 PM PDT 24
Peak memory 249192 kb
Host smart-6ff2c578-4261-415b-8d9a-eb4db15e2ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637109776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.637109776
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1164996263
Short name T91
Test name
Test status
Simulation time 9587595535 ps
CPU time 16.49 seconds
Started Jul 03 05:17:09 PM PDT 24
Finished Jul 03 05:17:26 PM PDT 24
Peak memory 239832 kb
Host smart-3f1feeaa-7a5f-44a6-a64e-f5b45904cc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164996263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1164996263
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1397452328
Short name T78
Test name
Test status
Simulation time 41137090 ps
CPU time 1.35 seconds
Started Jul 03 05:07:44 PM PDT 24
Finished Jul 03 05:07:46 PM PDT 24
Peak memory 215684 kb
Host smart-7d30dfae-51e4-4ef7-a5f7-18ac87a913fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397452328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1397452328
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1117345300
Short name T89
Test name
Test status
Simulation time 7709648385 ps
CPU time 79.49 seconds
Started Jul 03 05:19:10 PM PDT 24
Finished Jul 03 05:20:30 PM PDT 24
Peak memory 252616 kb
Host smart-a61b4e7c-d6f9-4494-8695-089c4281dfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117345300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1117345300
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.509898452
Short name T1123
Test name
Test status
Simulation time 687189450 ps
CPU time 4.96 seconds
Started Jul 03 05:07:37 PM PDT 24
Finished Jul 03 05:07:42 PM PDT 24
Peak memory 216132 kb
Host smart-a188e921-e431-438a-93ae-07efa989b1e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509898452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.509898452
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1683552177
Short name T1122
Test name
Test status
Simulation time 3057272627 ps
CPU time 16.11 seconds
Started Jul 03 05:07:44 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 215704 kb
Host smart-12d2169a-8e87-4263-bc82-0eb19737c949
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683552177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1683552177
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.949502313
Short name T1070
Test name
Test status
Simulation time 1810269303 ps
CPU time 34.99 seconds
Started Jul 03 05:07:44 PM PDT 24
Finished Jul 03 05:08:19 PM PDT 24
Peak memory 207384 kb
Host smart-d4bbd1cc-2a47-4b3a-a51a-99fd05f2fe88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949502313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.949502313
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2799970706
Short name T1115
Test name
Test status
Simulation time 107252071 ps
CPU time 1.19 seconds
Started Jul 03 05:07:46 PM PDT 24
Finished Jul 03 05:07:47 PM PDT 24
Peak memory 207412 kb
Host smart-41cb43e8-7703-415c-84d9-e55e053ef708
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799970706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2799970706
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.752612201
Short name T106
Test name
Test status
Simulation time 63662674 ps
CPU time 1.76 seconds
Started Jul 03 05:07:41 PM PDT 24
Finished Jul 03 05:07:43 PM PDT 24
Peak memory 215784 kb
Host smart-a72afd38-f028-4665-a21f-6dc890e0d070
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752612201 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.752612201
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2341466705
Short name T117
Test name
Test status
Simulation time 235866437 ps
CPU time 2.01 seconds
Started Jul 03 05:07:42 PM PDT 24
Finished Jul 03 05:07:45 PM PDT 24
Peak memory 215736 kb
Host smart-cca82bb4-c9ac-466f-bf6f-cb08a0351889
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341466705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
341466705
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.153031882
Short name T1063
Test name
Test status
Simulation time 49167623 ps
CPU time 0.68 seconds
Started Jul 03 05:07:38 PM PDT 24
Finished Jul 03 05:07:39 PM PDT 24
Peak memory 204604 kb
Host smart-519a38c5-1405-4e77-a5de-c24cef2384c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153031882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.153031882
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3016605221
Short name T111
Test name
Test status
Simulation time 53560270 ps
CPU time 1.18 seconds
Started Jul 03 05:07:42 PM PDT 24
Finished Jul 03 05:07:43 PM PDT 24
Peak memory 215788 kb
Host smart-e1c85411-ce68-42d1-8fe3-b8f0169b0969
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016605221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3016605221
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2565783484
Short name T1012
Test name
Test status
Simulation time 20798374 ps
CPU time 0.63 seconds
Started Jul 03 05:07:37 PM PDT 24
Finished Jul 03 05:07:39 PM PDT 24
Peak memory 204444 kb
Host smart-fa2a046b-268e-45d3-a544-258693ce1e6f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565783484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2565783484
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3495124260
Short name T1053
Test name
Test status
Simulation time 124253619 ps
CPU time 3.82 seconds
Started Jul 03 05:07:40 PM PDT 24
Finished Jul 03 05:07:44 PM PDT 24
Peak memory 215836 kb
Host smart-23dd2abd-9fe6-4cdf-8748-4fe50f3f005f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495124260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3495124260
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2487992946
Short name T1106
Test name
Test status
Simulation time 309161665 ps
CPU time 17.35 seconds
Started Jul 03 05:07:37 PM PDT 24
Finished Jul 03 05:07:55 PM PDT 24
Peak memory 215812 kb
Host smart-5f96065b-a520-4b98-a8a4-c8df7fa62309
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487992946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2487992946
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3048813091
Short name T1050
Test name
Test status
Simulation time 636073825 ps
CPU time 12.98 seconds
Started Jul 03 05:07:45 PM PDT 24
Finished Jul 03 05:07:58 PM PDT 24
Peak memory 207412 kb
Host smart-fc0287ed-1e10-46b4-84bd-7c0e6bff3ffe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048813091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3048813091
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1684613844
Short name T80
Test name
Test status
Simulation time 24424317 ps
CPU time 0.98 seconds
Started Jul 03 05:07:41 PM PDT 24
Finished Jul 03 05:07:42 PM PDT 24
Peak memory 207204 kb
Host smart-d6611914-ed82-437b-9ba5-1a30f05f0870
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684613844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1684613844
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3686639398
Short name T1028
Test name
Test status
Simulation time 333231964 ps
CPU time 2.65 seconds
Started Jul 03 05:07:46 PM PDT 24
Finished Jul 03 05:07:49 PM PDT 24
Peak memory 218512 kb
Host smart-29f9c28e-5bf1-479e-81ea-06df6413bdd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686639398 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3686639398
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3704167296
Short name T1038
Test name
Test status
Simulation time 168909839 ps
CPU time 1.47 seconds
Started Jul 03 05:07:41 PM PDT 24
Finished Jul 03 05:07:43 PM PDT 24
Peak memory 207472 kb
Host smart-53198a88-2636-48a0-a09d-6f9ed880f506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704167296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
704167296
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3461438222
Short name T1114
Test name
Test status
Simulation time 47139173 ps
CPU time 0.73 seconds
Started Jul 03 05:07:45 PM PDT 24
Finished Jul 03 05:07:46 PM PDT 24
Peak memory 204536 kb
Host smart-784e09f9-993e-4280-8056-849207dc4aaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461438222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
461438222
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.347011920
Short name T115
Test name
Test status
Simulation time 35311142 ps
CPU time 1.3 seconds
Started Jul 03 05:07:44 PM PDT 24
Finished Jul 03 05:07:46 PM PDT 24
Peak memory 215672 kb
Host smart-a64c0b47-45de-488b-b267-e83bfa3a2d00
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347011920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.347011920
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3055299625
Short name T1127
Test name
Test status
Simulation time 13865177 ps
CPU time 0.67 seconds
Started Jul 03 05:07:41 PM PDT 24
Finished Jul 03 05:07:42 PM PDT 24
Peak memory 204400 kb
Host smart-1f522db6-6a8d-4fe5-8d7e-c17b93b3a5a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055299625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3055299625
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2257295425
Short name T1075
Test name
Test status
Simulation time 219250964 ps
CPU time 4.46 seconds
Started Jul 03 05:07:45 PM PDT 24
Finished Jul 03 05:07:50 PM PDT 24
Peak memory 215840 kb
Host smart-17474d5c-1809-4ef3-b014-3ce63db3e805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257295425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2257295425
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2777097427
Short name T1091
Test name
Test status
Simulation time 130954080 ps
CPU time 4.28 seconds
Started Jul 03 05:07:44 PM PDT 24
Finished Jul 03 05:07:48 PM PDT 24
Peak memory 216028 kb
Host smart-7e7237a9-9ffa-42c1-884f-46b202c16c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777097427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
777097427
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.432228786
Short name T1047
Test name
Test status
Simulation time 28866032 ps
CPU time 1.78 seconds
Started Jul 03 05:07:59 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 217056 kb
Host smart-9b985024-db44-4d73-b8ed-c34e6191386d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432228786 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.432228786
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2276462422
Short name T118
Test name
Test status
Simulation time 239883842 ps
CPU time 1.94 seconds
Started Jul 03 05:08:02 PM PDT 24
Finished Jul 03 05:08:05 PM PDT 24
Peak memory 215708 kb
Host smart-dd169ee0-2a25-448c-965c-b6a7b4516544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276462422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2276462422
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2339978129
Short name T1118
Test name
Test status
Simulation time 68117830 ps
CPU time 0.8 seconds
Started Jul 03 05:08:01 PM PDT 24
Finished Jul 03 05:08:03 PM PDT 24
Peak memory 204264 kb
Host smart-08a82d1d-86f0-434d-a3f8-9ed499cdafa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339978129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2339978129
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4094569919
Short name T148
Test name
Test status
Simulation time 887103309 ps
CPU time 3.77 seconds
Started Jul 03 05:08:01 PM PDT 24
Finished Jul 03 05:08:06 PM PDT 24
Peak memory 215716 kb
Host smart-75aa300b-9e88-4c20-93b1-6a34175db9d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094569919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4094569919
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1257071961
Short name T98
Test name
Test status
Simulation time 92711501 ps
CPU time 1.84 seconds
Started Jul 03 05:08:01 PM PDT 24
Finished Jul 03 05:08:04 PM PDT 24
Peak memory 216072 kb
Host smart-8749a24b-85a6-4797-88ba-da782970b957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257071961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1257071961
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2301545044
Short name T176
Test name
Test status
Simulation time 1286956078 ps
CPU time 16.69 seconds
Started Jul 03 05:08:00 PM PDT 24
Finished Jul 03 05:08:17 PM PDT 24
Peak memory 215760 kb
Host smart-446c33e7-02f2-4253-be60-73f22291d5b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301545044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2301545044
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2068561973
Short name T1074
Test name
Test status
Simulation time 402628265 ps
CPU time 2.74 seconds
Started Jul 03 05:08:02 PM PDT 24
Finished Jul 03 05:08:05 PM PDT 24
Peak memory 217732 kb
Host smart-e8b00630-83e8-4fa8-b658-7d2e91e1e05c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068561973 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2068561973
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4158120876
Short name T1023
Test name
Test status
Simulation time 36520933 ps
CPU time 1.33 seconds
Started Jul 03 05:07:59 PM PDT 24
Finished Jul 03 05:08:02 PM PDT 24
Peak memory 207524 kb
Host smart-ba7d2296-de4c-46f6-8569-3299266b9824
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158120876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4158120876
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.685555627
Short name T1068
Test name
Test status
Simulation time 39096393 ps
CPU time 0.76 seconds
Started Jul 03 05:07:59 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 204576 kb
Host smart-a800b9f3-de72-41bd-9fb1-6648711cef6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685555627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.685555627
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.897300104
Short name T1130
Test name
Test status
Simulation time 1867442083 ps
CPU time 3.11 seconds
Started Jul 03 05:08:00 PM PDT 24
Finished Jul 03 05:08:05 PM PDT 24
Peak memory 215780 kb
Host smart-5578872d-38db-494b-af3f-b3f053ddc2dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897300104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.897300104
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.233866987
Short name T102
Test name
Test status
Simulation time 602042355 ps
CPU time 3.71 seconds
Started Jul 03 05:07:58 PM PDT 24
Finished Jul 03 05:08:02 PM PDT 24
Peak memory 216072 kb
Host smart-1485da05-d499-42ea-afa0-3358d3376d48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233866987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.233866987
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3774602761
Short name T179
Test name
Test status
Simulation time 978754899 ps
CPU time 21.35 seconds
Started Jul 03 05:08:02 PM PDT 24
Finished Jul 03 05:08:24 PM PDT 24
Peak memory 215732 kb
Host smart-cf373239-cb96-4f77-b659-0c05f22e8113
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774602761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3774602761
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1364182422
Short name T1117
Test name
Test status
Simulation time 88082786 ps
CPU time 2.48 seconds
Started Jul 03 05:08:00 PM PDT 24
Finished Jul 03 05:08:04 PM PDT 24
Peak memory 217616 kb
Host smart-6a4e2db8-c000-47b5-8b93-4fc70229c1da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364182422 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1364182422
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1218955502
Short name T1014
Test name
Test status
Simulation time 79450113 ps
CPU time 1.4 seconds
Started Jul 03 05:08:00 PM PDT 24
Finished Jul 03 05:08:03 PM PDT 24
Peak memory 215652 kb
Host smart-ee0f9e6f-6f29-4c0b-9c92-e9799613871e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218955502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1218955502
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1964418063
Short name T1032
Test name
Test status
Simulation time 15518594 ps
CPU time 0.75 seconds
Started Jul 03 05:08:00 PM PDT 24
Finished Jul 03 05:08:02 PM PDT 24
Peak memory 204268 kb
Host smart-0f557dd8-0e44-43d3-a090-f45f8d68c289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964418063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1964418063
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2559555771
Short name T153
Test name
Test status
Simulation time 1527254213 ps
CPU time 4.03 seconds
Started Jul 03 05:08:01 PM PDT 24
Finished Jul 03 05:08:06 PM PDT 24
Peak memory 215780 kb
Host smart-3c8d452e-5932-435f-89fd-2ce24e12d001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559555771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2559555771
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3226948610
Short name T1125
Test name
Test status
Simulation time 191589006 ps
CPU time 2.48 seconds
Started Jul 03 05:08:01 PM PDT 24
Finished Jul 03 05:08:04 PM PDT 24
Peak memory 215924 kb
Host smart-7fef7b8d-95f5-4512-88ee-f0b70eb0f757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226948610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3226948610
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2171450086
Short name T1097
Test name
Test status
Simulation time 2226286062 ps
CPU time 15.05 seconds
Started Jul 03 05:08:01 PM PDT 24
Finished Jul 03 05:08:17 PM PDT 24
Peak memory 217312 kb
Host smart-c6f37305-156c-49d9-b17e-be488ecf54d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171450086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2171450086
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1625717133
Short name T1045
Test name
Test status
Simulation time 178328005 ps
CPU time 2.55 seconds
Started Jul 03 05:08:04 PM PDT 24
Finished Jul 03 05:08:07 PM PDT 24
Peak memory 217080 kb
Host smart-d3fa5958-a995-4a7b-9f43-d94b120e7be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625717133 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1625717133
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1925105181
Short name T113
Test name
Test status
Simulation time 226347287 ps
CPU time 1.78 seconds
Started Jul 03 05:08:07 PM PDT 24
Finished Jul 03 05:08:09 PM PDT 24
Peak memory 215756 kb
Host smart-92d6f02e-0887-4134-a825-210821d5344e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925105181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1925105181
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3051597944
Short name T1021
Test name
Test status
Simulation time 46031907 ps
CPU time 0.72 seconds
Started Jul 03 05:07:59 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 204264 kb
Host smart-10f6c902-b662-41bd-9cce-56172dec9eff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051597944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3051597944
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1849706318
Short name T1078
Test name
Test status
Simulation time 27826035 ps
CPU time 1.88 seconds
Started Jul 03 05:08:06 PM PDT 24
Finished Jul 03 05:08:08 PM PDT 24
Peak memory 207532 kb
Host smart-b815a239-a67b-4bc6-9c00-92818e523093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849706318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1849706318
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.31012856
Short name T97
Test name
Test status
Simulation time 115016645 ps
CPU time 1.8 seconds
Started Jul 03 05:08:02 PM PDT 24
Finished Jul 03 05:08:05 PM PDT 24
Peak memory 216016 kb
Host smart-02755a2e-4a8e-43da-8205-1ac66565fb6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31012856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.31012856
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3212861037
Short name T1128
Test name
Test status
Simulation time 1276758602 ps
CPU time 18.64 seconds
Started Jul 03 05:08:00 PM PDT 24
Finished Jul 03 05:08:20 PM PDT 24
Peak memory 215816 kb
Host smart-77bdcc10-af90-4479-ad18-219a1afafe27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212861037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3212861037
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2817207635
Short name T1089
Test name
Test status
Simulation time 521693814 ps
CPU time 3.8 seconds
Started Jul 03 05:08:04 PM PDT 24
Finished Jul 03 05:08:08 PM PDT 24
Peak memory 217924 kb
Host smart-c22c607f-91d4-47e3-9375-3dc9ea89ee7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817207635 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2817207635
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.763780478
Short name T1102
Test name
Test status
Simulation time 75869891 ps
CPU time 2.65 seconds
Started Jul 03 05:08:06 PM PDT 24
Finished Jul 03 05:08:09 PM PDT 24
Peak memory 215604 kb
Host smart-8797e223-85bf-49da-a5ec-199859257ec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763780478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.763780478
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1341657859
Short name T1011
Test name
Test status
Simulation time 16941688 ps
CPU time 0.77 seconds
Started Jul 03 05:08:06 PM PDT 24
Finished Jul 03 05:08:07 PM PDT 24
Peak memory 204624 kb
Host smart-1c152c70-a577-4a5a-9f2a-5da82272c221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341657859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1341657859
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3356079855
Short name T1080
Test name
Test status
Simulation time 61785336 ps
CPU time 3.79 seconds
Started Jul 03 05:08:06 PM PDT 24
Finished Jul 03 05:08:10 PM PDT 24
Peak memory 215816 kb
Host smart-bb40a01a-45db-49a1-a231-1ae2c2974362
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356079855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3356079855
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2422096979
Short name T181
Test name
Test status
Simulation time 853996167 ps
CPU time 22.55 seconds
Started Jul 03 05:08:03 PM PDT 24
Finished Jul 03 05:08:27 PM PDT 24
Peak memory 215856 kb
Host smart-b2047c9e-37cf-4612-9503-c878462d7745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422096979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2422096979
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3918549781
Short name T1058
Test name
Test status
Simulation time 482637881 ps
CPU time 3.54 seconds
Started Jul 03 05:08:08 PM PDT 24
Finished Jul 03 05:08:12 PM PDT 24
Peak memory 219032 kb
Host smart-d7315998-8b95-4118-9090-9bb1cfb33f34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918549781 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3918549781
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2791999114
Short name T1039
Test name
Test status
Simulation time 79201142 ps
CPU time 2.58 seconds
Started Jul 03 05:08:05 PM PDT 24
Finished Jul 03 05:08:08 PM PDT 24
Peak memory 215568 kb
Host smart-65f940c6-37e8-4f96-a7f8-13cc89f0c4e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791999114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2791999114
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2827868418
Short name T1060
Test name
Test status
Simulation time 17401157 ps
CPU time 0.75 seconds
Started Jul 03 05:08:03 PM PDT 24
Finished Jul 03 05:08:05 PM PDT 24
Peak memory 204164 kb
Host smart-868fc30f-3572-4a72-8344-2ef93f37b036
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827868418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2827868418
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2610655235
Short name T1121
Test name
Test status
Simulation time 113590842 ps
CPU time 3.11 seconds
Started Jul 03 05:08:03 PM PDT 24
Finished Jul 03 05:08:06 PM PDT 24
Peak memory 215720 kb
Host smart-513586c3-54c4-4e62-b0d9-66c735bb9f53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610655235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2610655235
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1699495351
Short name T99
Test name
Test status
Simulation time 50931688 ps
CPU time 3.13 seconds
Started Jul 03 05:08:05 PM PDT 24
Finished Jul 03 05:08:08 PM PDT 24
Peak memory 215944 kb
Host smart-1ccf27c4-4763-42a9-b9b1-243be0897e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699495351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1699495351
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.273188976
Short name T1093
Test name
Test status
Simulation time 739730020 ps
CPU time 12.66 seconds
Started Jul 03 05:08:03 PM PDT 24
Finished Jul 03 05:08:17 PM PDT 24
Peak memory 216184 kb
Host smart-67a8f2a3-3b28-416e-9f12-ec0f9bf25f34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273188976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.273188976
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3779506603
Short name T67
Test name
Test status
Simulation time 59106574 ps
CPU time 3.88 seconds
Started Jul 03 05:08:16 PM PDT 24
Finished Jul 03 05:08:20 PM PDT 24
Peak memory 218552 kb
Host smart-e5266b5f-b3b9-4a73-b641-e028cdfdb903
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779506603 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3779506603
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1799637528
Short name T1059
Test name
Test status
Simulation time 34079835 ps
CPU time 1.15 seconds
Started Jul 03 05:08:10 PM PDT 24
Finished Jul 03 05:08:12 PM PDT 24
Peak memory 207472 kb
Host smart-d68b8042-60dc-4c46-b58c-36f3f6d31ac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799637528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1799637528
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3339543451
Short name T1064
Test name
Test status
Simulation time 46401605 ps
CPU time 0.69 seconds
Started Jul 03 05:08:07 PM PDT 24
Finished Jul 03 05:08:08 PM PDT 24
Peak memory 204260 kb
Host smart-a2676e56-c4df-4f9a-9059-f95f9b4fe051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339543451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3339543451
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.122578500
Short name T1131
Test name
Test status
Simulation time 222186630 ps
CPU time 2.83 seconds
Started Jul 03 05:08:08 PM PDT 24
Finished Jul 03 05:08:11 PM PDT 24
Peak memory 215692 kb
Host smart-229c1e53-73dd-4293-add8-48488cc477cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122578500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.122578500
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1463322968
Short name T100
Test name
Test status
Simulation time 165511138 ps
CPU time 3.21 seconds
Started Jul 03 05:08:08 PM PDT 24
Finished Jul 03 05:08:11 PM PDT 24
Peak memory 216000 kb
Host smart-7a19e0be-d936-4509-8640-8bc7781cb9bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463322968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1463322968
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2191407117
Short name T1034
Test name
Test status
Simulation time 88548271 ps
CPU time 1.6 seconds
Started Jul 03 05:08:12 PM PDT 24
Finished Jul 03 05:08:14 PM PDT 24
Peak memory 217032 kb
Host smart-91ef0260-2f45-424a-8dd7-4a28fcdb90b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191407117 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2191407117
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4138973801
Short name T1073
Test name
Test status
Simulation time 199578987 ps
CPU time 1.85 seconds
Started Jul 03 05:08:09 PM PDT 24
Finished Jul 03 05:08:11 PM PDT 24
Peak memory 215652 kb
Host smart-4c5281a8-9417-423f-98ce-178d5261da84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138973801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4138973801
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3982987320
Short name T1067
Test name
Test status
Simulation time 13604006 ps
CPU time 0.77 seconds
Started Jul 03 05:08:12 PM PDT 24
Finished Jul 03 05:08:13 PM PDT 24
Peak memory 204248 kb
Host smart-0b00f163-67c5-47ff-acf9-c1a6c1e194c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982987320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3982987320
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.615753163
Short name T1055
Test name
Test status
Simulation time 33835193 ps
CPU time 1.62 seconds
Started Jul 03 05:08:17 PM PDT 24
Finished Jul 03 05:08:19 PM PDT 24
Peak memory 207512 kb
Host smart-a18cc572-a64f-4287-97fd-6729226ca3e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615753163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.615753163
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3184314929
Short name T1051
Test name
Test status
Simulation time 79187283 ps
CPU time 2.21 seconds
Started Jul 03 05:08:08 PM PDT 24
Finished Jul 03 05:08:11 PM PDT 24
Peak memory 215912 kb
Host smart-81f66dd5-8d92-43fa-b45e-e26e81d809b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184314929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3184314929
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1724360320
Short name T94
Test name
Test status
Simulation time 4208463473 ps
CPU time 19.57 seconds
Started Jul 03 05:08:10 PM PDT 24
Finished Jul 03 05:08:29 PM PDT 24
Peak memory 216040 kb
Host smart-a7f25b4d-85a7-45c5-9ac1-df5da3b7ca11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724360320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1724360320
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.731582661
Short name T152
Test name
Test status
Simulation time 96685439 ps
CPU time 1.64 seconds
Started Jul 03 05:08:13 PM PDT 24
Finished Jul 03 05:08:15 PM PDT 24
Peak memory 215904 kb
Host smart-e3cbe6b1-b052-4527-a829-775c8361e701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731582661 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.731582661
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.86119065
Short name T1036
Test name
Test status
Simulation time 29003588 ps
CPU time 1.34 seconds
Started Jul 03 05:08:13 PM PDT 24
Finished Jul 03 05:08:15 PM PDT 24
Peak memory 207520 kb
Host smart-94495ef6-cb0e-4593-8b06-6650bd78f023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86119065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.86119065
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.735058566
Short name T1010
Test name
Test status
Simulation time 23783649 ps
CPU time 0.73 seconds
Started Jul 03 05:08:15 PM PDT 24
Finished Jul 03 05:08:16 PM PDT 24
Peak memory 204220 kb
Host smart-ec36082c-53b3-469b-af16-1effaee5b5e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735058566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.735058566
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4044723549
Short name T1076
Test name
Test status
Simulation time 105886669 ps
CPU time 2.97 seconds
Started Jul 03 05:08:16 PM PDT 24
Finished Jul 03 05:08:19 PM PDT 24
Peak memory 215720 kb
Host smart-aa7178c1-6f53-4d1d-b8fd-6043d7205514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044723549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4044723549
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1659227916
Short name T1124
Test name
Test status
Simulation time 256617698 ps
CPU time 3.14 seconds
Started Jul 03 05:08:14 PM PDT 24
Finished Jul 03 05:08:17 PM PDT 24
Peak memory 219680 kb
Host smart-2e74621f-4abc-4108-ba03-b243f8b47b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659227916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1659227916
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2775722674
Short name T177
Test name
Test status
Simulation time 13832193396 ps
CPU time 24.57 seconds
Started Jul 03 05:08:13 PM PDT 24
Finished Jul 03 05:08:38 PM PDT 24
Peak memory 217104 kb
Host smart-c4a81ba7-5053-4441-8027-ff307a80aabe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775722674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2775722674
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2229883933
Short name T1095
Test name
Test status
Simulation time 579229325 ps
CPU time 3.43 seconds
Started Jul 03 05:08:15 PM PDT 24
Finished Jul 03 05:08:18 PM PDT 24
Peak memory 217416 kb
Host smart-1260721f-fbc4-431b-8c99-ea00f9771d79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229883933 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2229883933
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.223391399
Short name T1086
Test name
Test status
Simulation time 88426329 ps
CPU time 1.47 seconds
Started Jul 03 05:08:12 PM PDT 24
Finished Jul 03 05:08:14 PM PDT 24
Peak memory 215760 kb
Host smart-09bd6e94-ebd2-495d-ba50-8f7604f5d676
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223391399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.223391399
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2920085904
Short name T1022
Test name
Test status
Simulation time 18192258 ps
CPU time 0.78 seconds
Started Jul 03 05:08:13 PM PDT 24
Finished Jul 03 05:08:14 PM PDT 24
Peak memory 204264 kb
Host smart-a746dd45-e895-4183-b561-1a819b1d43b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920085904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2920085904
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1985252473
Short name T1020
Test name
Test status
Simulation time 62107965 ps
CPU time 3.87 seconds
Started Jul 03 05:08:12 PM PDT 24
Finished Jul 03 05:08:16 PM PDT 24
Peak memory 215808 kb
Host smart-fc31dcc3-3a99-42cf-a470-1469107eeef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985252473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1985252473
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1805237629
Short name T92
Test name
Test status
Simulation time 211680081 ps
CPU time 4.74 seconds
Started Jul 03 05:08:14 PM PDT 24
Finished Jul 03 05:08:19 PM PDT 24
Peak memory 215940 kb
Host smart-7cc90840-10f5-4bee-a3c1-510336e47b0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805237629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1805237629
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.347666376
Short name T1062
Test name
Test status
Simulation time 3512804422 ps
CPU time 7.9 seconds
Started Jul 03 05:08:17 PM PDT 24
Finished Jul 03 05:08:25 PM PDT 24
Peak memory 215828 kb
Host smart-2573f666-726b-4aa4-9d4d-4384ba1bbbd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347666376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.347666376
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1863741440
Short name T151
Test name
Test status
Simulation time 747388784 ps
CPU time 8.34 seconds
Started Jul 03 05:07:47 PM PDT 24
Finished Jul 03 05:07:55 PM PDT 24
Peak memory 207356 kb
Host smart-3ebf5098-b4a2-4021-83bb-6c3cfb46844f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863741440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1863741440
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3227425808
Short name T1081
Test name
Test status
Simulation time 368652431 ps
CPU time 21.64 seconds
Started Jul 03 05:07:47 PM PDT 24
Finished Jul 03 05:08:09 PM PDT 24
Peak memory 207336 kb
Host smart-8e03742e-fba0-4164-91ed-3bed6f730b10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227425808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3227425808
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1499382097
Short name T1079
Test name
Test status
Simulation time 174613008 ps
CPU time 2.7 seconds
Started Jul 03 05:07:48 PM PDT 24
Finished Jul 03 05:07:51 PM PDT 24
Peak memory 216780 kb
Host smart-2db50d08-64c3-4a2e-8bdf-e6378f92ff32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499382097 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1499382097
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1887670384
Short name T110
Test name
Test status
Simulation time 598765732 ps
CPU time 2.78 seconds
Started Jul 03 05:07:48 PM PDT 24
Finished Jul 03 05:07:51 PM PDT 24
Peak memory 207472 kb
Host smart-19ecd991-4756-4848-93ab-b83d15f75d17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887670384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
887670384
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3332474634
Short name T1016
Test name
Test status
Simulation time 53911881 ps
CPU time 0.71 seconds
Started Jul 03 05:07:45 PM PDT 24
Finished Jul 03 05:07:46 PM PDT 24
Peak memory 204268 kb
Host smart-e99c3ddb-8a76-437b-bf74-8b9fae077551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332474634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
332474634
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1438058751
Short name T120
Test name
Test status
Simulation time 172268817 ps
CPU time 1.33 seconds
Started Jul 03 05:07:46 PM PDT 24
Finished Jul 03 05:07:47 PM PDT 24
Peak memory 215856 kb
Host smart-7eec5906-22ec-49d7-81d8-230fc35e8f35
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438058751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1438058751
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2739849502
Short name T1025
Test name
Test status
Simulation time 38524445 ps
CPU time 0.67 seconds
Started Jul 03 05:07:48 PM PDT 24
Finished Jul 03 05:07:49 PM PDT 24
Peak memory 204396 kb
Host smart-b8d6de8c-75c7-4d78-96a7-7a12268a088b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739849502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2739849502
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.816323899
Short name T1008
Test name
Test status
Simulation time 53892532 ps
CPU time 1.62 seconds
Started Jul 03 05:07:46 PM PDT 24
Finished Jul 03 05:07:48 PM PDT 24
Peak memory 215760 kb
Host smart-a555f2cb-ada7-49ee-a3bc-fba862d1afbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816323899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.816323899
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1230452810
Short name T1037
Test name
Test status
Simulation time 13466848 ps
CPU time 0.71 seconds
Started Jul 03 05:08:19 PM PDT 24
Finished Jul 03 05:08:20 PM PDT 24
Peak memory 204212 kb
Host smart-68b1acb5-1ed2-4085-9eff-8fa41a7e03b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230452810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1230452810
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2951701051
Short name T1049
Test name
Test status
Simulation time 55890909 ps
CPU time 0.72 seconds
Started Jul 03 05:08:11 PM PDT 24
Finished Jul 03 05:08:12 PM PDT 24
Peak memory 204288 kb
Host smart-b54ec099-30e6-4208-a531-b1413b9bd153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951701051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2951701051
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1781736007
Short name T1017
Test name
Test status
Simulation time 32151408 ps
CPU time 0.73 seconds
Started Jul 03 05:08:17 PM PDT 24
Finished Jul 03 05:08:18 PM PDT 24
Peak memory 204308 kb
Host smart-c42e972b-d8ca-4d46-b4c5-cb11f98a009f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781736007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1781736007
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4084402721
Short name T1100
Test name
Test status
Simulation time 15094175 ps
CPU time 0.68 seconds
Started Jul 03 05:08:17 PM PDT 24
Finished Jul 03 05:08:18 PM PDT 24
Peak memory 204252 kb
Host smart-7575e786-988f-478a-a5a0-9953cac5b3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084402721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4084402721
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4064775547
Short name T1018
Test name
Test status
Simulation time 38953674 ps
CPU time 0.72 seconds
Started Jul 03 05:08:16 PM PDT 24
Finished Jul 03 05:08:17 PM PDT 24
Peak memory 204336 kb
Host smart-229d037b-5dc8-45db-8cb6-a157b451bb53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064775547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4064775547
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2346392858
Short name T1094
Test name
Test status
Simulation time 36792773 ps
CPU time 0.7 seconds
Started Jul 03 05:08:13 PM PDT 24
Finished Jul 03 05:08:14 PM PDT 24
Peak memory 204260 kb
Host smart-8d377c33-71b1-40c2-9c66-115bbe577f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346392858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2346392858
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.525842789
Short name T1033
Test name
Test status
Simulation time 13977063 ps
CPU time 0.79 seconds
Started Jul 03 05:08:17 PM PDT 24
Finished Jul 03 05:08:18 PM PDT 24
Peak memory 204316 kb
Host smart-9e4c0f35-f34d-4116-9ed2-74c2a83bacda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525842789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.525842789
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3412257420
Short name T1110
Test name
Test status
Simulation time 25619349 ps
CPU time 0.77 seconds
Started Jul 03 05:08:20 PM PDT 24
Finished Jul 03 05:08:21 PM PDT 24
Peak memory 204200 kb
Host smart-6a5da01c-b4ab-4144-8207-a4dbfe56eede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412257420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3412257420
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3649612102
Short name T1105
Test name
Test status
Simulation time 30116389 ps
CPU time 0.79 seconds
Started Jul 03 05:08:12 PM PDT 24
Finished Jul 03 05:08:13 PM PDT 24
Peak memory 204608 kb
Host smart-79cd6461-a716-4071-a142-ea10d26d6280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649612102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3649612102
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2008990665
Short name T1057
Test name
Test status
Simulation time 18214626 ps
CPU time 0.76 seconds
Started Jul 03 05:08:19 PM PDT 24
Finished Jul 03 05:08:20 PM PDT 24
Peak memory 204208 kb
Host smart-cc26fb3d-b993-4f16-8985-df3a69112ec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008990665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2008990665
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1642688043
Short name T116
Test name
Test status
Simulation time 929978545 ps
CPU time 23.23 seconds
Started Jul 03 05:07:49 PM PDT 24
Finished Jul 03 05:08:13 PM PDT 24
Peak memory 215716 kb
Host smart-46ea4f87-10c8-4f27-8782-a7a22f26cfd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642688043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1642688043
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2327903627
Short name T1120
Test name
Test status
Simulation time 3746801037 ps
CPU time 14.16 seconds
Started Jul 03 05:07:50 PM PDT 24
Finished Jul 03 05:08:04 PM PDT 24
Peak memory 215732 kb
Host smart-9ebe3509-9887-4dfc-8ef4-23f1ce5f169c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327903627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2327903627
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4276377784
Short name T79
Test name
Test status
Simulation time 181123937 ps
CPU time 1.46 seconds
Started Jul 03 05:07:48 PM PDT 24
Finished Jul 03 05:07:51 PM PDT 24
Peak memory 207444 kb
Host smart-a91f9d74-34bb-4d43-b4d1-a3350aa0324a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276377784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4276377784
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3262704722
Short name T1077
Test name
Test status
Simulation time 461890651 ps
CPU time 3.28 seconds
Started Jul 03 05:07:51 PM PDT 24
Finished Jul 03 05:07:55 PM PDT 24
Peak memory 217876 kb
Host smart-7eb361d1-13d1-4712-a4f4-6be0acaca09a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262704722 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3262704722
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.383976963
Short name T1084
Test name
Test status
Simulation time 42411860 ps
CPU time 1.33 seconds
Started Jul 03 05:07:50 PM PDT 24
Finished Jul 03 05:07:52 PM PDT 24
Peak memory 207548 kb
Host smart-d8452dc5-5bd6-46a6-af1e-9c1282589916
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383976963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.383976963
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3291167721
Short name T1015
Test name
Test status
Simulation time 80002778 ps
CPU time 0.71 seconds
Started Jul 03 05:07:45 PM PDT 24
Finished Jul 03 05:07:46 PM PDT 24
Peak memory 204584 kb
Host smart-4fd9e164-53e9-4c40-a4dc-5421a220ec48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291167721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
291167721
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2622811111
Short name T112
Test name
Test status
Simulation time 279942096 ps
CPU time 1.83 seconds
Started Jul 03 05:07:46 PM PDT 24
Finished Jul 03 05:07:49 PM PDT 24
Peak memory 215816 kb
Host smart-a46e2322-5bfd-4238-9a29-2ce199fc6b75
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622811111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2622811111
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1562403103
Short name T1103
Test name
Test status
Simulation time 47109795 ps
CPU time 0.71 seconds
Started Jul 03 05:07:51 PM PDT 24
Finished Jul 03 05:07:52 PM PDT 24
Peak memory 204080 kb
Host smart-ce27a986-d141-43b3-8f1d-a07d2f0ad44f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562403103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1562403103
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2759900335
Short name T1104
Test name
Test status
Simulation time 312354230 ps
CPU time 4.06 seconds
Started Jul 03 05:07:49 PM PDT 24
Finished Jul 03 05:07:54 PM PDT 24
Peak memory 215772 kb
Host smart-3076c754-8d35-408b-880c-70b0a327bb55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759900335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2759900335
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2356996152
Short name T104
Test name
Test status
Simulation time 62728522 ps
CPU time 2.8 seconds
Started Jul 03 05:07:46 PM PDT 24
Finished Jul 03 05:07:50 PM PDT 24
Peak memory 215984 kb
Host smart-3e58de10-d028-4995-925d-1092cecdfdf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356996152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
356996152
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1278577818
Short name T183
Test name
Test status
Simulation time 512308967 ps
CPU time 6.36 seconds
Started Jul 03 05:07:47 PM PDT 24
Finished Jul 03 05:07:54 PM PDT 24
Peak memory 216400 kb
Host smart-9a1461a5-37a7-40ee-b05b-18f87c9c0adf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278577818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1278577818
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1320051910
Short name T1013
Test name
Test status
Simulation time 15870593 ps
CPU time 0.71 seconds
Started Jul 03 05:08:15 PM PDT 24
Finished Jul 03 05:08:16 PM PDT 24
Peak memory 204612 kb
Host smart-f5a3676b-1db8-4040-9762-f93ba546479a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320051910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1320051910
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4103004051
Short name T1109
Test name
Test status
Simulation time 114378868 ps
CPU time 0.75 seconds
Started Jul 03 05:08:12 PM PDT 24
Finished Jul 03 05:08:13 PM PDT 24
Peak memory 204256 kb
Host smart-112b38cc-da58-4689-b068-e10be4952550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103004051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4103004051
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4184047611
Short name T1040
Test name
Test status
Simulation time 30540096 ps
CPU time 0.76 seconds
Started Jul 03 05:08:16 PM PDT 24
Finished Jul 03 05:08:17 PM PDT 24
Peak memory 204252 kb
Host smart-8d736ede-daa4-43c4-8ec3-a1edd83f0d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184047611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4184047611
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1991183946
Short name T1065
Test name
Test status
Simulation time 21967799 ps
CPU time 0.75 seconds
Started Jul 03 05:08:19 PM PDT 24
Finished Jul 03 05:08:20 PM PDT 24
Peak memory 204232 kb
Host smart-6155c7ac-1bee-4021-aaf7-d20f2c6f4a42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991183946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1991183946
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2227685217
Short name T1112
Test name
Test status
Simulation time 15772087 ps
CPU time 0.76 seconds
Started Jul 03 05:08:19 PM PDT 24
Finished Jul 03 05:08:20 PM PDT 24
Peak memory 204288 kb
Host smart-3a95775f-7759-4e2c-9787-594b7e6a33a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227685217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2227685217
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2070638090
Short name T1082
Test name
Test status
Simulation time 55879259 ps
CPU time 0.7 seconds
Started Jul 03 05:08:14 PM PDT 24
Finished Jul 03 05:08:15 PM PDT 24
Peak memory 204280 kb
Host smart-0017f3d8-d04d-42b8-90e9-7336462381ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070638090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2070638090
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2652627883
Short name T1024
Test name
Test status
Simulation time 24311575 ps
CPU time 0.77 seconds
Started Jul 03 05:08:20 PM PDT 24
Finished Jul 03 05:08:21 PM PDT 24
Peak memory 204208 kb
Host smart-edb133db-b3e8-484e-8291-e100d640e988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652627883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2652627883
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.409399355
Short name T1019
Test name
Test status
Simulation time 48687515 ps
CPU time 0.73 seconds
Started Jul 03 05:08:18 PM PDT 24
Finished Jul 03 05:08:19 PM PDT 24
Peak memory 204296 kb
Host smart-63e69ff7-7a28-4f98-b53d-7112f1c3327f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409399355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.409399355
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1016997743
Short name T1090
Test name
Test status
Simulation time 45329284 ps
CPU time 0.75 seconds
Started Jul 03 05:08:18 PM PDT 24
Finished Jul 03 05:08:19 PM PDT 24
Peak memory 204288 kb
Host smart-dcfea651-c017-4545-83c3-ce03fa995294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016997743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1016997743
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.287264490
Short name T1088
Test name
Test status
Simulation time 32319318 ps
CPU time 0.75 seconds
Started Jul 03 05:08:19 PM PDT 24
Finished Jul 03 05:08:20 PM PDT 24
Peak memory 204300 kb
Host smart-9848eaa7-68ec-4bbf-adad-c650482c0b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287264490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.287264490
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.51921728
Short name T1099
Test name
Test status
Simulation time 322806667 ps
CPU time 8.61 seconds
Started Jul 03 05:07:54 PM PDT 24
Finished Jul 03 05:08:03 PM PDT 24
Peak memory 215732 kb
Host smart-b55c63eb-42b5-4d02-96e6-c1509e35a740
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51921728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
aliasing.51921728
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2196339829
Short name T1096
Test name
Test status
Simulation time 373105494 ps
CPU time 12.15 seconds
Started Jul 03 05:07:54 PM PDT 24
Finished Jul 03 05:08:06 PM PDT 24
Peak memory 207476 kb
Host smart-4dfb0b8f-99ba-42b1-b664-aa1ef732b8a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196339829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2196339829
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3416890381
Short name T77
Test name
Test status
Simulation time 64058775 ps
CPU time 1.13 seconds
Started Jul 03 05:07:48 PM PDT 24
Finished Jul 03 05:07:51 PM PDT 24
Peak memory 207504 kb
Host smart-39b0e648-99f3-4e3f-a83b-9a2010541000
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416890381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3416890381
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1101972015
Short name T1071
Test name
Test status
Simulation time 62422084 ps
CPU time 2.46 seconds
Started Jul 03 05:07:53 PM PDT 24
Finished Jul 03 05:07:56 PM PDT 24
Peak memory 218736 kb
Host smart-b7335756-0a9e-445d-bd84-33a45589675a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101972015 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1101972015
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2241483435
Short name T108
Test name
Test status
Simulation time 91432811 ps
CPU time 1.43 seconds
Started Jul 03 05:07:48 PM PDT 24
Finished Jul 03 05:07:50 PM PDT 24
Peak memory 207444 kb
Host smart-27f9646a-b14d-4fc0-97e0-e961fa04f3b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241483435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
241483435
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3569716352
Short name T1043
Test name
Test status
Simulation time 15932870 ps
CPU time 0.74 seconds
Started Jul 03 05:07:47 PM PDT 24
Finished Jul 03 05:07:48 PM PDT 24
Peak memory 204260 kb
Host smart-9f98adb7-887b-4c89-a9b2-b37c30e4400f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569716352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
569716352
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3650087051
Short name T119
Test name
Test status
Simulation time 372432088 ps
CPU time 2.24 seconds
Started Jul 03 05:07:46 PM PDT 24
Finished Jul 03 05:07:49 PM PDT 24
Peak memory 215828 kb
Host smart-8b4aeb16-0d05-499e-89e2-42c242c6ab99
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650087051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3650087051
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3043577640
Short name T1052
Test name
Test status
Simulation time 11973636 ps
CPU time 0.68 seconds
Started Jul 03 05:07:51 PM PDT 24
Finished Jul 03 05:07:52 PM PDT 24
Peak memory 204076 kb
Host smart-f44ace9d-3edc-4d30-8b5c-d59b7aa0bc09
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043577640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3043577640
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2027847645
Short name T149
Test name
Test status
Simulation time 583423335 ps
CPU time 3.18 seconds
Started Jul 03 05:07:53 PM PDT 24
Finished Jul 03 05:07:57 PM PDT 24
Peak memory 215732 kb
Host smart-a978726d-8e4e-46aa-ae42-951595092e35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027847645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2027847645
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3750914692
Short name T1119
Test name
Test status
Simulation time 275250823 ps
CPU time 4.13 seconds
Started Jul 03 05:07:44 PM PDT 24
Finished Jul 03 05:07:49 PM PDT 24
Peak memory 216992 kb
Host smart-4dbe6f0a-77d2-42be-b4ff-16fc0ecd18ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750914692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
750914692
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1861808338
Short name T1129
Test name
Test status
Simulation time 2933818860 ps
CPU time 16.48 seconds
Started Jul 03 05:07:48 PM PDT 24
Finished Jul 03 05:08:05 PM PDT 24
Peak memory 215884 kb
Host smart-12df51b9-5e2f-4bdd-9111-0baa1e338e49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861808338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1861808338
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.701062222
Short name T1031
Test name
Test status
Simulation time 38956120 ps
CPU time 0.72 seconds
Started Jul 03 05:08:16 PM PDT 24
Finished Jul 03 05:08:17 PM PDT 24
Peak memory 204488 kb
Host smart-b3644b79-d13a-4341-8f44-15fb351390c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701062222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.701062222
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2434411824
Short name T1113
Test name
Test status
Simulation time 57935632 ps
CPU time 0.77 seconds
Started Jul 03 05:08:17 PM PDT 24
Finished Jul 03 05:08:18 PM PDT 24
Peak memory 204312 kb
Host smart-657b4e60-3003-4437-9876-9028d4bbd448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434411824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2434411824
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4270578286
Short name T1072
Test name
Test status
Simulation time 24326526 ps
CPU time 0.73 seconds
Started Jul 03 05:08:15 PM PDT 24
Finished Jul 03 05:08:15 PM PDT 24
Peak memory 204592 kb
Host smart-573f74f0-02dd-4a0a-82f8-c653de38224a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270578286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4270578286
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1919220439
Short name T1085
Test name
Test status
Simulation time 45938810 ps
CPU time 0.71 seconds
Started Jul 03 05:08:17 PM PDT 24
Finished Jul 03 05:08:18 PM PDT 24
Peak memory 204540 kb
Host smart-10d06864-bb52-4b49-9355-5d5210524077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919220439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1919220439
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1857377344
Short name T1061
Test name
Test status
Simulation time 14623091 ps
CPU time 0.75 seconds
Started Jul 03 05:08:20 PM PDT 24
Finished Jul 03 05:08:21 PM PDT 24
Peak memory 204288 kb
Host smart-635af30d-2225-4041-9463-8c8334b44f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857377344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1857377344
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1621309487
Short name T1111
Test name
Test status
Simulation time 17599517 ps
CPU time 0.74 seconds
Started Jul 03 05:08:20 PM PDT 24
Finished Jul 03 05:08:21 PM PDT 24
Peak memory 204524 kb
Host smart-9dcded5e-1aff-4283-8d67-e46ef85c5cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621309487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1621309487
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.450073295
Short name T1009
Test name
Test status
Simulation time 43621437 ps
CPU time 0.81 seconds
Started Jul 03 05:08:19 PM PDT 24
Finished Jul 03 05:08:20 PM PDT 24
Peak memory 204284 kb
Host smart-882d2fa9-25c8-408f-8d8e-38e669eecd3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450073295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.450073295
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2965049275
Short name T1116
Test name
Test status
Simulation time 37114803 ps
CPU time 0.71 seconds
Started Jul 03 05:08:21 PM PDT 24
Finished Jul 03 05:08:22 PM PDT 24
Peak memory 204304 kb
Host smart-a0bf09d6-bf31-45c3-8c57-75f67051eb64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965049275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2965049275
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3303056059
Short name T1048
Test name
Test status
Simulation time 137249505 ps
CPU time 0.69 seconds
Started Jul 03 05:08:20 PM PDT 24
Finished Jul 03 05:08:21 PM PDT 24
Peak memory 204300 kb
Host smart-dc1db3e1-99af-476f-a003-8c37dc079331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303056059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3303056059
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.485162021
Short name T1066
Test name
Test status
Simulation time 21950070 ps
CPU time 0.8 seconds
Started Jul 03 05:08:20 PM PDT 24
Finished Jul 03 05:08:21 PM PDT 24
Peak memory 204284 kb
Host smart-ea7d6920-257f-497f-89d7-9b2e2ce33662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485162021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.485162021
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1067440806
Short name T1087
Test name
Test status
Simulation time 115839898 ps
CPU time 2.69 seconds
Started Jul 03 05:07:53 PM PDT 24
Finished Jul 03 05:07:56 PM PDT 24
Peak memory 216976 kb
Host smart-15618f66-9f83-4824-ac44-198c865173e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067440806 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1067440806
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2453978847
Short name T109
Test name
Test status
Simulation time 211958417 ps
CPU time 2.73 seconds
Started Jul 03 05:07:54 PM PDT 24
Finished Jul 03 05:07:57 PM PDT 24
Peak memory 215616 kb
Host smart-f56f8069-acc2-48dd-8d81-bd08ef1ace20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453978847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
453978847
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3469881386
Short name T1027
Test name
Test status
Simulation time 14439571 ps
CPU time 0.76 seconds
Started Jul 03 05:07:55 PM PDT 24
Finished Jul 03 05:07:56 PM PDT 24
Peak memory 204276 kb
Host smart-8c5dd94c-65cb-422e-8741-32ba5da54294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469881386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
469881386
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3338973303
Short name T1030
Test name
Test status
Simulation time 60159666 ps
CPU time 3.46 seconds
Started Jul 03 05:07:53 PM PDT 24
Finished Jul 03 05:07:56 PM PDT 24
Peak memory 215784 kb
Host smart-db3f2d41-a601-4b1c-9ffa-58961c3c4903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338973303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3338973303
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.568891447
Short name T66
Test name
Test status
Simulation time 52931469 ps
CPU time 1.68 seconds
Started Jul 03 05:07:52 PM PDT 24
Finished Jul 03 05:07:54 PM PDT 24
Peak memory 216852 kb
Host smart-c8268f82-49f8-47f3-8ef9-db2bad96eb82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568891447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.568891447
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3171393917
Short name T1108
Test name
Test status
Simulation time 1397754198 ps
CPU time 19.18 seconds
Started Jul 03 05:07:54 PM PDT 24
Finished Jul 03 05:08:13 PM PDT 24
Peak memory 216112 kb
Host smart-d38e5312-3259-4715-95f0-3fc5152b7ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171393917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3171393917
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.836417986
Short name T1029
Test name
Test status
Simulation time 98847571 ps
CPU time 2.96 seconds
Started Jul 03 05:07:57 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 218188 kb
Host smart-f4c3f87e-02e2-4011-b429-3343fa3fb683
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836417986 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.836417986
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3370636955
Short name T1101
Test name
Test status
Simulation time 41981503 ps
CPU time 1.29 seconds
Started Jul 03 05:07:58 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 207588 kb
Host smart-76635f65-26f1-468a-8a77-998cccf81f38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370636955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
370636955
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.811557206
Short name T1042
Test name
Test status
Simulation time 16808013 ps
CPU time 0.77 seconds
Started Jul 03 05:07:51 PM PDT 24
Finished Jul 03 05:07:52 PM PDT 24
Peak memory 204276 kb
Host smart-3e1c634e-4298-485d-b90d-668e705111e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811557206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.811557206
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3828354664
Short name T1046
Test name
Test status
Simulation time 155314357 ps
CPU time 2.69 seconds
Started Jul 03 05:07:56 PM PDT 24
Finished Jul 03 05:07:59 PM PDT 24
Peak memory 215780 kb
Host smart-d23d7d01-941a-48a8-922c-107d37ee8799
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828354664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3828354664
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3488585336
Short name T175
Test name
Test status
Simulation time 179841211 ps
CPU time 4.46 seconds
Started Jul 03 05:07:55 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 216080 kb
Host smart-60283126-377c-45c1-a4c5-84a07a946c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488585336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
488585336
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3199635249
Short name T182
Test name
Test status
Simulation time 3314386690 ps
CPU time 21 seconds
Started Jul 03 05:07:52 PM PDT 24
Finished Jul 03 05:08:14 PM PDT 24
Peak memory 215844 kb
Host smart-4db7326c-b98c-44b9-ab76-20e34e41fa00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199635249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3199635249
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1944599575
Short name T1035
Test name
Test status
Simulation time 90784826 ps
CPU time 2.52 seconds
Started Jul 03 05:07:58 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 216804 kb
Host smart-d9f6a510-810e-47d6-93fa-a734dbaf32c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944599575 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1944599575
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2659372816
Short name T1098
Test name
Test status
Simulation time 155950169 ps
CPU time 1.34 seconds
Started Jul 03 05:07:59 PM PDT 24
Finished Jul 03 05:08:02 PM PDT 24
Peak memory 207548 kb
Host smart-bfe372fb-739a-4ea0-a711-4ab70c1a24e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659372816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
659372816
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2176856554
Short name T1044
Test name
Test status
Simulation time 26956044 ps
CPU time 0.72 seconds
Started Jul 03 05:07:55 PM PDT 24
Finished Jul 03 05:07:56 PM PDT 24
Peak memory 204164 kb
Host smart-604dfb89-85b8-41a3-a82a-a5882bcbc3d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176856554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
176856554
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1981383818
Short name T1007
Test name
Test status
Simulation time 231937986 ps
CPU time 3 seconds
Started Jul 03 05:07:57 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 215804 kb
Host smart-4bc9d864-43b7-4d62-8007-bfa6f4043f98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981383818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1981383818
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3497651813
Short name T103
Test name
Test status
Simulation time 56886420 ps
CPU time 1.55 seconds
Started Jul 03 05:07:56 PM PDT 24
Finished Jul 03 05:07:58 PM PDT 24
Peak memory 216124 kb
Host smart-abc846f5-8622-463e-af09-7c97a2be9212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497651813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
497651813
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1750784962
Short name T150
Test name
Test status
Simulation time 622545311 ps
CPU time 13.75 seconds
Started Jul 03 05:07:58 PM PDT 24
Finished Jul 03 05:08:13 PM PDT 24
Peak memory 215692 kb
Host smart-4cb0c4a1-e303-48da-872f-bad8d52a5c6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750784962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1750784962
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1584507347
Short name T1041
Test name
Test status
Simulation time 119174157 ps
CPU time 3.29 seconds
Started Jul 03 05:07:58 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 217544 kb
Host smart-a377e3b3-0a2c-4def-a220-322f579e6da7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584507347 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1584507347
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2070509660
Short name T1107
Test name
Test status
Simulation time 70000573 ps
CPU time 1.22 seconds
Started Jul 03 05:07:55 PM PDT 24
Finished Jul 03 05:07:57 PM PDT 24
Peak memory 207624 kb
Host smart-e7d6a4fe-5dbb-47ae-a926-74a6302273dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070509660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
070509660
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2718333787
Short name T1069
Test name
Test status
Simulation time 35169678 ps
CPU time 0.7 seconds
Started Jul 03 05:08:00 PM PDT 24
Finished Jul 03 05:08:02 PM PDT 24
Peak memory 204176 kb
Host smart-b72409f9-42da-49af-8551-8fab99366c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718333787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
718333787
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2614339468
Short name T1092
Test name
Test status
Simulation time 224263802 ps
CPU time 1.76 seconds
Started Jul 03 05:07:58 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 215772 kb
Host smart-68029f27-9112-4119-bdcd-6d408ada75c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614339468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2614339468
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2408315451
Short name T1126
Test name
Test status
Simulation time 526418500 ps
CPU time 3.67 seconds
Started Jul 03 05:07:56 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 215924 kb
Host smart-36e813d4-b8f3-472c-a114-84d8b77bb62f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408315451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
408315451
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4272360198
Short name T65
Test name
Test status
Simulation time 2825067959 ps
CPU time 21.55 seconds
Started Jul 03 05:07:57 PM PDT 24
Finished Jul 03 05:08:19 PM PDT 24
Peak memory 215820 kb
Host smart-7537e22d-1e9c-42ee-a7eb-71e7ed94456b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272360198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4272360198
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.305814384
Short name T1056
Test name
Test status
Simulation time 65615961 ps
CPU time 1.59 seconds
Started Jul 03 05:07:59 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 215744 kb
Host smart-91a27c94-6593-4f62-81ec-83ed798040c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305814384 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.305814384
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3252055990
Short name T1026
Test name
Test status
Simulation time 22820276 ps
CPU time 1.32 seconds
Started Jul 03 05:07:59 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 215732 kb
Host smart-a2bfd4f5-8f39-48c7-a215-c85804d31bb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252055990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
252055990
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2480974117
Short name T1083
Test name
Test status
Simulation time 30897741 ps
CPU time 0.76 seconds
Started Jul 03 05:07:55 PM PDT 24
Finished Jul 03 05:07:56 PM PDT 24
Peak memory 204300 kb
Host smart-03d79e93-753e-40ec-94f4-503c174ee4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480974117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
480974117
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.378320891
Short name T1054
Test name
Test status
Simulation time 47243142 ps
CPU time 2.75 seconds
Started Jul 03 05:07:58 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 215796 kb
Host smart-cfdaa9bc-7c13-4c1b-b067-a13847066447
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378320891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.378320891
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3935513340
Short name T105
Test name
Test status
Simulation time 113142704 ps
CPU time 3.08 seconds
Started Jul 03 05:07:56 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 216056 kb
Host smart-a92fc74f-e955-45c7-832a-a43f309fb191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935513340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
935513340
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1620468933
Short name T907
Test name
Test status
Simulation time 21633957 ps
CPU time 0.77 seconds
Started Jul 03 05:16:42 PM PDT 24
Finished Jul 03 05:16:43 PM PDT 24
Peak memory 205836 kb
Host smart-439759c4-e141-40fb-bfc9-33691375adbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620468933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
620468933
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3204515579
Short name T783
Test name
Test status
Simulation time 1210347043 ps
CPU time 15.17 seconds
Started Jul 03 05:16:40 PM PDT 24
Finished Jul 03 05:16:56 PM PDT 24
Peak memory 232688 kb
Host smart-2a9cb53e-1324-4b75-a3d5-0aa75addde65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204515579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3204515579
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2203502169
Short name T438
Test name
Test status
Simulation time 33960959 ps
CPU time 0.78 seconds
Started Jul 03 05:16:33 PM PDT 24
Finished Jul 03 05:16:34 PM PDT 24
Peak memory 206620 kb
Host smart-d4d761f0-1c0f-477e-a8c9-c19a260374a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203502169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2203502169
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2927217270
Short name T220
Test name
Test status
Simulation time 12126325993 ps
CPU time 47.25 seconds
Started Jul 03 05:16:38 PM PDT 24
Finished Jul 03 05:17:26 PM PDT 24
Peak memory 249184 kb
Host smart-daf22a0b-1fa3-4c4b-b724-2583fe1fae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927217270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2927217270
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2963209745
Short name T712
Test name
Test status
Simulation time 17734625000 ps
CPU time 169.99 seconds
Started Jul 03 05:16:38 PM PDT 24
Finished Jul 03 05:19:28 PM PDT 24
Peak memory 251440 kb
Host smart-77296b07-ce59-437e-9ca1-3654a038b4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963209745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2963209745
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.736073920
Short name T202
Test name
Test status
Simulation time 35000179420 ps
CPU time 331.48 seconds
Started Jul 03 05:16:38 PM PDT 24
Finished Jul 03 05:22:10 PM PDT 24
Peak memory 249300 kb
Host smart-7cbe96ea-d50e-49d1-91a2-204b4fd4fb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736073920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
736073920
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.552102587
Short name T431
Test name
Test status
Simulation time 250114644 ps
CPU time 5.63 seconds
Started Jul 03 05:16:39 PM PDT 24
Finished Jul 03 05:16:45 PM PDT 24
Peak memory 233732 kb
Host smart-b7de4ce5-6c7d-4455-ab77-c3d0aff0c086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552102587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.552102587
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1759013381
Short name T410
Test name
Test status
Simulation time 105339130707 ps
CPU time 201.4 seconds
Started Jul 03 05:16:37 PM PDT 24
Finished Jul 03 05:19:59 PM PDT 24
Peak memory 249644 kb
Host smart-68659874-c417-4847-a41b-0061a5d4013d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759013381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1759013381
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2841148191
Short name T809
Test name
Test status
Simulation time 1645394325 ps
CPU time 18.77 seconds
Started Jul 03 05:16:38 PM PDT 24
Finished Jul 03 05:16:57 PM PDT 24
Peak memory 232728 kb
Host smart-82a5f6ca-d127-476a-9702-e2d5e380243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841148191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2841148191
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3007036177
Short name T168
Test name
Test status
Simulation time 4125978685 ps
CPU time 43.33 seconds
Started Jul 03 05:16:38 PM PDT 24
Finished Jul 03 05:17:22 PM PDT 24
Peak memory 232768 kb
Host smart-8c1fd829-80f6-493a-833c-ecb6dd44cfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007036177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3007036177
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.351892472
Short name T44
Test name
Test status
Simulation time 3499383448 ps
CPU time 10.2 seconds
Started Jul 03 05:16:38 PM PDT 24
Finished Jul 03 05:16:49 PM PDT 24
Peak memory 224612 kb
Host smart-365dce23-f78a-4b07-8801-e7e1f7644f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351892472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
351892472
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3022015187
Short name T414
Test name
Test status
Simulation time 662892713 ps
CPU time 8.42 seconds
Started Jul 03 05:16:37 PM PDT 24
Finished Jul 03 05:16:46 PM PDT 24
Peak memory 224448 kb
Host smart-4400efb0-e92c-4288-a078-e76a573016fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022015187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3022015187
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4151336599
Short name T961
Test name
Test status
Simulation time 88083305 ps
CPU time 4.15 seconds
Started Jul 03 05:16:41 PM PDT 24
Finished Jul 03 05:16:46 PM PDT 24
Peak memory 223176 kb
Host smart-1885bd09-b9d8-4f55-9bf7-9355913e1e86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4151336599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4151336599
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.736521886
Short name T70
Test name
Test status
Simulation time 33507473 ps
CPU time 0.96 seconds
Started Jul 03 05:16:41 PM PDT 24
Finished Jul 03 05:16:43 PM PDT 24
Peak memory 236608 kb
Host smart-c7e27c3a-73f7-42e2-90d3-65fd878b5573
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736521886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.736521886
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2000457611
Short name T573
Test name
Test status
Simulation time 2891182541 ps
CPU time 6.97 seconds
Started Jul 03 05:16:38 PM PDT 24
Finished Jul 03 05:16:46 PM PDT 24
Peak memory 219972 kb
Host smart-cd500dbe-4bc6-4cec-8fce-dc0b5aacc240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000457611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2000457611
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2382663273
Short name T337
Test name
Test status
Simulation time 5801911039 ps
CPU time 14.49 seconds
Started Jul 03 05:16:36 PM PDT 24
Finished Jul 03 05:16:51 PM PDT 24
Peak memory 216376 kb
Host smart-a0b535eb-afb6-4bb8-9088-ca6a2c200e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382663273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2382663273
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2303935833
Short name T654
Test name
Test status
Simulation time 129550364 ps
CPU time 1.37 seconds
Started Jul 03 05:16:40 PM PDT 24
Finished Jul 03 05:16:42 PM PDT 24
Peak memory 216132 kb
Host smart-8e1923de-494d-41c5-9ad2-02717b2f7f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303935833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2303935833
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3287832405
Short name T522
Test name
Test status
Simulation time 137707613 ps
CPU time 0.86 seconds
Started Jul 03 05:16:39 PM PDT 24
Finished Jul 03 05:16:40 PM PDT 24
Peak memory 205972 kb
Host smart-fccc02f5-b65d-45f0-be1f-d45d7e8b93b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287832405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3287832405
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.170493182
Short name T187
Test name
Test status
Simulation time 2382058746 ps
CPU time 11.47 seconds
Started Jul 03 05:16:38 PM PDT 24
Finished Jul 03 05:16:50 PM PDT 24
Peak memory 249112 kb
Host smart-81c51696-6b17-4c10-b5ae-f07b0341c504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170493182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.170493182
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.188443327
Short name T534
Test name
Test status
Simulation time 21026739 ps
CPU time 0.69 seconds
Started Jul 03 05:16:44 PM PDT 24
Finished Jul 03 05:16:45 PM PDT 24
Peak memory 205500 kb
Host smart-bacb0cea-430d-4fe0-a0bb-d37b50d07ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188443327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.188443327
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1954890564
Short name T423
Test name
Test status
Simulation time 76988809 ps
CPU time 2.16 seconds
Started Jul 03 05:16:41 PM PDT 24
Finished Jul 03 05:16:44 PM PDT 24
Peak memory 224356 kb
Host smart-bb145c5b-8648-4dee-827d-add418bbdc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954890564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1954890564
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1369872321
Short name T836
Test name
Test status
Simulation time 13294567 ps
CPU time 0.74 seconds
Started Jul 03 05:16:42 PM PDT 24
Finished Jul 03 05:16:43 PM PDT 24
Peak memory 205568 kb
Host smart-3f9eb7c8-c588-4007-b33b-77a78bdd5daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369872321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1369872321
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1196938595
Short name T869
Test name
Test status
Simulation time 2778071308 ps
CPU time 15.71 seconds
Started Jul 03 05:16:44 PM PDT 24
Finished Jul 03 05:17:01 PM PDT 24
Peak memory 224596 kb
Host smart-1a066ce7-1b2d-49fe-a3a7-590e1e3da888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196938595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1196938595
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1304182234
Short name T34
Test name
Test status
Simulation time 2781145400 ps
CPU time 40.06 seconds
Started Jul 03 05:16:44 PM PDT 24
Finished Jul 03 05:17:25 PM PDT 24
Peak memory 236292 kb
Host smart-1f3b402f-8621-4614-a279-d9245164d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304182234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1304182234
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2175384750
Short name T455
Test name
Test status
Simulation time 43950973 ps
CPU time 0.82 seconds
Started Jul 03 05:16:44 PM PDT 24
Finished Jul 03 05:16:46 PM PDT 24
Peak memory 217316 kb
Host smart-46579712-9644-4c96-8a4d-abff69105911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175384750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2175384750
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.550997978
Short name T709
Test name
Test status
Simulation time 5582066512 ps
CPU time 41.95 seconds
Started Jul 03 05:16:42 PM PDT 24
Finished Jul 03 05:17:24 PM PDT 24
Peak memory 232840 kb
Host smart-3e24d26d-bc5f-44ce-b3bf-1ae3b82138e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550997978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.550997978
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.4181002710
Short name T532
Test name
Test status
Simulation time 3713465058 ps
CPU time 42.36 seconds
Started Jul 03 05:16:44 PM PDT 24
Finished Jul 03 05:17:27 PM PDT 24
Peak memory 265568 kb
Host smart-bf38ebbd-2315-4fa5-8ea9-9b5fa9cbc698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181002710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.4181002710
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3469623744
Short name T332
Test name
Test status
Simulation time 62794749443 ps
CPU time 31.01 seconds
Started Jul 03 05:16:39 PM PDT 24
Finished Jul 03 05:17:11 PM PDT 24
Peak memory 224560 kb
Host smart-4aa59211-eded-4450-a76f-b6726af91c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469623744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3469623744
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.569531453
Short name T243
Test name
Test status
Simulation time 12920474316 ps
CPU time 156.65 seconds
Started Jul 03 05:16:41 PM PDT 24
Finished Jul 03 05:19:19 PM PDT 24
Peak memory 237448 kb
Host smart-78e03179-e13d-482f-b036-242725dcd242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569531453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.569531453
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2916534328
Short name T870
Test name
Test status
Simulation time 1120028414 ps
CPU time 2.93 seconds
Started Jul 03 05:16:40 PM PDT 24
Finished Jul 03 05:16:43 PM PDT 24
Peak memory 232928 kb
Host smart-25c52f11-e912-4771-82a5-3ccb4ba3a440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916534328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2916534328
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1373424023
Short name T863
Test name
Test status
Simulation time 75760674 ps
CPU time 2.66 seconds
Started Jul 03 05:16:41 PM PDT 24
Finished Jul 03 05:16:44 PM PDT 24
Peak memory 232616 kb
Host smart-88cc03ac-f46c-40e2-b497-634bc7d54d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373424023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1373424023
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1196344061
Short name T661
Test name
Test status
Simulation time 346002189 ps
CPU time 4.31 seconds
Started Jul 03 05:16:41 PM PDT 24
Finished Jul 03 05:16:46 PM PDT 24
Peak memory 218820 kb
Host smart-80c66732-e5ad-4974-860d-8cb0d5f8fdfd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1196344061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1196344061
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.359951916
Short name T72
Test name
Test status
Simulation time 1063253943 ps
CPU time 1.18 seconds
Started Jul 03 05:16:45 PM PDT 24
Finished Jul 03 05:16:47 PM PDT 24
Peak memory 237628 kb
Host smart-d827b6ff-4b20-46aa-a65d-492e4eec6521
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359951916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.359951916
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1119974061
Short name T775
Test name
Test status
Simulation time 24623179481 ps
CPU time 250.67 seconds
Started Jul 03 05:16:45 PM PDT 24
Finished Jul 03 05:20:57 PM PDT 24
Peak memory 281188 kb
Host smart-aabbaf5c-6f61-4484-b218-36632164026f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119974061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1119974061
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.598795046
Short name T356
Test name
Test status
Simulation time 6339143768 ps
CPU time 16.19 seconds
Started Jul 03 05:16:44 PM PDT 24
Finished Jul 03 05:17:01 PM PDT 24
Peak memory 220196 kb
Host smart-8088e3f4-9766-4708-8d96-f11b0eb5c105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598795046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.598795046
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2044732308
Short name T658
Test name
Test status
Simulation time 3568665745 ps
CPU time 11.43 seconds
Started Jul 03 05:16:40 PM PDT 24
Finished Jul 03 05:16:52 PM PDT 24
Peak memory 216332 kb
Host smart-0f9133d0-f51d-422e-94e1-4f3aacff4c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044732308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2044732308
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.506804963
Short name T441
Test name
Test status
Simulation time 40103584 ps
CPU time 0.74 seconds
Started Jul 03 05:16:41 PM PDT 24
Finished Jul 03 05:16:42 PM PDT 24
Peak memory 205544 kb
Host smart-08198ae7-1e5c-4d4c-962d-0cb28e03fbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506804963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.506804963
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3303571798
Short name T792
Test name
Test status
Simulation time 27012377 ps
CPU time 0.8 seconds
Started Jul 03 05:16:42 PM PDT 24
Finished Jul 03 05:16:44 PM PDT 24
Peak memory 205948 kb
Host smart-88a5e291-6b62-4203-9898-04b58a63d55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303571798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3303571798
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4234813148
Short name T900
Test name
Test status
Simulation time 321941001 ps
CPU time 3.2 seconds
Started Jul 03 05:16:44 PM PDT 24
Finished Jul 03 05:16:48 PM PDT 24
Peak memory 232660 kb
Host smart-ab66c66d-c220-436d-8bde-fad4c72110bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234813148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4234813148
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.651899743
Short name T762
Test name
Test status
Simulation time 14084402 ps
CPU time 0.7 seconds
Started Jul 03 05:17:21 PM PDT 24
Finished Jul 03 05:17:22 PM PDT 24
Peak memory 205528 kb
Host smart-12fd50b9-dbb4-49ae-ae37-84376ee65d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651899743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.651899743
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.628663421
Short name T612
Test name
Test status
Simulation time 3975117470 ps
CPU time 23.94 seconds
Started Jul 03 05:17:22 PM PDT 24
Finished Jul 03 05:17:46 PM PDT 24
Peak memory 224648 kb
Host smart-6ab8e6fc-37cc-4712-9ba0-d7c7a74efb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628663421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.628663421
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3337585272
Short name T404
Test name
Test status
Simulation time 14401966 ps
CPU time 0.79 seconds
Started Jul 03 05:17:17 PM PDT 24
Finished Jul 03 05:17:18 PM PDT 24
Peak memory 206904 kb
Host smart-d74db4e8-bf45-4351-854a-7d2635a3dd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337585272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3337585272
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1057144837
Short name T294
Test name
Test status
Simulation time 1093747694 ps
CPU time 8.07 seconds
Started Jul 03 05:17:21 PM PDT 24
Finished Jul 03 05:17:29 PM PDT 24
Peak memory 234496 kb
Host smart-224d1c65-bebd-4796-bbab-d2a73ca9820f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057144837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1057144837
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.377146131
Short name T378
Test name
Test status
Simulation time 31327778608 ps
CPU time 241.39 seconds
Started Jul 03 05:17:20 PM PDT 24
Finished Jul 03 05:21:22 PM PDT 24
Peak memory 256068 kb
Host smart-9bc5d641-b99d-47bc-afa6-2cbbbb835fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377146131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.377146131
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2624508517
Short name T955
Test name
Test status
Simulation time 844815352 ps
CPU time 9.36 seconds
Started Jul 03 05:17:19 PM PDT 24
Finished Jul 03 05:17:28 PM PDT 24
Peak memory 224520 kb
Host smart-bcef3381-5a53-49ee-aa28-8807c064d2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624508517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2624508517
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.101430161
Short name T841
Test name
Test status
Simulation time 17724712096 ps
CPU time 17.43 seconds
Started Jul 03 05:17:18 PM PDT 24
Finished Jul 03 05:17:35 PM PDT 24
Peak memory 240596 kb
Host smart-86d6c9cf-129f-43d0-ac19-c0bc8c67395e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101430161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.101430161
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3964883688
Short name T974
Test name
Test status
Simulation time 131433523 ps
CPU time 2.43 seconds
Started Jul 03 05:17:23 PM PDT 24
Finished Jul 03 05:17:26 PM PDT 24
Peak memory 224452 kb
Host smart-61bac90f-c710-4e05-a880-528ad411a2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964883688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3964883688
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4063612600
Short name T242
Test name
Test status
Simulation time 3683514934 ps
CPU time 8.67 seconds
Started Jul 03 05:17:19 PM PDT 24
Finished Jul 03 05:17:28 PM PDT 24
Peak memory 237576 kb
Host smart-31a34c01-6d7f-4253-9db3-a049ddeb8ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063612600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4063612600
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1102583428
Short name T939
Test name
Test status
Simulation time 2623157696 ps
CPU time 11.1 seconds
Started Jul 03 05:17:22 PM PDT 24
Finished Jul 03 05:17:33 PM PDT 24
Peak memory 219372 kb
Host smart-0e22e5df-e69e-4cab-b46e-1d0489aaf1e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1102583428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1102583428
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3902326672
Short name T322
Test name
Test status
Simulation time 1817773040 ps
CPU time 9.63 seconds
Started Jul 03 05:17:17 PM PDT 24
Finished Jul 03 05:17:27 PM PDT 24
Peak memory 216188 kb
Host smart-eaa2695a-1947-4a07-9f09-a94dade594f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902326672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3902326672
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3638040300
Short name T857
Test name
Test status
Simulation time 128552911 ps
CPU time 1.62 seconds
Started Jul 03 05:17:17 PM PDT 24
Finished Jul 03 05:17:19 PM PDT 24
Peak memory 216276 kb
Host smart-c37d4424-85fe-4338-8b94-98e52ddb1ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638040300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3638040300
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.298567085
Short name T602
Test name
Test status
Simulation time 98506600 ps
CPU time 0.95 seconds
Started Jul 03 05:17:19 PM PDT 24
Finished Jul 03 05:17:20 PM PDT 24
Peak memory 205960 kb
Host smart-37c136dc-e8ed-4e78-9ff1-8560242bee55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298567085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.298567085
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2510128627
Short name T128
Test name
Test status
Simulation time 594331289 ps
CPU time 3.46 seconds
Started Jul 03 05:17:21 PM PDT 24
Finished Jul 03 05:17:24 PM PDT 24
Peak memory 232672 kb
Host smart-a97f8ac6-23d7-4961-a04d-e4c145961f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510128627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2510128627
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1343157074
Short name T673
Test name
Test status
Simulation time 13188933 ps
CPU time 0.77 seconds
Started Jul 03 05:17:25 PM PDT 24
Finished Jul 03 05:17:27 PM PDT 24
Peak memory 205476 kb
Host smart-427a2eb6-d9f6-49d5-bc59-55a4d4da9ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343157074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1343157074
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4155032035
Short name T367
Test name
Test status
Simulation time 84075882 ps
CPU time 2.53 seconds
Started Jul 03 05:17:22 PM PDT 24
Finished Jul 03 05:17:25 PM PDT 24
Peak memory 224464 kb
Host smart-512cda09-fb0b-4f8a-89c8-053b6cb51853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155032035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4155032035
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1493298290
Short name T508
Test name
Test status
Simulation time 116176233 ps
CPU time 0.79 seconds
Started Jul 03 05:17:24 PM PDT 24
Finished Jul 03 05:17:25 PM PDT 24
Peak memory 205852 kb
Host smart-52a39478-0f4a-404d-a82c-d7905098a4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493298290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1493298290
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1087750937
Short name T575
Test name
Test status
Simulation time 28369101652 ps
CPU time 54.74 seconds
Started Jul 03 05:17:21 PM PDT 24
Finished Jul 03 05:18:16 PM PDT 24
Peak memory 249232 kb
Host smart-eeb1142f-79c3-4485-a887-2788879435fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087750937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1087750937
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2190904474
Short name T303
Test name
Test status
Simulation time 9239278851 ps
CPU time 108.87 seconds
Started Jul 03 05:17:23 PM PDT 24
Finished Jul 03 05:19:12 PM PDT 24
Peak memory 255196 kb
Host smart-b977bdf6-22de-459a-a271-41ed0b58c8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190904474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2190904474
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3205104424
Short name T619
Test name
Test status
Simulation time 16939384846 ps
CPU time 85.01 seconds
Started Jul 03 05:17:25 PM PDT 24
Finished Jul 03 05:18:50 PM PDT 24
Peak memory 257396 kb
Host smart-f5f22508-5ede-4ebe-a633-2453dcdbd8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205104424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3205104424
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1317477968
Short name T832
Test name
Test status
Simulation time 2237133117 ps
CPU time 28.73 seconds
Started Jul 03 05:17:20 PM PDT 24
Finished Jul 03 05:17:49 PM PDT 24
Peak memory 224564 kb
Host smart-1689b1d4-053f-4848-93a4-bd8e5d9f787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317477968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1317477968
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3620268484
Short name T164
Test name
Test status
Simulation time 157089572351 ps
CPU time 78.99 seconds
Started Jul 03 05:17:24 PM PDT 24
Finished Jul 03 05:18:44 PM PDT 24
Peak memory 249204 kb
Host smart-4f15922f-96eb-42b4-8991-f1e39117a2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620268484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3620268484
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1051578671
Short name T268
Test name
Test status
Simulation time 3089650386 ps
CPU time 15.47 seconds
Started Jul 03 05:17:23 PM PDT 24
Finished Jul 03 05:17:38 PM PDT 24
Peak memory 232840 kb
Host smart-4de15066-fb8f-4673-95da-e95dc01d5eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051578671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1051578671
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3067934168
Short name T192
Test name
Test status
Simulation time 1543887269 ps
CPU time 16.75 seconds
Started Jul 03 05:17:23 PM PDT 24
Finished Jul 03 05:17:41 PM PDT 24
Peak memory 232732 kb
Host smart-3d4fbe5d-929d-41dd-bceb-7f0381e42e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067934168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3067934168
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.32179855
Short name T603
Test name
Test status
Simulation time 11194306170 ps
CPU time 30.35 seconds
Started Jul 03 05:17:21 PM PDT 24
Finished Jul 03 05:17:51 PM PDT 24
Peak memory 224568 kb
Host smart-a4c309ac-fb5d-4740-94ea-3ec8d6ca23b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32179855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.32179855
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.101648046
Short name T577
Test name
Test status
Simulation time 4666154456 ps
CPU time 8.72 seconds
Started Jul 03 05:17:22 PM PDT 24
Finished Jul 03 05:17:31 PM PDT 24
Peak memory 232804 kb
Host smart-0d9d562b-d772-48f1-9c32-6a5bf9591279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101648046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.101648046
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2980377322
Short name T143
Test name
Test status
Simulation time 202574324 ps
CPU time 5.16 seconds
Started Jul 03 05:17:23 PM PDT 24
Finished Jul 03 05:17:29 PM PDT 24
Peak memory 220528 kb
Host smart-e11de4b1-a825-4f36-9afd-9b54a677096b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2980377322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2980377322
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1284940252
Short name T162
Test name
Test status
Simulation time 228166208 ps
CPU time 1.09 seconds
Started Jul 03 05:17:27 PM PDT 24
Finished Jul 03 05:17:29 PM PDT 24
Peak memory 206892 kb
Host smart-ec448970-2886-4a71-a911-bfc8efa9982d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284940252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1284940252
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2835860888
Short name T296
Test name
Test status
Simulation time 50905025979 ps
CPU time 52.35 seconds
Started Jul 03 05:17:26 PM PDT 24
Finished Jul 03 05:18:19 PM PDT 24
Peak memory 221680 kb
Host smart-536e5096-5e4e-46ba-a447-6159162a27e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835860888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2835860888
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3837458480
Short name T996
Test name
Test status
Simulation time 2285327167 ps
CPU time 5.49 seconds
Started Jul 03 05:17:27 PM PDT 24
Finished Jul 03 05:17:32 PM PDT 24
Peak memory 216216 kb
Host smart-3bd06e0d-83d8-4fcb-9bbd-4f45f2ef17f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837458480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3837458480
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3760158699
Short name T349
Test name
Test status
Simulation time 19140830 ps
CPU time 0.92 seconds
Started Jul 03 05:17:22 PM PDT 24
Finished Jul 03 05:17:23 PM PDT 24
Peak memory 207052 kb
Host smart-e7019259-fe18-4dbb-876e-4e588f8a59d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760158699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3760158699
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2604092511
Short name T734
Test name
Test status
Simulation time 301086084 ps
CPU time 0.94 seconds
Started Jul 03 05:17:21 PM PDT 24
Finished Jul 03 05:17:23 PM PDT 24
Peak memory 205976 kb
Host smart-ff1cdd38-545e-4c93-b656-e13fa9d9d40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604092511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2604092511
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2095755497
Short name T389
Test name
Test status
Simulation time 16116447340 ps
CPU time 13.88 seconds
Started Jul 03 05:17:24 PM PDT 24
Finished Jul 03 05:17:38 PM PDT 24
Peak memory 240972 kb
Host smart-12565205-38c0-4003-a5c6-fa425619892e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095755497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2095755497
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1642005183
Short name T807
Test name
Test status
Simulation time 14973817 ps
CPU time 0.72 seconds
Started Jul 03 05:17:27 PM PDT 24
Finished Jul 03 05:17:28 PM PDT 24
Peak memory 204952 kb
Host smart-6678131e-c570-4ed4-9710-c0be6b95945c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642005183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1642005183
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.455428526
Short name T927
Test name
Test status
Simulation time 438750592 ps
CPU time 2.24 seconds
Started Jul 03 05:17:23 PM PDT 24
Finished Jul 03 05:17:26 PM PDT 24
Peak memory 232700 kb
Host smart-8ea94262-9dba-4ce1-9905-abf3b5583a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455428526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.455428526
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1198274145
Short name T424
Test name
Test status
Simulation time 15506796 ps
CPU time 0.83 seconds
Started Jul 03 05:17:23 PM PDT 24
Finished Jul 03 05:17:24 PM PDT 24
Peak memory 206892 kb
Host smart-65aaceaf-b05f-4d1f-b2aa-e6de2ee6c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198274145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1198274145
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.398887574
Short name T769
Test name
Test status
Simulation time 570734367 ps
CPU time 7.91 seconds
Started Jul 03 05:17:24 PM PDT 24
Finished Jul 03 05:17:32 PM PDT 24
Peak memory 224448 kb
Host smart-61c25c85-8268-4e34-8940-e73a26675056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398887574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.398887574
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3242964569
Short name T671
Test name
Test status
Simulation time 12708154335 ps
CPU time 130.48 seconds
Started Jul 03 05:17:29 PM PDT 24
Finished Jul 03 05:19:39 PM PDT 24
Peak memory 240152 kb
Host smart-5cb49f13-f707-49db-b725-092517bc4e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242964569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3242964569
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4085562952
Short name T286
Test name
Test status
Simulation time 90810758036 ps
CPU time 300.59 seconds
Started Jul 03 05:17:32 PM PDT 24
Finished Jul 03 05:22:33 PM PDT 24
Peak memory 273384 kb
Host smart-55820b5b-36a8-423f-a58c-a8896c872a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085562952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4085562952
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1150815456
Short name T693
Test name
Test status
Simulation time 162865893 ps
CPU time 4.91 seconds
Started Jul 03 05:17:27 PM PDT 24
Finished Jul 03 05:17:32 PM PDT 24
Peak memory 232620 kb
Host smart-cad17a3e-300b-4bb1-949d-c0bfeccc4ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150815456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1150815456
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.654312286
Short name T552
Test name
Test status
Simulation time 86345362609 ps
CPU time 101.72 seconds
Started Jul 03 05:17:25 PM PDT 24
Finished Jul 03 05:19:07 PM PDT 24
Peak memory 252976 kb
Host smart-04282514-b3d0-43c8-a7e1-a6699c7771d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654312286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.654312286
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2176398364
Short name T950
Test name
Test status
Simulation time 71441402 ps
CPU time 2.08 seconds
Started Jul 03 05:17:27 PM PDT 24
Finished Jul 03 05:17:29 PM PDT 24
Peak memory 222964 kb
Host smart-5ff57fbd-c737-47fe-a404-13fe29d2bba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176398364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2176398364
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3806163984
Short name T571
Test name
Test status
Simulation time 298794063 ps
CPU time 3.22 seconds
Started Jul 03 05:17:27 PM PDT 24
Finished Jul 03 05:17:31 PM PDT 24
Peak memory 224440 kb
Host smart-25d159ea-eb3e-4a74-ab0d-8461b1054975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806163984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3806163984
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3225443777
Short name T759
Test name
Test status
Simulation time 11447090045 ps
CPU time 14.74 seconds
Started Jul 03 05:17:24 PM PDT 24
Finished Jul 03 05:17:39 PM PDT 24
Peak memory 232744 kb
Host smart-baad0256-6513-45b5-adde-32c0afbe4ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225443777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3225443777
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3167884907
Short name T428
Test name
Test status
Simulation time 2089771515 ps
CPU time 9.49 seconds
Started Jul 03 05:17:26 PM PDT 24
Finished Jul 03 05:17:36 PM PDT 24
Peak memory 232692 kb
Host smart-209e5a37-3752-4094-849f-16f38575bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167884907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3167884907
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2570184931
Short name T384
Test name
Test status
Simulation time 7481432754 ps
CPU time 7.75 seconds
Started Jul 03 05:17:25 PM PDT 24
Finished Jul 03 05:17:34 PM PDT 24
Peak memory 219084 kb
Host smart-df34bfd4-bb11-48df-8a2e-81be49c282d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2570184931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2570184931
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3293183706
Short name T581
Test name
Test status
Simulation time 51287341065 ps
CPU time 210.4 seconds
Started Jul 03 05:17:32 PM PDT 24
Finished Jul 03 05:21:02 PM PDT 24
Peak memory 263760 kb
Host smart-0243bd0d-17e6-48c5-a35a-06fb1972f1e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293183706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3293183706
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3615961575
Short name T633
Test name
Test status
Simulation time 10893780005 ps
CPU time 51.01 seconds
Started Jul 03 05:17:23 PM PDT 24
Finished Jul 03 05:18:15 PM PDT 24
Peak memory 216332 kb
Host smart-4984e2b3-0ae6-4ead-a491-db7a25180d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615961575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3615961575
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3776879934
Short name T675
Test name
Test status
Simulation time 90190059 ps
CPU time 1.27 seconds
Started Jul 03 05:17:24 PM PDT 24
Finished Jul 03 05:17:26 PM PDT 24
Peak memory 207056 kb
Host smart-ebdf462b-97d0-4aa3-86e4-c343577cf5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776879934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3776879934
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3565508578
Short name T345
Test name
Test status
Simulation time 33987260 ps
CPU time 0.71 seconds
Started Jul 03 05:17:25 PM PDT 24
Finished Jul 03 05:17:26 PM PDT 24
Peak memory 205652 kb
Host smart-d3597a27-2708-49d6-b217-a0d45d2261e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565508578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3565508578
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1294054666
Short name T385
Test name
Test status
Simulation time 88327828 ps
CPU time 0.85 seconds
Started Jul 03 05:17:27 PM PDT 24
Finished Jul 03 05:17:29 PM PDT 24
Peak memory 205940 kb
Host smart-18b20f47-c06d-4c74-9354-cd2c7d11e29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294054666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1294054666
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1568749817
Short name T771
Test name
Test status
Simulation time 3328044679 ps
CPU time 5.98 seconds
Started Jul 03 05:17:25 PM PDT 24
Finished Jul 03 05:17:32 PM PDT 24
Peak memory 232848 kb
Host smart-c8457eb6-fd24-4d6b-bbbd-9012ea057086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568749817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1568749817
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3632984086
Short name T459
Test name
Test status
Simulation time 16100655 ps
CPU time 0.72 seconds
Started Jul 03 05:17:36 PM PDT 24
Finished Jul 03 05:17:37 PM PDT 24
Peak memory 204956 kb
Host smart-283bed9f-e1e1-4a6a-92f1-f4b226502822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632984086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3632984086
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4151796869
Short name T8
Test name
Test status
Simulation time 1885858412 ps
CPU time 4.98 seconds
Started Jul 03 05:17:31 PM PDT 24
Finished Jul 03 05:17:36 PM PDT 24
Peak memory 224456 kb
Host smart-e1eab8d1-2f91-4fe3-98bc-400a75651645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151796869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4151796869
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2035297317
Short name T916
Test name
Test status
Simulation time 51243705 ps
CPU time 0.81 seconds
Started Jul 03 05:17:25 PM PDT 24
Finished Jul 03 05:17:27 PM PDT 24
Peak memory 206608 kb
Host smart-103c7196-0340-44bc-8493-4534c29c8348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035297317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2035297317
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3300624133
Short name T998
Test name
Test status
Simulation time 25772161827 ps
CPU time 31.11 seconds
Started Jul 03 05:17:28 PM PDT 24
Finished Jul 03 05:18:00 PM PDT 24
Peak memory 249176 kb
Host smart-aeaf84c9-55f8-4bd6-a081-09c4aea517c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300624133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3300624133
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2471296157
Short name T597
Test name
Test status
Simulation time 16751443144 ps
CPU time 22.5 seconds
Started Jul 03 05:17:30 PM PDT 24
Finished Jul 03 05:17:53 PM PDT 24
Peak memory 219368 kb
Host smart-54f5e540-1f2d-4d59-86f3-f1f7580da408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471296157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2471296157
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.211237064
Short name T496
Test name
Test status
Simulation time 2858283047 ps
CPU time 21.68 seconds
Started Jul 03 05:17:27 PM PDT 24
Finished Jul 03 05:17:49 PM PDT 24
Peak memory 224628 kb
Host smart-47f5d201-ec67-40e9-a5a3-594c3b333dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211237064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.211237064
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1972455922
Short name T784
Test name
Test status
Simulation time 87282446673 ps
CPU time 119.46 seconds
Started Jul 03 05:17:32 PM PDT 24
Finished Jul 03 05:19:31 PM PDT 24
Peak memory 249188 kb
Host smart-bda99dbd-b8c6-48d8-b951-e4f672a7a9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972455922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1972455922
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1484943181
Short name T549
Test name
Test status
Simulation time 441633062 ps
CPU time 7.44 seconds
Started Jul 03 05:17:28 PM PDT 24
Finished Jul 03 05:17:36 PM PDT 24
Peak memory 224460 kb
Host smart-ed402ebb-ed53-4284-8b3e-347d7245f87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484943181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1484943181
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2428169543
Short name T702
Test name
Test status
Simulation time 9071210530 ps
CPU time 46.9 seconds
Started Jul 03 05:17:35 PM PDT 24
Finished Jul 03 05:18:23 PM PDT 24
Peak memory 232752 kb
Host smart-bb65ceb5-7431-461e-b642-c345eb76f7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428169543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2428169543
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2419307242
Short name T914
Test name
Test status
Simulation time 202362038 ps
CPU time 2.37 seconds
Started Jul 03 05:17:28 PM PDT 24
Finished Jul 03 05:17:30 PM PDT 24
Peak memory 223456 kb
Host smart-7fc69db5-c819-461d-9ea9-2a2987031715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419307242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2419307242
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3804118951
Short name T697
Test name
Test status
Simulation time 1282178279 ps
CPU time 7.66 seconds
Started Jul 03 05:17:32 PM PDT 24
Finished Jul 03 05:17:40 PM PDT 24
Peak memory 235688 kb
Host smart-bcf9d875-b94e-4009-83e2-d0ebb4be0c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804118951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3804118951
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.488187482
Short name T770
Test name
Test status
Simulation time 1626007300 ps
CPU time 5.66 seconds
Started Jul 03 05:17:27 PM PDT 24
Finished Jul 03 05:17:33 PM PDT 24
Peak memory 222068 kb
Host smart-5b1447ca-5df7-4c2f-85cf-d4e5197de132
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=488187482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.488187482
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1439676669
Short name T154
Test name
Test status
Simulation time 97519725 ps
CPU time 1.03 seconds
Started Jul 03 05:17:33 PM PDT 24
Finished Jul 03 05:17:34 PM PDT 24
Peak memory 206932 kb
Host smart-a17759b6-120e-40a3-abee-7284bbe5b51a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439676669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1439676669
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2690419017
Short name T968
Test name
Test status
Simulation time 8537754218 ps
CPU time 10.36 seconds
Started Jul 03 05:17:36 PM PDT 24
Finished Jul 03 05:17:47 PM PDT 24
Peak memory 219728 kb
Host smart-e87245c8-eced-4024-96c9-6881a2a344ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690419017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2690419017
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3169970330
Short name T315
Test name
Test status
Simulation time 1837364404 ps
CPU time 8.97 seconds
Started Jul 03 05:17:33 PM PDT 24
Finished Jul 03 05:17:42 PM PDT 24
Peak memory 216260 kb
Host smart-476d8f0c-9047-4a77-ade0-287ce006ee6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169970330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3169970330
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1898519926
Short name T910
Test name
Test status
Simulation time 27558316 ps
CPU time 1.1 seconds
Started Jul 03 05:17:35 PM PDT 24
Finished Jul 03 05:17:37 PM PDT 24
Peak memory 207900 kb
Host smart-d4091940-0a4a-446f-9fb7-a3759c6bc091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898519926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1898519926
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.39951301
Short name T5
Test name
Test status
Simulation time 92684759 ps
CPU time 0.83 seconds
Started Jul 03 05:17:29 PM PDT 24
Finished Jul 03 05:17:30 PM PDT 24
Peak memory 205980 kb
Host smart-c86d7bf4-0d12-43b9-b2ae-12ef02d2b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39951301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.39951301
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.19461251
Short name T652
Test name
Test status
Simulation time 1033989088 ps
CPU time 2.96 seconds
Started Jul 03 05:17:35 PM PDT 24
Finished Jul 03 05:17:39 PM PDT 24
Peak memory 232704 kb
Host smart-79a4c6a5-b3da-4ddf-b1e7-cff6bb12f403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19461251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.19461251
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2954867418
Short name T817
Test name
Test status
Simulation time 13905979 ps
CPU time 0.74 seconds
Started Jul 03 05:17:37 PM PDT 24
Finished Jul 03 05:17:38 PM PDT 24
Peak memory 204940 kb
Host smart-968a7b57-a6bf-4c50-a1c3-60462dbcbce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954867418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2954867418
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.554204197
Short name T568
Test name
Test status
Simulation time 2591564988 ps
CPU time 21.63 seconds
Started Jul 03 05:17:33 PM PDT 24
Finished Jul 03 05:17:55 PM PDT 24
Peak memory 232720 kb
Host smart-c706415f-72b3-45f0-8b54-f81842877156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554204197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.554204197
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2307820282
Short name T690
Test name
Test status
Simulation time 16457843 ps
CPU time 0.72 seconds
Started Jul 03 05:17:33 PM PDT 24
Finished Jul 03 05:17:34 PM PDT 24
Peak memory 205548 kb
Host smart-f1b96c80-a33b-4b6e-830c-eb26dc489165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307820282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2307820282
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.759454755
Short name T440
Test name
Test status
Simulation time 127438188026 ps
CPU time 120.3 seconds
Started Jul 03 05:17:33 PM PDT 24
Finished Jul 03 05:19:34 PM PDT 24
Peak memory 254524 kb
Host smart-2f43e940-e5ed-4c5d-bf83-225a2315649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759454755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.759454755
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2697038195
Short name T773
Test name
Test status
Simulation time 3079471729 ps
CPU time 13.7 seconds
Started Jul 03 05:17:34 PM PDT 24
Finished Jul 03 05:17:48 PM PDT 24
Peak memory 217464 kb
Host smart-614d92c0-a39f-4d1d-b641-578ea0d5463a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697038195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2697038195
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.35323628
Short name T236
Test name
Test status
Simulation time 1734151950 ps
CPU time 21.05 seconds
Started Jul 03 05:17:33 PM PDT 24
Finished Jul 03 05:17:55 PM PDT 24
Peak memory 237172 kb
Host smart-b973f1db-51bc-425a-a135-8ee3d17afc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35323628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.35323628
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.960657484
Short name T845
Test name
Test status
Simulation time 203859307 ps
CPU time 2.65 seconds
Started Jul 03 05:17:30 PM PDT 24
Finished Jul 03 05:17:33 PM PDT 24
Peak memory 232652 kb
Host smart-213dd626-af73-4426-aafa-d1234fffbd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960657484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.960657484
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1719568824
Short name T963
Test name
Test status
Simulation time 7367975480 ps
CPU time 18.69 seconds
Started Jul 03 05:17:33 PM PDT 24
Finished Jul 03 05:17:52 PM PDT 24
Peak memory 232788 kb
Host smart-10fe2764-e848-4877-bd69-fca05a232177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719568824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1719568824
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2013195956
Short name T865
Test name
Test status
Simulation time 5538957269 ps
CPU time 4.79 seconds
Started Jul 03 05:17:37 PM PDT 24
Finished Jul 03 05:17:42 PM PDT 24
Peak memory 232736 kb
Host smart-53488f56-e148-4492-9e83-e02fd626330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013195956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2013195956
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.320985567
Short name T250
Test name
Test status
Simulation time 8723804272 ps
CPU time 7.84 seconds
Started Jul 03 05:17:35 PM PDT 24
Finished Jul 03 05:17:43 PM PDT 24
Peak memory 224608 kb
Host smart-f5467038-8850-4311-81b5-1b10970c6dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320985567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.320985567
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1500666666
Short name T584
Test name
Test status
Simulation time 295525069 ps
CPU time 5.13 seconds
Started Jul 03 05:17:34 PM PDT 24
Finished Jul 03 05:17:39 PM PDT 24
Peak memory 218740 kb
Host smart-7247c6b3-032a-402d-a152-22cb6f479294
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1500666666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1500666666
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.69809457
Short name T922
Test name
Test status
Simulation time 10271042282 ps
CPU time 41.13 seconds
Started Jul 03 05:17:33 PM PDT 24
Finished Jul 03 05:18:15 PM PDT 24
Peak memory 224684 kb
Host smart-1668adba-21a0-4455-8724-5d17001c2ba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69809457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress
_all.69809457
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.281358206
Short name T988
Test name
Test status
Simulation time 44107903 ps
CPU time 0.72 seconds
Started Jul 03 05:17:35 PM PDT 24
Finished Jul 03 05:17:36 PM PDT 24
Peak memory 205716 kb
Host smart-c6b7d876-f5bd-4d1f-bf6f-63c6bd9f3860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281358206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.281358206
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2793720600
Short name T313
Test name
Test status
Simulation time 91474243 ps
CPU time 1.2 seconds
Started Jul 03 05:17:34 PM PDT 24
Finished Jul 03 05:17:35 PM PDT 24
Peak memory 207920 kb
Host smart-fc887d90-146e-407c-a8f2-5771a0b588ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793720600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2793720600
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1030224009
Short name T7
Test name
Test status
Simulation time 20019010 ps
CPU time 0.87 seconds
Started Jul 03 05:17:35 PM PDT 24
Finished Jul 03 05:17:36 PM PDT 24
Peak memory 206008 kb
Host smart-7c277c69-f328-4f34-8acc-a794f404aa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030224009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1030224009
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1178387657
Short name T326
Test name
Test status
Simulation time 695950843 ps
CPU time 0.86 seconds
Started Jul 03 05:17:33 PM PDT 24
Finished Jul 03 05:17:34 PM PDT 24
Peak memory 205964 kb
Host smart-79bbdfb7-5509-49b0-8dcf-073fd1543bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178387657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1178387657
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.439108817
Short name T245
Test name
Test status
Simulation time 1509742043 ps
CPU time 6.19 seconds
Started Jul 03 05:17:34 PM PDT 24
Finished Jul 03 05:17:41 PM PDT 24
Peak memory 239768 kb
Host smart-b82f7e05-aa65-4f90-a9b4-a867fe20b5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439108817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.439108817
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1984614304
Short name T353
Test name
Test status
Simulation time 24374217 ps
CPU time 0.76 seconds
Started Jul 03 05:17:41 PM PDT 24
Finished Jul 03 05:17:42 PM PDT 24
Peak memory 205480 kb
Host smart-cc972ce8-9490-41a5-b526-e05b19593976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984614304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1984614304
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3595860333
Short name T932
Test name
Test status
Simulation time 229249487 ps
CPU time 4.38 seconds
Started Jul 03 05:17:36 PM PDT 24
Finished Jul 03 05:17:40 PM PDT 24
Peak memory 224456 kb
Host smart-0200194d-761e-49a7-ab6f-0584a6caf937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595860333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3595860333
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2528286073
Short name T351
Test name
Test status
Simulation time 229040379 ps
CPU time 0.8 seconds
Started Jul 03 05:17:34 PM PDT 24
Finished Jul 03 05:17:35 PM PDT 24
Peak memory 207148 kb
Host smart-834f64d3-c646-4752-8a24-2f569578308e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528286073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2528286073
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.491359052
Short name T272
Test name
Test status
Simulation time 8098722735 ps
CPU time 33.88 seconds
Started Jul 03 05:17:39 PM PDT 24
Finished Jul 03 05:18:13 PM PDT 24
Peak memory 254636 kb
Host smart-37299e25-3a4b-47fd-9eaf-f33461dc3696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491359052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.491359052
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3248697098
Short name T588
Test name
Test status
Simulation time 27362521693 ps
CPU time 97.63 seconds
Started Jul 03 05:17:38 PM PDT 24
Finished Jul 03 05:19:16 PM PDT 24
Peak memory 257460 kb
Host smart-0b615b06-4b78-4f98-8378-555d5d828200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248697098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3248697098
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3362405186
Short name T50
Test name
Test status
Simulation time 12574776372 ps
CPU time 162.17 seconds
Started Jul 03 05:17:40 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 255412 kb
Host smart-7e2d4849-08ac-437d-83f4-ddaa290c660c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362405186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3362405186
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1523041175
Short name T124
Test name
Test status
Simulation time 113491731 ps
CPU time 5.46 seconds
Started Jul 03 05:17:38 PM PDT 24
Finished Jul 03 05:17:44 PM PDT 24
Peak memory 224468 kb
Host smart-94fffccd-2fe2-4a34-989f-fbcb9f50dc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523041175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1523041175
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3154964609
Short name T831
Test name
Test status
Simulation time 4479488408 ps
CPU time 32.59 seconds
Started Jul 03 05:17:37 PM PDT 24
Finished Jul 03 05:18:10 PM PDT 24
Peak memory 238184 kb
Host smart-de4a6faf-d049-42d9-b459-6bd65e80fed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154964609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3154964609
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2847363371
Short name T265
Test name
Test status
Simulation time 30152912 ps
CPU time 1.98 seconds
Started Jul 03 05:17:36 PM PDT 24
Finished Jul 03 05:17:38 PM PDT 24
Peak memory 224488 kb
Host smart-1d809cbb-a6be-4b84-a48d-ce1a27460575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847363371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2847363371
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.108035963
Short name T695
Test name
Test status
Simulation time 4051144178 ps
CPU time 16.99 seconds
Started Jul 03 05:17:40 PM PDT 24
Finished Jul 03 05:17:57 PM PDT 24
Peak memory 224580 kb
Host smart-4002fb73-4453-4394-89ae-834745f3acd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108035963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.108035963
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.59320119
Short name T722
Test name
Test status
Simulation time 33904821292 ps
CPU time 24.05 seconds
Started Jul 03 05:17:39 PM PDT 24
Finished Jul 03 05:18:04 PM PDT 24
Peak memory 224648 kb
Host smart-eef46710-6bdc-4dc9-a4db-69b2cab7eabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59320119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.59320119
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.555607031
Short name T733
Test name
Test status
Simulation time 174865381 ps
CPU time 3.24 seconds
Started Jul 03 05:17:40 PM PDT 24
Finished Jul 03 05:17:43 PM PDT 24
Peak memory 224448 kb
Host smart-c1970964-6468-41b3-96d4-b899e253f6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555607031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.555607031
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.309152954
Short name T979
Test name
Test status
Simulation time 3966817377 ps
CPU time 11.68 seconds
Started Jul 03 05:17:36 PM PDT 24
Finished Jul 03 05:17:48 PM PDT 24
Peak memory 223212 kb
Host smart-5e00ce34-7530-44ee-8b72-2143e188ea7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=309152954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.309152954
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3249507677
Short name T884
Test name
Test status
Simulation time 18833055126 ps
CPU time 25.17 seconds
Started Jul 03 05:17:37 PM PDT 24
Finished Jul 03 05:18:03 PM PDT 24
Peak memory 216348 kb
Host smart-3970e47f-9ab2-42a8-9d1f-1e1fa6f9e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249507677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3249507677
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3007097756
Short name T730
Test name
Test status
Simulation time 2053185233 ps
CPU time 4.35 seconds
Started Jul 03 05:17:39 PM PDT 24
Finished Jul 03 05:17:44 PM PDT 24
Peak memory 216204 kb
Host smart-f12a4fcf-9813-4edd-bf55-f8f6ca9ca100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007097756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3007097756
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1982273083
Short name T308
Test name
Test status
Simulation time 93005744 ps
CPU time 1.02 seconds
Started Jul 03 05:17:38 PM PDT 24
Finished Jul 03 05:17:39 PM PDT 24
Peak memory 207032 kb
Host smart-cd081960-119a-4b54-9918-511d9e390a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982273083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1982273083
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2024540346
Short name T981
Test name
Test status
Simulation time 226387990 ps
CPU time 0.88 seconds
Started Jul 03 05:17:35 PM PDT 24
Finished Jul 03 05:17:37 PM PDT 24
Peak memory 206004 kb
Host smart-f65ead02-b0a6-46bd-8c4f-682d0e58f001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024540346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2024540346
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1631946192
Short name T354
Test name
Test status
Simulation time 1200971758 ps
CPU time 6.94 seconds
Started Jul 03 05:17:37 PM PDT 24
Finished Jul 03 05:17:44 PM PDT 24
Peak memory 240784 kb
Host smart-d9c321af-a444-443c-8bf9-8bd25227c96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631946192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1631946192
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.874354473
Short name T915
Test name
Test status
Simulation time 12999854 ps
CPU time 0.7 seconds
Started Jul 03 05:17:43 PM PDT 24
Finished Jul 03 05:17:44 PM PDT 24
Peak memory 204944 kb
Host smart-ac013737-4c2f-4b08-a85e-572b8b7b6b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874354473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.874354473
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3952600209
Short name T186
Test name
Test status
Simulation time 894840704 ps
CPU time 5.54 seconds
Started Jul 03 05:17:38 PM PDT 24
Finished Jul 03 05:17:44 PM PDT 24
Peak memory 232712 kb
Host smart-d04f4e25-649e-4844-9579-84770070e211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952600209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3952600209
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2682225321
Short name T371
Test name
Test status
Simulation time 69772824 ps
CPU time 0.85 seconds
Started Jul 03 05:17:41 PM PDT 24
Finished Jul 03 05:17:42 PM PDT 24
Peak memory 206868 kb
Host smart-82f5cd8f-682c-4f58-839f-70c0c14457ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682225321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2682225321
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2845718782
Short name T216
Test name
Test status
Simulation time 25409583880 ps
CPU time 99.17 seconds
Started Jul 03 05:17:41 PM PDT 24
Finished Jul 03 05:19:20 PM PDT 24
Peak memory 240192 kb
Host smart-7daacfa6-b39f-40ae-81fe-bdd3bc7179cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845718782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2845718782
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2990237831
Short name T125
Test name
Test status
Simulation time 469635328205 ps
CPU time 421.4 seconds
Started Jul 03 05:17:44 PM PDT 24
Finished Jul 03 05:24:45 PM PDT 24
Peak memory 264548 kb
Host smart-13a08f69-a0b9-4db4-98f8-b2e62949f753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990237831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2990237831
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3763210120
Short name T701
Test name
Test status
Simulation time 13166177447 ps
CPU time 92.11 seconds
Started Jul 03 05:17:44 PM PDT 24
Finished Jul 03 05:19:17 PM PDT 24
Peak memory 254900 kb
Host smart-da060e34-10ff-450d-a944-47705813d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763210120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3763210120
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2015473292
Short name T146
Test name
Test status
Simulation time 1086865847 ps
CPU time 5.16 seconds
Started Jul 03 05:17:40 PM PDT 24
Finished Jul 03 05:17:46 PM PDT 24
Peak memory 233488 kb
Host smart-209a8c3d-61d3-4d0b-b85f-ae6df5093caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015473292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2015473292
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3036158077
Short name T258
Test name
Test status
Simulation time 218071552473 ps
CPU time 265.91 seconds
Started Jul 03 05:17:39 PM PDT 24
Finished Jul 03 05:22:06 PM PDT 24
Peak memory 249168 kb
Host smart-301b843a-e4d8-45d1-b4f6-18462ff4a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036158077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3036158077
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1479535298
Short name T747
Test name
Test status
Simulation time 115224246 ps
CPU time 2.46 seconds
Started Jul 03 05:17:42 PM PDT 24
Finished Jul 03 05:17:45 PM PDT 24
Peak memory 232672 kb
Host smart-39b92ea3-3988-4d5e-bf05-d4e7dabc9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479535298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1479535298
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2096602392
Short name T704
Test name
Test status
Simulation time 468772427 ps
CPU time 5.58 seconds
Started Jul 03 05:17:41 PM PDT 24
Finished Jul 03 05:17:47 PM PDT 24
Peak memory 232680 kb
Host smart-c69ae363-90ee-4e2a-bfcc-8234a347cf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096602392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2096602392
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1059131563
Short name T436
Test name
Test status
Simulation time 1440147748 ps
CPU time 5.4 seconds
Started Jul 03 05:17:40 PM PDT 24
Finished Jul 03 05:17:45 PM PDT 24
Peak memory 224448 kb
Host smart-b15ce577-a3f5-4eb6-95a5-00ac75c18d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059131563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1059131563
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.371599840
Short name T735
Test name
Test status
Simulation time 6053305524 ps
CPU time 6.96 seconds
Started Jul 03 05:17:41 PM PDT 24
Finished Jul 03 05:17:48 PM PDT 24
Peak memory 232776 kb
Host smart-ca36d7b9-459b-44b2-83e5-af0966d56df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371599840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.371599840
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2686022648
Short name T387
Test name
Test status
Simulation time 1587012674 ps
CPU time 9.26 seconds
Started Jul 03 05:17:41 PM PDT 24
Finished Jul 03 05:17:51 PM PDT 24
Peak memory 219284 kb
Host smart-521d1fc1-99a2-496a-8deb-70e54557928c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2686022648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2686022648
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3392859559
Short name T377
Test name
Test status
Simulation time 53686726 ps
CPU time 1.12 seconds
Started Jul 03 05:17:41 PM PDT 24
Finished Jul 03 05:17:43 PM PDT 24
Peak memory 207736 kb
Host smart-d54600ec-3283-43b4-935f-19be2fbc380b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392859559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3392859559
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2317125937
Short name T306
Test name
Test status
Simulation time 4029138835 ps
CPU time 31.83 seconds
Started Jul 03 05:17:39 PM PDT 24
Finished Jul 03 05:18:11 PM PDT 24
Peak memory 216308 kb
Host smart-1e7b69b3-ddc9-4fc4-b767-e31c62b572d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317125937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2317125937
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1956436978
Short name T622
Test name
Test status
Simulation time 743069759 ps
CPU time 3.45 seconds
Started Jul 03 05:17:44 PM PDT 24
Finished Jul 03 05:17:48 PM PDT 24
Peak memory 216180 kb
Host smart-91b0c8ef-f935-440b-9373-e2fa9cce3e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956436978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1956436978
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1355856470
Short name T798
Test name
Test status
Simulation time 11519050 ps
CPU time 0.76 seconds
Started Jul 03 05:17:39 PM PDT 24
Finished Jul 03 05:17:40 PM PDT 24
Peak memory 205992 kb
Host smart-b93ad4d6-f464-4f39-a328-ba2ff344e342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355856470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1355856470
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2979872288
Short name T447
Test name
Test status
Simulation time 385679670 ps
CPU time 1.03 seconds
Started Jul 03 05:17:39 PM PDT 24
Finished Jul 03 05:17:41 PM PDT 24
Peak memory 206984 kb
Host smart-66226119-c42e-4b74-b949-5868a2f4f029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979872288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2979872288
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3210988955
Short name T696
Test name
Test status
Simulation time 2274260994 ps
CPU time 4.15 seconds
Started Jul 03 05:17:40 PM PDT 24
Finished Jul 03 05:17:45 PM PDT 24
Peak memory 224564 kb
Host smart-8685ea38-54f8-4c23-9be3-41b0d6326f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210988955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3210988955
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3864554016
Short name T312
Test name
Test status
Simulation time 10672655 ps
CPU time 0.73 seconds
Started Jul 03 05:17:41 PM PDT 24
Finished Jul 03 05:17:42 PM PDT 24
Peak memory 205824 kb
Host smart-ab90a3b8-4544-4142-8394-50b51a1923fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864554016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3864554016
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3790038342
Short name T750
Test name
Test status
Simulation time 743038099 ps
CPU time 8.25 seconds
Started Jul 03 05:17:44 PM PDT 24
Finished Jul 03 05:17:53 PM PDT 24
Peak memory 224484 kb
Host smart-d0a2311d-f94f-455a-84ac-8a522bf4d0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790038342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3790038342
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.379858954
Short name T947
Test name
Test status
Simulation time 17271220 ps
CPU time 0.82 seconds
Started Jul 03 05:17:44 PM PDT 24
Finished Jul 03 05:17:45 PM PDT 24
Peak memory 206576 kb
Host smart-96244231-eca8-4627-8f4e-f38c6cd75ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379858954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.379858954
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3040530400
Short name T641
Test name
Test status
Simulation time 10352293548 ps
CPU time 19.59 seconds
Started Jul 03 05:17:44 PM PDT 24
Finished Jul 03 05:18:04 PM PDT 24
Peak memory 224632 kb
Host smart-febabb39-a801-438a-8bfc-935473ac9ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040530400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3040530400
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1159752588
Short name T273
Test name
Test status
Simulation time 58436643266 ps
CPU time 145.31 seconds
Started Jul 03 05:17:47 PM PDT 24
Finished Jul 03 05:20:13 PM PDT 24
Peak memory 264328 kb
Host smart-02aecc98-e886-44e9-a45c-7f15ded87f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159752588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1159752588
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3499923887
Short name T816
Test name
Test status
Simulation time 4748174786 ps
CPU time 52.92 seconds
Started Jul 03 05:17:45 PM PDT 24
Finished Jul 03 05:18:38 PM PDT 24
Peak memory 234340 kb
Host smart-f58df21d-1644-4adf-ae57-d441efcf9dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499923887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3499923887
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3537702997
Short name T985
Test name
Test status
Simulation time 3922875002 ps
CPU time 28.48 seconds
Started Jul 03 05:17:44 PM PDT 24
Finished Jul 03 05:18:13 PM PDT 24
Peak memory 249024 kb
Host smart-675aeb7a-978a-472c-b25b-2931d56ff3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537702997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3537702997
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2165645425
Short name T899
Test name
Test status
Simulation time 16277232269 ps
CPU time 39.27 seconds
Started Jul 03 05:17:42 PM PDT 24
Finished Jul 03 05:18:22 PM PDT 24
Peak memory 252168 kb
Host smart-91599440-7ac0-40b6-a7d1-f41e16c63ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165645425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2165645425
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.508907715
Short name T764
Test name
Test status
Simulation time 180062699 ps
CPU time 4.98 seconds
Started Jul 03 05:17:47 PM PDT 24
Finished Jul 03 05:17:52 PM PDT 24
Peak memory 232696 kb
Host smart-c9849768-c54e-49d7-bc8a-ca78e66d454c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508907715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.508907715
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2789865737
Short name T706
Test name
Test status
Simulation time 2330034531 ps
CPU time 12.47 seconds
Started Jul 03 05:17:45 PM PDT 24
Finished Jul 03 05:17:58 PM PDT 24
Peak memory 232840 kb
Host smart-7ada14d0-06f9-4aac-945e-34f5b91bbcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789865737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2789865737
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2336367874
Short name T606
Test name
Test status
Simulation time 1191902565 ps
CPU time 8.36 seconds
Started Jul 03 05:17:45 PM PDT 24
Finished Jul 03 05:17:54 PM PDT 24
Peak memory 232736 kb
Host smart-bda40503-cd5c-4e6f-ae56-d9ef5fecc1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336367874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2336367874
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3832317520
Short name T213
Test name
Test status
Simulation time 9415736167 ps
CPU time 9.95 seconds
Started Jul 03 05:17:43 PM PDT 24
Finished Jul 03 05:17:53 PM PDT 24
Peak memory 232776 kb
Host smart-6bd5d948-c9e5-44a7-8df0-cd5c149473cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832317520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3832317520
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.109782653
Short name T480
Test name
Test status
Simulation time 1207696796 ps
CPU time 5.68 seconds
Started Jul 03 05:17:43 PM PDT 24
Finished Jul 03 05:17:49 PM PDT 24
Peak memory 223164 kb
Host smart-5fb34235-23a7-4f81-82a7-4ea4d650918f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=109782653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.109782653
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2287940719
Short name T157
Test name
Test status
Simulation time 312588967994 ps
CPU time 576.75 seconds
Started Jul 03 05:17:44 PM PDT 24
Finished Jul 03 05:27:21 PM PDT 24
Peak memory 270432 kb
Host smart-13ee08f8-b01f-40c2-9117-68ecac11698a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287940719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2287940719
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2831650433
Short name T763
Test name
Test status
Simulation time 17407508879 ps
CPU time 23.08 seconds
Started Jul 03 05:17:42 PM PDT 24
Finished Jul 03 05:18:06 PM PDT 24
Peak memory 216292 kb
Host smart-2e106d1d-cf2b-4184-9ad8-7bfd6b5fa57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831650433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2831650433
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3225209136
Short name T962
Test name
Test status
Simulation time 515953865 ps
CPU time 1.95 seconds
Started Jul 03 05:17:47 PM PDT 24
Finished Jul 03 05:17:49 PM PDT 24
Peak memory 207920 kb
Host smart-b5256e3d-50e5-4628-a310-b0b938a49c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225209136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3225209136
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1176520306
Short name T165
Test name
Test status
Simulation time 322518736 ps
CPU time 1.01 seconds
Started Jul 03 05:17:45 PM PDT 24
Finished Jul 03 05:17:47 PM PDT 24
Peak memory 207480 kb
Host smart-778d3158-db3d-4a7d-9201-dc87fa9c62b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176520306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1176520306
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3631840263
Short name T513
Test name
Test status
Simulation time 44403551 ps
CPU time 0.95 seconds
Started Jul 03 05:17:46 PM PDT 24
Finished Jul 03 05:17:47 PM PDT 24
Peak memory 206196 kb
Host smart-a47d3bd6-8bd9-4805-91ac-c21a53f88f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631840263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3631840263
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.566482322
Short name T590
Test name
Test status
Simulation time 100421796863 ps
CPU time 18.06 seconds
Started Jul 03 05:17:42 PM PDT 24
Finished Jul 03 05:18:01 PM PDT 24
Peak memory 232792 kb
Host smart-5bec18e5-702e-411d-8e96-eaba0090d9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566482322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.566482322
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1009530743
Short name T544
Test name
Test status
Simulation time 13661902 ps
CPU time 0.71 seconds
Started Jul 03 05:17:53 PM PDT 24
Finished Jul 03 05:17:54 PM PDT 24
Peak memory 205864 kb
Host smart-a36b6a63-48b1-47b4-9d77-dcb4a0977b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009530743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1009530743
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1558483496
Short name T787
Test name
Test status
Simulation time 859247573 ps
CPU time 2.23 seconds
Started Jul 03 05:17:47 PM PDT 24
Finished Jul 03 05:17:49 PM PDT 24
Peak memory 224064 kb
Host smart-db9f45b7-a0e3-4ec8-b302-125d6bfa70ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558483496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1558483496
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1214779098
Short name T167
Test name
Test status
Simulation time 19570316 ps
CPU time 0.8 seconds
Started Jul 03 05:17:42 PM PDT 24
Finished Jul 03 05:17:44 PM PDT 24
Peak memory 206876 kb
Host smart-c0b546cc-af76-4f89-90cd-d63f837fd75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214779098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1214779098
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.900098096
Short name T32
Test name
Test status
Simulation time 14513924173 ps
CPU time 76.04 seconds
Started Jul 03 05:17:51 PM PDT 24
Finished Jul 03 05:19:07 PM PDT 24
Peak memory 254856 kb
Host smart-0f655bcb-a0a9-41a8-912d-16708245a898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900098096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.900098096
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1585319057
Short name T287
Test name
Test status
Simulation time 11526915570 ps
CPU time 119.31 seconds
Started Jul 03 05:17:52 PM PDT 24
Finished Jul 03 05:19:52 PM PDT 24
Peak memory 249632 kb
Host smart-f2dfaf0f-2843-477d-bd63-4f792531a452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585319057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1585319057
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1766777595
Short name T276
Test name
Test status
Simulation time 126694648783 ps
CPU time 293.24 seconds
Started Jul 03 05:17:50 PM PDT 24
Finished Jul 03 05:22:44 PM PDT 24
Peak memory 256056 kb
Host smart-2ed05b9e-2903-4ed4-87e8-d130ab07f110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766777595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1766777595
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2284928909
Short name T960
Test name
Test status
Simulation time 2218877736 ps
CPU time 35.93 seconds
Started Jul 03 05:17:47 PM PDT 24
Finished Jul 03 05:18:23 PM PDT 24
Peak memory 233672 kb
Host smart-8947ac79-042b-4c09-bac8-ef09aeca7f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284928909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2284928909
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2312338149
Short name T374
Test name
Test status
Simulation time 22936749130 ps
CPU time 39.29 seconds
Started Jul 03 05:17:53 PM PDT 24
Finished Jul 03 05:18:33 PM PDT 24
Peak memory 232848 kb
Host smart-53edffc9-2536-434f-930c-2dcb45fcfd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312338149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2312338149
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.335096577
Short name T774
Test name
Test status
Simulation time 331529480 ps
CPU time 3.25 seconds
Started Jul 03 05:17:46 PM PDT 24
Finished Jul 03 05:17:50 PM PDT 24
Peak memory 232676 kb
Host smart-3ab82f13-b6f9-4a00-8c2f-24f084109b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335096577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.335096577
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.322602816
Short name T980
Test name
Test status
Simulation time 278083992 ps
CPU time 2.34 seconds
Started Jul 03 05:17:48 PM PDT 24
Finished Jul 03 05:17:51 PM PDT 24
Peak memory 223240 kb
Host smart-68dbf49b-2f5f-46c4-80ce-41dcfa9c3267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322602816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.322602816
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2682635061
Short name T445
Test name
Test status
Simulation time 497169764 ps
CPU time 2.34 seconds
Started Jul 03 05:17:48 PM PDT 24
Finished Jul 03 05:17:51 PM PDT 24
Peak memory 224132 kb
Host smart-b0614071-d5e3-4b74-b2f7-bc5e4ba16ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682635061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2682635061
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3680132362
Short name T986
Test name
Test status
Simulation time 5917692728 ps
CPU time 17.79 seconds
Started Jul 03 05:17:46 PM PDT 24
Finished Jul 03 05:18:04 PM PDT 24
Peak memory 224520 kb
Host smart-9036b0aa-aa59-40c6-92e4-7a12b0582875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680132362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3680132362
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2211457107
Short name T509
Test name
Test status
Simulation time 2296736160 ps
CPU time 9.14 seconds
Started Jul 03 05:17:51 PM PDT 24
Finished Jul 03 05:18:01 PM PDT 24
Peak memory 223156 kb
Host smart-90bd53e3-efa7-4057-a510-fa30a878bad7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2211457107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2211457107
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.4029733036
Short name T859
Test name
Test status
Simulation time 17998918 ps
CPU time 0.7 seconds
Started Jul 03 05:17:46 PM PDT 24
Finished Jul 03 05:17:47 PM PDT 24
Peak memory 205712 kb
Host smart-cdc7ea62-9279-4c38-b92c-d7d0f1d72d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029733036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.4029733036
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3929932319
Short name T365
Test name
Test status
Simulation time 1261471038 ps
CPU time 3.24 seconds
Started Jul 03 05:17:47 PM PDT 24
Finished Jul 03 05:17:50 PM PDT 24
Peak memory 216088 kb
Host smart-cc6a2cde-e69f-4170-8031-2e412c518518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929932319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3929932319
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2515667793
Short name T491
Test name
Test status
Simulation time 305637200 ps
CPU time 4.62 seconds
Started Jul 03 05:17:48 PM PDT 24
Finished Jul 03 05:17:53 PM PDT 24
Peak memory 216200 kb
Host smart-b0c5a0c0-d734-46b8-879b-f7034ea5ea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515667793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2515667793
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1396226813
Short name T768
Test name
Test status
Simulation time 18747155 ps
CPU time 0.75 seconds
Started Jul 03 05:17:48 PM PDT 24
Finished Jul 03 05:17:49 PM PDT 24
Peak memory 205984 kb
Host smart-90e385ba-e0a3-4d7e-9319-e9f446c9b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396226813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1396226813
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3972735673
Short name T872
Test name
Test status
Simulation time 48924918 ps
CPU time 2.66 seconds
Started Jul 03 05:17:47 PM PDT 24
Finished Jul 03 05:17:50 PM PDT 24
Peak memory 232724 kb
Host smart-dbe37ec9-a064-4b74-a082-8644ec596836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972735673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3972735673
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.844426611
Short name T479
Test name
Test status
Simulation time 15040196 ps
CPU time 0.78 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:18:06 PM PDT 24
Peak memory 204940 kb
Host smart-8627b548-af49-42c3-921f-6303deeb5c76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844426611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.844426611
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.288685374
Short name T1006
Test name
Test status
Simulation time 3250382805 ps
CPU time 9.36 seconds
Started Jul 03 05:17:55 PM PDT 24
Finished Jul 03 05:18:05 PM PDT 24
Peak memory 232776 kb
Host smart-32452919-ff34-4f9f-9903-23a73e969055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288685374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.288685374
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2057457576
Short name T742
Test name
Test status
Simulation time 39271196 ps
CPU time 0.8 seconds
Started Jul 03 05:17:52 PM PDT 24
Finished Jul 03 05:17:53 PM PDT 24
Peak memory 206592 kb
Host smart-4be15b7a-55dd-4904-98d2-7b9f4ed81a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057457576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2057457576
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4133025054
Short name T548
Test name
Test status
Simulation time 18754749534 ps
CPU time 43.68 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:48 PM PDT 24
Peak memory 249184 kb
Host smart-768393c1-e378-4b46-ab62-169ef9d2ff72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133025054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4133025054
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3407526166
Short name T850
Test name
Test status
Simulation time 97176274145 ps
CPU time 252.14 seconds
Started Jul 03 05:17:58 PM PDT 24
Finished Jul 03 05:22:11 PM PDT 24
Peak memory 250300 kb
Host smart-27f2fbc0-5cb9-4334-ad5e-3e7cb08b9fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407526166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3407526166
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.785814188
Short name T138
Test name
Test status
Simulation time 5219008114 ps
CPU time 111.05 seconds
Started Jul 03 05:18:03 PM PDT 24
Finished Jul 03 05:19:55 PM PDT 24
Peak memory 267488 kb
Host smart-05a5eae9-d8da-4539-91dc-6dc777ff316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785814188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.785814188
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1715167658
Short name T972
Test name
Test status
Simulation time 58805359 ps
CPU time 2.23 seconds
Started Jul 03 05:17:56 PM PDT 24
Finished Jul 03 05:17:58 PM PDT 24
Peak memory 224496 kb
Host smart-88be9384-22ba-4b60-8c26-e798a29c462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715167658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1715167658
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1920389851
Short name T88
Test name
Test status
Simulation time 149263520676 ps
CPU time 254.13 seconds
Started Jul 03 05:17:59 PM PDT 24
Finished Jul 03 05:22:14 PM PDT 24
Peak memory 257296 kb
Host smart-00650624-bdfe-4feb-b55f-e0af34c85d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920389851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1920389851
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4225223958
Short name T415
Test name
Test status
Simulation time 411633592 ps
CPU time 2.02 seconds
Started Jul 03 05:18:03 PM PDT 24
Finished Jul 03 05:18:06 PM PDT 24
Peak memory 223424 kb
Host smart-097e6131-1d3b-4708-8b5a-5c3ae736d720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225223958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4225223958
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.815219862
Short name T837
Test name
Test status
Simulation time 275942698 ps
CPU time 2.69 seconds
Started Jul 03 05:17:55 PM PDT 24
Finished Jul 03 05:17:58 PM PDT 24
Peak memory 224488 kb
Host smart-20251725-d009-42a9-ba92-59dc01858490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815219862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.815219862
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3996972930
Short name T736
Test name
Test status
Simulation time 1279510978 ps
CPU time 9.83 seconds
Started Jul 03 05:17:56 PM PDT 24
Finished Jul 03 05:18:06 PM PDT 24
Peak memory 232688 kb
Host smart-810fbe5e-0f84-45f1-bb57-f0bf74ade5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996972930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3996972930
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2214687182
Short name T409
Test name
Test status
Simulation time 1643594503 ps
CPU time 6.63 seconds
Started Jul 03 05:17:51 PM PDT 24
Finished Jul 03 05:17:58 PM PDT 24
Peak memory 224460 kb
Host smart-da7902c1-c9ba-4d21-a589-136df41d52fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214687182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2214687182
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4260268338
Short name T800
Test name
Test status
Simulation time 306174912 ps
CPU time 4.77 seconds
Started Jul 03 05:17:55 PM PDT 24
Finished Jul 03 05:18:00 PM PDT 24
Peak memory 223124 kb
Host smart-55283199-c262-40e7-b795-252873bced78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4260268338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4260268338
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4131691885
Short name T876
Test name
Test status
Simulation time 8910970161 ps
CPU time 45.54 seconds
Started Jul 03 05:17:52 PM PDT 24
Finished Jul 03 05:18:38 PM PDT 24
Peak memory 216316 kb
Host smart-08c97309-fa8d-4b54-b3ee-d02e4f13c828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131691885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4131691885
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1481386367
Short name T599
Test name
Test status
Simulation time 445643894 ps
CPU time 2.68 seconds
Started Jul 03 05:17:53 PM PDT 24
Finished Jul 03 05:17:56 PM PDT 24
Peak memory 216152 kb
Host smart-6790ef1e-50ce-46bc-b141-9c97458f27c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481386367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1481386367
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3691777842
Short name T33
Test name
Test status
Simulation time 103646098 ps
CPU time 1.33 seconds
Started Jul 03 05:17:52 PM PDT 24
Finished Jul 03 05:17:54 PM PDT 24
Peak memory 208028 kb
Host smart-ae3ac059-51c5-4134-afcf-6ed54ea97ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691777842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3691777842
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.128972992
Short name T708
Test name
Test status
Simulation time 109737044 ps
CPU time 0.79 seconds
Started Jul 03 05:17:52 PM PDT 24
Finished Jul 03 05:17:54 PM PDT 24
Peak memory 206308 kb
Host smart-529891ed-9be4-4beb-9ae3-9cb2804a5627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128972992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.128972992
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1106994817
Short name T453
Test name
Test status
Simulation time 220596737 ps
CPU time 2.64 seconds
Started Jul 03 05:17:56 PM PDT 24
Finished Jul 03 05:17:59 PM PDT 24
Peak memory 232728 kb
Host smart-00ed8223-8648-461e-956a-f4cfd08faa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106994817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1106994817
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.68737182
Short name T370
Test name
Test status
Simulation time 19958995 ps
CPU time 0.71 seconds
Started Jul 03 05:16:49 PM PDT 24
Finished Jul 03 05:16:50 PM PDT 24
Peak memory 205852 kb
Host smart-ffc03cd2-bccd-462b-8494-5a8161a73e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68737182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.68737182
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1564245265
Short name T362
Test name
Test status
Simulation time 125098023 ps
CPU time 3.44 seconds
Started Jul 03 05:16:45 PM PDT 24
Finished Jul 03 05:16:49 PM PDT 24
Peak memory 232692 kb
Host smart-a71948b3-d75e-4ac7-b55f-d46947f37964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564245265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1564245265
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2708963133
Short name T333
Test name
Test status
Simulation time 12566334 ps
CPU time 0.76 seconds
Started Jul 03 05:16:43 PM PDT 24
Finished Jul 03 05:16:44 PM PDT 24
Peak memory 205608 kb
Host smart-bd52617a-9af6-45e1-ad4f-59f2b877af52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708963133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2708963133
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1435708992
Short name T542
Test name
Test status
Simulation time 6186845091 ps
CPU time 46.78 seconds
Started Jul 03 05:16:51 PM PDT 24
Finished Jul 03 05:17:38 PM PDT 24
Peak memory 233756 kb
Host smart-41611cd7-83e9-4946-8fd7-62edae52c54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435708992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1435708992
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2266462416
Short name T249
Test name
Test status
Simulation time 25984767007 ps
CPU time 170.44 seconds
Started Jul 03 05:16:50 PM PDT 24
Finished Jul 03 05:19:42 PM PDT 24
Peak memory 272868 kb
Host smart-2f0b7bf2-9c50-4e13-a373-a24fc02ae56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266462416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2266462416
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3893401938
Short name T360
Test name
Test status
Simulation time 53406803 ps
CPU time 3.13 seconds
Started Jul 03 05:16:45 PM PDT 24
Finished Jul 03 05:16:48 PM PDT 24
Peak memory 232620 kb
Host smart-3a34c17d-f305-40a8-99d0-c1be14f7bad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893401938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3893401938
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3530469524
Short name T278
Test name
Test status
Simulation time 22754059879 ps
CPU time 236.28 seconds
Started Jul 03 05:16:45 PM PDT 24
Finished Jul 03 05:20:42 PM PDT 24
Peak memory 265324 kb
Host smart-61574b95-c319-4441-bcb1-fc8257532dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530469524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3530469524
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.844847200
Short name T691
Test name
Test status
Simulation time 782399369 ps
CPU time 4.81 seconds
Started Jul 03 05:16:42 PM PDT 24
Finished Jul 03 05:16:47 PM PDT 24
Peak memory 232840 kb
Host smart-b9850bb1-0ca3-4261-a345-3d93fa47d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844847200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.844847200
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3533361915
Short name T1000
Test name
Test status
Simulation time 29589456 ps
CPU time 2.1 seconds
Started Jul 03 05:16:44 PM PDT 24
Finished Jul 03 05:16:47 PM PDT 24
Peak memory 223512 kb
Host smart-8ca3cbd3-e181-4dcc-8d7c-dc40baaee107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533361915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3533361915
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2076088360
Short name T615
Test name
Test status
Simulation time 32778593910 ps
CPU time 8.69 seconds
Started Jul 03 05:16:46 PM PDT 24
Finished Jul 03 05:16:55 PM PDT 24
Peak memory 236520 kb
Host smart-89f01a3a-9f44-49ad-8ff5-804a86f9e17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076088360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2076088360
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1446831507
Short name T523
Test name
Test status
Simulation time 616392969 ps
CPU time 3.27 seconds
Started Jul 03 05:16:47 PM PDT 24
Finished Jul 03 05:16:51 PM PDT 24
Peak memory 224392 kb
Host smart-67dc74e7-a531-4b38-8e10-689bd7fe013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446831507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1446831507
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2707458162
Short name T666
Test name
Test status
Simulation time 221668584 ps
CPU time 3.9 seconds
Started Jul 03 05:16:47 PM PDT 24
Finished Jul 03 05:16:52 PM PDT 24
Peak memory 223028 kb
Host smart-720bd6df-6f73-403e-ad54-7a4550bf20c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2707458162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2707458162
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3288950786
Short name T71
Test name
Test status
Simulation time 113544668 ps
CPU time 1.2 seconds
Started Jul 03 05:16:46 PM PDT 24
Finished Jul 03 05:16:48 PM PDT 24
Peak memory 237068 kb
Host smart-cef6c2e3-ca07-4923-9031-e7be7b63188b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288950786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3288950786
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3976504755
Short name T329
Test name
Test status
Simulation time 3005148194 ps
CPU time 7.18 seconds
Started Jul 03 05:16:43 PM PDT 24
Finished Jul 03 05:16:51 PM PDT 24
Peak memory 219956 kb
Host smart-6e7d2419-88a0-4e60-bc9e-536ed8aa9c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976504755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3976504755
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1501523304
Short name T660
Test name
Test status
Simulation time 1516164760 ps
CPU time 7.37 seconds
Started Jul 03 05:16:45 PM PDT 24
Finished Jul 03 05:16:53 PM PDT 24
Peak memory 216256 kb
Host smart-70100f13-3f79-4ca8-b4b1-cd2a93ea41a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501523304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1501523304
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.674860269
Short name T794
Test name
Test status
Simulation time 264220517 ps
CPU time 1.39 seconds
Started Jul 03 05:16:44 PM PDT 24
Finished Jul 03 05:16:46 PM PDT 24
Peak memory 216216 kb
Host smart-50a63a75-813c-46f5-80ab-880169294b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674860269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.674860269
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2841695679
Short name T990
Test name
Test status
Simulation time 149762570 ps
CPU time 0.86 seconds
Started Jul 03 05:16:44 PM PDT 24
Finished Jul 03 05:16:46 PM PDT 24
Peak memory 207028 kb
Host smart-95a346cf-83f5-43f9-8fcf-f69d6da07465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841695679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2841695679
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2467858965
Short name T225
Test name
Test status
Simulation time 844246266 ps
CPU time 6.33 seconds
Started Jul 03 05:16:47 PM PDT 24
Finished Jul 03 05:16:54 PM PDT 24
Peak memory 224372 kb
Host smart-02828745-4df0-4d2b-a0ca-5717e1f97dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467858965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2467858965
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2910593478
Short name T501
Test name
Test status
Simulation time 14284114 ps
CPU time 0.71 seconds
Started Jul 03 05:18:03 PM PDT 24
Finished Jul 03 05:18:04 PM PDT 24
Peak memory 205480 kb
Host smart-042a1e13-b5c9-43dc-a882-77543fa139e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910593478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2910593478
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1081215659
Short name T397
Test name
Test status
Simulation time 2109655766 ps
CPU time 6.04 seconds
Started Jul 03 05:18:03 PM PDT 24
Finished Jul 03 05:18:09 PM PDT 24
Peak memory 224436 kb
Host smart-e20acf3d-7e6c-43b4-95fa-ddc8f687cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081215659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1081215659
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.83297973
Short name T350
Test name
Test status
Simulation time 120438679 ps
CPU time 0.87 seconds
Started Jul 03 05:17:56 PM PDT 24
Finished Jul 03 05:17:57 PM PDT 24
Peak memory 206588 kb
Host smart-568f8c38-d36c-421f-a876-fa9058511773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83297973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.83297973
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2803282373
Short name T172
Test name
Test status
Simulation time 115714592941 ps
CPU time 244.42 seconds
Started Jul 03 05:18:00 PM PDT 24
Finished Jul 03 05:22:05 PM PDT 24
Peak memory 265240 kb
Host smart-037d0991-8339-4cb1-ace8-03bbbe915ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803282373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2803282373
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2925187470
Short name T300
Test name
Test status
Simulation time 3354161158 ps
CPU time 33.13 seconds
Started Jul 03 05:18:02 PM PDT 24
Finished Jul 03 05:18:36 PM PDT 24
Peak memory 249288 kb
Host smart-a012fce4-e3e4-43eb-b3a4-8c1bdb6cc950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925187470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2925187470
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1061249079
Short name T648
Test name
Test status
Simulation time 665319621 ps
CPU time 12.27 seconds
Started Jul 03 05:17:58 PM PDT 24
Finished Jul 03 05:18:11 PM PDT 24
Peak memory 240900 kb
Host smart-09e644dc-195a-4dba-a4c6-a37b5d9773bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061249079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1061249079
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.707693156
Short name T931
Test name
Test status
Simulation time 3660739715 ps
CPU time 39.73 seconds
Started Jul 03 05:17:59 PM PDT 24
Finished Jul 03 05:18:39 PM PDT 24
Peak memory 248964 kb
Host smart-ba422e23-cde4-44ae-8157-2260ebbce70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707693156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.707693156
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3133446832
Short name T886
Test name
Test status
Simulation time 1135828624 ps
CPU time 5.14 seconds
Started Jul 03 05:17:56 PM PDT 24
Finished Jul 03 05:18:01 PM PDT 24
Peak memory 224464 kb
Host smart-a0d93c14-5ff9-4ffe-93dd-f3de8b99bd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133446832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3133446832
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3357083415
Short name T267
Test name
Test status
Simulation time 12618709144 ps
CPU time 46 seconds
Started Jul 03 05:17:59 PM PDT 24
Finished Jul 03 05:18:45 PM PDT 24
Peak memory 232828 kb
Host smart-e18ecb98-58d9-408d-8a8b-64ed055605b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357083415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3357083415
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1989865861
Short name T516
Test name
Test status
Simulation time 37680418 ps
CPU time 2.53 seconds
Started Jul 03 05:17:56 PM PDT 24
Finished Jul 03 05:17:59 PM PDT 24
Peak memory 232632 kb
Host smart-8ad0685d-cd24-47ea-af26-8960658fab32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989865861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1989865861
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3205955886
Short name T674
Test name
Test status
Simulation time 3436796025 ps
CPU time 11.17 seconds
Started Jul 03 05:17:53 PM PDT 24
Finished Jul 03 05:18:05 PM PDT 24
Peak memory 232752 kb
Host smart-f376fdcb-710d-4cac-84ca-1cb8a8614056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205955886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3205955886
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2520822853
Short name T140
Test name
Test status
Simulation time 1542578262 ps
CPU time 9.02 seconds
Started Jul 03 05:18:01 PM PDT 24
Finished Jul 03 05:18:10 PM PDT 24
Peak memory 219008 kb
Host smart-e5809d9f-a604-466e-a229-ccfe01c39b3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2520822853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2520822853
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1845049317
Short name T158
Test name
Test status
Simulation time 42875775 ps
CPU time 0.99 seconds
Started Jul 03 05:17:59 PM PDT 24
Finished Jul 03 05:18:01 PM PDT 24
Peak memory 206628 kb
Host smart-10eb140b-eea7-4052-b3be-8bc6b4c2d578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845049317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1845049317
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1026398701
Short name T891
Test name
Test status
Simulation time 28794965176 ps
CPU time 37.2 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:42 PM PDT 24
Peak memory 216316 kb
Host smart-d1a03f14-5200-461f-9b1b-48659e3eb6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026398701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1026398701
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1659490644
Short name T327
Test name
Test status
Simulation time 1704300507 ps
CPU time 6.33 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:18:13 PM PDT 24
Peak memory 216172 kb
Host smart-725b3d01-47db-410c-b557-f8d1a2f3b559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659490644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1659490644
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4102188175
Short name T871
Test name
Test status
Simulation time 248849181 ps
CPU time 1.37 seconds
Started Jul 03 05:17:57 PM PDT 24
Finished Jul 03 05:17:58 PM PDT 24
Peak memory 216276 kb
Host smart-66e9523b-0f9c-422e-80cc-aaf5692588ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102188175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4102188175
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3558479589
Short name T483
Test name
Test status
Simulation time 19529710 ps
CPU time 0.81 seconds
Started Jul 03 05:17:54 PM PDT 24
Finished Jul 03 05:17:55 PM PDT 24
Peak memory 205956 kb
Host smart-76297bd2-2a05-476d-8353-035a9959d808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558479589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3558479589
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1337321693
Short name T477
Test name
Test status
Simulation time 3242164023 ps
CPU time 7.24 seconds
Started Jul 03 05:17:55 PM PDT 24
Finished Jul 03 05:18:02 PM PDT 24
Peak memory 232784 kb
Host smart-ace6c937-34ec-4ab1-a1d4-e26ba5824b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337321693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1337321693
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1503886713
Short name T705
Test name
Test status
Simulation time 1051864818 ps
CPU time 2.61 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:18:09 PM PDT 24
Peak memory 224440 kb
Host smart-f6bc136c-12d3-46e2-8756-76ee0dc72889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503886713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1503886713
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3781597624
Short name T348
Test name
Test status
Simulation time 14765634 ps
CPU time 0.75 seconds
Started Jul 03 05:18:01 PM PDT 24
Finished Jul 03 05:18:02 PM PDT 24
Peak memory 206616 kb
Host smart-b3c44549-1db3-4464-8e7d-30e37c20a41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781597624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3781597624
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1136283818
Short name T289
Test name
Test status
Simulation time 7405631423 ps
CPU time 97.59 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:19:43 PM PDT 24
Peak memory 251704 kb
Host smart-a8d6ce1e-93a8-4a63-8617-1414bb4181db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136283818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1136283818
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1786450171
Short name T254
Test name
Test status
Simulation time 24443896447 ps
CPU time 84.42 seconds
Started Jul 03 05:17:59 PM PDT 24
Finished Jul 03 05:19:24 PM PDT 24
Peak memory 254912 kb
Host smart-b208b6f8-0683-4adf-bde1-f351d7d4b1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786450171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1786450171
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.727588470
Short name T789
Test name
Test status
Simulation time 1208449363 ps
CPU time 9.82 seconds
Started Jul 03 05:17:59 PM PDT 24
Finished Jul 03 05:18:10 PM PDT 24
Peak memory 232620 kb
Host smart-32571cfc-3a19-48dd-85fd-baeb3bcabc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727588470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.727588470
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2038259226
Short name T15
Test name
Test status
Simulation time 2423044787 ps
CPU time 21.15 seconds
Started Jul 03 05:18:01 PM PDT 24
Finished Jul 03 05:18:22 PM PDT 24
Peak memory 239436 kb
Host smart-331fd8b4-a65f-4c47-86ea-ad3512351e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038259226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2038259226
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1047680617
Short name T376
Test name
Test status
Simulation time 32751145 ps
CPU time 2.52 seconds
Started Jul 03 05:18:00 PM PDT 24
Finished Jul 03 05:18:03 PM PDT 24
Peak memory 226724 kb
Host smart-e23a5cac-ced4-4f0d-9765-35dfd052fd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047680617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1047680617
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3963833356
Short name T519
Test name
Test status
Simulation time 506901380 ps
CPU time 9.2 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:18:15 PM PDT 24
Peak memory 240052 kb
Host smart-6c5cbf77-45c9-4023-b225-4f888cfbbde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963833356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3963833356
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2225738972
Short name T688
Test name
Test status
Simulation time 423536786 ps
CPU time 6.5 seconds
Started Jul 03 05:17:59 PM PDT 24
Finished Jul 03 05:18:06 PM PDT 24
Peak memory 235116 kb
Host smart-9100afe4-db75-4b33-9300-a9eb0c499a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225738972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2225738972
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2240455982
Short name T898
Test name
Test status
Simulation time 135769698 ps
CPU time 2.69 seconds
Started Jul 03 05:18:01 PM PDT 24
Finished Jul 03 05:18:04 PM PDT 24
Peak memory 232648 kb
Host smart-cda4d6a1-a109-4eb3-adca-deda7fd17c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240455982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2240455982
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3654207443
Short name T791
Test name
Test status
Simulation time 8398110780 ps
CPU time 16.54 seconds
Started Jul 03 05:18:02 PM PDT 24
Finished Jul 03 05:18:19 PM PDT 24
Peak memory 220744 kb
Host smart-711f11e7-990b-4ebf-b1d7-fd1f2246e144
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3654207443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3654207443
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.68188303
Short name T347
Test name
Test status
Simulation time 85896380 ps
CPU time 1.02 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:06 PM PDT 24
Peak memory 206808 kb
Host smart-95207f27-f463-4a23-b254-5b89db0f35d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68188303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress
_all.68188303
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2686096132
Short name T806
Test name
Test status
Simulation time 945965479 ps
CPU time 8.48 seconds
Started Jul 03 05:18:02 PM PDT 24
Finished Jul 03 05:18:11 PM PDT 24
Peak memory 216156 kb
Host smart-9a1b2779-dea0-46b6-83c6-684a10e9571d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686096132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2686096132
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.464351222
Short name T403
Test name
Test status
Simulation time 258293688 ps
CPU time 1.19 seconds
Started Jul 03 05:18:00 PM PDT 24
Finished Jul 03 05:18:01 PM PDT 24
Peak memory 207904 kb
Host smart-5b2e227b-21c9-4db6-8434-be4e9c1c7f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464351222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.464351222
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2653131897
Short name T738
Test name
Test status
Simulation time 32416076 ps
CPU time 1.01 seconds
Started Jul 03 05:18:02 PM PDT 24
Finished Jul 03 05:18:03 PM PDT 24
Peak memory 207112 kb
Host smart-10b4024d-6eee-4fa4-9d3f-60f89ac1441f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653131897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2653131897
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2666248324
Short name T727
Test name
Test status
Simulation time 27579778 ps
CPU time 0.75 seconds
Started Jul 03 05:18:02 PM PDT 24
Finished Jul 03 05:18:03 PM PDT 24
Peak memory 205968 kb
Host smart-0c6c55d7-7ed3-4510-9a7e-139bbd95c349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666248324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2666248324
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1286207354
Short name T991
Test name
Test status
Simulation time 65141637 ps
CPU time 2.45 seconds
Started Jul 03 05:18:00 PM PDT 24
Finished Jul 03 05:18:03 PM PDT 24
Peak memory 224164 kb
Host smart-11d8d186-d396-456c-b3bc-9b92feeb4707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286207354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1286207354
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.437313476
Short name T499
Test name
Test status
Simulation time 20522988 ps
CPU time 0.77 seconds
Started Jul 03 05:18:06 PM PDT 24
Finished Jul 03 05:18:07 PM PDT 24
Peak memory 205500 kb
Host smart-22aad3b4-a444-42e1-a134-c2756e7225d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437313476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.437313476
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1022048551
Short name T951
Test name
Test status
Simulation time 2350713347 ps
CPU time 14.56 seconds
Started Jul 03 05:18:06 PM PDT 24
Finished Jul 03 05:18:21 PM PDT 24
Peak memory 224616 kb
Host smart-be10aa56-f9f9-42ec-9ea1-9c92613e4c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022048551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1022048551
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2523652800
Short name T959
Test name
Test status
Simulation time 60275603 ps
CPU time 0.76 seconds
Started Jul 03 05:18:03 PM PDT 24
Finished Jul 03 05:18:05 PM PDT 24
Peak memory 205588 kb
Host smart-993a2bb5-98ab-442c-ae42-11defdd9d6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523652800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2523652800
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1171533908
Short name T259
Test name
Test status
Simulation time 2614921042 ps
CPU time 56.36 seconds
Started Jul 03 05:18:03 PM PDT 24
Finished Jul 03 05:19:00 PM PDT 24
Peak memory 257376 kb
Host smart-03e30935-806b-4eae-aab2-9653ddc746dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171533908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1171533908
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1282085963
Short name T852
Test name
Test status
Simulation time 60154862523 ps
CPU time 557.61 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:27:23 PM PDT 24
Peak memory 251300 kb
Host smart-9953a1df-99d5-4b51-9d32-986f47b909e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282085963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1282085963
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.30054574
Short name T949
Test name
Test status
Simulation time 11929505266 ps
CPU time 109.91 seconds
Started Jul 03 05:18:02 PM PDT 24
Finished Jul 03 05:19:52 PM PDT 24
Peak memory 249264 kb
Host smart-de26c500-2134-49a7-84fb-ca19aed04e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30054574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.30054574
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.961973851
Short name T35
Test name
Test status
Simulation time 438497024 ps
CPU time 2.89 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:18:09 PM PDT 24
Peak memory 224472 kb
Host smart-8f973d68-d7e3-4761-9985-ff6b76878b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961973851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.961973851
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.884896829
Short name T206
Test name
Test status
Simulation time 20430817918 ps
CPU time 173.42 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:20:59 PM PDT 24
Peak memory 257388 kb
Host smart-21aeb695-abd5-4dd3-af3e-648a7344a401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884896829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.884896829
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2027628633
Short name T926
Test name
Test status
Simulation time 393712911 ps
CPU time 4.01 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:09 PM PDT 24
Peak memory 224420 kb
Host smart-1370943f-e061-4c66-87d1-250b8328f0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027628633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2027628633
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2455479203
Short name T720
Test name
Test status
Simulation time 58554276741 ps
CPU time 91.36 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:19:36 PM PDT 24
Peak memory 224584 kb
Host smart-2f4bdd03-a8d2-43ae-a3e9-b82e2b0fdf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455479203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2455479203
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2836072293
Short name T957
Test name
Test status
Simulation time 3597644584 ps
CPU time 7.14 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:12 PM PDT 24
Peak memory 232780 kb
Host smart-c4904e91-0ea6-49bb-a4ee-ca0253233d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836072293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2836072293
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.911346558
Short name T229
Test name
Test status
Simulation time 50667280119 ps
CPU time 18.07 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:18:25 PM PDT 24
Peak memory 232796 kb
Host smart-d5bd58b7-f2b0-4d2a-9239-92ac9a6cc632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911346558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.911346558
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.272256215
Short name T607
Test name
Test status
Simulation time 899425378 ps
CPU time 11.48 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:18:17 PM PDT 24
Peak memory 223128 kb
Host smart-b844c5a2-ae53-4eb6-a356-16f1a220f43a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=272256215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.272256215
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1530151381
Short name T653
Test name
Test status
Simulation time 1117907714 ps
CPU time 17.77 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:22 PM PDT 24
Peak memory 233864 kb
Host smart-9fbd7526-3139-4f7d-8123-292a1c3e7fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530151381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1530151381
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3837614181
Short name T828
Test name
Test status
Simulation time 2116509782 ps
CPU time 34.19 seconds
Started Jul 03 05:18:03 PM PDT 24
Finished Jul 03 05:18:38 PM PDT 24
Peak memory 216164 kb
Host smart-e599f874-2674-4f7a-98b5-061b83e610f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837614181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3837614181
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3616815448
Short name T338
Test name
Test status
Simulation time 11078237731 ps
CPU time 8.56 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:13 PM PDT 24
Peak memory 216312 kb
Host smart-6f9ab3d2-104e-425c-af4b-586f7ffca920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616815448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3616815448
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2471457370
Short name T659
Test name
Test status
Simulation time 32595911 ps
CPU time 0.84 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:18:08 PM PDT 24
Peak memory 207028 kb
Host smart-3e61343f-7383-45ea-aa2b-fc5c7e46415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471457370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2471457370
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2078942516
Short name T405
Test name
Test status
Simulation time 111832258 ps
CPU time 0.99 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:06 PM PDT 24
Peak memory 206008 kb
Host smart-ed8b7c9a-9f05-494b-8e84-25d33974b17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078942516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2078942516
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1297044493
Short name T2
Test name
Test status
Simulation time 452756881 ps
CPU time 2.4 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:18:09 PM PDT 24
Peak memory 223640 kb
Host smart-a1505588-27e6-4fac-8d7e-8d0825bed9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297044493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1297044493
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3654701244
Short name T482
Test name
Test status
Simulation time 17906476 ps
CPU time 0.81 seconds
Started Jul 03 05:18:10 PM PDT 24
Finished Jul 03 05:18:11 PM PDT 24
Peak memory 205492 kb
Host smart-9e3683a1-972e-4b26-9118-86f27d2130f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654701244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3654701244
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.688705588
Short name T928
Test name
Test status
Simulation time 2240050051 ps
CPU time 8.56 seconds
Started Jul 03 05:18:06 PM PDT 24
Finished Jul 03 05:18:15 PM PDT 24
Peak memory 232692 kb
Host smart-1429cc6d-49d6-49e0-b804-adcd57b3ccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688705588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.688705588
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2592372768
Short name T680
Test name
Test status
Simulation time 142458713 ps
CPU time 0.8 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:06 PM PDT 24
Peak memory 206884 kb
Host smart-7e18b120-da5b-49f9-8649-bf2b1b458b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592372768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2592372768
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.191264764
Short name T126
Test name
Test status
Simulation time 15213946293 ps
CPU time 123.24 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:20:11 PM PDT 24
Peak memory 249184 kb
Host smart-692f4e10-1a81-449a-b736-d3c3b7749450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191264764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.191264764
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.77376853
Short name T945
Test name
Test status
Simulation time 24574618812 ps
CPU time 260.55 seconds
Started Jul 03 05:18:06 PM PDT 24
Finished Jul 03 05:22:27 PM PDT 24
Peak memory 257456 kb
Host smart-44f931aa-c6e3-48bd-a1e0-658172a66c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77376853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.77376853
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2995957037
Short name T879
Test name
Test status
Simulation time 65950585476 ps
CPU time 151.02 seconds
Started Jul 03 05:18:06 PM PDT 24
Finished Jul 03 05:20:38 PM PDT 24
Peak memory 257416 kb
Host smart-689a113d-b5c4-4954-88c9-3c50a59e59af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995957037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2995957037
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1104705180
Short name T292
Test name
Test status
Simulation time 4102626262 ps
CPU time 8.59 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:18:16 PM PDT 24
Peak memory 232756 kb
Host smart-d567f9d3-7b14-41db-b3e1-9d404283b000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104705180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1104705180
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1368923301
Short name T995
Test name
Test status
Simulation time 1900348593 ps
CPU time 17.03 seconds
Started Jul 03 05:18:06 PM PDT 24
Finished Jul 03 05:18:24 PM PDT 24
Peak memory 237920 kb
Host smart-a7d70558-cb38-4079-a646-0fa1a5044b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368923301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1368923301
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.42118186
Short name T493
Test name
Test status
Simulation time 42460426059 ps
CPU time 28.83 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:18:36 PM PDT 24
Peak memory 232752 kb
Host smart-3edc8be4-2185-47d5-a911-65d2d79bb77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42118186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.42118186
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2105867135
Short name T755
Test name
Test status
Simulation time 16982262747 ps
CPU time 43.16 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:18:51 PM PDT 24
Peak memory 232748 kb
Host smart-0b62e374-0b9d-406c-98df-a928966bf05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105867135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2105867135
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.303936967
Short name T224
Test name
Test status
Simulation time 1569442257 ps
CPU time 3.95 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:09 PM PDT 24
Peak memory 224512 kb
Host smart-7f2c9fa9-14a5-43dc-b9f3-a207eaed0f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303936967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.303936967
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1233787446
Short name T616
Test name
Test status
Simulation time 8963827032 ps
CPU time 14.88 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:19 PM PDT 24
Peak memory 232800 kb
Host smart-c5c0e770-2a2c-462a-8325-e0bfa1a01f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233787446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1233787446
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3327231352
Short name T896
Test name
Test status
Simulation time 287946311 ps
CPU time 6.14 seconds
Started Jul 03 05:18:13 PM PDT 24
Finished Jul 03 05:18:20 PM PDT 24
Peak memory 223024 kb
Host smart-0ddd18b2-817a-4e5e-8c1e-a2686f5e7fd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3327231352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3327231352
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2087126182
Short name T196
Test name
Test status
Simulation time 66869101084 ps
CPU time 114.05 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:20:00 PM PDT 24
Peak memory 249200 kb
Host smart-98c88297-af85-4c39-8f35-b01697154af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087126182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2087126182
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2067679919
Short name T304
Test name
Test status
Simulation time 1577582984 ps
CPU time 16.61 seconds
Started Jul 03 05:18:04 PM PDT 24
Finished Jul 03 05:18:21 PM PDT 24
Peak memory 217624 kb
Host smart-4f20cc84-533e-48c7-9259-b157bfc9b5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067679919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2067679919
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3599038942
Short name T439
Test name
Test status
Simulation time 16023419740 ps
CPU time 14.89 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:18:20 PM PDT 24
Peak memory 216652 kb
Host smart-76de9ec6-0c73-42d5-96f0-0598a0595d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599038942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3599038942
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1726094021
Short name T818
Test name
Test status
Simulation time 13037526 ps
CPU time 0.71 seconds
Started Jul 03 05:18:03 PM PDT 24
Finished Jul 03 05:18:04 PM PDT 24
Peak memory 205636 kb
Host smart-b6869a5a-4867-471a-a2c0-1fcd3bb0b678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726094021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1726094021
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3927208348
Short name T323
Test name
Test status
Simulation time 70497004 ps
CPU time 0.77 seconds
Started Jul 03 05:18:03 PM PDT 24
Finished Jul 03 05:18:04 PM PDT 24
Peak memory 205984 kb
Host smart-039bf3cb-853b-484d-9d82-e9661cb65e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927208348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3927208348
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2967554832
Short name T269
Test name
Test status
Simulation time 34912102627 ps
CPU time 27.34 seconds
Started Jul 03 05:18:06 PM PDT 24
Finished Jul 03 05:18:34 PM PDT 24
Peak memory 232800 kb
Host smart-2afde9e3-b1ae-4d06-91f8-d27434bed851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967554832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2967554832
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1290372890
Short name T361
Test name
Test status
Simulation time 15625640 ps
CPU time 0.72 seconds
Started Jul 03 05:18:11 PM PDT 24
Finished Jul 03 05:18:12 PM PDT 24
Peak memory 205504 kb
Host smart-16286d4b-feac-4730-9d8d-42c8bc283b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290372890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1290372890
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1864541352
Short name T821
Test name
Test status
Simulation time 3691298539 ps
CPU time 12.43 seconds
Started Jul 03 05:18:11 PM PDT 24
Finished Jul 03 05:18:24 PM PDT 24
Peak memory 224592 kb
Host smart-6c600dd3-770e-4b22-ace9-8e1550891f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864541352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1864541352
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1210738689
Short name T471
Test name
Test status
Simulation time 16979339 ps
CPU time 0.77 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:18:08 PM PDT 24
Peak memory 206548 kb
Host smart-806b3df9-7145-406d-a71b-f5135efc758d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210738689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1210738689
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3344570993
Short name T197
Test name
Test status
Simulation time 1990817194 ps
CPU time 43.64 seconds
Started Jul 03 05:18:10 PM PDT 24
Finished Jul 03 05:18:54 PM PDT 24
Peak memory 251964 kb
Host smart-7b2e51d2-b302-4752-99d2-7f99259626ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344570993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3344570993
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2793373619
Short name T862
Test name
Test status
Simulation time 30547023981 ps
CPU time 106.69 seconds
Started Jul 03 05:18:11 PM PDT 24
Finished Jul 03 05:19:58 PM PDT 24
Peak memory 249228 kb
Host smart-d4b48669-75b5-432b-acdb-8824bc89b865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793373619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2793373619
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3089320141
Short name T211
Test name
Test status
Simulation time 4809518504 ps
CPU time 87.8 seconds
Started Jul 03 05:18:12 PM PDT 24
Finished Jul 03 05:19:40 PM PDT 24
Peak memory 257340 kb
Host smart-aec75478-e158-4497-a4c9-2aab8483f542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089320141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3089320141
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3794836676
Short name T929
Test name
Test status
Simulation time 619886636 ps
CPU time 12.86 seconds
Started Jul 03 05:18:11 PM PDT 24
Finished Jul 03 05:18:24 PM PDT 24
Peak memory 232656 kb
Host smart-67a0490f-0a86-41ef-8865-a09631cc8441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794836676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3794836676
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.498971492
Short name T282
Test name
Test status
Simulation time 26283234328 ps
CPU time 84.21 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:19:44 PM PDT 24
Peak memory 254464 kb
Host smart-48cb853b-7020-49e5-9fef-68347bd47a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498971492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.498971492
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.643628977
Short name T953
Test name
Test status
Simulation time 387630349 ps
CPU time 4.2 seconds
Started Jul 03 05:18:12 PM PDT 24
Finished Jul 03 05:18:16 PM PDT 24
Peak memory 224396 kb
Host smart-fbea66b3-4533-4590-a2f3-8930a83988ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643628977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.643628977
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3860880681
Short name T416
Test name
Test status
Simulation time 1478524378 ps
CPU time 3.08 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:18:10 PM PDT 24
Peak memory 224468 kb
Host smart-4a52a0e0-3fd3-43d3-aaaa-8475a0e0b885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860880681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3860880681
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2559868837
Short name T846
Test name
Test status
Simulation time 403165945 ps
CPU time 2.93 seconds
Started Jul 03 05:18:09 PM PDT 24
Finished Jul 03 05:18:12 PM PDT 24
Peak memory 224344 kb
Host smart-5f71bb24-d3c9-4bff-ab0d-46becd68caa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559868837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2559868837
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3368210167
Short name T472
Test name
Test status
Simulation time 154671261 ps
CPU time 2.95 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:18:10 PM PDT 24
Peak memory 224444 kb
Host smart-eee5fbeb-1a4a-42fc-84ea-7f67a8a0a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368210167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3368210167
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.226685454
Short name T412
Test name
Test status
Simulation time 1201619500 ps
CPU time 13.37 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:18:34 PM PDT 24
Peak memory 220492 kb
Host smart-1c8cc869-82a6-414b-8adb-98cd601fc232
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=226685454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.226685454
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.668821177
Short name T341
Test name
Test status
Simulation time 132182786 ps
CPU time 1.34 seconds
Started Jul 03 05:18:11 PM PDT 24
Finished Jul 03 05:18:13 PM PDT 24
Peak memory 215124 kb
Host smart-01f451c2-d69a-4257-a0a1-3dcf2e535a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668821177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.668821177
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2193261751
Short name T782
Test name
Test status
Simulation time 2990860941 ps
CPU time 15.14 seconds
Started Jul 03 05:18:06 PM PDT 24
Finished Jul 03 05:18:22 PM PDT 24
Peak memory 216492 kb
Host smart-bdc6d37e-069d-4c42-a60b-17ac155e1560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193261751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2193261751
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3666851854
Short name T743
Test name
Test status
Simulation time 13620880808 ps
CPU time 5.86 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:18:11 PM PDT 24
Peak memory 216304 kb
Host smart-15be06b0-c9a6-4425-9b7f-f9995d625761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666851854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3666851854
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.303259195
Short name T506
Test name
Test status
Simulation time 25197535 ps
CPU time 1.09 seconds
Started Jul 03 05:18:07 PM PDT 24
Finished Jul 03 05:18:09 PM PDT 24
Peak memory 207952 kb
Host smart-028334a2-f09d-4aef-ae01-c3d54b41ce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303259195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.303259195
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3911071000
Short name T311
Test name
Test status
Simulation time 12438982 ps
CPU time 0.72 seconds
Started Jul 03 05:18:08 PM PDT 24
Finished Jul 03 05:18:09 PM PDT 24
Peak memory 205664 kb
Host smart-f93a04e2-622f-44fc-b58b-b99b0af8d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911071000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3911071000
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.364882352
Short name T983
Test name
Test status
Simulation time 64079468 ps
CPU time 2.5 seconds
Started Jul 03 05:18:05 PM PDT 24
Finished Jul 03 05:18:09 PM PDT 24
Peak memory 217452 kb
Host smart-368a258b-0f5b-4cf1-8b69-20cc052698be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364882352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.364882352
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.879485485
Short name T533
Test name
Test status
Simulation time 14160559 ps
CPU time 0.78 seconds
Started Jul 03 05:18:13 PM PDT 24
Finished Jul 03 05:18:14 PM PDT 24
Peak memory 204656 kb
Host smart-252db826-c776-411d-a9c9-3588b5f7db1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879485485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.879485485
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3590056344
Short name T973
Test name
Test status
Simulation time 317792454 ps
CPU time 2.13 seconds
Started Jul 03 05:18:11 PM PDT 24
Finished Jul 03 05:18:14 PM PDT 24
Peak memory 223540 kb
Host smart-caf96551-226a-4c37-a1ff-54d0e079a6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590056344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3590056344
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1856328762
Short name T487
Test name
Test status
Simulation time 46942172 ps
CPU time 0.76 seconds
Started Jul 03 05:18:10 PM PDT 24
Finished Jul 03 05:18:11 PM PDT 24
Peak memory 205544 kb
Host smart-be660ed4-f2f8-448c-9dad-da89bfc88a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856328762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1856328762
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2675217329
Short name T638
Test name
Test status
Simulation time 76930949324 ps
CPU time 123.61 seconds
Started Jul 03 05:18:12 PM PDT 24
Finished Jul 03 05:20:16 PM PDT 24
Peak memory 249192 kb
Host smart-e64c8a46-9858-46fa-8d93-6896c08b4469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675217329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2675217329
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.154570677
Short name T133
Test name
Test status
Simulation time 5222457403 ps
CPU time 85.99 seconds
Started Jul 03 05:18:14 PM PDT 24
Finished Jul 03 05:19:41 PM PDT 24
Peak memory 257488 kb
Host smart-6102976f-6fc9-4450-9191-95825d4a7f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154570677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.154570677
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.316167070
Short name T610
Test name
Test status
Simulation time 44732417966 ps
CPU time 87.4 seconds
Started Jul 03 05:18:10 PM PDT 24
Finished Jul 03 05:19:38 PM PDT 24
Peak memory 257432 kb
Host smart-03e0918f-7950-4169-aa2f-edb00f9f4b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316167070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.316167070
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.4116251255
Short name T90
Test name
Test status
Simulation time 15146929638 ps
CPU time 121.4 seconds
Started Jul 03 05:18:13 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 248880 kb
Host smart-ea622404-cfa2-47fd-9795-729de36d0e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116251255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.4116251255
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1394414992
Short name T408
Test name
Test status
Simulation time 275868156 ps
CPU time 2.71 seconds
Started Jul 03 05:18:10 PM PDT 24
Finished Jul 03 05:18:13 PM PDT 24
Peak memory 232696 kb
Host smart-be7eace2-4523-41d6-8aa1-87402f97fdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394414992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1394414992
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1210243014
Short name T830
Test name
Test status
Simulation time 56406964079 ps
CPU time 144.92 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:20:45 PM PDT 24
Peak memory 240660 kb
Host smart-18098a93-4d56-4d98-baaf-7b1b5cbbad90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210243014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1210243014
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.573784951
Short name T271
Test name
Test status
Simulation time 9180645675 ps
CPU time 31.72 seconds
Started Jul 03 05:18:12 PM PDT 24
Finished Jul 03 05:18:44 PM PDT 24
Peak memory 240948 kb
Host smart-ad4db7c0-bc30-406d-b543-f8b44e2639e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573784951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.573784951
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1273583791
Short name T614
Test name
Test status
Simulation time 5079336648 ps
CPU time 16.14 seconds
Started Jul 03 05:18:13 PM PDT 24
Finished Jul 03 05:18:29 PM PDT 24
Peak memory 232732 kb
Host smart-36d0674b-fdf4-494d-9c54-bad457833ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273583791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1273583791
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3770537731
Short name T948
Test name
Test status
Simulation time 348757267 ps
CPU time 3.98 seconds
Started Jul 03 05:18:09 PM PDT 24
Finished Jul 03 05:18:13 PM PDT 24
Peak memory 218884 kb
Host smart-fa5e7d0e-1d7c-452c-bb1d-90d761cf4b1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3770537731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3770537731
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4006084264
Short name T280
Test name
Test status
Simulation time 7118043999 ps
CPU time 101.32 seconds
Started Jul 03 05:18:11 PM PDT 24
Finished Jul 03 05:19:52 PM PDT 24
Peak memory 257408 kb
Host smart-727d6c8a-bb06-4351-9715-4e63e5ef43ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006084264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4006084264
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.921415462
Short name T437
Test name
Test status
Simulation time 13089194264 ps
CPU time 18.44 seconds
Started Jul 03 05:18:16 PM PDT 24
Finished Jul 03 05:18:35 PM PDT 24
Peak memory 216324 kb
Host smart-df6dcf2d-cfee-4369-8884-6522ceb209da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921415462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.921415462
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2747636264
Short name T716
Test name
Test status
Simulation time 75039828312 ps
CPU time 16.59 seconds
Started Jul 03 05:18:10 PM PDT 24
Finished Jul 03 05:18:27 PM PDT 24
Peak memory 216356 kb
Host smart-93df26b6-23c4-4209-a975-78044a494989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747636264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2747636264
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1951112080
Short name T535
Test name
Test status
Simulation time 28073072 ps
CPU time 0.85 seconds
Started Jul 03 05:18:15 PM PDT 24
Finished Jul 03 05:18:16 PM PDT 24
Peak memory 206692 kb
Host smart-a1735732-7fe9-47db-bae1-6a6013f1242d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951112080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1951112080
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3969084108
Short name T1003
Test name
Test status
Simulation time 90612004 ps
CPU time 0.92 seconds
Started Jul 03 05:18:16 PM PDT 24
Finished Jul 03 05:18:17 PM PDT 24
Peak memory 205984 kb
Host smart-e5875f58-cbf7-402f-bda3-241771e7a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969084108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3969084108
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4197198809
Short name T541
Test name
Test status
Simulation time 832580064 ps
CPU time 3.69 seconds
Started Jul 03 05:18:15 PM PDT 24
Finished Jul 03 05:18:19 PM PDT 24
Peak memory 224524 kb
Host smart-7b020649-6c3c-48a7-b51e-86f65dbb51d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197198809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4197198809
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3270653733
Short name T339
Test name
Test status
Simulation time 24210275 ps
CPU time 0.71 seconds
Started Jul 03 05:18:17 PM PDT 24
Finished Jul 03 05:18:18 PM PDT 24
Peak memory 205496 kb
Host smart-daa04e48-37d7-4d6d-b7f0-786914c26925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270653733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3270653733
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.249066041
Short name T484
Test name
Test status
Simulation time 512473114 ps
CPU time 7.93 seconds
Started Jul 03 05:18:18 PM PDT 24
Finished Jul 03 05:18:26 PM PDT 24
Peak memory 232700 kb
Host smart-6499d597-5020-4082-b34f-2eecf6e96abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249066041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.249066041
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3452711071
Short name T554
Test name
Test status
Simulation time 19599043 ps
CPU time 0.78 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:18:20 PM PDT 24
Peak memory 206944 kb
Host smart-859f6a5b-2c77-4db5-9571-b5636fdab337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452711071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3452711071
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3807523072
Short name T129
Test name
Test status
Simulation time 101728511675 ps
CPU time 204.02 seconds
Started Jul 03 05:18:14 PM PDT 24
Finished Jul 03 05:21:39 PM PDT 24
Peak memory 255004 kb
Host smart-f6dfea6f-4636-4092-942d-8d245e5781a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807523072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3807523072
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1303386799
Short name T205
Test name
Test status
Simulation time 47935922292 ps
CPU time 161.23 seconds
Started Jul 03 05:18:16 PM PDT 24
Finished Jul 03 05:20:58 PM PDT 24
Peak memory 265784 kb
Host smart-48bb5786-c316-4975-8fa0-0d311d16644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303386799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1303386799
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2370985103
Short name T262
Test name
Test status
Simulation time 52401819485 ps
CPU time 162.76 seconds
Started Jul 03 05:18:20 PM PDT 24
Finished Jul 03 05:21:03 PM PDT 24
Peak memory 257432 kb
Host smart-4eb83b5c-e280-487a-a23f-77f8b5e37eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370985103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2370985103
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1951191758
Short name T295
Test name
Test status
Simulation time 414722888 ps
CPU time 6.17 seconds
Started Jul 03 05:18:13 PM PDT 24
Finished Jul 03 05:18:20 PM PDT 24
Peak memory 234828 kb
Host smart-d041fbd6-7f33-4644-b09d-0b8ffde2186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951191758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1951191758
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3566874241
Short name T42
Test name
Test status
Simulation time 64673254226 ps
CPU time 121.36 seconds
Started Jul 03 05:18:15 PM PDT 24
Finished Jul 03 05:20:17 PM PDT 24
Peak memory 254628 kb
Host smart-9cdf47b9-fc17-456c-af75-8d39f6702494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566874241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3566874241
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1379090603
Short name T803
Test name
Test status
Simulation time 1465930869 ps
CPU time 15.75 seconds
Started Jul 03 05:18:16 PM PDT 24
Finished Jul 03 05:18:32 PM PDT 24
Peak memory 224464 kb
Host smart-ad4be423-b3ee-4a87-83b9-78fa55b362b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379090603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1379090603
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1608413256
Short name T316
Test name
Test status
Simulation time 108939474 ps
CPU time 2.5 seconds
Started Jul 03 05:18:13 PM PDT 24
Finished Jul 03 05:18:16 PM PDT 24
Peak memory 232356 kb
Host smart-54726398-f4d7-4a7d-9eeb-1572c1ed9765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608413256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1608413256
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.465734153
Short name T45
Test name
Test status
Simulation time 12775625451 ps
CPU time 14.03 seconds
Started Jul 03 05:18:12 PM PDT 24
Finished Jul 03 05:18:27 PM PDT 24
Peak memory 239020 kb
Host smart-b3572fb1-e669-4d11-9058-56023dfefa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465734153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.465734153
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2710416130
Short name T558
Test name
Test status
Simulation time 4354319904 ps
CPU time 13.47 seconds
Started Jul 03 05:18:13 PM PDT 24
Finished Jul 03 05:18:27 PM PDT 24
Peak memory 240780 kb
Host smart-dec6101e-917c-4c79-ab8c-656b99fca438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710416130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2710416130
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.52351479
Short name T758
Test name
Test status
Simulation time 1123583880 ps
CPU time 13.88 seconds
Started Jul 03 05:18:16 PM PDT 24
Finished Jul 03 05:18:30 PM PDT 24
Peak memory 220120 kb
Host smart-318df3d9-99a0-4401-8cfd-641c778841d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=52351479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direc
t.52351479
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.69335912
Short name T160
Test name
Test status
Simulation time 29848913049 ps
CPU time 116.35 seconds
Started Jul 03 05:18:14 PM PDT 24
Finished Jul 03 05:20:11 PM PDT 24
Peak memory 249232 kb
Host smart-57959953-b956-41d6-8502-91c0dc97f681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69335912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress
_all.69335912
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.368971234
Short name T517
Test name
Test status
Simulation time 3726309898 ps
CPU time 12.88 seconds
Started Jul 03 05:18:12 PM PDT 24
Finished Jul 03 05:18:26 PM PDT 24
Peak memory 219672 kb
Host smart-d5f75af8-c802-4e1c-8809-1a28ff798bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368971234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.368971234
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3134263404
Short name T903
Test name
Test status
Simulation time 804017969 ps
CPU time 3.22 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:18:23 PM PDT 24
Peak memory 216216 kb
Host smart-74e7c273-5c3b-4dd1-9c0b-8917d364d438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134263404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3134263404
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1660244147
Short name T628
Test name
Test status
Simulation time 147352976 ps
CPU time 1.73 seconds
Started Jul 03 05:18:16 PM PDT 24
Finished Jul 03 05:18:18 PM PDT 24
Peak memory 216188 kb
Host smart-29328f10-6041-433f-8811-d10cec5ca9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660244147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1660244147
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3697804781
Short name T994
Test name
Test status
Simulation time 15342925 ps
CPU time 0.71 seconds
Started Jul 03 05:18:16 PM PDT 24
Finished Jul 03 05:18:17 PM PDT 24
Peak memory 205968 kb
Host smart-fb67b82a-3f81-413e-b5b0-e9a04ac00bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697804781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3697804781
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.527245978
Short name T231
Test name
Test status
Simulation time 429886037 ps
CPU time 7.48 seconds
Started Jul 03 05:18:16 PM PDT 24
Finished Jul 03 05:18:24 PM PDT 24
Peak memory 249120 kb
Host smart-3b19e8fe-259a-4602-9e76-997062d6544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527245978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.527245978
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2978012845
Short name T476
Test name
Test status
Simulation time 13593665 ps
CPU time 0.73 seconds
Started Jul 03 05:18:22 PM PDT 24
Finished Jul 03 05:18:23 PM PDT 24
Peak memory 205512 kb
Host smart-717c8018-dbf0-4650-bd0e-323b72b7236a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978012845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2978012845
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.939934125
Short name T918
Test name
Test status
Simulation time 77163390 ps
CPU time 2.39 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:18:22 PM PDT 24
Peak memory 224468 kb
Host smart-6c4a3f70-a3cc-4740-9d82-082b45614370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939934125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.939934125
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.258007988
Short name T443
Test name
Test status
Simulation time 79467554 ps
CPU time 0.82 seconds
Started Jul 03 05:18:15 PM PDT 24
Finished Jul 03 05:18:16 PM PDT 24
Peak memory 206936 kb
Host smart-95972bb1-0e44-49df-93c2-aaf7a84cbbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258007988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.258007988
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.459324601
Short name T536
Test name
Test status
Simulation time 10989283417 ps
CPU time 58.23 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:19:18 PM PDT 24
Peak memory 254412 kb
Host smart-8ae0ee45-3e91-4ddc-a924-8c5d1dd271a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459324601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.459324601
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.493889830
Short name T935
Test name
Test status
Simulation time 137639732104 ps
CPU time 320.19 seconds
Started Jul 03 05:18:20 PM PDT 24
Finished Jul 03 05:23:41 PM PDT 24
Peak memory 252448 kb
Host smart-c275e849-8a44-4f1b-8ee0-81a858c93bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493889830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.493889830
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3110981118
Short name T215
Test name
Test status
Simulation time 4065035602 ps
CPU time 78.89 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:19:39 PM PDT 24
Peak memory 265308 kb
Host smart-abd3a491-8a3e-4c6c-9bf2-a17e42566635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110981118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3110981118
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2491793770
Short name T970
Test name
Test status
Simulation time 358530165 ps
CPU time 6.15 seconds
Started Jul 03 05:18:18 PM PDT 24
Finished Jul 03 05:18:24 PM PDT 24
Peak memory 224388 kb
Host smart-a17235dd-967e-470b-9502-af882621b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491793770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2491793770
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1867691960
Short name T74
Test name
Test status
Simulation time 13359420216 ps
CPU time 121.33 seconds
Started Jul 03 05:18:23 PM PDT 24
Finished Jul 03 05:20:25 PM PDT 24
Peak memory 250168 kb
Host smart-bf651852-6b0d-498e-80e5-dfc069425aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867691960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1867691960
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1219054057
Short name T460
Test name
Test status
Simulation time 338838946 ps
CPU time 3.94 seconds
Started Jul 03 05:18:18 PM PDT 24
Finished Jul 03 05:18:22 PM PDT 24
Peak memory 232608 kb
Host smart-5f685286-cf51-4bac-9b8e-c4fc3512faf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219054057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1219054057
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3995549518
Short name T4
Test name
Test status
Simulation time 2702072004 ps
CPU time 6.32 seconds
Started Jul 03 05:18:24 PM PDT 24
Finished Jul 03 05:18:31 PM PDT 24
Peak memory 232424 kb
Host smart-dd021da7-f77a-4079-90b2-65819a7939f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995549518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3995549518
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4139351840
Short name T331
Test name
Test status
Simulation time 32520606 ps
CPU time 2.4 seconds
Started Jul 03 05:18:17 PM PDT 24
Finished Jul 03 05:18:20 PM PDT 24
Peak memory 232352 kb
Host smart-49346fad-a599-4a91-9f7a-6969c3c4b37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139351840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4139351840
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3566624655
Short name T746
Test name
Test status
Simulation time 8249751046 ps
CPU time 9.14 seconds
Started Jul 03 05:18:14 PM PDT 24
Finished Jul 03 05:18:23 PM PDT 24
Peak memory 224628 kb
Host smart-0918db1b-b5ac-4958-8cfb-16a40038a950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566624655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3566624655
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3684166549
Short name T457
Test name
Test status
Simulation time 2601402843 ps
CPU time 12.74 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:18:33 PM PDT 24
Peak memory 220284 kb
Host smart-ddb9d9d7-ba4c-460c-8a27-006b159a02f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3684166549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3684166549
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3256479929
Short name T22
Test name
Test status
Simulation time 176387936 ps
CPU time 1.05 seconds
Started Jul 03 05:18:37 PM PDT 24
Finished Jul 03 05:18:38 PM PDT 24
Peak memory 207740 kb
Host smart-c7cb9360-be3a-40c8-b212-b9e5098f70e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256479929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3256479929
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1989393851
Short name T561
Test name
Test status
Simulation time 4842670910 ps
CPU time 25.89 seconds
Started Jul 03 05:18:17 PM PDT 24
Finished Jul 03 05:18:43 PM PDT 24
Peak memory 216300 kb
Host smart-312992b1-605d-496f-8ed5-7cbbabf1b02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989393851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1989393851
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.171310009
Short name T670
Test name
Test status
Simulation time 4972823997 ps
CPU time 6.52 seconds
Started Jul 03 05:18:13 PM PDT 24
Finished Jul 03 05:18:20 PM PDT 24
Peak memory 216260 kb
Host smart-fc8201a9-e868-4d93-9930-147eeed53258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171310009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.171310009
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1272693078
Short name T401
Test name
Test status
Simulation time 71134968 ps
CPU time 3.36 seconds
Started Jul 03 05:18:18 PM PDT 24
Finished Jul 03 05:18:22 PM PDT 24
Peak memory 216308 kb
Host smart-37f5d179-6cb5-4118-9d1c-83d7b2a5fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272693078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1272693078
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1197203892
Short name T934
Test name
Test status
Simulation time 34877878 ps
CPU time 0.83 seconds
Started Jul 03 05:18:17 PM PDT 24
Finished Jul 03 05:18:18 PM PDT 24
Peak memory 206264 kb
Host smart-b1d515c3-2b87-4ea8-aa53-111472e3e8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197203892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1197203892
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2393011806
Short name T382
Test name
Test status
Simulation time 688879497 ps
CPU time 4.13 seconds
Started Jul 03 05:18:22 PM PDT 24
Finished Jul 03 05:18:27 PM PDT 24
Peak memory 239288 kb
Host smart-44485d1f-08ab-4ba3-8536-5355e702953f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393011806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2393011806
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.712207800
Short name T61
Test name
Test status
Simulation time 20283457 ps
CPU time 0.74 seconds
Started Jul 03 05:18:22 PM PDT 24
Finished Jul 03 05:18:23 PM PDT 24
Peak memory 205828 kb
Host smart-89e1cdeb-3ee6-4cdd-98ad-fac86d31be7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712207800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.712207800
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.4081829281
Short name T492
Test name
Test status
Simulation time 204843730 ps
CPU time 2.35 seconds
Started Jul 03 05:18:23 PM PDT 24
Finished Jul 03 05:18:26 PM PDT 24
Peak memory 223848 kb
Host smart-0b3acf3f-00fe-408b-ac86-718c5db8db01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081829281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4081829281
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.617504069
Short name T426
Test name
Test status
Simulation time 36872018 ps
CPU time 0.73 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:18:20 PM PDT 24
Peak memory 205920 kb
Host smart-7f30765f-d778-4658-88dd-b19e77cc2744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617504069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.617504069
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4212279335
Short name T672
Test name
Test status
Simulation time 16282827232 ps
CPU time 82.96 seconds
Started Jul 03 05:18:21 PM PDT 24
Finished Jul 03 05:19:44 PM PDT 24
Peak memory 253160 kb
Host smart-e40d6f59-a648-4457-a748-b1218345e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212279335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4212279335
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1805698174
Short name T139
Test name
Test status
Simulation time 26571143976 ps
CPU time 163.14 seconds
Started Jul 03 05:18:21 PM PDT 24
Finished Jul 03 05:21:05 PM PDT 24
Peak memory 260676 kb
Host smart-f95eab28-f9e0-4744-8bd3-c11ecf74a8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805698174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1805698174
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1833561879
Short name T396
Test name
Test status
Simulation time 583684556 ps
CPU time 4.14 seconds
Started Jul 03 05:18:25 PM PDT 24
Finished Jul 03 05:18:30 PM PDT 24
Peak memory 224392 kb
Host smart-47db6704-d507-4f2e-ae52-9c9fa5dd883c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833561879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1833561879
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1251540253
Short name T219
Test name
Test status
Simulation time 4230679740 ps
CPU time 26.47 seconds
Started Jul 03 05:18:25 PM PDT 24
Finished Jul 03 05:18:52 PM PDT 24
Peak memory 224548 kb
Host smart-01d191e9-dbf5-4d7d-ab1d-06453cf88e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251540253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1251540253
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3769863730
Short name T625
Test name
Test status
Simulation time 584451272 ps
CPU time 4.72 seconds
Started Jul 03 05:18:21 PM PDT 24
Finished Jul 03 05:18:26 PM PDT 24
Peak memory 232620 kb
Host smart-53a85814-f431-4531-add6-20e11045b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769863730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3769863730
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1166536201
Short name T195
Test name
Test status
Simulation time 804085800 ps
CPU time 16.79 seconds
Started Jul 03 05:18:17 PM PDT 24
Finished Jul 03 05:18:35 PM PDT 24
Peak memory 224376 kb
Host smart-06c05bcf-eca8-4ac0-83a7-e6a544fe979f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166536201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1166536201
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2224113442
Short name T786
Test name
Test status
Simulation time 2426262110 ps
CPU time 5.99 seconds
Started Jul 03 05:18:22 PM PDT 24
Finished Jul 03 05:18:29 PM PDT 24
Peak memory 224604 kb
Host smart-5a464f77-637e-4bcd-b95e-c8c823ad1a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224113442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2224113442
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.164348392
Short name T694
Test name
Test status
Simulation time 5469144046 ps
CPU time 9.07 seconds
Started Jul 03 05:18:20 PM PDT 24
Finished Jul 03 05:18:29 PM PDT 24
Peak memory 240576 kb
Host smart-701042da-7f60-4ee3-b531-7bd85ed43bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164348392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.164348392
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3666610317
Short name T38
Test name
Test status
Simulation time 2322711812 ps
CPU time 8.49 seconds
Started Jul 03 05:18:21 PM PDT 24
Finished Jul 03 05:18:30 PM PDT 24
Peak memory 222708 kb
Host smart-613e3bce-051c-4b0c-947a-d8dae0c612ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3666610317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3666610317
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2012700365
Short name T23
Test name
Test status
Simulation time 898917162 ps
CPU time 9.43 seconds
Started Jul 03 05:18:20 PM PDT 24
Finished Jul 03 05:18:30 PM PDT 24
Peak memory 216324 kb
Host smart-e48e8a3c-f23c-4031-a0a1-f084bb0b5db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012700365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2012700365
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1856052946
Short name T467
Test name
Test status
Simulation time 377600845 ps
CPU time 2.02 seconds
Started Jul 03 05:18:17 PM PDT 24
Finished Jul 03 05:18:20 PM PDT 24
Peak memory 207884 kb
Host smart-3337d1af-759d-4c3b-a8e3-765f4df47875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856052946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1856052946
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1128192031
Short name T529
Test name
Test status
Simulation time 33162043 ps
CPU time 0.66 seconds
Started Jul 03 05:18:17 PM PDT 24
Finished Jul 03 05:18:18 PM PDT 24
Peak memory 205624 kb
Host smart-0395aa5b-4732-411b-aabc-167fa31eacd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128192031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1128192031
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1360907226
Short name T909
Test name
Test status
Simulation time 80423969 ps
CPU time 0.97 seconds
Started Jul 03 05:18:24 PM PDT 24
Finished Jul 03 05:18:26 PM PDT 24
Peak memory 206156 kb
Host smart-2cd9181b-d5ea-4fd3-a5c6-58d06dff4fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360907226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1360907226
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.741685311
Short name T978
Test name
Test status
Simulation time 1018697710 ps
CPU time 5.72 seconds
Started Jul 03 05:18:18 PM PDT 24
Finished Jul 03 05:18:25 PM PDT 24
Peak memory 224488 kb
Host smart-721c5e76-11df-4e19-9e93-b5223afbb726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741685311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.741685311
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2450145671
Short name T761
Test name
Test status
Simulation time 66503113 ps
CPU time 0.75 seconds
Started Jul 03 05:18:26 PM PDT 24
Finished Jul 03 05:18:27 PM PDT 24
Peak memory 205516 kb
Host smart-88b8b24b-ae8f-4897-b454-4e6e23daba09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450145671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2450145671
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2231332644
Short name T398
Test name
Test status
Simulation time 185428124 ps
CPU time 4.42 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:18:24 PM PDT 24
Peak memory 232548 kb
Host smart-0a2552bc-3d4b-4b31-9ad0-f4b09996f028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231332644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2231332644
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1704123729
Short name T24
Test name
Test status
Simulation time 14096568 ps
CPU time 0.73 seconds
Started Jul 03 05:18:24 PM PDT 24
Finished Jul 03 05:18:25 PM PDT 24
Peak memory 205840 kb
Host smart-7e946d7d-454c-4270-b623-fecb3dca3bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704123729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1704123729
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2754796970
Short name T538
Test name
Test status
Simulation time 7393948319 ps
CPU time 38.52 seconds
Started Jul 03 05:18:24 PM PDT 24
Finished Jul 03 05:19:03 PM PDT 24
Peak memory 239136 kb
Host smart-15e1c725-38fe-42c6-80f0-cf6bdd04cddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754796970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2754796970
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3241944460
Short name T75
Test name
Test status
Simulation time 7250308425 ps
CPU time 129.8 seconds
Started Jul 03 05:18:22 PM PDT 24
Finished Jul 03 05:20:32 PM PDT 24
Peak memory 265668 kb
Host smart-5805fe8f-4440-432d-a90d-14c3bad196c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241944460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3241944460
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1518073011
Short name T989
Test name
Test status
Simulation time 9451640152 ps
CPU time 43.65 seconds
Started Jul 03 05:18:26 PM PDT 24
Finished Jul 03 05:19:10 PM PDT 24
Peak memory 255216 kb
Host smart-8c537834-32ee-43cb-804b-79a3aa20bfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518073011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1518073011
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3674720912
Short name T346
Test name
Test status
Simulation time 239877035 ps
CPU time 6.33 seconds
Started Jul 03 05:18:24 PM PDT 24
Finished Jul 03 05:18:31 PM PDT 24
Peak memory 224492 kb
Host smart-ae7107b7-75e4-4d66-b182-f98f1e9a2776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674720912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3674720912
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3840612991
Short name T55
Test name
Test status
Simulation time 1534195039 ps
CPU time 40.37 seconds
Started Jul 03 05:18:21 PM PDT 24
Finished Jul 03 05:19:02 PM PDT 24
Peak memory 240860 kb
Host smart-70e1bf8c-fb0d-4ffe-a252-2b692773c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840612991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3840612991
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1889822897
Short name T838
Test name
Test status
Simulation time 8894613741 ps
CPU time 8.99 seconds
Started Jul 03 05:18:24 PM PDT 24
Finished Jul 03 05:18:33 PM PDT 24
Peak memory 232684 kb
Host smart-f4d2df68-1e8a-49cb-a22f-baf793a250a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889822897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1889822897
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.439429517
Short name T586
Test name
Test status
Simulation time 40341042968 ps
CPU time 95.18 seconds
Started Jul 03 05:18:23 PM PDT 24
Finished Jul 03 05:19:58 PM PDT 24
Peak memory 249112 kb
Host smart-a0a900b3-32af-424c-80dc-85af6135089c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439429517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.439429517
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2433918261
Short name T400
Test name
Test status
Simulation time 3262269559 ps
CPU time 7.82 seconds
Started Jul 03 05:18:21 PM PDT 24
Finished Jul 03 05:18:29 PM PDT 24
Peak memory 232692 kb
Host smart-5b0e3e98-5024-4082-a410-96d858f392bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433918261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2433918261
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.307266369
Short name T600
Test name
Test status
Simulation time 654561225 ps
CPU time 2.95 seconds
Started Jul 03 05:18:23 PM PDT 24
Finished Jul 03 05:18:26 PM PDT 24
Peak memory 232632 kb
Host smart-d31005f5-34de-47e0-b281-cd3487b4a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307266369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.307266369
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.648973030
Short name T664
Test name
Test status
Simulation time 403941972 ps
CPU time 3.84 seconds
Started Jul 03 05:18:24 PM PDT 24
Finished Jul 03 05:18:29 PM PDT 24
Peak memory 219024 kb
Host smart-6360d79a-c62c-4bb1-b55e-2b3da7a88bf6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=648973030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.648973030
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3933958878
Short name T134
Test name
Test status
Simulation time 2823561031 ps
CPU time 21.15 seconds
Started Jul 03 05:18:26 PM PDT 24
Finished Jul 03 05:18:47 PM PDT 24
Peak memory 232868 kb
Host smart-6ee669fd-de1d-468c-b361-08f7f1896f5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933958878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3933958878
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.671309141
Short name T392
Test name
Test status
Simulation time 18849459049 ps
CPU time 43.57 seconds
Started Jul 03 05:18:21 PM PDT 24
Finished Jul 03 05:19:05 PM PDT 24
Peak memory 216352 kb
Host smart-4d6eeed3-9ddf-4f9a-bdff-c0c661729ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671309141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.671309141
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.506848188
Short name T729
Test name
Test status
Simulation time 1772652134 ps
CPU time 6.73 seconds
Started Jul 03 05:18:19 PM PDT 24
Finished Jul 03 05:18:27 PM PDT 24
Peak memory 216204 kb
Host smart-0e3b5586-b0cc-4648-b3cd-3fa56f00efda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506848188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.506848188
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2897400908
Short name T969
Test name
Test status
Simulation time 29999038 ps
CPU time 1.02 seconds
Started Jul 03 05:18:20 PM PDT 24
Finished Jul 03 05:18:22 PM PDT 24
Peak memory 207876 kb
Host smart-5662a5aa-de57-4b5e-9b9e-bd98c45139d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897400908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2897400908
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2182925328
Short name T419
Test name
Test status
Simulation time 116454773 ps
CPU time 1.09 seconds
Started Jul 03 05:18:22 PM PDT 24
Finished Jul 03 05:18:24 PM PDT 24
Peak memory 206480 kb
Host smart-1052785f-c20d-4224-b23d-b35d8889f33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182925328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2182925328
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3286828947
Short name T1004
Test name
Test status
Simulation time 4226988634 ps
CPU time 3.97 seconds
Started Jul 03 05:18:25 PM PDT 24
Finished Jul 03 05:18:29 PM PDT 24
Peak memory 224568 kb
Host smart-153d1faa-198f-46b2-bd40-1906fa117b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286828947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3286828947
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.425228258
Short name T860
Test name
Test status
Simulation time 17940523 ps
CPU time 0.77 seconds
Started Jul 03 05:16:56 PM PDT 24
Finished Jul 03 05:16:57 PM PDT 24
Peak memory 205540 kb
Host smart-b1763769-2391-4387-85dd-04dcfb247724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425228258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.425228258
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.728424620
Short name T87
Test name
Test status
Simulation time 2375323206 ps
CPU time 5.07 seconds
Started Jul 03 05:16:51 PM PDT 24
Finished Jul 03 05:16:57 PM PDT 24
Peak memory 224596 kb
Host smart-bccab2a5-5135-44bb-92a3-65b54e3f3649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728424620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.728424620
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1478043106
Short name T984
Test name
Test status
Simulation time 12106472 ps
CPU time 0.79 seconds
Started Jul 03 05:16:47 PM PDT 24
Finished Jul 03 05:16:49 PM PDT 24
Peak memory 205584 kb
Host smart-cc6cc7bd-5fe6-470e-9053-90960431977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478043106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1478043106
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.784579044
Short name T645
Test name
Test status
Simulation time 52498728 ps
CPU time 0.77 seconds
Started Jul 03 05:16:49 PM PDT 24
Finished Jul 03 05:16:51 PM PDT 24
Peak memory 215752 kb
Host smart-5731d69f-01cd-4fdd-9673-01e832698afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784579044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.784579044
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.218182685
Short name T233
Test name
Test status
Simulation time 40225443048 ps
CPU time 167.4 seconds
Started Jul 03 05:16:49 PM PDT 24
Finished Jul 03 05:19:38 PM PDT 24
Peak memory 253916 kb
Host smart-e68b17e4-c486-4440-9f18-e06af2c788c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218182685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.218182685
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3349016046
Short name T503
Test name
Test status
Simulation time 11580889526 ps
CPU time 37.45 seconds
Started Jul 03 05:16:53 PM PDT 24
Finished Jul 03 05:17:31 PM PDT 24
Peak memory 249244 kb
Host smart-582ea041-75f4-4b4f-adb9-a570171808db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349016046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3349016046
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.503602759
Short name T130
Test name
Test status
Simulation time 151407218 ps
CPU time 6.74 seconds
Started Jul 03 05:16:51 PM PDT 24
Finished Jul 03 05:16:58 PM PDT 24
Peak memory 224496 kb
Host smart-adb97216-50a0-4564-a881-77f7974837a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503602759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.503602759
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.184980092
Short name T511
Test name
Test status
Simulation time 143747879720 ps
CPU time 87.02 seconds
Started Jul 03 05:16:49 PM PDT 24
Finished Jul 03 05:18:18 PM PDT 24
Peak memory 249200 kb
Host smart-bb9743e7-91d3-4843-9cb2-69857913f17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184980092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
184980092
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.520317508
Short name T893
Test name
Test status
Simulation time 871772550 ps
CPU time 3.45 seconds
Started Jul 03 05:16:49 PM PDT 24
Finished Jul 03 05:16:53 PM PDT 24
Peak memory 224428 kb
Host smart-63afb305-6364-4d83-b2b2-38906b002fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520317508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.520317508
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1970590406
Short name T952
Test name
Test status
Simulation time 4070700522 ps
CPU time 16.57 seconds
Started Jul 03 05:16:49 PM PDT 24
Finished Jul 03 05:17:07 PM PDT 24
Peak memory 232836 kb
Host smart-16288c63-5ffb-4b00-b570-89197bb6a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970590406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1970590406
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3517272710
Short name T954
Test name
Test status
Simulation time 39702692 ps
CPU time 2.54 seconds
Started Jul 03 05:16:51 PM PDT 24
Finished Jul 03 05:16:54 PM PDT 24
Peak memory 232288 kb
Host smart-f2ad1550-8a60-46de-94f4-6b27aeb16b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517272710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3517272710
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1891854116
Short name T191
Test name
Test status
Simulation time 6451568947 ps
CPU time 8.5 seconds
Started Jul 03 05:16:51 PM PDT 24
Finished Jul 03 05:17:00 PM PDT 24
Peak memory 224596 kb
Host smart-c6319c13-13e7-4003-a3d6-d6728c9c6c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891854116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1891854116
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4155980015
Short name T662
Test name
Test status
Simulation time 6011134837 ps
CPU time 15.96 seconds
Started Jul 03 05:16:48 PM PDT 24
Finished Jul 03 05:17:04 PM PDT 24
Peak memory 220784 kb
Host smart-3e2faa1f-b0aa-40ff-bb99-8bbdb69e9e1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4155980015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4155980015
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3891643240
Short name T281
Test name
Test status
Simulation time 20265145223 ps
CPU time 167.32 seconds
Started Jul 03 05:16:56 PM PDT 24
Finished Jul 03 05:19:44 PM PDT 24
Peak memory 249708 kb
Host smart-b9318dab-e8af-4647-ab74-60bb83379b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891643240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3891643240
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1403226153
Short name T298
Test name
Test status
Simulation time 2194720741 ps
CPU time 8.5 seconds
Started Jul 03 05:16:49 PM PDT 24
Finished Jul 03 05:16:59 PM PDT 24
Peak memory 216424 kb
Host smart-b453f154-3f49-4bfc-bfac-c6ac337a4f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403226153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1403226153
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1830927712
Short name T16
Test name
Test status
Simulation time 837149206 ps
CPU time 2.57 seconds
Started Jul 03 05:16:50 PM PDT 24
Finished Jul 03 05:16:54 PM PDT 24
Peak memory 216232 kb
Host smart-670124e0-98a1-4198-803d-100a76bc4b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830927712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1830927712
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2118172684
Short name T307
Test name
Test status
Simulation time 303017035 ps
CPU time 1.97 seconds
Started Jul 03 05:16:52 PM PDT 24
Finished Jul 03 05:16:54 PM PDT 24
Peak memory 216248 kb
Host smart-4f989bc9-967c-4ace-bf95-062fda3c5b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118172684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2118172684
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.4186970795
Short name T375
Test name
Test status
Simulation time 170389016 ps
CPU time 0.86 seconds
Started Jul 03 05:16:49 PM PDT 24
Finished Jul 03 05:16:51 PM PDT 24
Peak memory 205960 kb
Host smart-f6979031-2e97-4289-9037-3eba72367537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186970795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.4186970795
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.4131675435
Short name T904
Test name
Test status
Simulation time 2691732785 ps
CPU time 6.33 seconds
Started Jul 03 05:16:51 PM PDT 24
Finished Jul 03 05:16:58 PM PDT 24
Peak memory 232832 kb
Host smart-8c1fc5bf-93a1-4f1c-a005-8286ea3e9682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131675435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4131675435
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3028465389
Short name T669
Test name
Test status
Simulation time 22989492 ps
CPU time 0.76 seconds
Started Jul 03 05:18:28 PM PDT 24
Finished Jul 03 05:18:29 PM PDT 24
Peak memory 205388 kb
Host smart-6a535ec9-5500-4f64-8563-2d07d323cd03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028465389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3028465389
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3599656571
Short name T363
Test name
Test status
Simulation time 558241647 ps
CPU time 2.98 seconds
Started Jul 03 05:18:27 PM PDT 24
Finished Jul 03 05:18:31 PM PDT 24
Peak memory 224460 kb
Host smart-a002ff35-1e04-4f3a-80cc-083eb4ce0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599656571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3599656571
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3749756398
Short name T596
Test name
Test status
Simulation time 40856672 ps
CPU time 0.75 seconds
Started Jul 03 05:18:27 PM PDT 24
Finished Jul 03 05:18:29 PM PDT 24
Peak memory 206596 kb
Host smart-51aff0f1-6141-4655-bbc9-76981b329e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749756398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3749756398
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3010950141
Short name T546
Test name
Test status
Simulation time 14366218332 ps
CPU time 58.79 seconds
Started Jul 03 05:18:27 PM PDT 24
Finished Jul 03 05:19:26 PM PDT 24
Peak memory 234260 kb
Host smart-d0cd4529-43b7-4c16-9c0e-0ac639192770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010950141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3010950141
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3916985701
Short name T253
Test name
Test status
Simulation time 262138014494 ps
CPU time 574.19 seconds
Started Jul 03 05:18:28 PM PDT 24
Finished Jul 03 05:28:03 PM PDT 24
Peak memory 267680 kb
Host smart-323d1df3-f69f-427c-b94a-10f7289665a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916985701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3916985701
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1080523065
Short name T29
Test name
Test status
Simulation time 24207761640 ps
CPU time 257.28 seconds
Started Jul 03 05:18:25 PM PDT 24
Finished Jul 03 05:22:43 PM PDT 24
Peak memory 252224 kb
Host smart-7d17483f-4c83-441d-90da-9958b275ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080523065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1080523065
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1029676314
Short name T543
Test name
Test status
Simulation time 27405062645 ps
CPU time 196.38 seconds
Started Jul 03 05:18:25 PM PDT 24
Finished Jul 03 05:21:41 PM PDT 24
Peak memory 249220 kb
Host smart-91fc3c1e-6f8f-4715-8b38-fb0437393987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029676314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1029676314
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3590080841
Short name T494
Test name
Test status
Simulation time 656770077 ps
CPU time 5.06 seconds
Started Jul 03 05:18:25 PM PDT 24
Finished Jul 03 05:18:30 PM PDT 24
Peak memory 232652 kb
Host smart-bcb7b90e-678f-4970-b631-6b854cf8bfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590080841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3590080841
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2899349952
Short name T933
Test name
Test status
Simulation time 1089023887 ps
CPU time 21.04 seconds
Started Jul 03 05:18:24 PM PDT 24
Finished Jul 03 05:18:45 PM PDT 24
Peak memory 234152 kb
Host smart-9af8637e-9ba7-4e23-8f8b-3f7362dfa63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899349952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2899349952
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2736592162
Short name T881
Test name
Test status
Simulation time 62739617 ps
CPU time 2.47 seconds
Started Jul 03 05:18:28 PM PDT 24
Finished Jul 03 05:18:31 PM PDT 24
Peak memory 232340 kb
Host smart-c68232e3-4c93-42bf-a70c-ff85f9a4c6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736592162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2736592162
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3974819854
Short name T12
Test name
Test status
Simulation time 1277591251 ps
CPU time 4.91 seconds
Started Jul 03 05:18:24 PM PDT 24
Finished Jul 03 05:18:30 PM PDT 24
Peak memory 232620 kb
Host smart-1cbcc31c-c979-4c89-b330-ba9d05f7616a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974819854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3974819854
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2994384642
Short name T710
Test name
Test status
Simulation time 226928763 ps
CPU time 5.67 seconds
Started Jul 03 05:18:25 PM PDT 24
Finished Jul 03 05:18:31 PM PDT 24
Peak memory 222128 kb
Host smart-4e6c233a-8cd9-422d-884d-2c26249775ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2994384642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2994384642
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2563781107
Short name T420
Test name
Test status
Simulation time 17144408 ps
CPU time 0.74 seconds
Started Jul 03 05:18:26 PM PDT 24
Finished Jul 03 05:18:28 PM PDT 24
Peak memory 205708 kb
Host smart-51520d85-5841-4dc5-8b1c-d706f822001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563781107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2563781107
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.21421810
Short name T520
Test name
Test status
Simulation time 361723562 ps
CPU time 3.21 seconds
Started Jul 03 05:18:28 PM PDT 24
Finished Jul 03 05:18:33 PM PDT 24
Peak memory 216184 kb
Host smart-caf9acec-5e06-4ad1-9731-7604ef4efe6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21421810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.21421810
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1035739025
Short name T330
Test name
Test status
Simulation time 131343878 ps
CPU time 1.66 seconds
Started Jul 03 05:18:27 PM PDT 24
Finished Jul 03 05:18:30 PM PDT 24
Peak memory 216256 kb
Host smart-f34b0650-e059-4b6b-b609-6e74c74b1c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035739025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1035739025
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2202537485
Short name T334
Test name
Test status
Simulation time 21259664 ps
CPU time 0.8 seconds
Started Jul 03 05:18:27 PM PDT 24
Finished Jul 03 05:18:28 PM PDT 24
Peak memory 205980 kb
Host smart-20134ef6-ed9b-40c6-8d76-839c20054af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202537485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2202537485
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2218910119
Short name T489
Test name
Test status
Simulation time 15567414163 ps
CPU time 14.79 seconds
Started Jul 03 05:18:28 PM PDT 24
Finished Jul 03 05:18:44 PM PDT 24
Peak memory 232832 kb
Host smart-54944a6d-eb14-4813-a540-3856e839a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218910119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2218910119
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3955057536
Short name T63
Test name
Test status
Simulation time 22245950 ps
CPU time 0.71 seconds
Started Jul 03 05:18:29 PM PDT 24
Finished Jul 03 05:18:31 PM PDT 24
Peak memory 205520 kb
Host smart-50f699ac-42c1-4316-835b-205f4eba129f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955057536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3955057536
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1122804115
Short name T793
Test name
Test status
Simulation time 776193173 ps
CPU time 6.15 seconds
Started Jul 03 05:18:29 PM PDT 24
Finished Jul 03 05:18:36 PM PDT 24
Peak memory 232676 kb
Host smart-f19e2684-1f00-4dcc-9127-c3d4e42e8b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122804115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1122804115
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.941120666
Short name T320
Test name
Test status
Simulation time 79060627 ps
CPU time 0.88 seconds
Started Jul 03 05:18:28 PM PDT 24
Finished Jul 03 05:18:30 PM PDT 24
Peak memory 205608 kb
Host smart-16c2d32e-21b7-4e69-879b-d6e15d2bba37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941120666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.941120666
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.407201673
Short name T595
Test name
Test status
Simulation time 8966377870 ps
CPU time 51.23 seconds
Started Jul 03 05:18:29 PM PDT 24
Finished Jul 03 05:19:21 PM PDT 24
Peak memory 251636 kb
Host smart-a4d9be04-2c26-4759-aba9-ffb50365a1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407201673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.407201673
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2599011588
Short name T711
Test name
Test status
Simulation time 206965789943 ps
CPU time 240.15 seconds
Started Jul 03 05:18:30 PM PDT 24
Finished Jul 03 05:22:31 PM PDT 24
Peak memory 257296 kb
Host smart-9beb0919-2623-44fd-b362-2a574b3621b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599011588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2599011588
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.390233236
Short name T613
Test name
Test status
Simulation time 7007735716 ps
CPU time 103.04 seconds
Started Jul 03 05:18:34 PM PDT 24
Finished Jul 03 05:20:17 PM PDT 24
Peak memory 261956 kb
Host smart-47568430-e95b-4aa6-a080-5cbf4633a3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390233236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.390233236
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4170614631
Short name T936
Test name
Test status
Simulation time 10130012856 ps
CPU time 40.46 seconds
Started Jul 03 05:18:29 PM PDT 24
Finished Jul 03 05:19:10 PM PDT 24
Peak memory 249752 kb
Host smart-6bfd5b4d-bbe0-4d10-92f2-696f8b2d6dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170614631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4170614631
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3645294517
Short name T540
Test name
Test status
Simulation time 74304914 ps
CPU time 2.57 seconds
Started Jul 03 05:18:28 PM PDT 24
Finished Jul 03 05:18:31 PM PDT 24
Peak memory 224444 kb
Host smart-72553142-75d1-44b1-8281-5c6269934398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645294517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3645294517
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2624640389
Short name T682
Test name
Test status
Simulation time 649329302 ps
CPU time 12.17 seconds
Started Jul 03 05:18:29 PM PDT 24
Finished Jul 03 05:18:42 PM PDT 24
Peak memory 224496 kb
Host smart-ab4e11f9-64ae-4e25-8f7c-1de14e36420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624640389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2624640389
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3682849629
Short name T188
Test name
Test status
Simulation time 1473201090 ps
CPU time 6.55 seconds
Started Jul 03 05:18:30 PM PDT 24
Finished Jul 03 05:18:37 PM PDT 24
Peak memory 232652 kb
Host smart-40cdc699-7270-4a3d-8f0c-93747ea8bc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682849629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3682849629
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1196121987
Short name T766
Test name
Test status
Simulation time 8845661638 ps
CPU time 7.56 seconds
Started Jul 03 05:18:34 PM PDT 24
Finished Jul 03 05:18:42 PM PDT 24
Peak memory 224628 kb
Host smart-8028842e-3146-44c2-9874-2db24b2d798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196121987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1196121987
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3133583984
Short name T527
Test name
Test status
Simulation time 5030216970 ps
CPU time 9.29 seconds
Started Jul 03 05:18:30 PM PDT 24
Finished Jul 03 05:18:40 PM PDT 24
Peak memory 222216 kb
Host smart-c1bc5d56-3bd6-4b76-9dfa-91f66cc0910c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3133583984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3133583984
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1685827883
Short name T170
Test name
Test status
Simulation time 32774044197 ps
CPU time 31.02 seconds
Started Jul 03 05:18:30 PM PDT 24
Finished Jul 03 05:19:01 PM PDT 24
Peak memory 216328 kb
Host smart-682e8774-8cf0-48af-b11f-4c12e79e9cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685827883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1685827883
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1887899406
Short name T373
Test name
Test status
Simulation time 644906635 ps
CPU time 1.43 seconds
Started Jul 03 05:18:34 PM PDT 24
Finished Jul 03 05:18:35 PM PDT 24
Peak memory 206884 kb
Host smart-eb588323-cb2f-495f-8107-4e984dfdbc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887899406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1887899406
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1024676452
Short name T444
Test name
Test status
Simulation time 36833410 ps
CPU time 1.01 seconds
Started Jul 03 05:18:28 PM PDT 24
Finished Jul 03 05:18:30 PM PDT 24
Peak memory 207476 kb
Host smart-a08e4297-3911-457c-ad7b-97a94ea23da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024676452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1024676452
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1659172853
Short name T456
Test name
Test status
Simulation time 348821783 ps
CPU time 0.99 seconds
Started Jul 03 05:18:31 PM PDT 24
Finished Jul 03 05:18:33 PM PDT 24
Peak memory 206316 kb
Host smart-0be44b78-6187-40f2-8677-860594f1ecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659172853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1659172853
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1444290818
Short name T107
Test name
Test status
Simulation time 901011297 ps
CPU time 3.68 seconds
Started Jul 03 05:18:34 PM PDT 24
Finished Jul 03 05:18:38 PM PDT 24
Peak memory 232664 kb
Host smart-be042a66-7fad-455b-be21-3517ad3ed7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444290818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1444290818
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3537827984
Short name T51
Test name
Test status
Simulation time 10842195 ps
CPU time 0.71 seconds
Started Jul 03 05:18:32 PM PDT 24
Finished Jul 03 05:18:33 PM PDT 24
Peak memory 204964 kb
Host smart-6190ab31-b2de-4e38-965c-aa39e1877ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537827984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3537827984
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3735921046
Short name T897
Test name
Test status
Simulation time 30813768 ps
CPU time 2.22 seconds
Started Jul 03 05:18:38 PM PDT 24
Finished Jul 03 05:18:41 PM PDT 24
Peak memory 224124 kb
Host smart-4efddc19-2a9d-4a0b-bf3b-a3e3f70915f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735921046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3735921046
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3554659029
Short name T317
Test name
Test status
Simulation time 49593687 ps
CPU time 0.78 seconds
Started Jul 03 05:18:36 PM PDT 24
Finished Jul 03 05:18:38 PM PDT 24
Peak memory 205616 kb
Host smart-13c9b1be-aa10-4a6d-947c-f3bf5b0f7092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554659029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3554659029
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1609216601
Short name T218
Test name
Test status
Simulation time 14698516730 ps
CPU time 157.73 seconds
Started Jul 03 05:18:32 PM PDT 24
Finished Jul 03 05:21:10 PM PDT 24
Peak memory 257128 kb
Host smart-f8fe7f26-a7ca-4dca-8e2b-85508b066259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609216601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1609216601
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2088298709
Short name T57
Test name
Test status
Simulation time 1318215782 ps
CPU time 11.55 seconds
Started Jul 03 05:18:39 PM PDT 24
Finished Jul 03 05:18:51 PM PDT 24
Peak memory 217380 kb
Host smart-2fc49f52-13ba-437a-831f-de5f285c4508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088298709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2088298709
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3787655016
Short name T274
Test name
Test status
Simulation time 13008218676 ps
CPU time 49.61 seconds
Started Jul 03 05:18:33 PM PDT 24
Finished Jul 03 05:19:23 PM PDT 24
Peak memory 248936 kb
Host smart-6bdf014b-07cf-4f9a-9776-39b041e7e134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787655016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3787655016
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2680860843
Short name T885
Test name
Test status
Simulation time 85622198313 ps
CPU time 146.95 seconds
Started Jul 03 05:18:33 PM PDT 24
Finished Jul 03 05:21:01 PM PDT 24
Peak memory 249196 kb
Host smart-2202adca-1f25-414d-b892-83bc69666bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680860843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2680860843
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.291212867
Short name T620
Test name
Test status
Simulation time 5493529731 ps
CPU time 14.43 seconds
Started Jul 03 05:18:32 PM PDT 24
Finished Jul 03 05:18:47 PM PDT 24
Peak memory 224636 kb
Host smart-f418b349-1155-46d3-b77f-f0f423248e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291212867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.291212867
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3903975290
Short name T797
Test name
Test status
Simulation time 2717711152 ps
CPU time 19.85 seconds
Started Jul 03 05:18:37 PM PDT 24
Finished Jul 03 05:18:57 PM PDT 24
Peak memory 232856 kb
Host smart-faf99bd5-8c82-45bc-9936-2e84a934c304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903975290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3903975290
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1637929924
Short name T808
Test name
Test status
Simulation time 651991280 ps
CPU time 9.31 seconds
Started Jul 03 05:18:32 PM PDT 24
Finished Jul 03 05:18:41 PM PDT 24
Peak memory 232676 kb
Host smart-53bc04d2-d378-4a8b-bd63-338c58535aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637929924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1637929924
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3271071988
Short name T930
Test name
Test status
Simulation time 1569894272 ps
CPU time 6.99 seconds
Started Jul 03 05:18:33 PM PDT 24
Finished Jul 03 05:18:40 PM PDT 24
Peak memory 240516 kb
Host smart-04dbd0a9-dac8-4e9d-801c-9d222bce1f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271071988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3271071988
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.53772740
Short name T714
Test name
Test status
Simulation time 924981816 ps
CPU time 13.34 seconds
Started Jul 03 05:18:37 PM PDT 24
Finished Jul 03 05:18:51 PM PDT 24
Peak memory 221552 kb
Host smart-d1870a67-3412-40d1-8482-cec521911ed0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=53772740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direc
t.53772740
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1948756992
Short name T20
Test name
Test status
Simulation time 49107312 ps
CPU time 0.93 seconds
Started Jul 03 05:18:32 PM PDT 24
Finished Jul 03 05:18:34 PM PDT 24
Peak memory 206896 kb
Host smart-3a0bd7c8-1bc9-43b8-af4a-d962a2bba478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948756992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1948756992
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3114557566
Short name T835
Test name
Test status
Simulation time 10212341420 ps
CPU time 7.03 seconds
Started Jul 03 05:18:31 PM PDT 24
Finished Jul 03 05:18:39 PM PDT 24
Peak memory 220652 kb
Host smart-8a6d27b0-41c0-49fb-9ac3-61b7c89e740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114557566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3114557566
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2678950222
Short name T418
Test name
Test status
Simulation time 2381755622 ps
CPU time 4.89 seconds
Started Jul 03 05:18:39 PM PDT 24
Finished Jul 03 05:18:44 PM PDT 24
Peak memory 216396 kb
Host smart-f00d57ff-90bd-4474-870e-f99fbe2f3c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678950222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2678950222
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1211142353
Short name T481
Test name
Test status
Simulation time 223898207 ps
CPU time 1.7 seconds
Started Jul 03 05:18:32 PM PDT 24
Finished Jul 03 05:18:34 PM PDT 24
Peak memory 216192 kb
Host smart-a25c70ad-81e2-456c-8278-fa86498977c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211142353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1211142353
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.474259301
Short name T618
Test name
Test status
Simulation time 102970434 ps
CPU time 0.88 seconds
Started Jul 03 05:18:31 PM PDT 24
Finished Jul 03 05:18:32 PM PDT 24
Peak memory 207036 kb
Host smart-0d318e5d-fd28-4cdb-a473-6224d41b5fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474259301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.474259301
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2131083004
Short name T434
Test name
Test status
Simulation time 801582777 ps
CPU time 7.66 seconds
Started Jul 03 05:18:34 PM PDT 24
Finished Jul 03 05:18:42 PM PDT 24
Peak memory 218260 kb
Host smart-413a6ba5-e5fd-4e2e-949e-3d355a888c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131083004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2131083004
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1392261207
Short name T478
Test name
Test status
Simulation time 11945141 ps
CPU time 0.76 seconds
Started Jul 03 05:18:36 PM PDT 24
Finished Jul 03 05:18:37 PM PDT 24
Peak memory 205852 kb
Host smart-bd058ba6-08a5-4154-b167-42231c3e123e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392261207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1392261207
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3950357586
Short name T46
Test name
Test status
Simulation time 103330720 ps
CPU time 3.12 seconds
Started Jul 03 05:18:37 PM PDT 24
Finished Jul 03 05:18:41 PM PDT 24
Peak memory 232732 kb
Host smart-2712b439-9db4-4a36-8a0d-2afd6c4ee4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950357586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3950357586
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.132186029
Short name T448
Test name
Test status
Simulation time 77709840 ps
CPU time 0.78 seconds
Started Jul 03 05:18:35 PM PDT 24
Finished Jul 03 05:18:36 PM PDT 24
Peak memory 206576 kb
Host smart-607df715-b3d1-454d-87a4-b1c0bfb0377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132186029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.132186029
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2251410095
Short name T725
Test name
Test status
Simulation time 6253341710 ps
CPU time 60.55 seconds
Started Jul 03 05:18:37 PM PDT 24
Finished Jul 03 05:19:38 PM PDT 24
Peak memory 249228 kb
Host smart-b4f53824-2358-4557-b399-30d381a73686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251410095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2251410095
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3887293159
Short name T825
Test name
Test status
Simulation time 5353465253 ps
CPU time 78.64 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:20:01 PM PDT 24
Peak memory 249244 kb
Host smart-1fe1e888-f7f5-4564-9875-c1b90793b0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887293159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3887293159
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.814327455
Short name T122
Test name
Test status
Simulation time 9076990960 ps
CPU time 71 seconds
Started Jul 03 05:18:38 PM PDT 24
Finished Jul 03 05:19:49 PM PDT 24
Peak memory 265136 kb
Host smart-01fbcf08-7a67-4f85-9b90-0f85318cf814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814327455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.814327455
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3835397054
Short name T473
Test name
Test status
Simulation time 5446561453 ps
CPU time 28.38 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:19:11 PM PDT 24
Peak memory 240964 kb
Host smart-8d3a5ecd-6961-430a-b59c-4aa23cae4d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835397054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3835397054
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1853078323
Short name T228
Test name
Test status
Simulation time 11055726599 ps
CPU time 83.26 seconds
Started Jul 03 05:18:36 PM PDT 24
Finished Jul 03 05:20:00 PM PDT 24
Peak memory 240616 kb
Host smart-befe593f-9126-419a-aa39-995f3e076e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853078323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1853078323
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2090418837
Short name T790
Test name
Test status
Simulation time 905234222 ps
CPU time 11.03 seconds
Started Jul 03 05:18:38 PM PDT 24
Finished Jul 03 05:18:49 PM PDT 24
Peak memory 218780 kb
Host smart-47c88d60-5731-4e3e-a6b5-132db405a885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090418837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2090418837
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2438153833
Short name T780
Test name
Test status
Simulation time 8483670519 ps
CPU time 25.28 seconds
Started Jul 03 05:18:37 PM PDT 24
Finished Jul 03 05:19:03 PM PDT 24
Peak memory 232780 kb
Host smart-c86ebfb2-2275-481c-8152-ec03c26b7c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438153833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2438153833
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.972611263
Short name T1001
Test name
Test status
Simulation time 43002014015 ps
CPU time 29.89 seconds
Started Jul 03 05:18:35 PM PDT 24
Finished Jul 03 05:19:06 PM PDT 24
Peak memory 224584 kb
Host smart-dd824273-5d68-43a4-9fbc-93e4855d681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972611263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.972611263
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1106826927
Short name T920
Test name
Test status
Simulation time 2386876711 ps
CPU time 7 seconds
Started Jul 03 05:18:40 PM PDT 24
Finished Jul 03 05:18:48 PM PDT 24
Peak memory 232784 kb
Host smart-65e356d7-929b-49af-b96e-a11fa9450944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106826927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1106826927
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.739241824
Short name T778
Test name
Test status
Simulation time 446165651 ps
CPU time 7.26 seconds
Started Jul 03 05:18:36 PM PDT 24
Finished Jul 03 05:18:44 PM PDT 24
Peak memory 219188 kb
Host smart-a1134c0a-7b2f-4ce4-b845-6a530ac01a62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=739241824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.739241824
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1802163284
Short name T856
Test name
Test status
Simulation time 42710196316 ps
CPU time 178.72 seconds
Started Jul 03 05:18:39 PM PDT 24
Finished Jul 03 05:21:38 PM PDT 24
Peak memory 256652 kb
Host smart-55f891fd-cad8-4cf4-ae0f-1a82de1447d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802163284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1802163284
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1492035057
Short name T726
Test name
Test status
Simulation time 10414970419 ps
CPU time 49.41 seconds
Started Jul 03 05:18:32 PM PDT 24
Finished Jul 03 05:19:22 PM PDT 24
Peak memory 216312 kb
Host smart-b1bf1b3c-344d-48d2-bd63-cdf97e7974ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492035057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1492035057
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3347119178
Short name T358
Test name
Test status
Simulation time 9820100529 ps
CPU time 22.51 seconds
Started Jul 03 05:18:32 PM PDT 24
Finished Jul 03 05:18:55 PM PDT 24
Peak memory 216308 kb
Host smart-052d9140-7fed-4b6e-a500-65947a068368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347119178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3347119178
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3023388489
Short name T56
Test name
Test status
Simulation time 132165452 ps
CPU time 1.44 seconds
Started Jul 03 05:18:40 PM PDT 24
Finished Jul 03 05:18:42 PM PDT 24
Peak memory 207944 kb
Host smart-9833447c-d8f7-41ac-8145-1e1db2e048ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023388489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3023388489
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3777619231
Short name T965
Test name
Test status
Simulation time 31110159 ps
CPU time 0.78 seconds
Started Jul 03 05:18:39 PM PDT 24
Finished Jul 03 05:18:40 PM PDT 24
Peak memory 205992 kb
Host smart-5fdc3b3a-bc99-4bb7-87fb-ee784fbd5871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777619231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3777619231
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1340349533
Short name T663
Test name
Test status
Simulation time 8255253390 ps
CPU time 33.35 seconds
Started Jul 03 05:18:38 PM PDT 24
Finished Jul 03 05:19:11 PM PDT 24
Peak memory 239172 kb
Host smart-33d856c3-1f7a-487a-b40b-ab372b8e49db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340349533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1340349533
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1612143279
Short name T840
Test name
Test status
Simulation time 44533498 ps
CPU time 0.75 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:18:43 PM PDT 24
Peak memory 205524 kb
Host smart-b6c6ef7a-04a8-4362-a499-17744991f968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612143279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1612143279
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2742399950
Short name T724
Test name
Test status
Simulation time 1756159217 ps
CPU time 5.32 seconds
Started Jul 03 05:18:39 PM PDT 24
Finished Jul 03 05:18:45 PM PDT 24
Peak memory 224512 kb
Host smart-e77d7332-8581-4ad4-81ea-c6af8f033b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742399950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2742399950
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1023231116
Short name T598
Test name
Test status
Simulation time 20501640 ps
CPU time 0.77 seconds
Started Jul 03 05:18:38 PM PDT 24
Finished Jul 03 05:18:40 PM PDT 24
Peak memory 206632 kb
Host smart-3d0866a1-7943-4fa9-aae9-7363c40a7faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023231116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1023231116
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1035905134
Short name T234
Test name
Test status
Simulation time 5109946003 ps
CPU time 52.28 seconds
Started Jul 03 05:18:38 PM PDT 24
Finished Jul 03 05:19:31 PM PDT 24
Peak memory 235248 kb
Host smart-76ba5058-2679-4943-8295-61e2a4de87dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035905134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1035905134
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3938584167
Short name T848
Test name
Test status
Simulation time 30869817649 ps
CPU time 118.05 seconds
Started Jul 03 05:18:43 PM PDT 24
Finished Jul 03 05:20:41 PM PDT 24
Peak memory 249628 kb
Host smart-2bb6144e-8b30-4d11-a0b9-4b31ff85c878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938584167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3938584167
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2949142655
Short name T937
Test name
Test status
Simulation time 591328847 ps
CPU time 3.59 seconds
Started Jul 03 05:18:39 PM PDT 24
Finished Jul 03 05:18:43 PM PDT 24
Peak memory 232648 kb
Host smart-61a60ca8-6c5b-4499-814f-53a7e3a2fec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949142655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2949142655
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1156577434
Short name T530
Test name
Test status
Simulation time 3849496555 ps
CPU time 12.12 seconds
Started Jul 03 05:18:40 PM PDT 24
Finished Jul 03 05:18:53 PM PDT 24
Peak memory 232840 kb
Host smart-99395858-6963-45fe-a07a-f5cd5310c827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156577434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1156577434
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.299495381
Short name T621
Test name
Test status
Simulation time 1363839415 ps
CPU time 15.37 seconds
Started Jul 03 05:18:40 PM PDT 24
Finished Jul 03 05:18:56 PM PDT 24
Peak memory 232668 kb
Host smart-15ade749-06f4-4046-91cf-84db8cd1383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299495381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.299495381
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3047993328
Short name T266
Test name
Test status
Simulation time 82428312 ps
CPU time 2.51 seconds
Started Jul 03 05:18:40 PM PDT 24
Finished Jul 03 05:18:43 PM PDT 24
Peak memory 224464 kb
Host smart-f6d7f74d-db04-4e8a-9533-01be22e136e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047993328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3047993328
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.490796817
Short name T96
Test name
Test status
Simulation time 4144005463 ps
CPU time 8.32 seconds
Started Jul 03 05:18:42 PM PDT 24
Finished Jul 03 05:18:51 PM PDT 24
Peak memory 224536 kb
Host smart-4e616de8-985b-450d-ae06-3b52ced3f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490796817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.490796817
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4032009522
Short name T749
Test name
Test status
Simulation time 1640697638 ps
CPU time 10.98 seconds
Started Jul 03 05:18:40 PM PDT 24
Finished Jul 03 05:18:52 PM PDT 24
Peak memory 222564 kb
Host smart-17be4be8-f64c-476e-8a41-2d05eea2bcc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4032009522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4032009522
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.726143284
Short name T833
Test name
Test status
Simulation time 15547495313 ps
CPU time 148.55 seconds
Started Jul 03 05:18:40 PM PDT 24
Finished Jul 03 05:21:09 PM PDT 24
Peak memory 253988 kb
Host smart-d85af2af-a5a2-4e26-b86d-2f8a7e274c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726143284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.726143284
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3829004658
Short name T302
Test name
Test status
Simulation time 655419914 ps
CPU time 2.17 seconds
Started Jul 03 05:18:38 PM PDT 24
Finished Jul 03 05:18:41 PM PDT 24
Peak memory 216264 kb
Host smart-6f4a10dd-ab59-423a-b417-8a18de1bb088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829004658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3829004658
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1088582903
Short name T559
Test name
Test status
Simulation time 152083228 ps
CPU time 1.38 seconds
Started Jul 03 05:18:38 PM PDT 24
Finished Jul 03 05:18:40 PM PDT 24
Peak memory 207912 kb
Host smart-3c36368f-fe0e-43e7-94bd-c8094c4e87ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088582903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1088582903
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3993585867
Short name T309
Test name
Test status
Simulation time 568452724 ps
CPU time 2.39 seconds
Started Jul 03 05:18:40 PM PDT 24
Finished Jul 03 05:18:43 PM PDT 24
Peak memory 216236 kb
Host smart-bc3805a4-8334-4915-ab9e-bce009d27d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993585867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3993585867
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1256589110
Short name T461
Test name
Test status
Simulation time 53886756 ps
CPU time 0.8 seconds
Started Jul 03 05:18:39 PM PDT 24
Finished Jul 03 05:18:40 PM PDT 24
Peak memory 206004 kb
Host smart-3f42a89f-05c1-49b7-ae49-5cec8508239c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256589110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1256589110
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2852834757
Short name T703
Test name
Test status
Simulation time 39159166 ps
CPU time 2.48 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:18:44 PM PDT 24
Peak memory 224152 kb
Host smart-72f6f1f8-b633-42d4-b498-bf9d0db8420e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852834757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2852834757
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2921119733
Short name T587
Test name
Test status
Simulation time 12392151 ps
CPU time 0.74 seconds
Started Jul 03 05:18:45 PM PDT 24
Finished Jul 03 05:18:47 PM PDT 24
Peak memory 205464 kb
Host smart-f435eb97-db11-4533-9932-56b87c729e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921119733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2921119733
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1394575705
Short name T993
Test name
Test status
Simulation time 1009859512 ps
CPU time 16.32 seconds
Started Jul 03 05:18:44 PM PDT 24
Finished Jul 03 05:19:01 PM PDT 24
Peak memory 224428 kb
Host smart-2a2490a1-b181-4e4d-bede-3df32977ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394575705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1394575705
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3867534274
Short name T912
Test name
Test status
Simulation time 92843027 ps
CPU time 0.74 seconds
Started Jul 03 05:18:40 PM PDT 24
Finished Jul 03 05:18:41 PM PDT 24
Peak memory 205900 kb
Host smart-81a7231c-c9fe-42f3-9b70-b7f1778c34b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867534274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3867534274
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2363077086
Short name T207
Test name
Test status
Simulation time 715921386 ps
CPU time 9.74 seconds
Started Jul 03 05:18:43 PM PDT 24
Finished Jul 03 05:18:53 PM PDT 24
Peak memory 224440 kb
Host smart-3345441c-bde5-4b53-a515-b64ac9fa0133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363077086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2363077086
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2113281897
Short name T601
Test name
Test status
Simulation time 4117687172 ps
CPU time 66.61 seconds
Started Jul 03 05:18:42 PM PDT 24
Finished Jul 03 05:19:50 PM PDT 24
Peak memory 255764 kb
Host smart-8c89c575-1935-4fba-a68c-215d752fbb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113281897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2113281897
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1957090714
Short name T450
Test name
Test status
Simulation time 2090644829 ps
CPU time 9.21 seconds
Started Jul 03 05:18:45 PM PDT 24
Finished Jul 03 05:18:54 PM PDT 24
Peak memory 217616 kb
Host smart-4edfc08c-d448-4165-8c2a-f1db9cfaa63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957090714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1957090714
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2745995275
Short name T359
Test name
Test status
Simulation time 55692417026 ps
CPU time 34.17 seconds
Started Jul 03 05:18:45 PM PDT 24
Finished Jul 03 05:19:20 PM PDT 24
Peak memory 239748 kb
Host smart-36fae03a-da6d-4b9c-a406-a43167e8715f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745995275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2745995275
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2353458267
Short name T715
Test name
Test status
Simulation time 45631197610 ps
CPU time 199.93 seconds
Started Jul 03 05:18:44 PM PDT 24
Finished Jul 03 05:22:05 PM PDT 24
Peak memory 256280 kb
Host smart-f72c6ab0-270e-47a1-9dfe-c0011fb367f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353458267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2353458267
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.221231541
Short name T336
Test name
Test status
Simulation time 191570276 ps
CPU time 3.23 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:18:45 PM PDT 24
Peak memory 232656 kb
Host smart-767f4a2a-d470-4b78-acd0-9b7dd9a5bb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221231541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.221231541
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3005184202
Short name T58
Test name
Test status
Simulation time 11258121987 ps
CPU time 31.51 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:19:13 PM PDT 24
Peak memory 249148 kb
Host smart-7f65a49f-3aac-462d-b50e-a5bdcb18806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005184202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3005184202
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2564808681
Short name T498
Test name
Test status
Simulation time 5738242288 ps
CPU time 10.62 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:18:53 PM PDT 24
Peak memory 234376 kb
Host smart-5b63c74b-0eac-4ff7-98ca-892aadc7db3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564808681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2564808681
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1130258723
Short name T11
Test name
Test status
Simulation time 569364949 ps
CPU time 3.34 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:18:45 PM PDT 24
Peak memory 232660 kb
Host smart-53ed99e5-b686-46bf-be7d-e4d52380b3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130258723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1130258723
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.644690334
Short name T574
Test name
Test status
Simulation time 291199842 ps
CPU time 3.79 seconds
Started Jul 03 05:18:47 PM PDT 24
Finished Jul 03 05:18:51 PM PDT 24
Peak memory 219344 kb
Host smart-513a3684-ce4f-4607-bb54-2c4cbc186e07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=644690334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.644690334
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2762668903
Short name T737
Test name
Test status
Simulation time 4995009582 ps
CPU time 11.41 seconds
Started Jul 03 05:18:39 PM PDT 24
Finished Jul 03 05:18:51 PM PDT 24
Peak memory 216872 kb
Host smart-f91e2437-fdab-4b23-b3bb-ffcdbbd1876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762668903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2762668903
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.865065942
Short name T842
Test name
Test status
Simulation time 2512983831 ps
CPU time 1.87 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:18:44 PM PDT 24
Peak memory 207472 kb
Host smart-05c8b8cd-59bf-4722-b7fc-5cbc5f313110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865065942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.865065942
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2670801977
Short name T352
Test name
Test status
Simulation time 36259839 ps
CPU time 0.7 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:18:43 PM PDT 24
Peak memory 205636 kb
Host smart-e5668458-6a05-41a2-8a19-96158ae87730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670801977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2670801977
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2818999200
Short name T751
Test name
Test status
Simulation time 16459592 ps
CPU time 0.72 seconds
Started Jul 03 05:18:41 PM PDT 24
Finished Jul 03 05:18:43 PM PDT 24
Peak memory 205940 kb
Host smart-771af051-6df3-44e5-8cef-a113e1bd27e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818999200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2818999200
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2563122832
Short name T779
Test name
Test status
Simulation time 2364073568 ps
CPU time 11.74 seconds
Started Jul 03 05:18:45 PM PDT 24
Finished Jul 03 05:18:57 PM PDT 24
Peak memory 249032 kb
Host smart-6228786c-ff95-4ba4-98c0-aac6aa80ffdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563122832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2563122832
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4120146777
Short name T866
Test name
Test status
Simulation time 47477206 ps
CPU time 0.74 seconds
Started Jul 03 05:18:48 PM PDT 24
Finished Jul 03 05:18:50 PM PDT 24
Peak memory 205876 kb
Host smart-ca4e510d-c197-46f1-bc75-c903ae39c7a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120146777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4120146777
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.568175654
Short name T887
Test name
Test status
Simulation time 47343723 ps
CPU time 2.57 seconds
Started Jul 03 05:18:45 PM PDT 24
Finished Jul 03 05:18:48 PM PDT 24
Peak memory 232648 kb
Host smart-fbe4138d-c859-4910-9b89-660217e39977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568175654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.568175654
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3820552214
Short name T502
Test name
Test status
Simulation time 17069979 ps
CPU time 0.77 seconds
Started Jul 03 05:18:48 PM PDT 24
Finished Jul 03 05:18:49 PM PDT 24
Peak memory 205912 kb
Host smart-45ac9db4-6951-418e-83f4-818f456d44ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820552214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3820552214
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2338309810
Short name T526
Test name
Test status
Simulation time 6393171675 ps
CPU time 52.98 seconds
Started Jul 03 05:18:50 PM PDT 24
Finished Jul 03 05:19:44 PM PDT 24
Peak memory 239052 kb
Host smart-f34ff5f1-038f-426e-9b80-39145a35029e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338309810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2338309810
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.821462001
Short name T200
Test name
Test status
Simulation time 29840559364 ps
CPU time 246.96 seconds
Started Jul 03 05:18:47 PM PDT 24
Finished Jul 03 05:22:54 PM PDT 24
Peak memory 238756 kb
Host smart-b50cd118-15ea-4c54-8aa5-92cc7f6e6037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821462001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.821462001
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1089614229
Short name T137
Test name
Test status
Simulation time 80020044869 ps
CPU time 195.43 seconds
Started Jul 03 05:18:48 PM PDT 24
Finished Jul 03 05:22:04 PM PDT 24
Peak memory 265472 kb
Host smart-66eb3a02-2c4c-4fee-8f53-388f3f24c624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089614229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1089614229
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1741597082
Short name T757
Test name
Test status
Simulation time 7209133259 ps
CPU time 70.22 seconds
Started Jul 03 05:18:51 PM PDT 24
Finished Jul 03 05:20:02 PM PDT 24
Peak memory 250752 kb
Host smart-34461cb6-bdf3-4587-9c1c-a0b8d1323324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741597082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1741597082
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3959510071
Short name T585
Test name
Test status
Simulation time 24366757977 ps
CPU time 198.66 seconds
Started Jul 03 05:18:48 PM PDT 24
Finished Jul 03 05:22:07 PM PDT 24
Peak memory 262112 kb
Host smart-eba01d11-f0a2-4e5d-b2f5-d238a7e80d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959510071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3959510071
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.121231566
Short name T252
Test name
Test status
Simulation time 125350637 ps
CPU time 2.89 seconds
Started Jul 03 05:18:47 PM PDT 24
Finished Jul 03 05:18:50 PM PDT 24
Peak memory 224392 kb
Host smart-e100b6ca-0683-40a8-9f8f-914aa7a65810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121231566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.121231566
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1239473556
Short name T707
Test name
Test status
Simulation time 640820028 ps
CPU time 14.53 seconds
Started Jul 03 05:18:44 PM PDT 24
Finished Jul 03 05:18:59 PM PDT 24
Peak memory 239628 kb
Host smart-699f814e-9cb8-4348-8154-70ecbcf9ea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239473556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1239473556
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1604594524
Short name T605
Test name
Test status
Simulation time 7698141807 ps
CPU time 22.8 seconds
Started Jul 03 05:18:46 PM PDT 24
Finished Jul 03 05:19:09 PM PDT 24
Peak memory 240608 kb
Host smart-dc038c65-b818-4295-a5d1-b8eb64a17320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604594524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1604594524
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1062833798
Short name T867
Test name
Test status
Simulation time 14905713770 ps
CPU time 20.42 seconds
Started Jul 03 05:18:43 PM PDT 24
Finished Jul 03 05:19:04 PM PDT 24
Peak memory 232768 kb
Host smart-408a0cb6-9bf9-4f1e-9f51-cca2f07590d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062833798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1062833798
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1908290133
Short name T919
Test name
Test status
Simulation time 1955221015 ps
CPU time 7.48 seconds
Started Jul 03 05:18:51 PM PDT 24
Finished Jul 03 05:18:59 PM PDT 24
Peak memory 222108 kb
Host smart-34ac2643-03a9-47b2-814e-ac2ca6055e15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1908290133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1908290133
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1847294667
Short name T700
Test name
Test status
Simulation time 12110065259 ps
CPU time 36.06 seconds
Started Jul 03 05:18:46 PM PDT 24
Finished Jul 03 05:19:22 PM PDT 24
Peak memory 216252 kb
Host smart-65d0745e-2520-43e3-ae64-4d58992199df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847294667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1847294667
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1145402369
Short name T634
Test name
Test status
Simulation time 1849770698 ps
CPU time 4.93 seconds
Started Jul 03 05:18:47 PM PDT 24
Finished Jul 03 05:18:53 PM PDT 24
Peak memory 216240 kb
Host smart-0579c5e1-424f-4dc3-88d9-78f90eaaae21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145402369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1145402369
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.784845656
Short name T781
Test name
Test status
Simulation time 171412852 ps
CPU time 2.12 seconds
Started Jul 03 05:18:45 PM PDT 24
Finished Jul 03 05:18:48 PM PDT 24
Peak memory 216216 kb
Host smart-78bb80ed-2345-484e-bc2c-e74954917ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784845656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.784845656
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1059794065
Short name T643
Test name
Test status
Simulation time 66647098 ps
CPU time 0.8 seconds
Started Jul 03 05:18:44 PM PDT 24
Finished Jul 03 05:18:45 PM PDT 24
Peak memory 206000 kb
Host smart-032c9fa9-87e7-4142-893a-2f41b846eb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059794065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1059794065
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1713649549
Short name T227
Test name
Test status
Simulation time 3064116008 ps
CPU time 12.69 seconds
Started Jul 03 05:18:44 PM PDT 24
Finished Jul 03 05:18:57 PM PDT 24
Peak memory 232864 kb
Host smart-1a9a6dcd-8a8c-4c26-a61f-f4e039d74903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713649549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1713649549
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.997674527
Short name T524
Test name
Test status
Simulation time 37796826 ps
CPU time 0.76 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:18:56 PM PDT 24
Peak memory 205512 kb
Host smart-78e6b41f-6dc9-43b3-84da-4fd1dcf9df9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997674527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.997674527
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1584153332
Short name T241
Test name
Test status
Simulation time 1028065704 ps
CPU time 8.24 seconds
Started Jul 03 05:18:49 PM PDT 24
Finished Jul 03 05:18:57 PM PDT 24
Peak memory 224412 kb
Host smart-92b8b641-7ff5-4744-9964-834aea7007af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584153332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1584153332
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1810987908
Short name T656
Test name
Test status
Simulation time 16114247 ps
CPU time 0.81 seconds
Started Jul 03 05:18:47 PM PDT 24
Finished Jul 03 05:18:48 PM PDT 24
Peak memory 206600 kb
Host smart-080a0e48-b9ce-416d-9d44-475c988a6ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810987908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1810987908
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.337209109
Short name T285
Test name
Test status
Simulation time 6578074575 ps
CPU time 89.44 seconds
Started Jul 03 05:18:54 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 251832 kb
Host smart-b49e66a8-81a8-4d56-b571-57e836d92b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337209109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.337209109
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1785433005
Short name T402
Test name
Test status
Simulation time 25493592769 ps
CPU time 264.64 seconds
Started Jul 03 05:18:50 PM PDT 24
Finished Jul 03 05:23:14 PM PDT 24
Peak memory 256936 kb
Host smart-6c34b96e-1d40-4fd3-b729-342c80b7a0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785433005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1785433005
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2562978489
Short name T822
Test name
Test status
Simulation time 11754654407 ps
CPU time 36.81 seconds
Started Jul 03 05:18:51 PM PDT 24
Finished Jul 03 05:19:28 PM PDT 24
Peak memory 224588 kb
Host smart-0b4c6519-498f-4eaf-bcd2-45061cab5153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562978489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2562978489
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.901817658
Short name T982
Test name
Test status
Simulation time 247808682 ps
CPU time 8.92 seconds
Started Jul 03 05:18:51 PM PDT 24
Finished Jul 03 05:19:00 PM PDT 24
Peak memory 232700 kb
Host smart-fec84ba6-1124-47f3-8a41-a055197682bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901817658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.901817658
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3544975812
Short name T640
Test name
Test status
Simulation time 7535943017 ps
CPU time 36.79 seconds
Started Jul 03 05:18:47 PM PDT 24
Finished Jul 03 05:19:25 PM PDT 24
Peak memory 253324 kb
Host smart-6cb3541c-4b2f-47c1-9795-3b2aa7174e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544975812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3544975812
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3748238602
Short name T814
Test name
Test status
Simulation time 1655262659 ps
CPU time 16.54 seconds
Started Jul 03 05:18:48 PM PDT 24
Finished Jul 03 05:19:05 PM PDT 24
Peak memory 232644 kb
Host smart-5701044d-8cd0-4ac2-9017-aaf0aa27df2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748238602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3748238602
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.263886833
Short name T824
Test name
Test status
Simulation time 810692399 ps
CPU time 19.35 seconds
Started Jul 03 05:18:51 PM PDT 24
Finished Jul 03 05:19:11 PM PDT 24
Peak memory 232620 kb
Host smart-8c86f494-a12f-46a2-b8a6-bccd444ac1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263886833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.263886833
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2459231998
Short name T255
Test name
Test status
Simulation time 745158782 ps
CPU time 4.85 seconds
Started Jul 03 05:18:50 PM PDT 24
Finished Jul 03 05:18:56 PM PDT 24
Peak memory 238500 kb
Host smart-b959a131-bce5-4608-bcad-61f2a0ec0490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459231998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2459231998
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.885708600
Short name T964
Test name
Test status
Simulation time 12388836270 ps
CPU time 10.79 seconds
Started Jul 03 05:18:51 PM PDT 24
Finished Jul 03 05:19:03 PM PDT 24
Peak memory 224536 kb
Host smart-47b07153-fed0-45d6-8a05-e7042d8be1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885708600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.885708600
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3372601533
Short name T999
Test name
Test status
Simulation time 29439744629 ps
CPU time 19.57 seconds
Started Jul 03 05:18:51 PM PDT 24
Finished Jul 03 05:19:11 PM PDT 24
Peak memory 219404 kb
Host smart-faf809a8-21e9-4361-afac-578aeb8548ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3372601533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3372601533
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1469841973
Short name T677
Test name
Test status
Simulation time 2088040690 ps
CPU time 20.03 seconds
Started Jul 03 05:18:47 PM PDT 24
Finished Jul 03 05:19:08 PM PDT 24
Peak memory 216260 kb
Host smart-f04f18b9-b8e3-4bf3-89f7-b16f80406a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469841973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1469841973
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2013600334
Short name T921
Test name
Test status
Simulation time 30375991 ps
CPU time 0.67 seconds
Started Jul 03 05:18:50 PM PDT 24
Finished Jul 03 05:18:51 PM PDT 24
Peak memory 205744 kb
Host smart-bc3f2da4-b1bb-42d3-98e9-efba462e2ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013600334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2013600334
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.994891403
Short name T874
Test name
Test status
Simulation time 92161849 ps
CPU time 0.92 seconds
Started Jul 03 05:18:49 PM PDT 24
Finished Jul 03 05:18:50 PM PDT 24
Peak memory 207640 kb
Host smart-2a1e55a0-f507-42a4-b4aa-ea5e7a8c9d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994891403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.994891403
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1674992430
Short name T940
Test name
Test status
Simulation time 17579269 ps
CPU time 0.72 seconds
Started Jul 03 05:18:47 PM PDT 24
Finished Jul 03 05:18:48 PM PDT 24
Peak memory 206572 kb
Host smart-af518bb5-0dfe-449d-a0ed-081420904c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674992430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1674992430
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2203446321
Short name T617
Test name
Test status
Simulation time 7914727148 ps
CPU time 9.58 seconds
Started Jul 03 05:18:50 PM PDT 24
Finished Jul 03 05:19:01 PM PDT 24
Peak memory 240932 kb
Host smart-485b9169-49dd-4027-a3fd-fe86dc2648fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203446321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2203446321
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3364568671
Short name T572
Test name
Test status
Simulation time 14908550 ps
CPU time 0.74 seconds
Started Jul 03 05:18:56 PM PDT 24
Finished Jul 03 05:18:57 PM PDT 24
Peak memory 205876 kb
Host smart-52633881-a303-4399-a5b8-0ce8c61fce3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364568671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3364568671
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2177056533
Short name T646
Test name
Test status
Simulation time 212965032 ps
CPU time 2.62 seconds
Started Jul 03 05:18:54 PM PDT 24
Finished Jul 03 05:18:57 PM PDT 24
Peak memory 232616 kb
Host smart-eef5696c-9905-4ab3-9ff3-7a8d9ac3b697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177056533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2177056533
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3469310973
Short name T411
Test name
Test status
Simulation time 56647968 ps
CPU time 0.84 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:18:56 PM PDT 24
Peak memory 206584 kb
Host smart-58534346-3b34-4f3c-ac03-47e502c44789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469310973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3469310973
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3047645635
Short name T435
Test name
Test status
Simulation time 26810999060 ps
CPU time 111.33 seconds
Started Jul 03 05:18:57 PM PDT 24
Finished Jul 03 05:20:49 PM PDT 24
Peak memory 241028 kb
Host smart-79aeac6b-2459-4324-9bca-17b6cb0f716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047645635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3047645635
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1610657051
Short name T194
Test name
Test status
Simulation time 189558555654 ps
CPU time 389.64 seconds
Started Jul 03 05:18:58 PM PDT 24
Finished Jul 03 05:25:29 PM PDT 24
Peak memory 265856 kb
Host smart-b4e58313-4a9f-4541-8079-884c882858c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610657051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1610657051
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.393192758
Short name T505
Test name
Test status
Simulation time 11088299360 ps
CPU time 99.62 seconds
Started Jul 03 05:18:54 PM PDT 24
Finished Jul 03 05:20:34 PM PDT 24
Peak memory 251448 kb
Host smart-2ae63f1e-3f02-4a93-8957-5554839f2586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393192758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.393192758
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1387903693
Short name T567
Test name
Test status
Simulation time 2125000362 ps
CPU time 15.53 seconds
Started Jul 03 05:18:53 PM PDT 24
Finished Jul 03 05:19:08 PM PDT 24
Peak memory 232692 kb
Host smart-91c2a934-235e-45d6-b84a-f5a4f142c284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387903693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1387903693
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3624597186
Short name T576
Test name
Test status
Simulation time 145554530027 ps
CPU time 128.03 seconds
Started Jul 03 05:18:59 PM PDT 24
Finished Jul 03 05:21:08 PM PDT 24
Peak memory 250104 kb
Host smart-bb23713d-1e78-4bb1-bfca-eb20f052d442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624597186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3624597186
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1794606092
Short name T406
Test name
Test status
Simulation time 1754924172 ps
CPU time 5.73 seconds
Started Jul 03 05:18:54 PM PDT 24
Finished Jul 03 05:19:00 PM PDT 24
Peak memory 232688 kb
Host smart-01684d03-cace-481c-82f6-174d7175265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794606092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1794606092
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2032663956
Short name T263
Test name
Test status
Simulation time 2483009511 ps
CPU time 20.58 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:19:17 PM PDT 24
Peak memory 232784 kb
Host smart-44278677-c932-44b2-ba84-e92f5782a08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032663956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2032663956
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3755260586
Short name T966
Test name
Test status
Simulation time 5033327478 ps
CPU time 20.66 seconds
Started Jul 03 05:18:52 PM PDT 24
Finished Jul 03 05:19:13 PM PDT 24
Peak memory 236856 kb
Host smart-c9e03c60-ae00-47aa-8c35-431d9dbbae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755260586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3755260586
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.386117910
Short name T760
Test name
Test status
Simulation time 211146765 ps
CPU time 2.68 seconds
Started Jul 03 05:18:54 PM PDT 24
Finished Jul 03 05:18:57 PM PDT 24
Peak memory 232676 kb
Host smart-8d6d6367-364f-42bb-84a8-5ccd66e8ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386117910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.386117910
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.868559956
Short name T977
Test name
Test status
Simulation time 175941944 ps
CPU time 3.81 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:18:59 PM PDT 24
Peak memory 219196 kb
Host smart-c97aad59-f8e8-451f-a307-60fa130f4c3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=868559956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.868559956
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.793181423
Short name T579
Test name
Test status
Simulation time 181347240 ps
CPU time 1 seconds
Started Jul 03 05:18:54 PM PDT 24
Finished Jul 03 05:18:56 PM PDT 24
Peak memory 215300 kb
Host smart-02d3d604-7b39-4592-9a61-dc36f1ac52b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793181423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.793181423
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.5508803
Short name T681
Test name
Test status
Simulation time 2328017151 ps
CPU time 9.93 seconds
Started Jul 03 05:18:51 PM PDT 24
Finished Jul 03 05:19:01 PM PDT 24
Peak memory 216396 kb
Host smart-3ab06e98-3b27-4723-8161-7ffb8ad2f6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5508803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.5508803
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.744880300
Short name T639
Test name
Test status
Simulation time 26539346778 ps
CPU time 20.8 seconds
Started Jul 03 05:18:52 PM PDT 24
Finished Jul 03 05:19:13 PM PDT 24
Peak memory 216268 kb
Host smart-1ea4342e-7d2c-43c4-97c8-7b1fd01cb67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744880300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.744880300
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2854287317
Short name T644
Test name
Test status
Simulation time 12971914 ps
CPU time 0.75 seconds
Started Jul 03 05:18:52 PM PDT 24
Finished Jul 03 05:18:53 PM PDT 24
Peak memory 205952 kb
Host smart-8afc856f-96bc-49e9-8ff2-b74cc00ecfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854287317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2854287317
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.935829587
Short name T169
Test name
Test status
Simulation time 205758482 ps
CPU time 0.88 seconds
Started Jul 03 05:18:50 PM PDT 24
Finished Jul 03 05:18:51 PM PDT 24
Peak memory 205968 kb
Host smart-0f40db4f-efca-4986-b793-b6622cbf01e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935829587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.935829587
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1690253684
Short name T1002
Test name
Test status
Simulation time 28620542440 ps
CPU time 23.09 seconds
Started Jul 03 05:18:50 PM PDT 24
Finished Jul 03 05:19:13 PM PDT 24
Peak memory 232848 kb
Host smart-8b629ffa-6c34-4e08-85bc-7681ae6a545f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690253684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1690253684
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1376900427
Short name T342
Test name
Test status
Simulation time 38154971 ps
CPU time 0.69 seconds
Started Jul 03 05:19:11 PM PDT 24
Finished Jul 03 05:19:12 PM PDT 24
Peak memory 204988 kb
Host smart-9f1e005a-7da7-4178-8445-79e408f8f2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376900427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1376900427
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3861537033
Short name T390
Test name
Test status
Simulation time 123261760 ps
CPU time 2.12 seconds
Started Jul 03 05:18:56 PM PDT 24
Finished Jul 03 05:18:59 PM PDT 24
Peak memory 224100 kb
Host smart-5ab5f453-8ad2-4269-9823-2fed04ec6688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861537033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3861537033
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.402304399
Short name T563
Test name
Test status
Simulation time 45025487 ps
CPU time 0.77 seconds
Started Jul 03 05:18:54 PM PDT 24
Finished Jul 03 05:18:56 PM PDT 24
Peak memory 205572 kb
Host smart-ea360b2b-f4e0-4775-a4ba-cccffde1e8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402304399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.402304399
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3503355710
Short name T987
Test name
Test status
Simulation time 45467443590 ps
CPU time 344.13 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:24:40 PM PDT 24
Peak memory 257360 kb
Host smart-417d6266-c82f-496b-acc5-83d69af0f932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503355710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3503355710
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.343011184
Short name T630
Test name
Test status
Simulation time 173904875594 ps
CPU time 137.84 seconds
Started Jul 03 05:18:54 PM PDT 24
Finished Jul 03 05:21:12 PM PDT 24
Peak memory 255640 kb
Host smart-783e1f74-9500-46c5-9b17-0ea42d5b1d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343011184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.343011184
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3070546118
Short name T683
Test name
Test status
Simulation time 3585745834 ps
CPU time 60.72 seconds
Started Jul 03 05:18:59 PM PDT 24
Finished Jul 03 05:20:00 PM PDT 24
Peak memory 254312 kb
Host smart-15c6319a-8016-466b-adb6-42a8452e0f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070546118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3070546118
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2033601793
Short name T847
Test name
Test status
Simulation time 4396573005 ps
CPU time 24.34 seconds
Started Jul 03 05:18:57 PM PDT 24
Finished Jul 03 05:19:22 PM PDT 24
Peak memory 234732 kb
Host smart-b40e3ec4-0b9d-41c8-802d-51ff82844da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033601793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2033601793
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1181651720
Short name T651
Test name
Test status
Simulation time 3498355517 ps
CPU time 17.15 seconds
Started Jul 03 05:18:56 PM PDT 24
Finished Jul 03 05:19:14 PM PDT 24
Peak memory 240984 kb
Host smart-53665e9d-8a63-4b12-8e62-a4a2249d8d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181651720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1181651720
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1904016245
Short name T810
Test name
Test status
Simulation time 34712685016 ps
CPU time 25.49 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:19:21 PM PDT 24
Peak memory 232780 kb
Host smart-a65f4ec1-3c34-4944-b08a-234244b48c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904016245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1904016245
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2564842797
Short name T551
Test name
Test status
Simulation time 346125307 ps
CPU time 6.91 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:19:03 PM PDT 24
Peak memory 240564 kb
Host smart-a742bbac-4e86-46f2-93ec-c7bfb40f50db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564842797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2564842797
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.666510497
Short name T256
Test name
Test status
Simulation time 2399334791 ps
CPU time 4.85 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:19:01 PM PDT 24
Peak memory 232752 kb
Host smart-83c9eacb-d2fd-4c6b-8680-bc91ec81379c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666510497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.666510497
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1661290103
Short name T557
Test name
Test status
Simulation time 40523372758 ps
CPU time 26.64 seconds
Started Jul 03 05:18:57 PM PDT 24
Finished Jul 03 05:19:24 PM PDT 24
Peak memory 232800 kb
Host smart-a8fc2112-21e2-4763-a697-4fc5dc648abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661290103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1661290103
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1350507023
Short name T85
Test name
Test status
Simulation time 81509960 ps
CPU time 3.7 seconds
Started Jul 03 05:18:56 PM PDT 24
Finished Jul 03 05:19:01 PM PDT 24
Peak memory 223148 kb
Host smart-7942d717-7ab3-4a98-a90f-68e5b89f7cbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1350507023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1350507023
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3846692214
Short name T537
Test name
Test status
Simulation time 49557456 ps
CPU time 1.1 seconds
Started Jul 03 05:18:58 PM PDT 24
Finished Jul 03 05:19:00 PM PDT 24
Peak memory 207704 kb
Host smart-e5597881-d06f-40e2-9eb1-9c0ff8e1e9c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846692214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3846692214
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3848135973
Short name T796
Test name
Test status
Simulation time 12817033872 ps
CPU time 18.84 seconds
Started Jul 03 05:18:56 PM PDT 24
Finished Jul 03 05:19:15 PM PDT 24
Peak memory 220000 kb
Host smart-a40a7be4-9a23-4485-a28c-a935555f3211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848135973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3848135973
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3090335735
Short name T679
Test name
Test status
Simulation time 1189201443 ps
CPU time 6.18 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:19:02 PM PDT 24
Peak memory 216164 kb
Host smart-afa27dc0-f64f-4a29-ba11-2b0d703fa2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090335735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3090335735
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1508472563
Short name T507
Test name
Test status
Simulation time 13096745 ps
CPU time 0.71 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:18:57 PM PDT 24
Peak memory 205676 kb
Host smart-ec27b56c-a873-45c3-9b76-1595ef72bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508472563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1508472563
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.991282864
Short name T925
Test name
Test status
Simulation time 33843081 ps
CPU time 0.91 seconds
Started Jul 03 05:18:55 PM PDT 24
Finished Jul 03 05:18:56 PM PDT 24
Peak memory 205972 kb
Host smart-362034d8-ac60-46cb-9311-699eeb798e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991282864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.991282864
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3807036350
Short name T391
Test name
Test status
Simulation time 3651895960 ps
CPU time 14.24 seconds
Started Jul 03 05:18:56 PM PDT 24
Finished Jul 03 05:19:11 PM PDT 24
Peak memory 240936 kb
Host smart-17b94db6-8d84-4dd5-aa9c-8d26a0c57f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807036350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3807036350
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1018694763
Short name T642
Test name
Test status
Simulation time 15076318 ps
CPU time 0.76 seconds
Started Jul 03 05:16:55 PM PDT 24
Finished Jul 03 05:16:56 PM PDT 24
Peak memory 204976 kb
Host smart-7de99a0c-482b-41cd-a7d2-1eed220044b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018694763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
018694763
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3212749403
Short name T324
Test name
Test status
Simulation time 525236393 ps
CPU time 2.64 seconds
Started Jul 03 05:16:54 PM PDT 24
Finished Jul 03 05:16:58 PM PDT 24
Peak memory 232380 kb
Host smart-192e5940-be93-4cf1-b50f-e5cc222c4d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212749403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3212749403
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2918479363
Short name T593
Test name
Test status
Simulation time 19988600 ps
CPU time 0.75 seconds
Started Jul 03 05:16:54 PM PDT 24
Finished Jul 03 05:16:55 PM PDT 24
Peak memory 205576 kb
Host smart-a1bb7e89-e314-41a2-af28-af7e24d9b066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918479363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2918479363
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3005773551
Short name T43
Test name
Test status
Simulation time 10437070620 ps
CPU time 54.82 seconds
Started Jul 03 05:16:54 PM PDT 24
Finished Jul 03 05:17:50 PM PDT 24
Peak memory 252116 kb
Host smart-3b329f42-4b2c-4f8c-a2ed-42a5e89f0d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005773551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3005773551
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.86728678
Short name T199
Test name
Test status
Simulation time 1981874305 ps
CPU time 38.27 seconds
Started Jul 03 05:16:56 PM PDT 24
Finished Jul 03 05:17:35 PM PDT 24
Peak memory 252184 kb
Host smart-47371ae8-6a6d-4501-897b-28d3f185f83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86728678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.86728678
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3535603652
Short name T54
Test name
Test status
Simulation time 2073425923 ps
CPU time 20.55 seconds
Started Jul 03 05:16:55 PM PDT 24
Finished Jul 03 05:17:17 PM PDT 24
Peak memory 217604 kb
Host smart-0d563ec9-8247-4abb-b4cf-9a12718b0c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535603652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3535603652
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2557618457
Short name T380
Test name
Test status
Simulation time 594710338 ps
CPU time 3.58 seconds
Started Jul 03 05:16:54 PM PDT 24
Finished Jul 03 05:16:59 PM PDT 24
Peak memory 224364 kb
Host smart-626ac253-bcb9-4742-801a-c248730cccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557618457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2557618457
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.753747812
Short name T470
Test name
Test status
Simulation time 20213776696 ps
CPU time 66.22 seconds
Started Jul 03 05:16:54 PM PDT 24
Finished Jul 03 05:18:01 PM PDT 24
Peak memory 249172 kb
Host smart-2a09bcb2-0e04-458c-8fe1-9af0dca3a91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753747812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
753747812
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2669971244
Short name T407
Test name
Test status
Simulation time 897283610 ps
CPU time 9.52 seconds
Started Jul 03 05:16:55 PM PDT 24
Finished Jul 03 05:17:05 PM PDT 24
Peak memory 224508 kb
Host smart-b20dc73f-6f7e-400d-b023-9157538c324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669971244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2669971244
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1527407858
Short name T827
Test name
Test status
Simulation time 2973611936 ps
CPU time 22.82 seconds
Started Jul 03 05:16:58 PM PDT 24
Finished Jul 03 05:17:21 PM PDT 24
Peak memory 240760 kb
Host smart-6c2cd7d3-b69e-4d9c-bd09-9e83e7062d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527407858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1527407858
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1243995916
Short name T270
Test name
Test status
Simulation time 4014126847 ps
CPU time 7.14 seconds
Started Jul 03 05:16:56 PM PDT 24
Finished Jul 03 05:17:03 PM PDT 24
Peak memory 237900 kb
Host smart-232da599-edf7-4095-8482-b9f4a7557dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243995916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1243995916
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.229555392
Short name T629
Test name
Test status
Simulation time 6414901205 ps
CPU time 11.63 seconds
Started Jul 03 05:16:56 PM PDT 24
Finished Jul 03 05:17:08 PM PDT 24
Peak memory 248256 kb
Host smart-c973b0fb-51b3-440e-91a7-d5180d3d8f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229555392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.229555392
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1093855921
Short name T37
Test name
Test status
Simulation time 7359691353 ps
CPU time 9.9 seconds
Started Jul 03 05:16:54 PM PDT 24
Finished Jul 03 05:17:04 PM PDT 24
Peak memory 223328 kb
Host smart-a4ce0a69-3ea4-4d17-b6b1-3304252e072d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1093855921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1093855921
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2545950275
Short name T69
Test name
Test status
Simulation time 61854864 ps
CPU time 0.98 seconds
Started Jul 03 05:16:55 PM PDT 24
Finished Jul 03 05:16:57 PM PDT 24
Peak memory 235572 kb
Host smart-09de52ec-7e2b-40b6-8185-4f0b2d4f2730
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545950275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2545950275
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.507104953
Short name T305
Test name
Test status
Simulation time 6657746861 ps
CPU time 36.2 seconds
Started Jul 03 05:16:55 PM PDT 24
Finished Jul 03 05:17:32 PM PDT 24
Peak memory 219920 kb
Host smart-086c7543-00c1-454a-92e4-681a18568cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507104953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.507104953
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.281781108
Short name T555
Test name
Test status
Simulation time 124643445 ps
CPU time 1.13 seconds
Started Jul 03 05:16:57 PM PDT 24
Finished Jul 03 05:16:58 PM PDT 24
Peak memory 207204 kb
Host smart-f511770c-5741-49d6-8abb-96c2d56871fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281781108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.281781108
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3010125164
Short name T383
Test name
Test status
Simulation time 224638168 ps
CPU time 1.3 seconds
Started Jul 03 05:16:53 PM PDT 24
Finished Jul 03 05:16:55 PM PDT 24
Peak memory 216168 kb
Host smart-b478580f-7f35-49f1-808f-8e95f933f911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010125164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3010125164
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1408943179
Short name T815
Test name
Test status
Simulation time 10678472 ps
CPU time 0.71 seconds
Started Jul 03 05:17:02 PM PDT 24
Finished Jul 03 05:17:03 PM PDT 24
Peak memory 205600 kb
Host smart-97f25ad6-13d6-4102-a972-7ae84d747ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408943179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1408943179
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2694300015
Short name T10
Test name
Test status
Simulation time 367863570 ps
CPU time 4.23 seconds
Started Jul 03 05:16:55 PM PDT 24
Finished Jul 03 05:17:00 PM PDT 24
Peak memory 224492 kb
Host smart-0671e0ac-75b1-4438-906c-af0c1c372a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694300015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2694300015
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1930445238
Short name T699
Test name
Test status
Simulation time 20294561 ps
CPU time 0.7 seconds
Started Jul 03 05:19:05 PM PDT 24
Finished Jul 03 05:19:06 PM PDT 24
Peak memory 204940 kb
Host smart-863ab80e-a6cf-4aba-b139-26df184db63b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930445238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1930445238
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.717347160
Short name T185
Test name
Test status
Simulation time 317477373 ps
CPU time 2.84 seconds
Started Jul 03 05:19:05 PM PDT 24
Finished Jul 03 05:19:09 PM PDT 24
Peak memory 224372 kb
Host smart-39ec9af0-4e56-44e7-bf42-3a5bcefb1f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717347160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.717347160
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.668632105
Short name T321
Test name
Test status
Simulation time 15413784 ps
CPU time 0.75 seconds
Started Jul 03 05:19:04 PM PDT 24
Finished Jul 03 05:19:06 PM PDT 24
Peak memory 205916 kb
Host smart-5c374401-c245-4937-a215-e85fdb140c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668632105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.668632105
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2205592933
Short name T668
Test name
Test status
Simulation time 2783507972 ps
CPU time 32.42 seconds
Started Jul 03 05:19:01 PM PDT 24
Finished Jul 03 05:19:34 PM PDT 24
Peak memory 238952 kb
Host smart-1326a31c-f836-4171-80dd-b9adbc07b4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205592933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2205592933
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2215453706
Short name T510
Test name
Test status
Simulation time 25297624860 ps
CPU time 30.65 seconds
Started Jul 03 05:19:01 PM PDT 24
Finished Jul 03 05:19:33 PM PDT 24
Peak memory 224516 kb
Host smart-ba3b8e7f-1e6c-46f2-986f-21bb1ddc7130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215453706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2215453706
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3704459224
Short name T127
Test name
Test status
Simulation time 10309687992 ps
CPU time 19.54 seconds
Started Jul 03 05:19:05 PM PDT 24
Finished Jul 03 05:19:25 PM PDT 24
Peak memory 217616 kb
Host smart-0756f99b-9418-4418-8b3c-2969e0fe6e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704459224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3704459224
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.51266271
Short name T975
Test name
Test status
Simulation time 4957554331 ps
CPU time 22.29 seconds
Started Jul 03 05:19:01 PM PDT 24
Finished Jul 03 05:19:24 PM PDT 24
Peak memory 232780 kb
Host smart-8a9c2581-5222-42c4-a056-05e7f240db98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51266271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.51266271
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2772729469
Short name T944
Test name
Test status
Simulation time 75225052790 ps
CPU time 107.22 seconds
Started Jul 03 05:18:56 PM PDT 24
Finished Jul 03 05:20:45 PM PDT 24
Peak memory 249396 kb
Host smart-ab163d39-fe09-4bdf-98af-4a62d6f39285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772729469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2772729469
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.614274985
Short name T221
Test name
Test status
Simulation time 250314827 ps
CPU time 5.9 seconds
Started Jul 03 05:19:00 PM PDT 24
Finished Jul 03 05:19:06 PM PDT 24
Peak memory 232644 kb
Host smart-577c012e-08e4-4062-a1b0-265a13d82e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614274985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.614274985
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3277646612
Short name T623
Test name
Test status
Simulation time 882731110 ps
CPU time 9.33 seconds
Started Jul 03 05:18:59 PM PDT 24
Finished Jul 03 05:19:09 PM PDT 24
Peak memory 232556 kb
Host smart-e9812743-b0c1-42d3-9938-0cfb8453a1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277646612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3277646612
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3416502627
Short name T906
Test name
Test status
Simulation time 137892566 ps
CPU time 2.69 seconds
Started Jul 03 05:19:02 PM PDT 24
Finished Jul 03 05:19:06 PM PDT 24
Peak memory 232668 kb
Host smart-d1a335b6-f045-472f-8292-17c82fe34ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416502627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3416502627
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.693039632
Short name T490
Test name
Test status
Simulation time 4642664175 ps
CPU time 6.36 seconds
Started Jul 03 05:18:57 PM PDT 24
Finished Jul 03 05:19:04 PM PDT 24
Peak memory 232784 kb
Host smart-e43a8ff4-f711-49b6-8f26-39da96a83d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693039632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.693039632
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3904995646
Short name T145
Test name
Test status
Simulation time 462934670 ps
CPU time 4.53 seconds
Started Jul 03 05:18:59 PM PDT 24
Finished Jul 03 05:19:04 PM PDT 24
Peak memory 222624 kb
Host smart-27422ebf-aec3-4edf-9613-b701b07dd8e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3904995646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3904995646
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3861472625
Short name T17
Test name
Test status
Simulation time 10044946286 ps
CPU time 117.9 seconds
Started Jul 03 05:19:00 PM PDT 24
Finished Jul 03 05:20:59 PM PDT 24
Peak memory 255744 kb
Host smart-48b38f32-0186-4631-b083-e03176a98b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861472625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3861472625
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.112879743
Short name T627
Test name
Test status
Simulation time 1738379896 ps
CPU time 6.06 seconds
Started Jul 03 05:19:02 PM PDT 24
Finished Jul 03 05:19:09 PM PDT 24
Peak memory 216304 kb
Host smart-915ec8dc-d9d4-470e-b464-743c3bb3885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112879743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.112879743
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1364755655
Short name T858
Test name
Test status
Simulation time 1819941792 ps
CPU time 3.78 seconds
Started Jul 03 05:18:57 PM PDT 24
Finished Jul 03 05:19:02 PM PDT 24
Peak memory 216268 kb
Host smart-480fb6f7-751e-46a4-a10a-4d960cbc0aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364755655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1364755655
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3155924502
Short name T611
Test name
Test status
Simulation time 32899942 ps
CPU time 1.56 seconds
Started Jul 03 05:19:06 PM PDT 24
Finished Jul 03 05:19:08 PM PDT 24
Peak memory 216200 kb
Host smart-f7ed8ae7-0c80-4eeb-9bd4-ede83241a91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155924502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3155924502
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3794919488
Short name T388
Test name
Test status
Simulation time 79701978 ps
CPU time 0.96 seconds
Started Jul 03 05:18:58 PM PDT 24
Finished Jul 03 05:19:00 PM PDT 24
Peak memory 206996 kb
Host smart-185d0bd3-0cc7-4518-931b-d7500b43bfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794919488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3794919488
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1568476171
Short name T805
Test name
Test status
Simulation time 213731252 ps
CPU time 3.01 seconds
Started Jul 03 05:19:02 PM PDT 24
Finished Jul 03 05:19:06 PM PDT 24
Peak memory 232716 kb
Host smart-d053b0f6-4aa1-4fbc-b172-df54b626bf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568476171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1568476171
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.136437308
Short name T880
Test name
Test status
Simulation time 38088654 ps
CPU time 0.72 seconds
Started Jul 03 05:19:03 PM PDT 24
Finished Jul 03 05:19:05 PM PDT 24
Peak memory 205500 kb
Host smart-09ed0c89-7ffd-4a91-aeb8-5d27a76811d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136437308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.136437308
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.596965481
Short name T452
Test name
Test status
Simulation time 46751514 ps
CPU time 2.52 seconds
Started Jul 03 05:19:01 PM PDT 24
Finished Jul 03 05:19:05 PM PDT 24
Peak memory 232648 kb
Host smart-e423698d-4fe8-4d63-825f-09f6540c5c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596965481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.596965481
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3192387688
Short name T462
Test name
Test status
Simulation time 26165005 ps
CPU time 0.79 seconds
Started Jul 03 05:19:04 PM PDT 24
Finished Jul 03 05:19:06 PM PDT 24
Peak memory 205568 kb
Host smart-bdc23022-ff45-4ede-9f9c-1127ec40df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192387688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3192387688
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2654974626
Short name T731
Test name
Test status
Simulation time 144870036503 ps
CPU time 119.73 seconds
Started Jul 03 05:19:02 PM PDT 24
Finished Jul 03 05:21:03 PM PDT 24
Peak memory 257400 kb
Host smart-565d9bef-5630-4511-ad5f-b450a8b7eced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654974626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2654974626
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2598239090
Short name T698
Test name
Test status
Simulation time 30708312326 ps
CPU time 63.19 seconds
Started Jul 03 05:19:02 PM PDT 24
Finished Jul 03 05:20:06 PM PDT 24
Peak memory 240708 kb
Host smart-eece1f9d-9afc-48e5-8512-c80a84b38e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598239090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2598239090
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3955481068
Short name T27
Test name
Test status
Simulation time 36770744786 ps
CPU time 80.37 seconds
Started Jul 03 05:19:03 PM PDT 24
Finished Jul 03 05:20:24 PM PDT 24
Peak memory 257440 kb
Host smart-01c06800-06a8-4bb2-a1d4-ff1874fdc6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955481068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3955481068
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3657802384
Short name T890
Test name
Test status
Simulation time 1710606298 ps
CPU time 12.74 seconds
Started Jul 03 05:19:01 PM PDT 24
Finished Jul 03 05:19:15 PM PDT 24
Peak memory 232652 kb
Host smart-cc33f681-0fdc-4c6b-91d2-0b5df54821ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657802384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3657802384
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.203004518
Short name T163
Test name
Test status
Simulation time 164109857 ps
CPU time 0.73 seconds
Started Jul 03 05:19:00 PM PDT 24
Finished Jul 03 05:19:02 PM PDT 24
Peak memory 215748 kb
Host smart-09a1c09f-6270-41ab-8781-f530098ba67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203004518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.203004518
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1925827873
Short name T728
Test name
Test status
Simulation time 976521633 ps
CPU time 6.67 seconds
Started Jul 03 05:19:03 PM PDT 24
Finished Jul 03 05:19:10 PM PDT 24
Peak memory 227012 kb
Host smart-3f27569f-1a69-404b-ad0b-49a5438aa8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925827873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1925827873
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2958106938
Short name T905
Test name
Test status
Simulation time 292380328 ps
CPU time 7.18 seconds
Started Jul 03 05:19:02 PM PDT 24
Finished Jul 03 05:19:10 PM PDT 24
Peak memory 227104 kb
Host smart-ac60a9a3-1e9f-415d-818d-428c23fbd5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958106938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2958106938
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4102545231
Short name T237
Test name
Test status
Simulation time 395972823 ps
CPU time 6.71 seconds
Started Jul 03 05:19:05 PM PDT 24
Finished Jul 03 05:19:13 PM PDT 24
Peak memory 232724 kb
Host smart-99350194-521f-488c-b400-6c7b34659287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102545231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4102545231
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3694056650
Short name T464
Test name
Test status
Simulation time 74576318 ps
CPU time 2.28 seconds
Started Jul 03 05:19:02 PM PDT 24
Finished Jul 03 05:19:05 PM PDT 24
Peak memory 224144 kb
Host smart-af19e16e-b08f-4660-bffc-2d7ae6afaf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694056650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3694056650
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3424814353
Short name T413
Test name
Test status
Simulation time 1588528318 ps
CPU time 7.57 seconds
Started Jul 03 05:19:02 PM PDT 24
Finished Jul 03 05:19:11 PM PDT 24
Peak memory 219192 kb
Host smart-bde9f97a-0e9d-436c-ac9c-5d40d17876f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3424814353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3424814353
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.829194187
Short name T754
Test name
Test status
Simulation time 153735104 ps
CPU time 1.21 seconds
Started Jul 03 05:19:05 PM PDT 24
Finished Jul 03 05:19:06 PM PDT 24
Peak memory 206888 kb
Host smart-67b4f39d-f439-454e-b059-e4d48a845b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829194187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.829194187
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.735262511
Short name T395
Test name
Test status
Simulation time 25525834911 ps
CPU time 35.14 seconds
Started Jul 03 05:19:05 PM PDT 24
Finished Jul 03 05:19:40 PM PDT 24
Peak memory 216352 kb
Host smart-816c51bb-0ce6-48ed-9a20-7308e06b82b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735262511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.735262511
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2453894877
Short name T992
Test name
Test status
Simulation time 1929326043 ps
CPU time 8.56 seconds
Started Jul 03 05:19:00 PM PDT 24
Finished Jul 03 05:19:09 PM PDT 24
Peak memory 216252 kb
Host smart-52e48fdd-e7ea-4725-bc64-653dbaa334d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453894877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2453894877
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2333738298
Short name T369
Test name
Test status
Simulation time 39935587 ps
CPU time 0.97 seconds
Started Jul 03 05:19:03 PM PDT 24
Finished Jul 03 05:19:05 PM PDT 24
Peak memory 207144 kb
Host smart-23814fa3-5898-4f84-8da3-e94740a42358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333738298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2333738298
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3546396029
Short name T594
Test name
Test status
Simulation time 363971891 ps
CPU time 0.84 seconds
Started Jul 03 05:19:02 PM PDT 24
Finished Jul 03 05:19:03 PM PDT 24
Peak memory 205964 kb
Host smart-4532b5f9-6929-4e36-b538-64529391fbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546396029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3546396029
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3547922633
Short name T394
Test name
Test status
Simulation time 802477567 ps
CPU time 6.05 seconds
Started Jul 03 05:19:01 PM PDT 24
Finished Jul 03 05:19:08 PM PDT 24
Peak memory 240200 kb
Host smart-86e7d3ed-d581-4d27-8195-0c126d63c51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547922633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3547922633
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1399595143
Short name T545
Test name
Test status
Simulation time 32491025 ps
CPU time 0.7 seconds
Started Jul 03 05:19:13 PM PDT 24
Finished Jul 03 05:19:14 PM PDT 24
Peak memory 204988 kb
Host smart-06bb6187-c06a-4276-bb26-72537ae0d895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399595143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1399595143
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2845436632
Short name T829
Test name
Test status
Simulation time 249752027 ps
CPU time 4.71 seconds
Started Jul 03 05:19:12 PM PDT 24
Finished Jul 03 05:19:17 PM PDT 24
Peak memory 232668 kb
Host smart-8579464c-7d90-446f-9958-0e6904a910f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845436632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2845436632
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2795331847
Short name T591
Test name
Test status
Simulation time 68593939 ps
CPU time 0.79 seconds
Started Jul 03 05:19:02 PM PDT 24
Finished Jul 03 05:19:04 PM PDT 24
Peak memory 205600 kb
Host smart-e8a9d631-fbe8-4e8e-8820-2aa95ac3df97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795331847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2795331847
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.121857151
Short name T834
Test name
Test status
Simulation time 22162716 ps
CPU time 0.8 seconds
Started Jul 03 05:19:07 PM PDT 24
Finished Jul 03 05:19:08 PM PDT 24
Peak memory 215832 kb
Host smart-eaa57387-7082-4909-afee-56c8e0bc0dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121857151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.121857151
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1218712431
Short name T723
Test name
Test status
Simulation time 1617745533 ps
CPU time 25.39 seconds
Started Jul 03 05:19:05 PM PDT 24
Finished Jul 03 05:19:31 PM PDT 24
Peak memory 224544 kb
Host smart-39ffbfa8-cdee-4ace-8acd-275a08582bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218712431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1218712431
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2048514692
Short name T938
Test name
Test status
Simulation time 27268915054 ps
CPU time 262.62 seconds
Started Jul 03 05:19:06 PM PDT 24
Finished Jul 03 05:23:29 PM PDT 24
Peak memory 254148 kb
Host smart-3e918c3e-7331-411b-bc63-b1496f138a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048514692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2048514692
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2824750656
Short name T393
Test name
Test status
Simulation time 458624796 ps
CPU time 3.74 seconds
Started Jul 03 05:19:08 PM PDT 24
Finished Jul 03 05:19:12 PM PDT 24
Peak memory 224440 kb
Host smart-930ba23a-9f69-4a38-8306-9b4277da2096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824750656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2824750656
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3348885270
Short name T193
Test name
Test status
Simulation time 98815611252 ps
CPU time 262.78 seconds
Started Jul 03 05:19:08 PM PDT 24
Finished Jul 03 05:23:32 PM PDT 24
Peak memory 255952 kb
Host smart-6b2bd8f5-e7ce-4e4a-b899-3ddacef74997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348885270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3348885270
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3632766930
Short name T531
Test name
Test status
Simulation time 546335257 ps
CPU time 3.04 seconds
Started Jul 03 05:19:05 PM PDT 24
Finished Jul 03 05:19:08 PM PDT 24
Peak memory 218832 kb
Host smart-f7d6dd5f-4eff-4abe-b11b-077cc1db97c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632766930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3632766930
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1971101088
Short name T475
Test name
Test status
Simulation time 1447010765 ps
CPU time 7.46 seconds
Started Jul 03 05:19:06 PM PDT 24
Finished Jul 03 05:19:14 PM PDT 24
Peak memory 232652 kb
Host smart-a5951578-96c2-416f-98b7-045559276e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971101088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1971101088
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.996226524
Short name T569
Test name
Test status
Simulation time 6699858528 ps
CPU time 11.24 seconds
Started Jul 03 05:19:06 PM PDT 24
Finished Jul 03 05:19:18 PM PDT 24
Peak memory 224592 kb
Host smart-679edc49-2ad3-4178-89b9-8ec99e2353d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996226524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.996226524
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1148033679
Short name T248
Test name
Test status
Simulation time 1036870073 ps
CPU time 8.02 seconds
Started Jul 03 05:19:06 PM PDT 24
Finished Jul 03 05:19:14 PM PDT 24
Peak memory 224472 kb
Host smart-289b20b0-0643-4444-be12-22f5cbe1c3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148033679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1148033679
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3861088722
Short name T892
Test name
Test status
Simulation time 1302663033 ps
CPU time 8.32 seconds
Started Jul 03 05:19:09 PM PDT 24
Finished Jul 03 05:19:18 PM PDT 24
Peak memory 218844 kb
Host smart-85e8540e-07d2-4937-a7b7-19bfcf05f093
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3861088722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3861088722
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1419193726
Short name T156
Test name
Test status
Simulation time 58090827054 ps
CPU time 432.2 seconds
Started Jul 03 05:19:09 PM PDT 24
Finished Jul 03 05:26:21 PM PDT 24
Peak memory 267960 kb
Host smart-c82782a8-38d1-4043-b175-33601fcb21c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419193726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1419193726
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3315556008
Short name T500
Test name
Test status
Simulation time 6057801309 ps
CPU time 22.25 seconds
Started Jul 03 05:19:09 PM PDT 24
Finished Jul 03 05:19:32 PM PDT 24
Peak memory 220112 kb
Host smart-6f6851d9-1c78-4ec4-99d9-73e7d7560320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315556008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3315556008
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1589063511
Short name T553
Test name
Test status
Simulation time 96502778 ps
CPU time 1.25 seconds
Started Jul 03 05:19:04 PM PDT 24
Finished Jul 03 05:19:05 PM PDT 24
Peak memory 216284 kb
Host smart-02981f53-226e-47ac-8d1b-c8945728b594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589063511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1589063511
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2927916938
Short name T855
Test name
Test status
Simulation time 284302022 ps
CPU time 0.9 seconds
Started Jul 03 05:19:09 PM PDT 24
Finished Jul 03 05:19:10 PM PDT 24
Peak memory 206372 kb
Host smart-f825251d-6918-4b67-8ed7-d956fa4d00b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927916938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2927916938
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3881401483
Short name T469
Test name
Test status
Simulation time 879441560 ps
CPU time 4.68 seconds
Started Jul 03 05:19:06 PM PDT 24
Finished Jul 03 05:19:11 PM PDT 24
Peak memory 240124 kb
Host smart-99146cd6-45da-40be-a18c-7db5d7df6ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881401483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3881401483
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2356112302
Short name T62
Test name
Test status
Simulation time 12077781 ps
CPU time 0.69 seconds
Started Jul 03 05:19:10 PM PDT 24
Finished Jul 03 05:19:11 PM PDT 24
Peak memory 204928 kb
Host smart-0c92803f-634d-4cca-8fec-e0cf58721125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356112302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2356112302
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3079536409
Short name T454
Test name
Test status
Simulation time 77337173 ps
CPU time 2.56 seconds
Started Jul 03 05:19:12 PM PDT 24
Finished Jul 03 05:19:15 PM PDT 24
Peak memory 232652 kb
Host smart-a64e12ae-a3a2-47cc-a56c-e0f8a787e95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079536409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3079536409
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2073212539
Short name T60
Test name
Test status
Simulation time 41200333 ps
CPU time 0.75 seconds
Started Jul 03 05:19:07 PM PDT 24
Finished Jul 03 05:19:08 PM PDT 24
Peak memory 205604 kb
Host smart-64cdb5c6-2bd7-4992-9cf4-44df2041513e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073212539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2073212539
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1782821715
Short name T131
Test name
Test status
Simulation time 121445123131 ps
CPU time 148.01 seconds
Started Jul 03 05:19:12 PM PDT 24
Finished Jul 03 05:21:41 PM PDT 24
Peak memory 255188 kb
Host smart-2ab6cb2e-c8d5-4e93-9d73-02363e37551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782821715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1782821715
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1069870437
Short name T466
Test name
Test status
Simulation time 11543657122 ps
CPU time 103.55 seconds
Started Jul 03 05:19:09 PM PDT 24
Finished Jul 03 05:20:53 PM PDT 24
Peak memory 254000 kb
Host smart-59d56620-d2c4-4c9e-8d59-f0b255706b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069870437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1069870437
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.566737067
Short name T497
Test name
Test status
Simulation time 1359187270 ps
CPU time 7.57 seconds
Started Jul 03 05:19:10 PM PDT 24
Finished Jul 03 05:19:18 PM PDT 24
Peak memory 232652 kb
Host smart-fbecc18c-dd77-428d-af62-cb0373f2d850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566737067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.566737067
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.965972785
Short name T942
Test name
Test status
Simulation time 2664553639 ps
CPU time 6.72 seconds
Started Jul 03 05:19:06 PM PDT 24
Finished Jul 03 05:19:14 PM PDT 24
Peak memory 232796 kb
Host smart-992ffe3b-f496-4a97-bcb3-5adb4d1488e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965972785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.965972785
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.463233889
Short name T318
Test name
Test status
Simulation time 409132866 ps
CPU time 2.23 seconds
Started Jul 03 05:19:10 PM PDT 24
Finished Jul 03 05:19:12 PM PDT 24
Peak memory 223344 kb
Host smart-3a94236d-e375-4f68-bd7f-59aa11ce9921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463233889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.463233889
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2318901892
Short name T264
Test name
Test status
Simulation time 152399695868 ps
CPU time 53.01 seconds
Started Jul 03 05:19:04 PM PDT 24
Finished Jul 03 05:19:57 PM PDT 24
Peak memory 249192 kb
Host smart-1473e419-406f-42a3-bcc0-bc2984c40223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318901892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2318901892
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4093068976
Short name T59
Test name
Test status
Simulation time 8840055821 ps
CPU time 6.76 seconds
Started Jul 03 05:19:09 PM PDT 24
Finished Jul 03 05:19:16 PM PDT 24
Peak memory 224492 kb
Host smart-aeb11d76-350b-4e90-ae85-9c84080e9292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093068976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4093068976
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2158509074
Short name T141
Test name
Test status
Simulation time 110562205 ps
CPU time 4.29 seconds
Started Jul 03 05:19:12 PM PDT 24
Finished Jul 03 05:19:17 PM PDT 24
Peak memory 222776 kb
Host smart-a5b7bd5b-d16e-43c3-87f6-e6285132499d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2158509074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2158509074
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1863999041
Short name T637
Test name
Test status
Simulation time 65580662681 ps
CPU time 186.94 seconds
Started Jul 03 05:19:11 PM PDT 24
Finished Jul 03 05:22:19 PM PDT 24
Peak memory 257448 kb
Host smart-dd7acfe8-9066-4d1a-b864-6562dce99bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863999041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1863999041
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.409435053
Short name T647
Test name
Test status
Simulation time 1873917290 ps
CPU time 19.94 seconds
Started Jul 03 05:19:07 PM PDT 24
Finished Jul 03 05:19:28 PM PDT 24
Peak memory 216260 kb
Host smart-cf7d1c93-0bd7-49c5-8aa7-5765ba9e7b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409435053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.409435053
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1420536024
Short name T844
Test name
Test status
Simulation time 3989989666 ps
CPU time 5.02 seconds
Started Jul 03 05:19:12 PM PDT 24
Finished Jul 03 05:19:17 PM PDT 24
Peak memory 216336 kb
Host smart-aecadcdd-500e-488c-9f75-495ab606bc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420536024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1420536024
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1875792630
Short name T883
Test name
Test status
Simulation time 70828692 ps
CPU time 1.33 seconds
Started Jul 03 05:19:09 PM PDT 24
Finished Jul 03 05:19:10 PM PDT 24
Peak memory 216192 kb
Host smart-53c601f9-c27b-4d4d-bcb5-15673ff847ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875792630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1875792630
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.575309078
Short name T314
Test name
Test status
Simulation time 37327548 ps
CPU time 0.9 seconds
Started Jul 03 05:19:07 PM PDT 24
Finished Jul 03 05:19:08 PM PDT 24
Peak memory 207028 kb
Host smart-8310125a-1c7d-4a56-9526-cb9013b1ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575309078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.575309078
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2789706765
Short name T198
Test name
Test status
Simulation time 8049083345 ps
CPU time 30.89 seconds
Started Jul 03 05:19:06 PM PDT 24
Finished Jul 03 05:19:38 PM PDT 24
Peak memory 249056 kb
Host smart-e054dbfa-8598-48fd-8ea5-4524c86c24ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789706765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2789706765
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.869130752
Short name T335
Test name
Test status
Simulation time 52330188 ps
CPU time 0.67 seconds
Started Jul 03 05:19:15 PM PDT 24
Finished Jul 03 05:19:16 PM PDT 24
Peak memory 205520 kb
Host smart-16c26311-22aa-44d8-99d5-222b928a2fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869130752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.869130752
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4017873475
Short name T713
Test name
Test status
Simulation time 273866199 ps
CPU time 5.38 seconds
Started Jul 03 05:19:15 PM PDT 24
Finished Jul 03 05:19:20 PM PDT 24
Peak memory 224460 kb
Host smart-a9d176b2-bc84-441e-8172-173b6476fc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017873475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4017873475
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.103718454
Short name T504
Test name
Test status
Simulation time 53412058 ps
CPU time 0.76 seconds
Started Jul 03 05:19:12 PM PDT 24
Finished Jul 03 05:19:13 PM PDT 24
Peak memory 205920 kb
Host smart-aa7e5eac-f33a-4b83-8175-0c64b876e0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103718454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.103718454
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1581269035
Short name T967
Test name
Test status
Simulation time 16493153935 ps
CPU time 99.76 seconds
Started Jul 03 05:19:18 PM PDT 24
Finished Jul 03 05:20:58 PM PDT 24
Peak memory 250232 kb
Host smart-1962bf39-fe9b-4df3-b9ba-2222c2bbd96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581269035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1581269035
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2784774394
Short name T958
Test name
Test status
Simulation time 2983882349 ps
CPU time 9.33 seconds
Started Jul 03 05:19:13 PM PDT 24
Finished Jul 03 05:19:23 PM PDT 24
Peak memory 217496 kb
Host smart-f08eb9f2-6f9b-4caf-ba01-4c8f007e655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784774394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2784774394
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.698451075
Short name T368
Test name
Test status
Simulation time 29384832925 ps
CPU time 16.87 seconds
Started Jul 03 05:19:14 PM PDT 24
Finished Jul 03 05:19:31 PM PDT 24
Peak memory 217708 kb
Host smart-217f3b33-6971-4b3e-9b09-2b5c629292b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698451075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.698451075
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.203083421
Short name T578
Test name
Test status
Simulation time 13291313485 ps
CPU time 92.73 seconds
Started Jul 03 05:19:16 PM PDT 24
Finished Jul 03 05:20:49 PM PDT 24
Peak memory 253344 kb
Host smart-4bd94239-71ff-4868-858c-26f401fa27b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203083421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.203083421
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.161637777
Short name T284
Test name
Test status
Simulation time 37713914671 ps
CPU time 273.16 seconds
Started Jul 03 05:19:16 PM PDT 24
Finished Jul 03 05:23:50 PM PDT 24
Peak memory 254020 kb
Host smart-af216cd4-0788-4786-8c80-ba4346b47c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161637777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.161637777
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3628189917
Short name T232
Test name
Test status
Simulation time 8644258353 ps
CPU time 23.81 seconds
Started Jul 03 05:19:08 PM PDT 24
Finished Jul 03 05:19:32 PM PDT 24
Peak memory 232720 kb
Host smart-7dc4be58-9b3a-4e21-806f-e06897593c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628189917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3628189917
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2921032834
Short name T667
Test name
Test status
Simulation time 1753713757 ps
CPU time 5.47 seconds
Started Jul 03 05:19:11 PM PDT 24
Finished Jul 03 05:19:17 PM PDT 24
Peak memory 232692 kb
Host smart-4dfc1098-65a7-4174-a298-f8d5720feeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921032834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2921032834
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3708037191
Short name T795
Test name
Test status
Simulation time 863780562 ps
CPU time 9.11 seconds
Started Jul 03 05:19:12 PM PDT 24
Finished Jul 03 05:19:21 PM PDT 24
Peak memory 232700 kb
Host smart-07f1de6b-e038-42ba-9d7a-28df79774dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708037191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3708037191
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3688309548
Short name T956
Test name
Test status
Simulation time 40475797163 ps
CPU time 30.57 seconds
Started Jul 03 05:19:11 PM PDT 24
Finished Jul 03 05:19:42 PM PDT 24
Peak memory 248388 kb
Host smart-4c68fff4-89cc-4eea-9f0f-501efe83669a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688309548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3688309548
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2221624696
Short name T592
Test name
Test status
Simulation time 62311444 ps
CPU time 3.14 seconds
Started Jul 03 05:19:16 PM PDT 24
Finished Jul 03 05:19:19 PM PDT 24
Peak memory 219100 kb
Host smart-f81d3910-77b3-4869-9b2d-548db91bf31b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2221624696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2221624696
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3512112167
Short name T6
Test name
Test status
Simulation time 12467166932 ps
CPU time 73.52 seconds
Started Jul 03 05:19:15 PM PDT 24
Finished Jul 03 05:20:29 PM PDT 24
Peak memory 253216 kb
Host smart-f98ce9f9-0559-4ed9-b199-32d8f8c55b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512112167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3512112167
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2058947986
Short name T421
Test name
Test status
Simulation time 1866662723 ps
CPU time 24.26 seconds
Started Jul 03 05:19:12 PM PDT 24
Finished Jul 03 05:19:36 PM PDT 24
Peak memory 219656 kb
Host smart-995db6d0-26dc-4f1d-a825-fe746050955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058947986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2058947986
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3354604040
Short name T582
Test name
Test status
Simulation time 3107257170 ps
CPU time 5.47 seconds
Started Jul 03 05:19:11 PM PDT 24
Finished Jul 03 05:19:17 PM PDT 24
Peak memory 216296 kb
Host smart-44b8c114-d3d6-4ec7-9ec1-20d39547ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354604040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3354604040
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.188398523
Short name T52
Test name
Test status
Simulation time 515120819 ps
CPU time 2.9 seconds
Started Jul 03 05:19:11 PM PDT 24
Finished Jul 03 05:19:14 PM PDT 24
Peak memory 216184 kb
Host smart-005dbd99-6155-421e-87a8-587352321e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188398523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.188398523
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3896311270
Short name T386
Test name
Test status
Simulation time 38943208 ps
CPU time 0.73 seconds
Started Jul 03 05:19:10 PM PDT 24
Finished Jul 03 05:19:11 PM PDT 24
Peak memory 205984 kb
Host smart-ea5e6006-cc7f-4033-823f-6b59450ee707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896311270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3896311270
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3570505774
Short name T785
Test name
Test status
Simulation time 549018015 ps
CPU time 5.51 seconds
Started Jul 03 05:19:16 PM PDT 24
Finished Jul 03 05:19:21 PM PDT 24
Peak memory 232716 kb
Host smart-e4b8670d-d173-4702-968c-e59865668ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570505774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3570505774
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1862235183
Short name T64
Test name
Test status
Simulation time 16047523 ps
CPU time 0.69 seconds
Started Jul 03 05:19:16 PM PDT 24
Finished Jul 03 05:19:17 PM PDT 24
Peak memory 204984 kb
Host smart-cf402ba7-1552-404f-8d31-506fe18847ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862235183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1862235183
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.777779411
Short name T901
Test name
Test status
Simulation time 114716230 ps
CPU time 2.6 seconds
Started Jul 03 05:19:18 PM PDT 24
Finished Jul 03 05:19:21 PM PDT 24
Peak memory 232644 kb
Host smart-db9e233a-540e-4048-b4c0-14e797ce8d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777779411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.777779411
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1583036133
Short name T665
Test name
Test status
Simulation time 24833675 ps
CPU time 0.81 seconds
Started Jul 03 05:19:16 PM PDT 24
Finished Jul 03 05:19:17 PM PDT 24
Peak memory 205576 kb
Host smart-60141a53-6e36-44ad-a557-4a61c3bba700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583036133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1583036133
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3451491493
Short name T717
Test name
Test status
Simulation time 5129224874 ps
CPU time 91.33 seconds
Started Jul 03 05:19:16 PM PDT 24
Finished Jul 03 05:20:48 PM PDT 24
Peak memory 256432 kb
Host smart-3988e1c7-2166-4dc5-bcef-66db39ab22fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451491493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3451491493
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2749663595
Short name T802
Test name
Test status
Simulation time 76392835 ps
CPU time 0.79 seconds
Started Jul 03 05:19:20 PM PDT 24
Finished Jul 03 05:19:21 PM PDT 24
Peak memory 217332 kb
Host smart-f8356c86-4b60-4e7f-9db0-696dd48d3d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749663595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2749663595
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1661935350
Short name T946
Test name
Test status
Simulation time 8671139844 ps
CPU time 36.01 seconds
Started Jul 03 05:19:18 PM PDT 24
Finished Jul 03 05:19:54 PM PDT 24
Peak memory 238408 kb
Host smart-f9149598-8221-45d2-8610-b77ae010ccae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661935350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1661935350
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.575794695
Short name T719
Test name
Test status
Simulation time 728157147 ps
CPU time 9.11 seconds
Started Jul 03 05:19:16 PM PDT 24
Finished Jul 03 05:19:26 PM PDT 24
Peak memory 232656 kb
Host smart-8da58335-d4c8-48d7-9027-0c2c6d3d3944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575794695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.575794695
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.411139901
Short name T813
Test name
Test status
Simulation time 29453915468 ps
CPU time 56 seconds
Started Jul 03 05:19:19 PM PDT 24
Finished Jul 03 05:20:15 PM PDT 24
Peak memory 235676 kb
Host smart-e01637c6-af97-44aa-b916-ad7d856080ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411139901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.411139901
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3261180867
Short name T917
Test name
Test status
Simulation time 3891467573 ps
CPU time 19.34 seconds
Started Jul 03 05:19:18 PM PDT 24
Finished Jul 03 05:19:38 PM PDT 24
Peak memory 224556 kb
Host smart-690c8f82-6422-47a8-abe3-1d7f9fffae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261180867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3261180867
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2038498254
Short name T84
Test name
Test status
Simulation time 1204828195 ps
CPU time 7.44 seconds
Started Jul 03 05:19:17 PM PDT 24
Finished Jul 03 05:19:25 PM PDT 24
Peak memory 232632 kb
Host smart-7b0a5add-cdce-4847-870d-e11491bb02ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038498254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2038498254
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2177356354
Short name T608
Test name
Test status
Simulation time 925173470 ps
CPU time 9.93 seconds
Started Jul 03 05:19:16 PM PDT 24
Finished Jul 03 05:19:26 PM PDT 24
Peak memory 224436 kb
Host smart-6ec537dc-8d1e-41b1-9a34-1e05ab45f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177356354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2177356354
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3715073749
Short name T626
Test name
Test status
Simulation time 7533977347 ps
CPU time 6.39 seconds
Started Jul 03 05:19:18 PM PDT 24
Finished Jul 03 05:19:25 PM PDT 24
Peak memory 224584 kb
Host smart-b5d2cdc2-a65f-4495-a016-2e6062819237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715073749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3715073749
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2631543897
Short name T343
Test name
Test status
Simulation time 1316775779 ps
CPU time 13.32 seconds
Started Jul 03 05:19:17 PM PDT 24
Finished Jul 03 05:19:31 PM PDT 24
Peak memory 222612 kb
Host smart-3214d307-f56c-48a0-bc1f-3223124ed2de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2631543897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2631543897
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3309548268
Short name T911
Test name
Test status
Simulation time 36518107669 ps
CPU time 251.89 seconds
Started Jul 03 05:19:17 PM PDT 24
Finished Jul 03 05:23:29 PM PDT 24
Peak memory 257296 kb
Host smart-2e60ae20-3a59-45a6-a9d9-f4ff49c79d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309548268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3309548268
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.98785937
Short name T297
Test name
Test status
Simulation time 119818276529 ps
CPU time 31.11 seconds
Started Jul 03 05:19:18 PM PDT 24
Finished Jul 03 05:19:50 PM PDT 24
Peak memory 216396 kb
Host smart-65194153-8883-467b-9911-bd6e421d40a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98785937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.98785937
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2358026416
Short name T692
Test name
Test status
Simulation time 860237675 ps
CPU time 6.91 seconds
Started Jul 03 05:19:16 PM PDT 24
Finished Jul 03 05:19:23 PM PDT 24
Peak memory 216268 kb
Host smart-716d3cae-27dd-4a0a-954a-ad8baedb2f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358026416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2358026416
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3353394878
Short name T417
Test name
Test status
Simulation time 89253986 ps
CPU time 1.27 seconds
Started Jul 03 05:19:17 PM PDT 24
Finished Jul 03 05:19:19 PM PDT 24
Peak memory 216200 kb
Host smart-8b70e3c8-c728-4ffa-8720-3c1bc7808619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353394878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3353394878
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.314696458
Short name T854
Test name
Test status
Simulation time 14032845 ps
CPU time 0.71 seconds
Started Jul 03 05:19:12 PM PDT 24
Finished Jul 03 05:19:14 PM PDT 24
Peak memory 206004 kb
Host smart-5eda43c4-4a83-4f13-9bb8-a852298217a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314696458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.314696458
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2928302773
Short name T512
Test name
Test status
Simulation time 653803806 ps
CPU time 8.21 seconds
Started Jul 03 05:19:14 PM PDT 24
Finished Jul 03 05:19:22 PM PDT 24
Peak memory 233800 kb
Host smart-6f29e894-a0bb-4d9d-8fa8-4ce9d7fba1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928302773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2928302773
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3373822412
Short name T495
Test name
Test status
Simulation time 14292917 ps
CPU time 0.77 seconds
Started Jul 03 05:19:21 PM PDT 24
Finished Jul 03 05:19:22 PM PDT 24
Peak memory 205540 kb
Host smart-93746230-1f56-435f-a706-7430c3009675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373822412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3373822412
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3443870
Short name T678
Test name
Test status
Simulation time 32901338 ps
CPU time 2.62 seconds
Started Jul 03 05:19:21 PM PDT 24
Finished Jul 03 05:19:24 PM PDT 24
Peak memory 232384 kb
Host smart-cd32b7cf-157d-442b-9b2c-285383a2395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3443870
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1810381929
Short name T739
Test name
Test status
Simulation time 32504590 ps
CPU time 0.8 seconds
Started Jul 03 05:19:20 PM PDT 24
Finished Jul 03 05:19:21 PM PDT 24
Peak memory 206884 kb
Host smart-a0bdac4c-3b7f-4d37-a20e-f13fe35278af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810381929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1810381929
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1904064738
Short name T53
Test name
Test status
Simulation time 143319587687 ps
CPU time 125.61 seconds
Started Jul 03 05:19:21 PM PDT 24
Finished Jul 03 05:21:27 PM PDT 24
Peak memory 257040 kb
Host smart-35712120-090e-491f-a8d6-98e963df2832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904064738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1904064738
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3870676372
Short name T235
Test name
Test status
Simulation time 8069727475 ps
CPU time 35.9 seconds
Started Jul 03 05:19:22 PM PDT 24
Finished Jul 03 05:19:58 PM PDT 24
Peak memory 240588 kb
Host smart-11bcaa0d-a194-4d39-94b1-df28e371fba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870676372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3870676372
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3915003609
Short name T47
Test name
Test status
Simulation time 52085199128 ps
CPU time 268.88 seconds
Started Jul 03 05:19:21 PM PDT 24
Finished Jul 03 05:23:50 PM PDT 24
Peak memory 267460 kb
Host smart-3afa9738-4683-4336-9f54-5616b57527e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915003609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3915003609
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3797615713
Short name T826
Test name
Test status
Simulation time 1157607595 ps
CPU time 5.68 seconds
Started Jul 03 05:19:23 PM PDT 24
Finished Jul 03 05:19:29 PM PDT 24
Peak memory 232672 kb
Host smart-2df72525-f67c-4add-b2f8-2a577bf0d64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797615713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3797615713
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.359995117
Short name T657
Test name
Test status
Simulation time 5111049278 ps
CPU time 36.28 seconds
Started Jul 03 05:19:25 PM PDT 24
Finished Jul 03 05:20:01 PM PDT 24
Peak memory 233864 kb
Host smart-cb398fc7-b75f-4c69-9cda-176dc3d69366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359995117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.359995117
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3260085071
Short name T777
Test name
Test status
Simulation time 304795381 ps
CPU time 5.16 seconds
Started Jul 03 05:19:19 PM PDT 24
Finished Jul 03 05:19:24 PM PDT 24
Peak memory 232720 kb
Host smart-157a3bb7-ba1d-4858-8ade-1f29458e023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260085071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3260085071
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1387490731
Short name T875
Test name
Test status
Simulation time 7539871144 ps
CPU time 54.17 seconds
Started Jul 03 05:19:17 PM PDT 24
Finished Jul 03 05:20:11 PM PDT 24
Peak memory 240632 kb
Host smart-34342706-1bb9-4c4f-920e-4aef285f1c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387490731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1387490731
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.800013420
Short name T756
Test name
Test status
Simulation time 36133431 ps
CPU time 2.5 seconds
Started Jul 03 05:19:20 PM PDT 24
Finished Jul 03 05:19:23 PM PDT 24
Peak memory 232584 kb
Host smart-42d0d251-1d74-4b86-8c25-521e06efe9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800013420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.800013420
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2664686546
Short name T247
Test name
Test status
Simulation time 8680171388 ps
CPU time 22.72 seconds
Started Jul 03 05:19:18 PM PDT 24
Finished Jul 03 05:19:41 PM PDT 24
Peak memory 232776 kb
Host smart-212f8ed9-152d-4905-b386-63fc26c713e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664686546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2664686546
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.11280466
Short name T344
Test name
Test status
Simulation time 5845838899 ps
CPU time 8.75 seconds
Started Jul 03 05:19:22 PM PDT 24
Finished Jul 03 05:19:31 PM PDT 24
Peak memory 220740 kb
Host smart-dbf6eca7-6f69-4f23-a065-d0730fb32c5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=11280466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direc
t.11280466
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1565080872
Short name T745
Test name
Test status
Simulation time 35884758 ps
CPU time 0.96 seconds
Started Jul 03 05:19:22 PM PDT 24
Finished Jul 03 05:19:23 PM PDT 24
Peak memory 206920 kb
Host smart-9a3a53a0-4a38-4996-b687-9e0ea3282615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565080872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1565080872
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2023680959
Short name T547
Test name
Test status
Simulation time 8019367724 ps
CPU time 11.72 seconds
Started Jul 03 05:19:20 PM PDT 24
Finished Jul 03 05:19:32 PM PDT 24
Peak memory 216336 kb
Host smart-6073a872-f75c-413d-adcd-3e5e0c38062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023680959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2023680959
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1187030453
Short name T25
Test name
Test status
Simulation time 884323126 ps
CPU time 3.96 seconds
Started Jul 03 05:19:17 PM PDT 24
Finished Jul 03 05:19:21 PM PDT 24
Peak memory 216276 kb
Host smart-234b896f-b65b-48ca-81f1-44b1e8f2d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187030453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1187030453
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3373394771
Short name T539
Test name
Test status
Simulation time 279636592 ps
CPU time 1.57 seconds
Started Jul 03 05:19:18 PM PDT 24
Finished Jul 03 05:19:20 PM PDT 24
Peak memory 216148 kb
Host smart-78b67881-d77a-420d-a92d-62940f1d2429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373394771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3373394771
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3259708838
Short name T432
Test name
Test status
Simulation time 20574785 ps
CPU time 0.79 seconds
Started Jul 03 05:19:17 PM PDT 24
Finished Jul 03 05:19:18 PM PDT 24
Peak memory 206000 kb
Host smart-11929f45-691d-4709-8e36-02c86d8ff5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259708838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3259708838
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2632121896
Short name T463
Test name
Test status
Simulation time 1010597928 ps
CPU time 4.36 seconds
Started Jul 03 05:19:18 PM PDT 24
Finished Jul 03 05:19:23 PM PDT 24
Peak memory 224428 kb
Host smart-d1b6cf70-915a-4d64-b52c-65cf23fc28b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632121896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2632121896
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2549821113
Short name T525
Test name
Test status
Simulation time 13074066 ps
CPU time 0.73 seconds
Started Jul 03 05:19:25 PM PDT 24
Finished Jul 03 05:19:27 PM PDT 24
Peak memory 205864 kb
Host smart-344e597c-0e0b-4bf8-b142-40742c3993e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549821113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2549821113
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2334633691
Short name T147
Test name
Test status
Simulation time 7357339824 ps
CPU time 18.92 seconds
Started Jul 03 05:19:27 PM PDT 24
Finished Jul 03 05:19:46 PM PDT 24
Peak memory 224636 kb
Host smart-2c888b46-d411-46bd-8474-7c39732ef9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334633691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2334633691
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3191216191
Short name T399
Test name
Test status
Simulation time 26049500 ps
CPU time 0.75 seconds
Started Jul 03 05:19:20 PM PDT 24
Finished Jul 03 05:19:21 PM PDT 24
Peak memory 205540 kb
Host smart-566d44ac-5fe5-45f0-9a97-9634840db84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191216191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3191216191
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1395282413
Short name T849
Test name
Test status
Simulation time 123425667144 ps
CPU time 187.35 seconds
Started Jul 03 05:19:26 PM PDT 24
Finished Jul 03 05:22:33 PM PDT 24
Peak memory 252976 kb
Host smart-5d51e3a0-b243-45f3-8fad-376b2e74edd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395282413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1395282413
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2494056881
Short name T226
Test name
Test status
Simulation time 3702192724 ps
CPU time 26.78 seconds
Started Jul 03 05:19:26 PM PDT 24
Finished Jul 03 05:19:53 PM PDT 24
Peak memory 249256 kb
Host smart-71d2db64-eebd-4f4c-b492-2a302600c7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494056881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2494056881
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2271856661
Short name T366
Test name
Test status
Simulation time 5490230461 ps
CPU time 23.49 seconds
Started Jul 03 05:19:25 PM PDT 24
Finished Jul 03 05:19:49 PM PDT 24
Peak memory 224624 kb
Host smart-b4f92daa-36ef-4dac-b154-11fb2032efc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271856661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2271856661
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2886653957
Short name T753
Test name
Test status
Simulation time 2997156781 ps
CPU time 18.21 seconds
Started Jul 03 05:19:29 PM PDT 24
Finished Jul 03 05:19:48 PM PDT 24
Peak memory 241012 kb
Host smart-c0d36d50-868d-49d0-9151-78e12cd44c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886653957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2886653957
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1217700492
Short name T624
Test name
Test status
Simulation time 4925086283 ps
CPU time 61.49 seconds
Started Jul 03 05:19:26 PM PDT 24
Finished Jul 03 05:20:28 PM PDT 24
Peak memory 249160 kb
Host smart-4846a412-2773-4619-98ec-3d7a7ac560e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217700492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1217700492
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3500548058
Short name T853
Test name
Test status
Simulation time 73962621 ps
CPU time 2.74 seconds
Started Jul 03 05:19:24 PM PDT 24
Finished Jul 03 05:19:27 PM PDT 24
Peak memory 232388 kb
Host smart-589fa9e3-0616-4df2-b47c-029c419de770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500548058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3500548058
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1250639602
Short name T201
Test name
Test status
Simulation time 904611574 ps
CPU time 4.12 seconds
Started Jul 03 05:19:23 PM PDT 24
Finished Jul 03 05:19:28 PM PDT 24
Peak memory 224396 kb
Host smart-e55d1391-5c40-478e-9ef2-3cfe7cbb3b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250639602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1250639602
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2134413219
Short name T583
Test name
Test status
Simulation time 4631431497 ps
CPU time 13.23 seconds
Started Jul 03 05:19:21 PM PDT 24
Finished Jul 03 05:19:34 PM PDT 24
Peak memory 224584 kb
Host smart-3633c868-0c72-4c89-95ed-c92fe92b7c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134413219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2134413219
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1705277108
Short name T556
Test name
Test status
Simulation time 2595863765 ps
CPU time 9.05 seconds
Started Jul 03 05:19:20 PM PDT 24
Finished Jul 03 05:19:29 PM PDT 24
Peak memory 232764 kb
Host smart-c4713fed-08fa-4b61-8f70-8998790ed6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705277108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1705277108
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2733149765
Short name T142
Test name
Test status
Simulation time 1434297144 ps
CPU time 6.44 seconds
Started Jul 03 05:19:24 PM PDT 24
Finished Jul 03 05:19:31 PM PDT 24
Peak memory 223100 kb
Host smart-50b1ad45-fa25-4735-a5aa-27c5761a6584
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2733149765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2733149765
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.705634403
Short name T924
Test name
Test status
Simulation time 73745757422 ps
CPU time 160.57 seconds
Started Jul 03 05:19:25 PM PDT 24
Finished Jul 03 05:22:06 PM PDT 24
Peak memory 254612 kb
Host smart-c9304c72-6646-4591-b43a-c7a29635e6b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705634403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.705634403
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.356195249
Short name T843
Test name
Test status
Simulation time 2190992495 ps
CPU time 28.63 seconds
Started Jul 03 05:19:24 PM PDT 24
Finished Jul 03 05:19:53 PM PDT 24
Peak memory 220376 kb
Host smart-4c206a92-1b69-48c7-96a8-b2d91179bc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356195249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.356195249
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3714234164
Short name T741
Test name
Test status
Simulation time 6749440599 ps
CPU time 18.58 seconds
Started Jul 03 05:19:21 PM PDT 24
Finished Jul 03 05:19:40 PM PDT 24
Peak memory 216352 kb
Host smart-c4e7639d-0c8c-4dd3-9cdf-ebf255891fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714234164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3714234164
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3220497295
Short name T877
Test name
Test status
Simulation time 201960250 ps
CPU time 1.05 seconds
Started Jul 03 05:19:19 PM PDT 24
Finished Jul 03 05:19:20 PM PDT 24
Peak memory 207900 kb
Host smart-0062da3e-e3f5-407e-8030-78c708aef749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220497295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3220497295
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1506040729
Short name T873
Test name
Test status
Simulation time 113612787 ps
CPU time 0.84 seconds
Started Jul 03 05:19:23 PM PDT 24
Finished Jul 03 05:19:24 PM PDT 24
Peak memory 207028 kb
Host smart-33f89392-17ec-4613-a0c0-6ac6c5fb93df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506040729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1506040729
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2050465352
Short name T355
Test name
Test status
Simulation time 2209254713 ps
CPU time 9.1 seconds
Started Jul 03 05:19:27 PM PDT 24
Finished Jul 03 05:19:36 PM PDT 24
Peak memory 232736 kb
Host smart-f1efd8d4-a6ce-4b80-9ea7-15ccd527541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050465352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2050465352
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2451354836
Short name T565
Test name
Test status
Simulation time 13048830 ps
CPU time 0.72 seconds
Started Jul 03 05:19:29 PM PDT 24
Finished Jul 03 05:19:30 PM PDT 24
Peak memory 205824 kb
Host smart-b1fccfd7-fefa-4977-a51e-a1ecc3ed7113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451354836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2451354836
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1744714279
Short name T650
Test name
Test status
Simulation time 29526666604 ps
CPU time 19.57 seconds
Started Jul 03 05:19:30 PM PDT 24
Finished Jul 03 05:19:50 PM PDT 24
Peak memory 232836 kb
Host smart-a5d4a2ca-529f-4f1e-9b28-0a1fbdf5cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744714279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1744714279
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3702799758
Short name T340
Test name
Test status
Simulation time 14744936 ps
CPU time 0.76 seconds
Started Jul 03 05:19:26 PM PDT 24
Finished Jul 03 05:19:27 PM PDT 24
Peak memory 205884 kb
Host smart-4be0c958-5ba3-4d2d-951d-abc4c8393c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702799758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3702799758
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2971960313
Short name T222
Test name
Test status
Simulation time 8310560258 ps
CPU time 80.26 seconds
Started Jul 03 05:19:29 PM PDT 24
Finished Jul 03 05:20:49 PM PDT 24
Peak memory 252104 kb
Host smart-b5c88711-9da4-48b8-8d27-1514e80f58af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971960313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2971960313
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2684836047
Short name T685
Test name
Test status
Simulation time 3270217906 ps
CPU time 68.1 seconds
Started Jul 03 05:19:30 PM PDT 24
Finished Jul 03 05:20:38 PM PDT 24
Peak memory 251048 kb
Host smart-50709f79-9b41-4be5-b35a-535b7b7a846d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684836047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2684836047
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3814543780
Short name T257
Test name
Test status
Simulation time 85757297915 ps
CPU time 406.93 seconds
Started Jul 03 05:19:28 PM PDT 24
Finished Jul 03 05:26:15 PM PDT 24
Peak memory 257452 kb
Host smart-4afc2bc8-06ca-4e7b-af70-40fa13d870ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814543780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3814543780
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.859812804
Short name T291
Test name
Test status
Simulation time 835954316 ps
CPU time 10.59 seconds
Started Jul 03 05:19:30 PM PDT 24
Finished Jul 03 05:19:41 PM PDT 24
Peak memory 250012 kb
Host smart-ba2517b7-0307-484b-918f-7b2fcb72c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859812804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.859812804
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.937197741
Short name T811
Test name
Test status
Simulation time 17129736958 ps
CPU time 108.99 seconds
Started Jul 03 05:19:29 PM PDT 24
Finished Jul 03 05:21:19 PM PDT 24
Peak memory 232832 kb
Host smart-b7095c22-32c1-48aa-a072-6d6fecd65711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937197741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.937197741
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.4112413894
Short name T851
Test name
Test status
Simulation time 7092270818 ps
CPU time 16.77 seconds
Started Jul 03 05:19:24 PM PDT 24
Finished Jul 03 05:19:41 PM PDT 24
Peak memory 232788 kb
Host smart-fbcbc087-39f9-4452-bb88-4ec996898b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112413894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4112413894
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3515493178
Short name T521
Test name
Test status
Simulation time 4573478391 ps
CPU time 18.56 seconds
Started Jul 03 05:19:25 PM PDT 24
Finished Jul 03 05:19:44 PM PDT 24
Peak memory 248744 kb
Host smart-0f1dd813-1e55-48b4-a99e-602d527a5170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515493178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3515493178
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2246361117
Short name T744
Test name
Test status
Simulation time 3517743287 ps
CPU time 8.62 seconds
Started Jul 03 05:19:25 PM PDT 24
Finished Jul 03 05:19:34 PM PDT 24
Peak memory 224556 kb
Host smart-d152e74b-9b2f-4367-8675-8c4dabb3519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246361117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2246361117
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1876179332
Short name T244
Test name
Test status
Simulation time 919589436 ps
CPU time 7.31 seconds
Started Jul 03 05:19:25 PM PDT 24
Finished Jul 03 05:19:33 PM PDT 24
Peak memory 240828 kb
Host smart-a5eca031-2226-4e5f-bb40-e946540cc72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876179332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1876179332
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1148187328
Short name T36
Test name
Test status
Simulation time 1357887721 ps
CPU time 5.73 seconds
Started Jul 03 05:19:29 PM PDT 24
Finished Jul 03 05:19:36 PM PDT 24
Peak memory 220324 kb
Host smart-4c60b285-4fd8-401e-bf14-33b32e14826f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1148187328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1148187328
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3617885259
Short name T310
Test name
Test status
Simulation time 368231485537 ps
CPU time 333.85 seconds
Started Jul 03 05:19:29 PM PDT 24
Finished Jul 03 05:25:03 PM PDT 24
Peak memory 267248 kb
Host smart-763c614e-c6f5-4286-870c-a224c8127446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617885259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3617885259
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2832370745
Short name T908
Test name
Test status
Simulation time 13471533746 ps
CPU time 41.59 seconds
Started Jul 03 05:19:24 PM PDT 24
Finished Jul 03 05:20:06 PM PDT 24
Peak memory 216348 kb
Host smart-5d36156c-4fe0-4e8f-8330-ec594c440c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832370745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2832370745
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.793592437
Short name T381
Test name
Test status
Simulation time 21665804843 ps
CPU time 11.87 seconds
Started Jul 03 05:19:24 PM PDT 24
Finished Jul 03 05:19:37 PM PDT 24
Peak memory 216488 kb
Host smart-901e0463-2fc2-44fb-a6d4-c4eaacc3abba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793592437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.793592437
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.4083257740
Short name T48
Test name
Test status
Simulation time 171576015 ps
CPU time 2.81 seconds
Started Jul 03 05:19:24 PM PDT 24
Finished Jul 03 05:19:27 PM PDT 24
Peak memory 216244 kb
Host smart-acd7ad39-71cd-41fc-b9a0-e031ce56b4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083257740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.4083257740
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1499900530
Short name T888
Test name
Test status
Simulation time 18142486 ps
CPU time 0.76 seconds
Started Jul 03 05:19:26 PM PDT 24
Finished Jul 03 05:19:27 PM PDT 24
Peak memory 206000 kb
Host smart-59066729-9e42-4910-b322-609ac0478ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499900530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1499900530
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3769808664
Short name T261
Test name
Test status
Simulation time 5823845916 ps
CPU time 11.97 seconds
Started Jul 03 05:19:25 PM PDT 24
Finished Jul 03 05:19:38 PM PDT 24
Peak memory 224560 kb
Host smart-46508e6d-7bc3-44df-b20b-8b87dca43995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769808664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3769808664
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2788741881
Short name T325
Test name
Test status
Simulation time 12082951 ps
CPU time 0.73 seconds
Started Jul 03 05:19:34 PM PDT 24
Finished Jul 03 05:19:35 PM PDT 24
Peak memory 205832 kb
Host smart-ca199282-1441-48bb-b599-de3eb6c16d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788741881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2788741881
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3969624938
Short name T812
Test name
Test status
Simulation time 365148194 ps
CPU time 3.33 seconds
Started Jul 03 05:19:33 PM PDT 24
Finished Jul 03 05:19:36 PM PDT 24
Peak memory 224448 kb
Host smart-977fb290-48c9-4434-856b-f7614cd77fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969624938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3969624938
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3581704662
Short name T895
Test name
Test status
Simulation time 14943150 ps
CPU time 0.75 seconds
Started Jul 03 05:19:30 PM PDT 24
Finished Jul 03 05:19:31 PM PDT 24
Peak memory 205880 kb
Host smart-02a82d56-b8c6-4768-ba1b-6c6a4d43333e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581704662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3581704662
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.571794924
Short name T173
Test name
Test status
Simulation time 11741070667 ps
CPU time 120.94 seconds
Started Jul 03 05:19:39 PM PDT 24
Finished Jul 03 05:21:40 PM PDT 24
Peak memory 252136 kb
Host smart-276ff4f3-ce59-46f1-9b51-c1078a43892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571794924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.571794924
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3191274366
Short name T260
Test name
Test status
Simulation time 64941203345 ps
CPU time 611.5 seconds
Started Jul 03 05:19:32 PM PDT 24
Finished Jul 03 05:29:44 PM PDT 24
Peak memory 263516 kb
Host smart-8161c893-1216-4122-87f2-cd715224a5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191274366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3191274366
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1960871150
Short name T718
Test name
Test status
Simulation time 2787865956 ps
CPU time 55.99 seconds
Started Jul 03 05:19:34 PM PDT 24
Finished Jul 03 05:20:30 PM PDT 24
Peak memory 239136 kb
Host smart-b42d6ff6-df06-4469-bb9e-a9c37b70c24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960871150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1960871150
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.615097053
Short name T649
Test name
Test status
Simulation time 1589808434 ps
CPU time 8.38 seconds
Started Jul 03 05:19:35 PM PDT 24
Finished Jul 03 05:19:44 PM PDT 24
Peak memory 234524 kb
Host smart-73abcda4-4ed3-422c-8e26-e91a463e1dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615097053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.615097053
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3141854717
Short name T485
Test name
Test status
Simulation time 18880462812 ps
CPU time 36.96 seconds
Started Jul 03 05:19:39 PM PDT 24
Finished Jul 03 05:20:16 PM PDT 24
Peak memory 224636 kb
Host smart-23802201-0bc7-4eb5-8ee8-5f3d2a011d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141854717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3141854717
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.831462662
Short name T765
Test name
Test status
Simulation time 9494350441 ps
CPU time 26.07 seconds
Started Jul 03 05:19:39 PM PDT 24
Finished Jul 03 05:20:05 PM PDT 24
Peak memory 232852 kb
Host smart-aa31646b-edbe-4ed9-8829-12331f8c3669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831462662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.831462662
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1503002501
Short name T868
Test name
Test status
Simulation time 9119371656 ps
CPU time 49.47 seconds
Started Jul 03 05:19:33 PM PDT 24
Finished Jul 03 05:20:22 PM PDT 24
Peak memory 232856 kb
Host smart-4c9f66f6-3274-4d9a-a12b-3d636d81d016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503002501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1503002501
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3989019300
Short name T430
Test name
Test status
Simulation time 264120587 ps
CPU time 3.14 seconds
Started Jul 03 05:19:33 PM PDT 24
Finished Jul 03 05:19:36 PM PDT 24
Peak memory 224484 kb
Host smart-b8b2aeee-ec47-43cb-9291-e41bef77546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989019300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3989019300
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1397120065
Short name T39
Test name
Test status
Simulation time 2905240861 ps
CPU time 10.29 seconds
Started Jul 03 05:19:32 PM PDT 24
Finished Jul 03 05:19:42 PM PDT 24
Peak memory 232752 kb
Host smart-f8b6bbab-432d-46fa-8c1b-a0a6ea84aee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397120065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1397120065
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2124564842
Short name T468
Test name
Test status
Simulation time 583771965 ps
CPU time 3.61 seconds
Started Jul 03 05:19:35 PM PDT 24
Finished Jul 03 05:19:39 PM PDT 24
Peak memory 219380 kb
Host smart-67f0cadb-ae12-436a-b13c-c4cdd6cdbf06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2124564842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2124564842
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3414909903
Short name T136
Test name
Test status
Simulation time 4009380658 ps
CPU time 73.17 seconds
Started Jul 03 05:19:34 PM PDT 24
Finished Jul 03 05:20:48 PM PDT 24
Peak memory 265668 kb
Host smart-71b5b96e-7f53-46a4-8a02-2cabeb796d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414909903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3414909903
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1305118235
Short name T687
Test name
Test status
Simulation time 36886760706 ps
CPU time 31.58 seconds
Started Jul 03 05:19:30 PM PDT 24
Finished Jul 03 05:20:02 PM PDT 24
Peak memory 216316 kb
Host smart-40d2c990-5990-4adb-b441-800fd3f52dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305118235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1305118235
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.4286518622
Short name T451
Test name
Test status
Simulation time 13206580531 ps
CPU time 8.16 seconds
Started Jul 03 05:19:30 PM PDT 24
Finished Jul 03 05:19:39 PM PDT 24
Peak memory 216384 kb
Host smart-46610088-f752-4520-8cdd-004f63cf587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286518622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.4286518622
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3917714683
Short name T635
Test name
Test status
Simulation time 1081765611 ps
CPU time 11.55 seconds
Started Jul 03 05:19:31 PM PDT 24
Finished Jul 03 05:19:43 PM PDT 24
Peak memory 216292 kb
Host smart-b9774c13-4098-4baf-a67b-807fbf9d3f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917714683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3917714683
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1229246293
Short name T732
Test name
Test status
Simulation time 175321077 ps
CPU time 0.9 seconds
Started Jul 03 05:19:29 PM PDT 24
Finished Jul 03 05:19:31 PM PDT 24
Peak memory 206980 kb
Host smart-035ef9a5-e20a-46e8-a48d-a59963615365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229246293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1229246293
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2990054060
Short name T550
Test name
Test status
Simulation time 728247899 ps
CPU time 3.82 seconds
Started Jul 03 05:19:32 PM PDT 24
Finished Jul 03 05:19:36 PM PDT 24
Peak memory 224376 kb
Host smart-595c83e0-1ef3-4fee-ba1a-d94fb3675d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990054060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2990054060
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3359629793
Short name T882
Test name
Test status
Simulation time 11642828 ps
CPU time 0.74 seconds
Started Jul 03 05:16:59 PM PDT 24
Finished Jul 03 05:17:00 PM PDT 24
Peak memory 205568 kb
Host smart-76f84efa-7f4d-49fa-8a35-43a311e33d8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359629793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
359629793
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3156426258
Short name T379
Test name
Test status
Simulation time 2033236626 ps
CPU time 9.54 seconds
Started Jul 03 05:16:55 PM PDT 24
Finished Jul 03 05:17:06 PM PDT 24
Peak memory 224452 kb
Host smart-7cd9fe5a-3ded-4ce4-a9f7-f3dad44791d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156426258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3156426258
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3506059264
Short name T566
Test name
Test status
Simulation time 18310442 ps
CPU time 0.84 seconds
Started Jul 03 05:16:54 PM PDT 24
Finished Jul 03 05:16:56 PM PDT 24
Peak memory 206560 kb
Host smart-41f84da5-1deb-40e7-9616-85b9cb01be45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506059264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3506059264
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1128698301
Short name T878
Test name
Test status
Simulation time 6713976559 ps
CPU time 32.47 seconds
Started Jul 03 05:17:03 PM PDT 24
Finished Jul 03 05:17:36 PM PDT 24
Peak memory 249156 kb
Host smart-1306909a-3b24-4804-87fc-42ef7c7c2a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128698301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1128698301
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.117129494
Short name T364
Test name
Test status
Simulation time 1818663441 ps
CPU time 13.83 seconds
Started Jul 03 05:16:59 PM PDT 24
Finished Jul 03 05:17:13 PM PDT 24
Peak memory 236988 kb
Host smart-fbd85559-881e-4bd0-9731-e713b627bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117129494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.117129494
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1543791861
Short name T41
Test name
Test status
Simulation time 123076644543 ps
CPU time 207.63 seconds
Started Jul 03 05:16:58 PM PDT 24
Finished Jul 03 05:20:26 PM PDT 24
Peak memory 251012 kb
Host smart-6281fb91-322a-45ba-b549-e75450c72ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543791861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1543791861
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3881806998
Short name T941
Test name
Test status
Simulation time 5215613254 ps
CPU time 4.82 seconds
Started Jul 03 05:16:58 PM PDT 24
Finished Jul 03 05:17:03 PM PDT 24
Peak memory 233808 kb
Host smart-140852bb-5a6e-49f4-a874-ec790c253ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881806998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3881806998
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3883013650
Short name T514
Test name
Test status
Simulation time 55266777994 ps
CPU time 52.35 seconds
Started Jul 03 05:16:57 PM PDT 24
Finished Jul 03 05:17:49 PM PDT 24
Peak memory 253520 kb
Host smart-85c12e73-b2f7-4b44-9160-4946b0b68f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883013650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3883013650
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4120624873
Short name T465
Test name
Test status
Simulation time 288998586 ps
CPU time 4.56 seconds
Started Jul 03 05:17:02 PM PDT 24
Finished Jul 03 05:17:07 PM PDT 24
Peak memory 224404 kb
Host smart-8492ef08-18fe-49ef-abfa-34cf7ea11952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120624873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4120624873
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2863391906
Short name T425
Test name
Test status
Simulation time 5481878863 ps
CPU time 29.95 seconds
Started Jul 03 05:16:57 PM PDT 24
Finished Jul 03 05:17:27 PM PDT 24
Peak memory 241012 kb
Host smart-59dd3eb7-9342-4b3d-b75c-6ca7bcddd243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863391906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2863391906
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4116181240
Short name T570
Test name
Test status
Simulation time 5151515255 ps
CPU time 10 seconds
Started Jul 03 05:16:58 PM PDT 24
Finished Jul 03 05:17:09 PM PDT 24
Peak memory 224556 kb
Host smart-e13082cf-0e2c-4abb-a8ed-559b48b22403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116181240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4116181240
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.371373060
Short name T240
Test name
Test status
Simulation time 6848533836 ps
CPU time 12.87 seconds
Started Jul 03 05:16:58 PM PDT 24
Finished Jul 03 05:17:11 PM PDT 24
Peak memory 224592 kb
Host smart-3fbb6254-8b52-434c-ab3d-f08cc51b23b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371373060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.371373060
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2779493628
Short name T839
Test name
Test status
Simulation time 1204189312 ps
CPU time 9.1 seconds
Started Jul 03 05:16:56 PM PDT 24
Finished Jul 03 05:17:06 PM PDT 24
Peak memory 222120 kb
Host smart-97785041-aa24-4560-a906-4c046dc1a461
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2779493628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2779493628
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4117704887
Short name T819
Test name
Test status
Simulation time 75083447 ps
CPU time 0.91 seconds
Started Jul 03 05:17:01 PM PDT 24
Finished Jul 03 05:17:02 PM PDT 24
Peak memory 205920 kb
Host smart-6e91bdd4-8d57-42d8-9cc3-06432d4d88ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117704887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4117704887
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3992299048
Short name T772
Test name
Test status
Simulation time 45374227742 ps
CPU time 22.33 seconds
Started Jul 03 05:16:56 PM PDT 24
Finished Jul 03 05:17:19 PM PDT 24
Peak memory 220220 kb
Host smart-46940c79-9da2-4374-b213-4f96670b9ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992299048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3992299048
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.466521243
Short name T26
Test name
Test status
Simulation time 1669297438 ps
CPU time 4.56 seconds
Started Jul 03 05:16:55 PM PDT 24
Finished Jul 03 05:17:00 PM PDT 24
Peak memory 216164 kb
Host smart-78f17f0d-6ab9-4d18-beb4-109ba928ba78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466521243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.466521243
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3569628406
Short name T73
Test name
Test status
Simulation time 38908950 ps
CPU time 0.71 seconds
Started Jul 03 05:16:56 PM PDT 24
Finished Jul 03 05:16:57 PM PDT 24
Peak memory 205680 kb
Host smart-5798a4ce-f1a4-4d84-acb5-bec987e3ddf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569628406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3569628406
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3712833888
Short name T580
Test name
Test status
Simulation time 181170810 ps
CPU time 0.83 seconds
Started Jul 03 05:16:54 PM PDT 24
Finished Jul 03 05:16:56 PM PDT 24
Peak memory 205960 kb
Host smart-a085e95d-d644-49c5-a16f-7aa8a7ee3d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712833888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3712833888
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3838495798
Short name T433
Test name
Test status
Simulation time 160337880 ps
CPU time 2.53 seconds
Started Jul 03 05:16:58 PM PDT 24
Finished Jul 03 05:17:01 PM PDT 24
Peak memory 224384 kb
Host smart-2dbfcf99-ebd1-4efa-a3e8-caac07c6d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838495798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3838495798
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1174400897
Short name T861
Test name
Test status
Simulation time 16355890 ps
CPU time 0.78 seconds
Started Jul 03 05:17:01 PM PDT 24
Finished Jul 03 05:17:02 PM PDT 24
Peak memory 205480 kb
Host smart-824771f1-b25e-4d7e-ad62-2d3a1d3d921d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174400897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
174400897
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.114581533
Short name T748
Test name
Test status
Simulation time 620944691 ps
CPU time 5.59 seconds
Started Jul 03 05:17:00 PM PDT 24
Finished Jul 03 05:17:06 PM PDT 24
Peak memory 232656 kb
Host smart-055c2d81-375e-4f34-abc4-7ba9419767b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114581533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.114581533
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3569870162
Short name T488
Test name
Test status
Simulation time 13773476 ps
CPU time 0.8 seconds
Started Jul 03 05:16:58 PM PDT 24
Finished Jul 03 05:16:59 PM PDT 24
Peak memory 206612 kb
Host smart-f8b7c4e6-9662-4573-822d-61cf077a2af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569870162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3569870162
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1350573553
Short name T976
Test name
Test status
Simulation time 8403414827 ps
CPU time 33.92 seconds
Started Jul 03 05:17:01 PM PDT 24
Finished Jul 03 05:17:35 PM PDT 24
Peak memory 249816 kb
Host smart-7e3309f2-c073-4ced-b2e8-1f46a1383dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350573553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1350573553
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3743224854
Short name T204
Test name
Test status
Simulation time 48135495542 ps
CPU time 452.88 seconds
Started Jul 03 05:17:03 PM PDT 24
Finished Jul 03 05:24:36 PM PDT 24
Peak memory 254244 kb
Host smart-314ae9ab-8fdb-45d3-a674-fda71d5dd5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743224854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3743224854
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.193097471
Short name T864
Test name
Test status
Simulation time 7272867928 ps
CPU time 49.45 seconds
Started Jul 03 05:17:00 PM PDT 24
Finished Jul 03 05:17:50 PM PDT 24
Peak memory 241048 kb
Host smart-f93c509b-f7b7-42a4-a210-9bca9aef1dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193097471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
193097471
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2290947871
Short name T486
Test name
Test status
Simulation time 706598476 ps
CPU time 16.8 seconds
Started Jul 03 05:17:07 PM PDT 24
Finished Jul 03 05:17:24 PM PDT 24
Peak memory 252308 kb
Host smart-e61fb07b-3c01-4b1f-ac91-6552bf088b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290947871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2290947871
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3133272154
Short name T518
Test name
Test status
Simulation time 563709852 ps
CPU time 5.24 seconds
Started Jul 03 05:17:03 PM PDT 24
Finished Jul 03 05:17:09 PM PDT 24
Peak memory 224428 kb
Host smart-bf898b69-ae5e-4078-bfa7-2ebcff3fd4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133272154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3133272154
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1510920402
Short name T246
Test name
Test status
Simulation time 29322987827 ps
CPU time 62.28 seconds
Started Jul 03 05:17:01 PM PDT 24
Finished Jul 03 05:18:04 PM PDT 24
Peak memory 232788 kb
Host smart-c594fe05-8ccb-4f01-b5f8-380e65350a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510920402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1510920402
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1117670092
Short name T40
Test name
Test status
Simulation time 3166285527 ps
CPU time 6.16 seconds
Started Jul 03 05:17:02 PM PDT 24
Finished Jul 03 05:17:08 PM PDT 24
Peak memory 222428 kb
Host smart-4f9dfe24-faae-46bd-991e-b5fda651af24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117670092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1117670092
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.492251908
Short name T894
Test name
Test status
Simulation time 3616583729 ps
CPU time 5.04 seconds
Started Jul 03 05:16:57 PM PDT 24
Finished Jul 03 05:17:02 PM PDT 24
Peak memory 232736 kb
Host smart-7c2a4873-2888-4c7a-8dc7-017702b589a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492251908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.492251908
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3726108963
Short name T632
Test name
Test status
Simulation time 828191678 ps
CPU time 12.86 seconds
Started Jul 03 05:17:04 PM PDT 24
Finished Jul 03 05:17:17 PM PDT 24
Peak memory 220352 kb
Host smart-3b84bf9e-acde-41ed-bc18-761e91d9cf72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3726108963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3726108963
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.935717280
Short name T121
Test name
Test status
Simulation time 20475966247 ps
CPU time 160.35 seconds
Started Jul 03 05:17:07 PM PDT 24
Finished Jul 03 05:19:47 PM PDT 24
Peak memory 257428 kb
Host smart-a9ec5840-df00-4e4c-974f-81a49906fe7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935717280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.935717280
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3609135224
Short name T589
Test name
Test status
Simulation time 10714510801 ps
CPU time 27.06 seconds
Started Jul 03 05:16:57 PM PDT 24
Finished Jul 03 05:17:24 PM PDT 24
Peak memory 216268 kb
Host smart-ccdaf45a-a92a-41b9-900c-7c77d16aca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609135224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3609135224
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3090287041
Short name T943
Test name
Test status
Simulation time 3823915881 ps
CPU time 12.94 seconds
Started Jul 03 05:16:58 PM PDT 24
Finished Jul 03 05:17:11 PM PDT 24
Peak memory 216304 kb
Host smart-621053db-05a7-48a6-aec5-a5dc35b0f814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090287041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3090287041
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2576090258
Short name T442
Test name
Test status
Simulation time 15674551 ps
CPU time 0.7 seconds
Started Jul 03 05:16:56 PM PDT 24
Finished Jul 03 05:16:57 PM PDT 24
Peak memory 205552 kb
Host smart-fbefd7a1-2840-4e8c-bcea-79580f88164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576090258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2576090258
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3598076281
Short name T83
Test name
Test status
Simulation time 278155334 ps
CPU time 0.83 seconds
Started Jul 03 05:16:59 PM PDT 24
Finished Jul 03 05:17:01 PM PDT 24
Peak memory 205996 kb
Host smart-57f4c6d9-b2a4-46fa-a6b4-4259c65bc69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598076281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3598076281
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1646703711
Short name T238
Test name
Test status
Simulation time 252658435 ps
CPU time 4.35 seconds
Started Jul 03 05:17:01 PM PDT 24
Finished Jul 03 05:17:06 PM PDT 24
Peak memory 224492 kb
Host smart-d6268afa-1b4d-472b-89da-5bd54dd9e27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646703711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1646703711
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2992940700
Short name T422
Test name
Test status
Simulation time 13836504 ps
CPU time 0.75 seconds
Started Jul 03 05:17:05 PM PDT 24
Finished Jul 03 05:17:06 PM PDT 24
Peak memory 205524 kb
Host smart-67b37c98-3ef2-4b96-8859-912f94d89978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992940700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
992940700
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2768193621
Short name T564
Test name
Test status
Simulation time 91402765 ps
CPU time 2.48 seconds
Started Jul 03 05:17:05 PM PDT 24
Finished Jul 03 05:17:08 PM PDT 24
Peak memory 224436 kb
Host smart-be75c0f7-1442-407f-a350-b89656f2b803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768193621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2768193621
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1221200087
Short name T328
Test name
Test status
Simulation time 30574358 ps
CPU time 0.8 seconds
Started Jul 03 05:17:02 PM PDT 24
Finished Jul 03 05:17:03 PM PDT 24
Peak memory 206612 kb
Host smart-b54e66c5-7be4-49fa-bd88-3de482f52049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221200087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1221200087
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2887358555
Short name T288
Test name
Test status
Simulation time 113214415012 ps
CPU time 198.14 seconds
Started Jul 03 05:17:04 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 249224 kb
Host smart-68064b66-2e98-4e34-ac61-65cd109fc528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887358555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2887358555
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1774458475
Short name T676
Test name
Test status
Simulation time 76574870605 ps
CPU time 226.37 seconds
Started Jul 03 05:17:04 PM PDT 24
Finished Jul 03 05:20:51 PM PDT 24
Peak memory 254168 kb
Host smart-4092807d-47d9-4d61-952a-6438a8e3d5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774458475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1774458475
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2797797450
Short name T1005
Test name
Test status
Simulation time 158987816892 ps
CPU time 760.35 seconds
Started Jul 03 05:17:04 PM PDT 24
Finished Jul 03 05:29:45 PM PDT 24
Peak memory 281752 kb
Host smart-c60eec2e-fe96-45a9-bd8a-78c3cf702835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797797450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2797797450
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1468005599
Short name T446
Test name
Test status
Simulation time 8428613343 ps
CPU time 29.2 seconds
Started Jul 03 05:17:04 PM PDT 24
Finished Jul 03 05:17:33 PM PDT 24
Peak memory 249176 kb
Host smart-a20b58e4-80bc-4888-8aa2-ed81d9938b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468005599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1468005599
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1630979827
Short name T902
Test name
Test status
Simulation time 14039454005 ps
CPU time 83.36 seconds
Started Jul 03 05:17:06 PM PDT 24
Finished Jul 03 05:18:29 PM PDT 24
Peak memory 249216 kb
Host smart-f2f4dc17-dbdf-4896-afea-ba2afac52582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630979827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1630979827
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3218516637
Short name T767
Test name
Test status
Simulation time 17089869756 ps
CPU time 28.06 seconds
Started Jul 03 05:17:03 PM PDT 24
Finished Jul 03 05:17:31 PM PDT 24
Peak memory 232856 kb
Host smart-45cd2fee-6a6f-4b65-aac6-3facaa0edfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218516637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3218516637
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3836369645
Short name T223
Test name
Test status
Simulation time 9461549411 ps
CPU time 27.56 seconds
Started Jul 03 05:17:08 PM PDT 24
Finished Jul 03 05:17:36 PM PDT 24
Peak memory 232824 kb
Host smart-071ab2fa-f27e-4a26-9634-160a025211e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836369645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3836369645
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3315919548
Short name T820
Test name
Test status
Simulation time 2570559649 ps
CPU time 7.7 seconds
Started Jul 03 05:17:03 PM PDT 24
Finished Jul 03 05:17:11 PM PDT 24
Peak memory 224492 kb
Host smart-ad326f88-d976-444e-af11-2fb91b08fedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315919548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3315919548
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2787835521
Short name T230
Test name
Test status
Simulation time 4394088504 ps
CPU time 12.67 seconds
Started Jul 03 05:17:01 PM PDT 24
Finished Jul 03 05:17:14 PM PDT 24
Peak memory 224556 kb
Host smart-a8ca33c4-4af5-4c8b-8598-d603ab513f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787835521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2787835521
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.281794474
Short name T474
Test name
Test status
Simulation time 4917142033 ps
CPU time 14.9 seconds
Started Jul 03 05:17:06 PM PDT 24
Finished Jul 03 05:17:21 PM PDT 24
Peak memory 222364 kb
Host smart-843d2d33-a8a9-4917-837d-71e6066c5ee4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=281794474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.281794474
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.414581159
Short name T655
Test name
Test status
Simulation time 41298255 ps
CPU time 0.94 seconds
Started Jul 03 05:17:07 PM PDT 24
Finished Jul 03 05:17:08 PM PDT 24
Peak memory 207596 kb
Host smart-dc1d5afe-a735-4e98-979e-0bf46ee64fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414581159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.414581159
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3672812024
Short name T562
Test name
Test status
Simulation time 6669258338 ps
CPU time 37.1 seconds
Started Jul 03 05:17:04 PM PDT 24
Finished Jul 03 05:17:41 PM PDT 24
Peak memory 216480 kb
Host smart-b92cbf46-9ee9-4057-be0a-bba1e601dd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672812024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3672812024
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2870764964
Short name T82
Test name
Test status
Simulation time 8912484025 ps
CPU time 9.24 seconds
Started Jul 03 05:17:02 PM PDT 24
Finished Jul 03 05:17:12 PM PDT 24
Peak memory 216332 kb
Host smart-bc2654c6-d16f-49a6-bacc-84da0c6cef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870764964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2870764964
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2376863742
Short name T357
Test name
Test status
Simulation time 38717272 ps
CPU time 0.73 seconds
Started Jul 03 05:17:04 PM PDT 24
Finished Jul 03 05:17:05 PM PDT 24
Peak memory 205672 kb
Host smart-e432f9b4-27a7-4c0a-b305-f1c9f51ae1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376863742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2376863742
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.904552371
Short name T604
Test name
Test status
Simulation time 36314361 ps
CPU time 0.84 seconds
Started Jul 03 05:17:01 PM PDT 24
Finished Jul 03 05:17:02 PM PDT 24
Peak memory 205948 kb
Host smart-8cf05c9a-cc06-4980-af8f-4722a7cd390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904552371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.904552371
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3385616479
Short name T799
Test name
Test status
Simulation time 515522758 ps
CPU time 2.57 seconds
Started Jul 03 05:17:06 PM PDT 24
Finished Jul 03 05:17:09 PM PDT 24
Peak memory 232668 kb
Host smart-15f3a195-32d2-4b62-b0d5-c2afd73caa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385616479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3385616479
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3268615878
Short name T788
Test name
Test status
Simulation time 91073631 ps
CPU time 0.71 seconds
Started Jul 03 05:17:08 PM PDT 24
Finished Jul 03 05:17:09 PM PDT 24
Peak memory 205468 kb
Host smart-a2197742-d25d-4372-b61f-94b06e46994a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268615878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
268615878
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.843763653
Short name T560
Test name
Test status
Simulation time 2811635354 ps
CPU time 8.49 seconds
Started Jul 03 05:17:12 PM PDT 24
Finished Jul 03 05:17:21 PM PDT 24
Peak memory 232744 kb
Host smart-8d7b6d14-e6fa-4e5a-bf99-1064c2ec20a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843763653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.843763653
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2768552503
Short name T427
Test name
Test status
Simulation time 36466574 ps
CPU time 0.79 seconds
Started Jul 03 05:17:04 PM PDT 24
Finished Jul 03 05:17:05 PM PDT 24
Peak memory 206572 kb
Host smart-434bdbf6-d9dc-4f74-a5dd-7f1a97dfca97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768552503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2768552503
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1553562438
Short name T458
Test name
Test status
Simulation time 9831773633 ps
CPU time 25.36 seconds
Started Jul 03 05:17:11 PM PDT 24
Finished Jul 03 05:17:37 PM PDT 24
Peak memory 224520 kb
Host smart-6d51ac33-a035-417e-92b4-f09d941462b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553562438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1553562438
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3482448619
Short name T372
Test name
Test status
Simulation time 58287913301 ps
CPU time 50.03 seconds
Started Jul 03 05:17:10 PM PDT 24
Finished Jul 03 05:18:00 PM PDT 24
Peak memory 241052 kb
Host smart-f021ab35-77d8-44ed-a12a-d4e94df6463f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482448619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3482448619
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2824332944
Short name T515
Test name
Test status
Simulation time 199923113 ps
CPU time 5.06 seconds
Started Jul 03 05:17:09 PM PDT 24
Finished Jul 03 05:17:15 PM PDT 24
Peak memory 240876 kb
Host smart-17bee0d2-8e4a-454c-9f8c-64502351c78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824332944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2824332944
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1928289087
Short name T283
Test name
Test status
Simulation time 15731313926 ps
CPU time 157.08 seconds
Started Jul 03 05:17:11 PM PDT 24
Finished Jul 03 05:19:48 PM PDT 24
Peak memory 273436 kb
Host smart-3ce1efc4-0fd6-4109-91e5-98039acb019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928289087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1928289087
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2758257970
Short name T429
Test name
Test status
Simulation time 27927150 ps
CPU time 2.07 seconds
Started Jul 03 05:17:10 PM PDT 24
Finished Jul 03 05:17:12 PM PDT 24
Peak memory 223120 kb
Host smart-be559472-daf0-49e8-b59f-88cceb26c90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758257970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2758257970
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3466209019
Short name T740
Test name
Test status
Simulation time 271806728 ps
CPU time 6.06 seconds
Started Jul 03 05:17:09 PM PDT 24
Finished Jul 03 05:17:15 PM PDT 24
Peak memory 224472 kb
Host smart-36c8258c-b67c-4845-9eb4-1d0dab6e2e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466209019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3466209019
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1855290588
Short name T166
Test name
Test status
Simulation time 2635722050 ps
CPU time 8.61 seconds
Started Jul 03 05:17:11 PM PDT 24
Finished Jul 03 05:17:20 PM PDT 24
Peak memory 224496 kb
Host smart-7363e0d7-a891-41ca-ab13-6fa587746c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855290588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1855290588
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.809752678
Short name T776
Test name
Test status
Simulation time 3016307259 ps
CPU time 13.69 seconds
Started Jul 03 05:17:08 PM PDT 24
Finished Jul 03 05:17:22 PM PDT 24
Peak memory 224032 kb
Host smart-5a22c739-0946-455d-b0f2-f25547ec9162
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=809752678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.809752678
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2319114486
Short name T217
Test name
Test status
Simulation time 19543861264 ps
CPU time 216.35 seconds
Started Jul 03 05:17:08 PM PDT 24
Finished Jul 03 05:20:44 PM PDT 24
Peak memory 268496 kb
Host smart-3a1ecf3c-ea0d-4d72-bcfa-b8901c5146f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319114486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2319114486
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1858029775
Short name T299
Test name
Test status
Simulation time 5905556900 ps
CPU time 29.24 seconds
Started Jul 03 05:17:06 PM PDT 24
Finished Jul 03 05:17:36 PM PDT 24
Peak memory 216372 kb
Host smart-50d1678e-755b-445c-99f0-6fe74e9ab160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858029775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1858029775
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.784292604
Short name T686
Test name
Test status
Simulation time 6684324029 ps
CPU time 10.3 seconds
Started Jul 03 05:17:06 PM PDT 24
Finished Jul 03 05:17:16 PM PDT 24
Peak memory 216352 kb
Host smart-5bb00b2a-1ea2-45aa-8057-b20fa27bff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784292604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.784292604
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.114717861
Short name T923
Test name
Test status
Simulation time 10170135 ps
CPU time 0.72 seconds
Started Jul 03 05:17:05 PM PDT 24
Finished Jul 03 05:17:06 PM PDT 24
Peak memory 205664 kb
Host smart-abfe7c3b-79e6-42dd-8d38-d80bacff12c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114717861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.114717861
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2800596051
Short name T752
Test name
Test status
Simulation time 189062804 ps
CPU time 0.81 seconds
Started Jul 03 05:17:04 PM PDT 24
Finished Jul 03 05:17:05 PM PDT 24
Peak memory 206000 kb
Host smart-db44a2cf-379c-443f-8565-a2e3fbab3c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800596051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2800596051
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3755687832
Short name T528
Test name
Test status
Simulation time 4438013177 ps
CPU time 14.71 seconds
Started Jul 03 05:17:10 PM PDT 24
Finished Jul 03 05:17:25 PM PDT 24
Peak memory 240980 kb
Host smart-b01061fa-4b50-42a7-ac97-cab55eedf1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755687832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3755687832
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3008473355
Short name T889
Test name
Test status
Simulation time 14703043 ps
CPU time 0.8 seconds
Started Jul 03 05:17:19 PM PDT 24
Finished Jul 03 05:17:20 PM PDT 24
Peak memory 205512 kb
Host smart-ed6d194d-586b-45c2-a974-0215aa101c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008473355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
008473355
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.181946967
Short name T631
Test name
Test status
Simulation time 502394536 ps
CPU time 2.33 seconds
Started Jul 03 05:17:15 PM PDT 24
Finished Jul 03 05:17:18 PM PDT 24
Peak memory 224432 kb
Host smart-03dc972e-80c5-4d90-a206-87f0e79c0fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181946967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.181946967
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3528345266
Short name T689
Test name
Test status
Simulation time 102930784 ps
CPU time 0.81 seconds
Started Jul 03 05:17:10 PM PDT 24
Finished Jul 03 05:17:11 PM PDT 24
Peak memory 206608 kb
Host smart-b4773b39-66b4-4f0b-8d7f-03ba9383de26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528345266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3528345266
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.703838861
Short name T971
Test name
Test status
Simulation time 52494149111 ps
CPU time 107.42 seconds
Started Jul 03 05:17:18 PM PDT 24
Finished Jul 03 05:19:05 PM PDT 24
Peak memory 256752 kb
Host smart-3c448a84-d209-4cf7-87fb-b09779b47452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703838861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.703838861
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.207161655
Short name T275
Test name
Test status
Simulation time 91007995427 ps
CPU time 452.71 seconds
Started Jul 03 05:17:19 PM PDT 24
Finished Jul 03 05:24:52 PM PDT 24
Peak memory 251500 kb
Host smart-38cce832-b729-4a17-af20-01f987804997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207161655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.207161655
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.26433402
Short name T804
Test name
Test status
Simulation time 60577490119 ps
CPU time 145.17 seconds
Started Jul 03 05:17:17 PM PDT 24
Finished Jul 03 05:19:43 PM PDT 24
Peak memory 254320 kb
Host smart-b80c2702-182c-46a2-95c5-ca96166a6dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26433402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.26433402
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2273266608
Short name T171
Test name
Test status
Simulation time 451544077 ps
CPU time 7.49 seconds
Started Jul 03 05:17:15 PM PDT 24
Finished Jul 03 05:17:23 PM PDT 24
Peak memory 224488 kb
Host smart-81097cc8-4ae1-48ef-b0f6-eec8f84e2d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273266608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2273266608
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.381841631
Short name T203
Test name
Test status
Simulation time 25047751946 ps
CPU time 153.97 seconds
Started Jul 03 05:17:17 PM PDT 24
Finished Jul 03 05:19:51 PM PDT 24
Peak memory 249268 kb
Host smart-1d7e9303-c16b-45f6-bdc0-7aad864b6d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381841631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
381841631
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1346495590
Short name T251
Test name
Test status
Simulation time 2377822209 ps
CPU time 7.09 seconds
Started Jul 03 05:17:17 PM PDT 24
Finished Jul 03 05:17:24 PM PDT 24
Peak memory 224584 kb
Host smart-908c4914-bec6-4749-982e-cbe09ef958c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346495590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1346495590
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2381203654
Short name T210
Test name
Test status
Simulation time 2921103773 ps
CPU time 6.88 seconds
Started Jul 03 05:17:18 PM PDT 24
Finished Jul 03 05:17:25 PM PDT 24
Peak memory 240540 kb
Host smart-0fbd63fa-94f2-45a6-b9cf-439cba595a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381203654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2381203654
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.992158249
Short name T208
Test name
Test status
Simulation time 20316284955 ps
CPU time 17.49 seconds
Started Jul 03 05:17:13 PM PDT 24
Finished Jul 03 05:17:30 PM PDT 24
Peak memory 232816 kb
Host smart-521f0518-cd5c-4605-9d36-2dcf93fe9549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992158249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
992158249
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.165667091
Short name T997
Test name
Test status
Simulation time 7946362557 ps
CPU time 13.42 seconds
Started Jul 03 05:17:13 PM PDT 24
Finished Jul 03 05:17:27 PM PDT 24
Peak memory 232816 kb
Host smart-aa4dc902-489d-47e3-ab7c-051acf11df5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165667091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.165667091
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2091482246
Short name T449
Test name
Test status
Simulation time 1064255861 ps
CPU time 4.89 seconds
Started Jul 03 05:17:17 PM PDT 24
Finished Jul 03 05:17:22 PM PDT 24
Peak memory 223136 kb
Host smart-a61d1689-c00c-409e-8f40-4fce64146230
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2091482246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2091482246
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3615388949
Short name T801
Test name
Test status
Simulation time 39570112 ps
CPU time 0.94 seconds
Started Jul 03 05:17:19 PM PDT 24
Finished Jul 03 05:17:20 PM PDT 24
Peak memory 205792 kb
Host smart-43eabdc0-4750-458b-ba85-e86d2b53676d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615388949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3615388949
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3883148010
Short name T721
Test name
Test status
Simulation time 1689315600 ps
CPU time 13.02 seconds
Started Jul 03 05:17:14 PM PDT 24
Finished Jul 03 05:17:27 PM PDT 24
Peak memory 216260 kb
Host smart-d2313864-8e56-40c1-9337-acaf02cf53b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883148010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3883148010
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4101668194
Short name T609
Test name
Test status
Simulation time 2670046953 ps
CPU time 10.03 seconds
Started Jul 03 05:17:16 PM PDT 24
Finished Jul 03 05:17:27 PM PDT 24
Peak memory 216288 kb
Host smart-1c6e3b86-07f9-4e87-b8d3-71b153873c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101668194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4101668194
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1791585975
Short name T823
Test name
Test status
Simulation time 101666438 ps
CPU time 1.21 seconds
Started Jul 03 05:17:15 PM PDT 24
Finished Jul 03 05:17:17 PM PDT 24
Peak memory 216184 kb
Host smart-fb666eb2-c8c1-496f-908b-eefe2546891e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791585975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1791585975
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1345667466
Short name T684
Test name
Test status
Simulation time 51776310 ps
CPU time 0.8 seconds
Started Jul 03 05:17:16 PM PDT 24
Finished Jul 03 05:17:17 PM PDT 24
Peak memory 205996 kb
Host smart-bc43f049-dd82-4415-b4c7-75d092f57799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345667466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1345667466
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3898317089
Short name T239
Test name
Test status
Simulation time 9007409255 ps
CPU time 9.82 seconds
Started Jul 03 05:17:13 PM PDT 24
Finished Jul 03 05:17:23 PM PDT 24
Peak memory 238848 kb
Host smart-f51a6d4e-deb6-48a5-902f-ed49baf169a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898317089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3898317089
Directory /workspace/9.spi_device_upload/latest
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