Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2150425	1			T1	1		T2	1838		T3	1
all_values[1]	2150425	1			T1	1		T2	1838		T3	1
all_values[2]	2150425	1			T1	1		T2	1838		T3	1
all_values[3]	2150425	1			T1	1		T2	1838		T3	1
all_values[4]	2150425	1			T1	1		T2	1838		T3	1
all_values[5]	2150425	1			T1	1		T2	1838		T3	1
all_values[6]	2150425	1			T1	1		T2	1838		T3	1
all_values[7]	2150425	1			T1	1		T2	1838		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16674444

1

T1

8

T2

14704

T3

8

auto[1]

528956

1

T12

52

T13

36

T15

71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17180340

1

T1

8

T2

14704

T3

8

auto[1]

23060

1

T10

12

T31

230

T12

45

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2110580	1			T1	1		T2	1838		T3	1
all_values[0]	auto[0]	auto[1]	10486	1			T10	6		T31	84		T12	5
all_values[0]	auto[1]	auto[0]	28976	1			T12	6		T13	2		T15	5
all_values[0]	auto[1]	auto[1]	383	1			T12	3		T13	1		T15	3
all_values[1]	auto[0]	auto[0]	2062735	1			T1	1		T2	1838		T3	1
all_values[1]	auto[0]	auto[1]	6441	1			T10	6		T31	84		T12	5
all_values[1]	auto[1]	auto[0]	80773	1			T12	4		T13	2		T15	4
all_values[1]	auto[1]	auto[1]	476	1			T12	1		T13	4		T15	5
all_values[2]	auto[0]	auto[0]	2137853	1			T1	1		T2	1838		T3	1
all_values[2]	auto[0]	auto[1]	2786	1			T31	62		T12	5		T23	38
all_values[2]	auto[1]	auto[0]	9568	1			T12	4		T13	1		T15	4
all_values[2]	auto[1]	auto[1]	218	1			T12	2		T15	3		T18	5
all_values[3]	auto[0]	auto[0]	2041498	1			T1	1		T2	1838		T3	1
all_values[3]	auto[0]	auto[1]	230	1			T12	5		T13	1		T15	1
all_values[3]	auto[1]	auto[0]	108464	1			T12	5		T13	2		T15	9
all_values[3]	auto[1]	auto[1]	233	1			T15	4		T18	4		T19	3
all_values[4]	auto[0]	auto[0]	2100517	1			T1	1		T2	1838		T3	1
all_values[4]	auto[0]	auto[1]	250	1			T12	7		T13	2		T15	5
all_values[4]	auto[1]	auto[0]	49438	1			T12	1		T13	3		T15	3
all_values[4]	auto[1]	auto[1]	220	1			T12	3		T13	2		T15	3
all_values[5]	auto[0]	auto[0]	2065742	1			T1	1		T2	1838		T3	1
all_values[5]	auto[0]	auto[1]	203	1			T12	3		T15	1		T18	4
all_values[5]	auto[1]	auto[0]	84276	1			T12	6		T13	5		T15	7
all_values[5]	auto[1]	auto[1]	204	1			T12	2		T15	5		T18	3
all_values[6]	auto[0]	auto[0]	2068947	1			T1	1		T2	1838		T3	1
all_values[6]	auto[0]	auto[1]	225	1			T15	2		T18	2		T19	6
all_values[6]	auto[1]	auto[0]	81012	1			T12	11		T13	5		T15	3
all_values[6]	auto[1]	auto[1]	241	1			T13	2		T15	6		T18	3
all_values[7]	auto[0]	auto[0]	2065720	1			T1	1		T2	1838		T3	1
all_values[7]	auto[0]	auto[1]	231	1			T12	2		T15	5		T18	2
all_values[7]	auto[1]	auto[0]	84241	1			T12	2		T13	4		T15	2
all_values[7]	auto[1]	auto[1]	233	1			T12	2		T13	3		T15	5