Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33143	1			T1	4		T3	4		T5	45
auto[SpiFlashAddrCfg]	7331	1			T5	11		T7	8		T8	2
auto[SpiFlashAddr3b]	8824	1			T3	2		T5	19		T7	4
auto[SpiFlashAddr4b]	7161	1			T3	6		T5	12		T9	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32595

1

T1

4

T3

12

T5

66

auto[1]

23864

1

T5

21

T7

12

T10

8

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29941

1

T1

4

T3

6

T5

54

auto[1]

26518

1

T3

6

T5

33

T7

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37498	1			T1	4		T3	6		T5	54
values[1]	1079	1			T5	2		T37	8		T27	2
values[2]	1377	1			T5	8		T9	2		T31	4
values[3]	1381	1			T5	1		T9	2		T10	1
values[4]	1434	1			T5	5		T8	2		T31	4
values[5]	1385	1			T5	2		T7	4		T31	7
values[6]	1356	1			T5	2		T7	2		T31	2
values[7]	1482	1			T5	2		T7	6		T10	1
values[8]	9467	1			T3	6		T5	11		T9	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28318

1

T1

4

T3

12

T6

6

auto[1]

28141

1

T5

87

T10

22

T37

200

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

53438

1

T1

4

T3

12

T5

83

write

3021

1

T5

4

T10

2

T11

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18484

1

T3

6

T5

38

T6

6

valids[0x1]

37975

1

T1

4

T3

6

T5

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1480	1			T31	4		T37	11		T23	1
internal_process_ops[0x5a]	1499	1			T7	4		T10	3		T31	3
internal_process_ops[0x05]	19822	1			T1	2		T5	30		T10	2
internal_process_ops[0x35]	1501	1			T3	4		T5	3		T10	1
internal_process_ops[0x15]	1449	1			T1	2		T5	1		T9	2
internal_process_ops[0x03]	1025	1			T3	2		T5	1		T7	2
internal_process_ops[0x0b]	994	1			T5	3		T10	1		T31	2
internal_process_ops[0x3b]	1036	1			T8	2		T10	1		T31	6
internal_process_ops[0x6b]	988	1			T9	2		T10	1		T31	2
internal_process_ops[0xbb]	1002	1			T3	2		T5	1		T7	4
internal_process_ops[0xeb]	962	1			T3	4		T9	2		T31	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54987

1

T1

4

T3

12

T5

85

auto[1]

1472

1

T5

2

T10

1

T31

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54273

1

T1

4

T3

12

T5

85

auto[1]

2186

1

T5

2

T10

1

T31

12

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9531

1

T1

4

T3

4

T6

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5970

1

T31

130

T23

1

T33

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1939

1

T8

2

T31

10

T23

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1707

1

T7

8

T31

16

T33

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2302

1

T3

2

T9

4

T31

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1938

1

T7

4

T31

13

T23

1

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1921

1

T3

6

T9

2

T11

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1627

1

T31

6

T23

4

T33

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

130

1

T11

2

T31

1

T23

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

88

1

T31

1

T33

1

T39

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

59

1

T39

1

T147

1

T148

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

53

1

T33

1

T149

2

T148

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

100

1

T43

2

T44

1

T150

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

76

1

T31

5

T33

4

T44

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

61

1

T31

3

T45

1

T39

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

92

1

T45

2

T39

1

T150

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

109

1

T31

2

T47

1

T151

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

69

1

T23

2

T45

1

T39

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

101

1

T33

1

T44

4

T39

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

93

1

T31

2

T34

1

T44

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T31

2

T34

2

T39

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

72

1

T33

1

T34

1

T44

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

70

1

T34

1

T44

1

T39

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T31

1

T45

1

T17

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10537

1

T5

41

T10

6

T37

58

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6347

1

T5

3

T10

2

T37

32

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1538

1

T5

6

T10

1

T37

19

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1411

1

T5

5

T37

12

T27

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1819

1

T5

10

T10

5

T37

24

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1991

1

T5

7

T10

3

T37

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1464

1

T5

7

T10

1

T37

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1396

1

T5

4

T10

2

T37

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

90

1

T152

2

T78

1

T153

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

119

1

T37

2

T13

5

T38

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

86

1

T5

1

T37

2

T27

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

133

1

T27

2

T38

4

T78

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

110

1

T37

3

T27

2

T38

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

97

1

T27

1

T13

1

T78

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

119

1

T13

3

T38

1

T152

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

81

1

T13

6

T38

1

T152

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

109

1

T37

1

T27

3

T13

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

103

1

T5

2

T10

1

T27

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

110

1

T10

1

T13

6

T38

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

80

1

T37

2

T27

2

T13

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

95

1

T37

5

T27

2

T13

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

81

1

T37

3

T27

1

T13

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

104

1

T5

1

T27

1

T13

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

121

1

T37

1

T27

3

T13

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3507	1			T6	6		T31	20		T23	3
auto[0]	values[0]	valids[0x1]	14463	1			T1	4		T3	6		T9	2
auto[0]	values[1]	valids[0x1]	560	1			T33	5		T43	3		T34	2
auto[0]	values[2]	valids[0x0]	515	1			T9	2		T31	2		T24	2
auto[0]	values[2]	valids[0x1]	279	1			T31	2		T43	2		T34	2
auto[0]	values[3]	valids[0x0]	490	1			T9	2		T33	3		T43	2
auto[0]	values[3]	valids[0x1]	270	1			T31	1		T43	2		T44	1
auto[0]	values[4]	valids[0x0]	457	1			T8	2		T33	4		T43	4
auto[0]	values[4]	valids[0x1]	324	1			T31	4		T34	1		T44	1
auto[0]	values[5]	valids[0x0]	431	1			T7	4		T31	7		T23	1
auto[0]	values[5]	valids[0x1]	288	1			T45	4		T39	2		T154	2
auto[0]	values[6]	valids[0x0]	531	1			T31	2		T23	3		T33	4
auto[0]	values[6]	valids[0x1]	206	1			T7	2		T34	2		T44	3
auto[0]	values[7]	valids[0x0]	565	1			T7	2		T31	4		T23	2
auto[0]	values[7]	valids[0x1]	287	1			T7	4		T31	1		T34	2
auto[0]	values[8]	valids[0x0]	3209	1			T3	6		T9	2		T11	4
auto[0]	values[8]	valids[0x1]	1936	1			T31	9		T23	2		T33	3
auto[1]	values[0]	valids[0x0]	3976	1			T5	13		T10	5		T37	43
auto[1]	values[0]	valids[0x1]	15552	1			T5	41		T10	8		T37	78
auto[1]	values[1]	valids[0x1]	519	1			T5	2		T37	8		T27	2
auto[1]	values[2]	valids[0x0]	327	1			T5	8		T27	4		T13	5
auto[1]	values[2]	valids[0x1]	256	1			T37	1		T13	13		T78	1
auto[1]	values[3]	valids[0x0]	382	1			T5	1		T10	1		T37	4
auto[1]	values[3]	valids[0x1]	239	1			T37	1		T27	1		T13	2
auto[1]	values[4]	valids[0x0]	373	1			T5	5		T37	9		T27	1
auto[1]	values[4]	valids[0x1]	280	1			T37	4		T13	3		T38	2
auto[1]	values[5]	valids[0x0]	393	1			T5	2		T37	6		T27	9
auto[1]	values[5]	valids[0x1]	273	1			T37	1		T27	2		T38	3
auto[1]	values[6]	valids[0x0]	371	1			T5	2		T37	3		T27	5
auto[1]	values[6]	valids[0x1]	248	1			T37	4		T27	2		T13	5
auto[1]	values[7]	valids[0x0]	389	1			T5	1		T37	1		T27	2
auto[1]	values[7]	valids[0x1]	241	1			T5	1		T10	1		T37	1
auto[1]	values[8]	valids[0x0]	2568	1			T5	6		T10	2		T37	23
auto[1]	values[8]	valids[0x1]	1754	1			T5	5		T10	5		T37	13